JP2023161954A - Semiconductor module and semiconductor module manufacturing method - Google Patents

Abstract

[Problem] It is possible to reduce the influence of parasitic inductance on terminals, and it is necessary to reduce the number of terminals and increase the package size, which is essential compared to general semiconductor modules in order to reduce the influence of parasitic inductance. To provide a semiconductor module and a method for manufacturing the same. A semiconductor module 1 includes a semiconductor chip 10 having a source electrode 12, a drain electrode (not shown), and a gate electrode 16, a junction 22 joined to the source electrode 12, and a source protruding from the junction 22. A clip 20 having Kelvin source terminals 26 and 27 protruding from the joint portion 22 separately from the terminal 24 and the source terminal 24, and a sealing resin 50 for sealing the semiconductor chip 10, the Kelvin source terminals 26 and 27 are It is also a hanging pin that protrudes from the joint portion 22 in a direction different from that of the source terminal 24 . [Selection diagram] Figure 3

Description

The present invention relates to a semiconductor module and a method for manufacturing a semiconductor module.

In the technical field of power semiconductor modules, higher current and higher speed are always required. On the other hand, power semiconductor modules that use MOSFETs have three types of terminals: a source terminal, a drain terminal, and a gate terminal, but as the current and speed increase, the influence of parasitic inductance at the source terminal can no longer be ignored. ing. For this reason, semiconductor modules having a Kelvin source terminal in addition to a source terminal have been known for the purpose of reducing the influence of parasitic inductance (for example, see Patent Document 1).

FIG. 17 is a plan view of a conventional semiconductor module 900.
As shown in FIG. 17, a conventional semiconductor module 900 includes a semiconductor chip 910 (MOSFET) having a source electrode 912, a drain electrode (not shown), and a gate electrode 916, a clip 920 (source connector), and a drain terminal. 934, a gate clip (gate connector) 940, a source terminal 928, a Kelvin source terminal 929, and a gate terminal 942. Further, the semiconductor module 900 is sealed with a sealing resin (not shown) except for the ends of each terminal. The clip 920 includes a chip joint 922 joined to the source electrode 912, a source terminal joint 924 protruding from the chip joint 922 and joined to a source terminal 928, and a clip 920 protruding from the chip joint 922 separately from the source terminal joint 924. It has a Kelvin source terminal junction 926 that is joined to a Kelvin source terminal 929 .

Since the conventional semiconductor module 900 includes the Kelvin source terminal 929, it is possible to reduce the influence of parasitic inductance at the source terminal 928, thereby suppressing malfunctions and noise generation.

JP2018-63993A

However, compared to a semiconductor module that does not have a Kelvin source terminal (hereinafter referred to as a "general semiconductor module"), the conventional semiconductor module 900 has an essential terminal (a terminal other than a Kelvin source terminal, especially a source terminal). ) or increase the package size. For example, it can be said that in the conventional semiconductor module 900, one of the source terminals 928, which is three in a general semiconductor module, is used as the Kelvin source terminal 929. In other words, compared to a general semiconductor module, in the conventional semiconductor module 900, the number of source terminals 928 is reduced to 2/3, so by simple calculation, the current capacity of the entire source terminal 928 is reduced to 2/3. The source wiring resistance increases by 1.5 times. To avoid this, it may be possible to increase the number of Kelvin source terminals while maintaining the number of source terminals, but in this case, the package size of the semiconductor module may have to be increased to account for the increased number of terminals. many. This problem has a particularly large effect on small, high-current power semiconductor modules whose package size cannot be easily expanded.

Therefore, the present invention has been made to solve the above-mentioned problems, and is capable of reducing the influence of parasitic inductance on terminals, and can be applied to general semiconductor modules to reduce the influence of parasitic inductance. It is an object of the present invention to provide a semiconductor module that does not require a reduction in the number of required terminals and an increase in the package size compared to the conventional semiconductor module. Another object of the present invention is to provide a method for manufacturing such a semiconductor module.

A semiconductor module of the present invention includes a semiconductor chip having a first electrode, a second electrode, and a third electrode, a joint portion joined to the first electrode, a first terminal protruding from the joint portion, and the first terminal. The clip also includes a clip having a second terminal protruding from the joint, and a sealing resin for sealing the semiconductor chip, wherein the second terminal protrudes from the joint in a direction different from that of the first terminal. It is also characterized by being a hanging pin.

The method for manufacturing a semiconductor module of the present invention includes a joint portion and a first terminal protruding from the joint portion, and is fixed to a frame by a hanging pin protruding from the joint portion in a direction different from the first terminal. a clip mounting step of mounting a clip on the first electrode side of a semiconductor chip having a first electrode, a second electrode, and a third electrode; a bonding step of bonding the bonding portion and the first electrode; a resin sealing step of sealing the semiconductor chip with a sealing resin, and cutting the hanging pin so that a portion protruding from the sealing resin remains, and moving the pin from the joint in a direction different from the first terminal. The method is characterized in that it includes a second terminal forming step of forming a protruding second terminal.

By the way, when manufacturing a semiconductor module including a clip, a structure called a hanging pin is generally used (see Embodiment 1 and FIG. 7, which will be described later). The hanging pin fixes the clip to the frame-shaped outer frame, and is generally formed from a metal plate together with the outer frame and the clip. By performing the process of bonding the semiconductor chip and the clip and the process of resin-sealing the semiconductor chip with the clip fixed to the outer frame using hanging pins, the misalignment, tilting, deformation, etc. of the clip can be suppressed. I can do it. In a typical semiconductor module manufacturing method, after the hanging pin is sealed with resin, the entire portion protruding from the sealing resin is cut off. Therefore, although the hanging pin remains in the sealing resin of a semiconductor module manufactured using the hanging pin, the hanging pin does not play any role electrically. The inventors of the present invention discovered the possibility of effectively utilizing hanging pins and completed the present invention.

According to the semiconductor module of the present invention, the second terminal is also a hanging pin that protrudes from the joint in a direction different from that of the first terminal, so the hanging pin, which has conventionally existed but has not been utilized, can be used as the second terminal. Can be used. As a result, the semiconductor module of the present invention is capable of reducing the effect of parasitic inductance on the terminals, and the number of terminals required is reduced compared to a general semiconductor module to reduce the effect of parasitic inductance. And it becomes a semiconductor module that does not require expansion of package size.

In the method for manufacturing a semiconductor module of the present invention, the hanging pin is cut so that the portion protruding from the sealing resin remains, and the second terminal is formed to protrude from the joint in a direction different from the first terminal. Because it includes a formation process, it is possible to reduce the influence of parasitic inductance on the terminals, and to reduce the influence of parasitic inductance, it is possible to reduce the number of terminals and package size, which are essential compared to general semiconductor modules. This is a semiconductor module manufacturing method that can manufacture a semiconductor module that does not require expansion.

1 is a perspective view of a semiconductor module 1 according to Embodiment 1. FIG. FIG. 3 is a hexagonal view of the semiconductor module 1 according to the first embodiment. 1 is a plan view shown to explain the internal structure of the semiconductor module 1 according to the first embodiment. FIG. 6 is a hexagonal view of the clip 20 in Embodiment 1. FIG. 3 is a flowchart of a method for manufacturing a semiconductor module according to Embodiment 1. FIG. 3 is a diagram shown to explain a semiconductor chip mounting step S10 in the first embodiment. FIG. It is a figure shown in order to explain clip mounting process S20 in Embodiment 1. It is a figure shown in order to explain the state where the outer frame F1 was removed after joining process S30 in Embodiment 1. FIG. 3 is a diagram shown to explain a resin sealing step S40 in Embodiment 1. FIG. FIG. 3 is a diagram shown to explain a Kelvin source terminal forming step S50 (second terminal forming step) in the first embodiment. FIG. 2 is a perspective view of a semiconductor module 2 according to a second embodiment. 6 is a six-sided view of a semiconductor module 2 according to a second embodiment. FIG. FIG. 3 is a plan view shown to explain the internal structure of a semiconductor module 2 according to a second embodiment. FIG. 6 is a hexagonal view of clips 20a and 20b in Embodiment 2. FIG. 7 is a hexagonal view of a semiconductor module 3 according to modification example 1. FIG. 7 is a hexagonal view of a semiconductor module 4 according to a second modification. FIG. FIG. 9 is a plan view of a conventional semiconductor module 900.

EMBODIMENT OF THE INVENTION Hereinafter, the semiconductor module and the manufacturing method of the semiconductor module of this invention are demonstrated based on each embodiment shown in a figure. Note that each embodiment described below does not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in each embodiment are essential to the solution of the present invention.

[Embodiment 1]
1. Semiconductor module 1
First, a semiconductor module 1 according to a first embodiment will be described.
FIG. 1 is a perspective view of a semiconductor module 1 according to a first embodiment.
FIG. 2 is a six-sided view of the semiconductor module 1 according to the first embodiment. 2(a) is a front view of the semiconductor module 1, FIG. 2(b) is a rear view of the semiconductor module 1, FIG. 2(c) is a plan view of the semiconductor module 1, and FIG. 2(d) is a front view of the semiconductor module 1. is a bottom view of the semiconductor module 1, FIG. 2(e) is a left side view of the semiconductor module 1, and FIG. 2(f) is a right side view of the semiconductor module 1.
FIG. 3 is a plan view shown to explain the internal structure of the semiconductor module 1 according to the first embodiment. In FIG. 3, the outer shape of the sealing resin 50 is illustrated with broken lines.
FIG. 4 is a hexagonal view of the clip 20 in the first embodiment. 4(a) is a front view of the clip 20, FIG. 4(b) is a rear view of the clip 20, FIG. 4(c) is a plan view of the clip 20, and FIG. 4(d) is a front view of the clip 20. FIG. 4(e) is a left side view of the clip 20, and FIG. 4(f) is a right side view of the clip 20.

The semiconductor module 1 according to the first embodiment includes a semiconductor chip 10, a clip 20, a die pad frame 30, a gate clip 40, and a sealing resin 50, as shown in FIGS. 1 to 3. Note that since this is a general matter, detailed explanations and illustrations will be omitted, but portions of each component that require electrical continuity are bonded using a conductive bonding material such as solder.

The semiconductor chip 10 is a MOSFET. As shown in FIG. 3, the semiconductor chip 10 has a source electrode 12 (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16 (third electrode).

As shown in FIGS. 3 and 4, the clip 20 includes a joint portion 22 joined to the source electrode 12 (first electrode), a source terminal 24 (first terminal) protruding from the joint portion 22, and a source terminal 24 (first terminal). In addition to the first terminal), Kelvin source terminals 26 and 27 (second terminals) protrude from the joint 22. The Kelvin source terminals 26 and 27 (second terminals) are also hanging pins that protrude from the joint portion 22 in a different direction from the source terminal 24 (first terminal).

The joint portion 22 of the clip 20 is a rectangular portion corresponding to the source electrode 12 . The source terminal 24 and the Kelvin source terminals 26 and 27 are bent toward the same side (bottom side). There are three source terminals 24 in the semiconductor module 1. The three source terminals 24 ultimately (ends) extend in the same direction when viewed from above.

The cross-sectional area of the Kelvin source terminals 26 and 27 (second terminal) is smaller than the cross-sectional area of the source terminal 24 (first terminal). Further, when the semiconductor module 1 is viewed from above, the width of the Kelvin source terminals 26 and 27 (second terminal) is narrower than the width of the source terminal 24 (first terminal). The object of comparison for "cross-sectional area of Kelvin source terminal (second terminal)" is "cross-sectional area of one source terminal (first terminal)", and "cross-sectional area of source terminal (entire first terminal)" is compared with "cross-sectional area of one source terminal (first terminal)". "isn't it. The same applies to the width.

The semiconductor module 1 includes a first Kelvin source terminal 26 (second terminal) protruding in the first direction, and a first Kelvin source terminal 26 (second terminal) as Kelvin source terminals 26 and 27 (second terminal), which is opposite to the first direction. The second Kelvin source terminal 27 (second terminal) protrudes in the second direction. When the semiconductor module 1 is viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) are connected to each other when the source terminal 24 (first terminal) finally extends. Extends in a direction perpendicular to the direction of Furthermore, when the semiconductor module 1 is viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) are on the same straight line.

"The direction in which the first terminal finally extends" refers to the direction in which the end of the first terminal extends. Note that in the case where there are a plurality of first terminals (source terminals 24) as in the semiconductor module 1, the first second terminal and the second The above condition is satisfied if the second terminals (Kelvin source terminals 26, 27) extend in the vertical direction.

As shown in FIG. 3, when the semiconductor module 1 is viewed from above, the source terminal 24 (first terminal) and the Kelvin source terminals 26 and 27 (second terminals) pass through the center of gravity C of the joint 22 and the source The terminals 24 (first terminals) protrude from the joint 22 starting from different sides of the joint 22 separated by virtual lines V perpendicular to the direction in which the terminals 24 (first terminals) project. The "center of gravity of the joint" in this case is a virtual center of gravity derived from the shape of the joint when viewed from above.

The die pad frame 30 is a member on which the semiconductor chip 10 is placed. The die pad frame 30 has a die pad (not shown) connected to the drain electrode of the semiconductor chip 10 and a drain terminal 34 .

The gate clip 40 has a gate electrode junction 42 joined to the gate electrode 16 and a gate terminal 44 protruding from the gate electrode junction 42 .

The sealing resin 50 seals the semiconductor chip 10. As shown in FIGS. 1 and 2, the bottom surfaces of the source terminal 24, the Kelvin source terminals 26 and 27, the drain terminal 34, the gate terminal 44, and the die pad frame 30 are exposed from the sealing resin 50. Note that the bottom surface of the die pad frame 30 is exposed from the sealing resin 50 mainly for heat radiation, and if there is no problem with heat radiation, the bottom surface of the die pad frame 30 is not necessarily exposed from the sealing resin 50. It doesn't have to be.

2. Method for Manufacturing a Semiconductor Module Next, a method for manufacturing a semiconductor module according to the first embodiment will be described.
FIG. 5 is a flowchart of a method for manufacturing a semiconductor module according to the first embodiment.
FIG. 6 is a diagram shown to explain the semiconductor chip mounting step S10 in the first embodiment. 6(a) is a diagram showing the state of the die pad frame 30 fixed to the outer frame F1 via the pin FP1, and FIG. 6(b) is a diagram showing the state of the die pad frame 30 after the semiconductor chip 10 is mounted on the die pad frame 30. FIG. In order to avoid complicating the display of symbols, in FIG. 6, the symbol is displayed only in one of the components related to the semiconductor module 1, which is located at the upper left of the page. The same applies to FIGS. 7 to 10, which will be described later.
FIG. 7 is a diagram shown to explain the clip mounting step S20 in the first embodiment. 7(a) is a diagram showing the state of the clip 20 fixed to the outer frame F2 via the hanging pin FP2, and FIG. 7(b) is a diagram showing the state after the clip 20 is placed on the semiconductor chip 10. FIG.
FIG. 8 is a diagram shown to explain a state in which the outer frame F1 is removed after the joining step S30 in the first embodiment.
FIG. 9 is a diagram shown to explain the resin sealing step S40 in the first embodiment.
FIG. 10 is a diagram shown for explaining the Kelvin source terminal forming step S50 (second terminal forming step) in the first embodiment. FIG. 10(a) is a diagram showing a state immediately after cutting the hanging pin FP2, and FIG. 10(b) is a diagram showing a state in which the hanging pin FP2 is used as Kelvin source terminals 26, 27.

As shown in FIG. 5, the method for manufacturing a semiconductor module according to the first embodiment includes a semiconductor chip mounting step S10, a clip mounting step S20, a bonding step S30, a resin sealing step S40, and a Kelvin source terminal formation. Step S50 (second terminal forming step). Each step will be explained below.

The semiconductor chip mounting step S10 is a step of mounting the semiconductor chip 10 on the die pad frame 30. In the semiconductor chip mounting step S10, first, the die pad frame 30 fixed to the outer frame F1 via pins FP1 is prepared (see FIG. 6(a)). Although nine die pad frames 30 are fixed to one outer frame F1 in FIG. 6, this is just an example. The number of die pad frames 30 fixed to the outer frame F1, that is, the number of semiconductor modules 1 manufactured at the same time, may be eight or less, or may be ten or more. Further, in FIG. 6, four pins FP1 are connected to one die pad frame 30, but this is also an example. The number of pins FP1 connected to the die pad frame 30 may be three or less, or five or more.

Next, the source electrode 12 (first electrode) and the drain electrode (second electrode) (not shown) are attached to the die pad frame 30 via a conductive bonding material or its precursor (for example, solder paste, not shown). ) and a gate electrode 16 (third electrode) (see FIG. 6(b)). The mounting is performed so that the die pad of the die pad frame 30 and the drain electrode of the semiconductor chip 10 are aligned.

The clip mounting step S20 includes a hanging pin that has a joint portion 22 and a source terminal 24 (first terminal) protruding from the joint portion 22, and that protrudes from the joint portion 22 in a direction different from the source terminal 24 (first terminal). This is a step of placing the clip 20 fixed to the outer frame by the FP 2 on the source electrode 12 (first electrode) side of the semiconductor chip 10.

In the clip mounting step S20, first, the clip 20 fixed to the outer frame F2 via the hanging pin FP2 is prepared (see FIG. 7(a)). The number and position of clips 20 correspond to the number and position of semiconductor chips 10. Note that the clip 20 prepared in the clip mounting step S20 does not need to have the same final shape as the final shape of the clip 20 in the semiconductor module 1, and in particular, the shape of the source terminal 24 may not be arranged. In this case, shaping the shape of the clip 20 can be performed after the joining step S30 and the resin sealing step S40. Next, the clip 20 is placed on the semiconductor chip 10 via a conductive bonding material or its precursor (for example, solder paste, not shown) (see FIG. 7(b)). The mounting is performed so that the source electrode 12 of the semiconductor chip 10 and the joint portion 22 of the clip 20 are aligned. At this time, by overlapping the outer frame F1 and the outer frame F2, it is possible to suppress misalignment and inclination of each component.

Furthermore, in the clip mounting step S20, the gate clip 40 is also mounted on the semiconductor chip 10. That is, the gate clip 40 is placed on the semiconductor chip 10 via a conductive bonding material or its precursor (for example, solder paste, not shown). The mounting is performed so that the gate electrode 16 of the semiconductor chip 10 and the gate electrode joint portion 42 of the gate clip 40 are aligned. Note that the gate clip 40 may be connected to the outer frame F2 via a hanging pin. In this case, the mounting of the clip 20 and the mounting of the gate clip 40 can be carried out simultaneously, and the positional shift and inclination of the gate clip 40 can also be suppressed.

The bonding step S30 is a step of bonding the bonding portion 22 and the source electrode 12 (first electrode). When using a conductive bonding material or its precursor (for example, solder paste) that melts when heated, this step can be performed by heating and cooling (reflow). In the bonding step S30, the semiconductor chip 10 and the die pad frame 30 are bonded together (the drain electrode and the die pad are bonded) and the semiconductor chip 10 and the gate clip 40 are bonded by heating and cooling the entire component that will become the semiconductor module 1. The bonding (bonding between the gate electrode 16 and the gate electrode bonding portion 42) is also performed at the same time. Thereafter, the pin FP1 is cut from the root on the die pad frame 30 side, and the outer frame F1 is removed (see FIG. 8).

The resin sealing step S40 is a step of sealing the semiconductor chip 10 with the sealing resin 50. In the resin sealing step S40, resin sealing is performed so that the source terminal 24, the Kelvin source terminals 26 and 27, the drain terminal 34, the gate terminal 44, and the bottom surfaces of the die pad frame 30 are exposed from the sealing resin 50 (FIG. 9). reference.). The resin sealing step S40 can be carried out, for example, by setting each component together with the hanging pin FP2 in a mold of a predetermined shape (not shown), and pouring the sealing resin 50 into the mold and hardening it. .

In the Kelvin source terminal forming step S50 (second terminal forming step), the hanging pin FP2 is cut so that a portion protruding from the sealing resin 50 remains, and the source terminal 24 (different from the first terminal) is formed from the joint portion 22. This is a step of forming Kelvin source terminals 26 and 27 (second terminals) that protrude in the direction. The outer frame F2 is removed after cutting the hanging pin FP2 (see FIG. 10(a)). The hanging pins FP2 after being cut become Kelvin source terminals 26 and 27 by performing appropriate bending processing, etc. (see FIG. 10(b)). In the first embodiment, the semiconductor module 1 is completed by performing the Kelvin source terminal forming step S50.

3. Effects of the semiconductor module 1 according to the first embodiment and the semiconductor module manufacturing method According to the semiconductor module 1 according to the first embodiment, the Kelvin source terminals 26 and 27 (second terminals) are connected from the junction 22 to the source terminal 24 (second terminal). Since it is also a hanging pin that protrudes in a different direction from the first terminal), it is possible to utilize the hanging pin, which has existed in the past but has not been utilized, as the Kelvin source terminals 26 and 27 (second terminal). As a result, the semiconductor module 1 according to the first embodiment is capable of reducing the influence of parasitic inductance on the terminals, and has the essential features compared to general semiconductor modules for reducing the influence of parasitic inductance. This results in a semiconductor module that does not require a reduction in terminals or an increase in package size.

Further, according to the semiconductor module 1 according to the first embodiment, the cross-sectional area of the Kelvin source terminals 26 and 27 (second terminal) is smaller than the cross-sectional area of the source terminal 24 (first terminal). It becomes possible to make the cross-sectional area of the Kelvin source terminals 26 and 27, which do not require current capacity, appropriate.

Further, according to the semiconductor module 1 according to the first embodiment, the width of the Kelvin source terminals 26 and 27 (second terminal) is narrower than the width of the source terminal 24 (first terminal) when viewed from above. It becomes possible to make the width of the Kelvin source terminals 26 and 27 appropriate so that a current capacity as large as 24 is not required.

Further, according to the semiconductor module 1 according to the first embodiment, the first Kelvin source terminal 26 (second terminal) protrudes in the first direction, and the first Kelvin source terminal 26 (second terminal) protrudes in the second direction opposite to the first direction. Since it has the second Kelvin source terminal 27 (second terminal) protruding toward the terminal, it becomes possible to provide the Kelvin source terminals 26 and 27 that directly utilize the preferred direction of protrusion as a hanging pin.

Further, according to the semiconductor module 1 according to the first embodiment, when viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) are connected to the source terminal 24 ( Since the first terminal (first terminal) extends in a direction perpendicular to the direction in which it finally extends, it is possible to make Kelvin source terminals 26 and 27 by directly utilizing the direction in which the suspension pin extends, which is preferable in terms of balance. becomes.

Further, according to the semiconductor module 1 according to the first embodiment, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) are on the same straight line when viewed from above. Therefore, it is possible to create Kelvin source terminals 26 and 27 that directly utilize the direction in which the hanging pins protrude, which is more preferable in terms of balance.

Further, according to the semiconductor module 1 according to the first embodiment, when viewed from above, the source terminal 24 (first terminal) and the Kelvin source terminals 26 and 27 (second terminals) pass through the center of gravity C of the joint portion 22. In addition, since the source terminal 24 (first terminal) projects from different sides of the joint 22 separated by the virtual line V perpendicular to the projecting direction, the starting point of the source terminal 24 and the Kelvin source are different from each other. It becomes possible to maintain a sufficient distance between the starting points of the terminals 26 and 27.

In the method for manufacturing a semiconductor module according to the first embodiment, the hanging pin FP2 is cut so that a portion protruding from the sealing resin 50 remains, and the hanging pin FP2 protrudes from the joint in a direction different from the source terminal 24 (first terminal). Since it includes the Kelvin source terminal forming step S50 (second terminal forming step) for forming the Kelvin source terminals 26 and 27 (second terminals), it is possible to reduce the influence of parasitic inductance on the terminals, and to reduce the parasitic inductance. The present invention provides a method for manufacturing a semiconductor module that can manufacture a semiconductor module that does not require a reduction in terminals or an increase in package size compared to a general semiconductor module in order to reduce the influence of .

[Embodiment 2]
FIG. 11 is a perspective view of the semiconductor module 2 according to the second embodiment.
FIG. 12 is a six-sided view of the semiconductor module 2 according to the second embodiment. 12(a) is a front view of the semiconductor module 2, FIG. 12(b) is a rear view of the semiconductor module 2, FIG. 12(c) is a plan view of the semiconductor module 2, and FIG. 12(d) is a front view of the semiconductor module 2. is a bottom view of the semiconductor module 2, FIG. 12(e) is a left side view of the semiconductor module 2, and FIG. 12(f) is a right side view of the semiconductor module 2.
FIG. 13 is a plan view shown to explain the internal structure of the semiconductor module 2 according to the second embodiment. In FIG. 13, the outer shape of the sealing resin 50 is illustrated with broken lines.
FIG. 14 is a hexagonal view of the clips 20a and 20b in the second embodiment. 14(a) is a front view of the clips 20a, 20b, FIG. 14(b) is a rear view of the clips 20a, 20b, FIG. 14(c) is a plan view of the clips 20a, 20b, and FIG. (d) is a bottom view of the clips 20a, 20b, FIG. 14(e) is a left side view of the clip 20a, FIG. 14(f) is a right side view of the clip 20a, and FIG. 14(g) is a bottom view of the clips 20a, 20b. 14(h) is a left side view of the clip 20b, and FIG. 14(h) is a right side view of the clip 20b.

The semiconductor module 2 according to Embodiment 2 basically has the same configuration as the semiconductor module 2 according to Embodiment 1, but differs from the semiconductor module 2 according to Embodiment 1 in that it each includes two components other than the sealing resin. This is different from case 1. Hereinafter, differences between the semiconductor module 2 and the semiconductor module 1 will be explained.

As shown in FIGS. 11 to 13, the semiconductor module 2 according to the second embodiment includes semiconductor chips 10a, 10b, clips 20a, 20b, die pad frames 30a, 30b, gate clips 40a, 40b, and a sealing resin. 50. The sealing resin 50 is the same as the sealing resin 50 in Embodiment 1, so a description thereof will be omitted.

As shown in FIG. 13, the semiconductor chip 10a has a source electrode 12a (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16a (third electrode). The semiconductor chip 10b has a source electrode 12b (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16b (third electrode).

As shown in FIGS. 13 and 14, the clip 20a has a joint 22a, a source terminal 24a (first terminal), and a Kelvin source terminal 26a (second terminal). The clip 20b has a joint portion 22b, a source terminal 24b (first terminal), and a Kelvin source terminal 26b (second terminal). The Kelvin source terminals 26a, 26b (second terminals) are also hanging pins that respectively protrude from the joints 22a, 22b in different directions from the source terminals 24a, 24b (first terminals).

The die pad frames 30a and 30b are members for mounting the semiconductor chips 10a and 10b, respectively. The die pad frames 30a and 30b each have a die pad (not shown) connected to the drain electrode of the semiconductor chips 10a and 10b and drain terminals 34a and 34b, respectively.

The gate clips 40a, 40b have gate electrode junctions 42a, 42b joined to the gate electrodes 16a, 16b, and gate terminals 44a, 44b protruding from the gate electrode junctions 42a, 42b, respectively.

Although illustrations and detailed explanations are omitted, the semiconductor module 2 according to the second embodiment is manufactured by a method basically similar to that of the semiconductor module according to the first embodiment (that is, clips fixed to the outer frame with hanging pins). It can be manufactured by a manufacturing method using

The semiconductor module 2 according to the second embodiment differs from the semiconductor module 1 according to the first embodiment in that each component includes two components other than the sealing resin, but according to the semiconductor module 2 according to the second embodiment , the Kelvin source terminals 26a, 26b (second terminals) are also hanging pins that protrude from the joints 22a, 22b in a different direction from the source terminals 24a, 24b (first terminals), so they are not utilized even though they have existed in the past. The unused hanging pins can be used as Kelvin source terminals 26a, 26b (second terminals). As a result, the semiconductor module 2 according to the second embodiment, like the semiconductor module 1 according to the first embodiment, can reduce the influence of parasitic inductance at the terminals, and can reduce the influence of parasitic inductance. Compared to general semiconductor modules, this semiconductor module does not require a reduction in the number of required terminals or an increase in package size.

Note that the semiconductor module 2 according to the second embodiment also has the corresponding effects among the effects other than those described above that the semiconductor module 1 according to the first embodiment has.

Although the present invention has been described above based on the above embodiments, the present invention is not limited to the above embodiments. It is possible to implement the present invention in various ways without departing from the spirit thereof, and for example, the following modifications are also possible.

(1) The shapes, positions, sizes, etc. described in each of the above embodiments (including each modified example described later) are merely examples, and can be changed within a range that does not impair the effects of the present invention.

(2) Although the cross-sectional area of the Kelvin source terminals 26, 27, 26a, 26b (second terminal) in each of the above embodiments is smaller than the cross-sectional area of the source terminals 24, 24a, 24b (first terminal), The present invention is not limited to this. The cross-sectional area of the Kelvin source terminal (second terminal) may be the same as the cross-sectional area of the source terminal (first terminal).

(3) Although the width of the Kelvin source terminals 26, 27, 26a, 26b (second terminals) in each of the above embodiments is narrower than the width of the source terminals 24, 24a, 24b (first terminals), the present invention is not limited to this. The width of the Kelvin source terminal (second terminal) may be the same as the width of the source terminal (first terminal).

(4) Although the number of hanging pins (Kelvin source terminals 26, 27, 26a, 26b) in each of the above embodiments was two per semiconductor module, the present invention is not limited to this. At least one hanging pin (Kelvin source terminal) is required for each clip, and the number can be set to any number depending on the convenience of the manufacturing method. In addition, when two or more hanging pins exist in one clip, it is not necessarily necessary to use all the hanging pins as the second terminals. Hanging pins that are not used as second terminals may be removed without being converted into terminals.

(5) Although the Kelvin source terminals 26, 27, 26a, and 26b in each of the above embodiments are bent to the same side as the source terminals 24, 24a, and 24b, the present invention is not limited to this. FIG. 15 is a six-sided view of the semiconductor module 3 according to the first modification. 15(a) is a front view, FIG. 15(b) is a rear view, FIG. 15(c) is a top view, FIG. 15(d) is a bottom view, and FIG. 15(e) is a It is a left side view, and FIG.15(f) is a right side view. The second terminal (Kelvin source terminal) can be bent in any direction depending on the application of the chip. For example, as shown in FIG. 15, the second terminal (Kelvin source terminal 26c, 27c) It may be bent to the side opposite to the terminal (source terminal 24).

(6) In the semiconductor modules 1 and 2 according to each of the above embodiments, the sealing resin 50 includes the source terminals 24, 24a, 24b, the Kelvin source terminals 26, 27, 26a, 26b, and the drain terminals 34, 34a, 34b. Although the gate terminals 44, 44a, 44b and the bottom surfaces of the die pad frames 30, 30a, 30b are exposed, the present invention is not limited thereto. FIG. 16 is a hexagonal view of the semiconductor module 4 according to the second modification. 16(a) is a front view, FIG. 16(b) is a rear view, FIG. 16(c) is a top view, FIG. 16(d) is a bottom view, and FIG. 16(e) is a It is a left side view, and FIG.16(f) is a right side view. In the semiconductor module 4 according to the second modification, the upper surface (the surface opposite to the semiconductor chip side) of the joint portion 22c in the clip 20c is also exposed from the sealing resin 50 for the purpose of further heat dissipation. Since the joint portion 22c in the semiconductor module 4 is thicker than the joint portion 22 in the first embodiment, it is exposed from the sealing resin 50. The present invention is also applicable to such semiconductor modules.

(7) Although the semiconductor chips 10, 10a, and 10b in each of the above embodiments are MOSFETs, the present invention is not limited to this. The present invention can also be applied to semiconductor modules including three-terminal semiconductor chips other than MOSFETs (for example, IGBTs).

(8) Although the method for manufacturing a semiconductor module according to the first embodiment includes the semiconductor chip mounting step S10 described above, the present invention is not limited thereto. For example, the die pad frame 30 that is fixed to the outer frame F1 via the pin FP1 is prepared, but this is an example, and a die pad frame that is not fixed to the outer frame may be prepared. Furthermore, depending on the configuration of the semiconductor module to be manufactured, it may not be necessary to perform the semiconductor chip mounting process as described above.

1, 2, 3, 4... Semiconductor module, 10, 10a, 10b... Semiconductor chip, 12, 12a, 12b... Source electrode, 16, 16a, 16b... Gate electrode, 20, 20a, 20b... Clip, 22, 22a, 22b...Joint portion, 24, 24a, 24b...Source terminal, 26, 26a, 26b, 26c, 27, 27c...Kelvin source terminal, 30, 30a, 30b...Die pad frame, 34, 34a, 34b...Drain terminal, 40, 40a, 40b... Gate clip, 42, 42a, 42b... Gate electrode joint, 44, 44a, 44b... Gate terminal, 50, 50a... Sealing resin, C... Center of gravity of the joint, F1, F2... Outer frame, FP1 ...Pin, FP2...Hanging pin, V...Virtual line

Claims (8)

a semiconductor chip having a first electrode, a second electrode, and a third electrode;
a clip having a joint portion joined to the first electrode, a first terminal protruding from the joint portion, and a second terminal protruding from the joint portion separately from the first terminal;
and a sealing resin that seals the semiconductor chip,
The semiconductor module, wherein the second terminal is also a hanging pin that protrudes from the joint in a direction different from that of the first terminal. The semiconductor module according to claim 1, wherein the cross-sectional area of the second terminal is the same as or smaller than the cross-sectional area of the first terminal. 3. The semiconductor module according to claim 2, wherein the width of the second terminal is the same as or narrower than the width of the first terminal when viewed in plan. The second terminal includes a first second terminal protruding in a first direction and a second second terminal protruding in a second direction opposite to the first direction. The semiconductor module according to any one of claims 1 to 3, characterized in that: When viewed in plan, the first second terminal and the second second terminal extend in a direction perpendicular to a direction in which the first terminal ultimately extends. The semiconductor module according to claim 4. 5. The semiconductor module according to claim 4, wherein the first second terminal and the second second terminal are on the same straight line when viewed in plan. When viewed in a plan view, the first terminal and the second terminal are on different sides of the joint section separated by an imaginary line that passes through the center of gravity of the joint section and is perpendicular to the protruding direction of the first terminal. 4. The semiconductor module according to claim 1, wherein the semiconductor module protrudes from the joint portion starting from the junction. A clip that has a joint portion and a first terminal protruding from the joint portion, and is fixed to the outer frame by a hanging pin that protrudes from the joint portion in a direction different from that of the first terminal, is connected to the first electrode and the second terminal. a clip mounting step of mounting a semiconductor chip having an electrode and a third electrode on the first electrode side;
a bonding step of bonding the bonding portion and the first electrode;
a resin sealing step of sealing the semiconductor chip with a sealing resin;
a second terminal forming step of cutting the hanging pin so that a portion protruding from the sealing resin remains, and forming a second terminal protruding from the joint in a direction different from the first terminal. A method for manufacturing a semiconductor module characterized by:

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