JP2023119421A - wiring board - Google Patents

Abstract

To improve connection reliability of a wiring board.SOLUTION: A wiring board 100 includes: a first insulation layer 31, a first conductor layer 1, a second insulation layer 32, a second conductor layer 2, and a third conductor layer 3; a first via conductor 61 which connects the first conductor layer 1 to the third conductor layer 3; and a second via conductor 62 which connects the first conductor layer 1 to the second conductor layer 2. The second insulation layer 32 covers a surface, of the first conductor layer 1, opposite to the first insulation layer 31 and a lateral surface of the first conductor layer 1. The surface of the first conductor layer is a polished surface. The first conductor layer 1 includes: a first layer 1a which is made of a metal film constituting the lateral surface and a lower surface that is a surface on the first insulation layer 31 side; and a second layer 1b which is made of an electrolytic plating film formed on an inner side than the first layer 1a. In plan view, the second via conductor 62 overlaps the first via conductor 61.SELECTED DRAWING: Figure 1

Description

The present invention relates to wiring boards.

Patent Document 1 discloses a multilayer printed wiring board in which conductor circuits are connected through via holes having a stack via structure. A land of at least one via hole of the via holes having the stacked via structure is formed to extend into a conductive circuit non-formation region formed around the via hole of the stacked via structure.

Japanese Patent Application Laid-Open No. 2002-280739

In the multilayer printed wiring board disclosed in Patent Document 1, there is a possibility that peeling may occur between the via hole or land and the interlayer resin insulation layer.

A wiring board of the present invention comprises a first insulating layer, a first conductor layer formed on the first insulating layer, a second insulating layer covering the first insulating layer and the first conductor layer, It includes a second conductor layer formed on the second insulation layer and a third conductor layer covered with the first insulation layer. The wiring board further includes a first via conductor formed inside a first through hole penetrating the first insulating layer and connecting the first conductor layer and the third conductor layer; a second via conductor formed inside a second through hole penetrating an insulating layer and connecting the first conductor layer and the second conductor layer, wherein the second insulating layer comprises the first conductor; a surface of the layer opposite to the first insulating layer and a side surface of the first conductor layer, the surface of the first conductor layer opposite to the first insulating layer being a polished surface; One conductor layer includes a first layer made of a metal film forming a side surface and a lower surface, which is a surface on the side of the first insulating layer, and a second layer made of an electrolytic plating film formed inside the first layer. , and the second via conductor overlaps the first via conductor in plan view.

According to the embodiments of the present invention, it is possible to provide a wiring board with high connection reliability in which stress applied to via conductors can be dispersed.

1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention; FIG. The enlarged view of the II section of FIG. FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board according to one embodiment of the present invention;

A wiring board according to one embodiment of the present invention will be described with reference to the drawings. It should be noted that the drawings referred to hereinafter are not intended to show the exact proportions of the constituent elements, but are drawn so that the features of the present invention can be easily understood. FIG. 1 is a cross-sectional view showing a wiring board 100 that is an example of a wiring board according to one embodiment. FIG. 2 shows an enlarged view of part II of FIG. Note that the wiring board 100 is merely an example of the wiring board of the present embodiment. The laminated structure of the wiring board of the embodiment and the number of conductor layers and insulating layers are not limited to the laminated structure of wiring board 100 in FIG.

As shown in FIG. 1, the wiring board 100 includes an insulating layer 31 (first insulating layer), a conductor layer 1 (first conductor layer) formed on the insulating layer 31, and a conductor layer 1 covering the conductor layer 1. An insulating layer 32 (second insulating layer) covering the surface of the insulating layer 31 and the conductor layer 1 which is not exposed, and a conductor layer 2 (second conductor layer) formed on the insulating layer 32. . The wiring board 100 of FIG. 1 further includes a core substrate 4, an insulating layer 33 (third insulating layer) laminated on one surface of the core substrate 4, and a conductor layer 3 formed on the insulating layer 33. (third conductor layer) and The insulating layer 31 is laminated on the insulating layer 33 and the conductor layer 3 . The surface of the insulating layer 33 not covered with the conductor layer 3 and the conductor layer 3 are covered with the insulating layer 31 .

The core substrate 4 includes an insulating layer 34 and a conductor layer 41 formed on one surface 34 s of the insulating layer 34 . The core substrate 4 further includes a through-hole conductor 42 passing through the insulating layer 34, and also includes a conductor layer (not shown) similar to the conductor layer 41 on the other surface (not shown) of the insulating layer 34. I'm in. The conductor layer 41 is connected to a conductor layer on the other surface (not shown) of the insulating layer 34 by a through-hole conductor 42 . The inside of the through-hole conductor 42 is filled with a resin body 43 containing epoxy resin or the like. The conductor layer 41 has a multi-layer structure including a lower layer made of metal foil on the insulating layer 34 , a middle layer integrated with the through-hole conductor 42 , and an upper layer covering the resin body 43 . Although not shown, the wiring board 100 includes any number of conductor layers including any conductor pattern and any number of insulating layers laminated or formed on the surface opposite to the one surface 34s of the insulating layer 34 . It can contain layers.

In the description of the embodiments, the side farther from the insulating layer 34 in the thickness direction of the wiring board 100 is also referred to as "outer", "upper" or "upper", or simply "upper", and the side closer to the insulating layer 34 is , "inner", "lower" or "lower", or simply "lower". Furthermore, in each conductor layer and each insulating layer, the surface facing away from the insulating layer 34 is also referred to as the "upper surface", and the surface facing the insulating layer 34 is also referred to as the "lower surface".

The insulating layers 31-34 contain any insulating resin. Insulating resins include thermosetting resins such as epoxy resins, bismaleimide triazine resins (BT resins), and phenolic resins, as well as fluororesins, liquid crystal polymers (LCP), fluoroethylene (PTFE) resins, polyester ( PE) resins, and thermoplastic resins such as modified polyimide (MPI) resins. Each insulating layer may contain the same insulating resin, or may contain different insulating resins. Further, each insulating layer may contain a core material (reinforcing material) made of glass fiber or aramid fiber. In the example of FIG. 1, the insulating layer 34 includes a core material 34b. Each insulating layer may further include an inorganic filler (not shown) consisting of particulates such as silica ( _SiO2 ), alumina, or mullite. An insulating layer containing such an inorganic filler may be preferable because it can have a coefficient of thermal expansion close to that of each conductor layer, for example.

Connection conductors (via conductors) are formed in the respective insulating layers 31, 32 and 33 to penetrate the respective insulating layers and connect the adjacent conductor layers via the respective insulating layers. Via conductors 61 (first via conductors) connecting the conductor layers 3 and 1 are formed in the insulating layer 31 . Via conductors 61 are formed inside through holes 31 a (first through holes) penetrating insulating layer 31 . Via conductors 62 (second via conductors) connecting the conductor layers 1 and 2 are formed in the insulating layer 32 . Via conductors 62 are formed inside through-holes 32 a (second through-holes) penetrating insulating layer 32 . Via conductors 63 connecting the fourth conductor layer 41 and the conductor layer 3 are formed in the insulating layer 33 . Via conductors 63 are formed inside through-holes 33 a penetrating insulating layer 33 .

Conductor layers 1 to 3 and 41 each include arbitrary conductor patterns. For example, in the example of FIG. 1, the conductor layer 1 includes conductor patterns 11 . Conductive pattern 11 includes via land 113 (first via land) integrally formed with via conductor 61 . That is, conductor layer 1 includes via land 113 connected to via conductor 61 . Also, the conductor pattern 11 may include, for example, a wiring pattern 112 formed in a wiring pattern having a relatively small wiring width and a relatively small distance between wirings. Moreover, in the example of FIG. 1, the conductor layer 3 includes a conductor pattern 13 . Conductive pattern 13 includes via land 313 integrally formed with via conductor 63 and wiring pattern 312 . The conductor layer 2 includes a conductor pattern 12 including via lands 213 (second via lands) integrally formed with the via conductors 62 in a predetermined pattern. That is, conductor layer 2 includes via land 213 connected to via conductor 62 . In the example shown in the figure, the surface composed of the insulating layer 32 and the conductor layer 2 is one of the two surfaces of the wiring board 100 (the surface orthogonal to the thickness direction of the wiring board 100) (the first surface 100s). ). When the wiring board 100 is used, a component (not shown) to be mounted on the wiring board 100 can be placed on the first surface 100s. That is, the first surface 100s of the wiring board 100 may be a component mounting surface. Therefore, the via land 213 may be a component mounting via pad that is used as a connecting portion when an external component is mounted on the wiring board 100 .

Conductor layers 1, 2, 3, 41 and via conductors 61, 62, 63 are formed using any metal such as copper or nickel. In the example of FIG. 1, the conductor layers 1-3 have a two-layer structure. The conductor layer 1 includes a first layer 1a formed on a surface 31s of the insulating layer 31 on the insulating layer 32 side, and a second layer 1b formed on the first layer 1a. The conductor layer 2 includes a lower layer 2a formed on the surface 32s of the insulating layer 32 and an upper layer 2b formed on the lower layer 2a. The conductor layer 3 includes a lower layer 3a formed on the surface 33s of the insulating layer 33 and an upper layer 3b formed on the lower layer 3a.

The conductor layers 1 to 3 and the via conductors 61 to 63 are further detailed with reference to FIG. As shown in FIG. 2 , the insulating layer 32 covers the upper surface 11 s of the conductor layer 1 on the side opposite to the insulating layer 31 . This insulating layer 32 also covers the side surfaces of the conductor layer 1 . That is, the insulating layer 32 covers the side surfaces of the via lands 113 included in the conductor layer 1 . Moreover, the insulating layer 32 covers the side surface of the conductor pattern 11 such as the wiring pattern 112 . Conductive pattern 11 includes first layer 1a and second layer 1b included in conductive layer 1 . The first layer 1a is made of a metal film and constitutes the side surface of the conductor layer 1 and the lower surface, which is the surface on the insulating layer 31 side. The second layer 1b is an electroplated film formed inside the first layer 1a in the conductor layer 1, that is, inside each conductor pattern 11 relative to the first layer 1a. In each via land 113, the side surface of the second layer 1b and the surface on the insulating layer 31 side are covered with the first layer 1a.

In this embodiment, in each conductor pattern 11 as well, the first layer 1a constitutes the side surface and the lower surface, which is the surface on the insulating layer 31 side. The second layer 1b is formed inside each conductor pattern 11 from the first layer 1a. The first layer 1a covers the side surface of the second layer 1b in each conductor pattern 11 and the surface on the insulating layer 31 side. In other words, the first layer 1a of the conductor layer 1 constitutes the entire surface of the conductor layer 1 except for the upper surface 11s.

For example, the metal film forming the first layer 1a is a sputtering film, an electroless plating film, or the like. The second layer 1b made of an electrolytic plated film is formed, for example, by pattern plating including electrolytic plating using the first layer 1a as a power supply layer.

As shown in FIG. 2 , via conductors 61 are formed integrally with conductor layer 1 . That is, the first layer 1a and the second layer 1b constituting the conductor layer 1 are continuously formed from the surface 31s of the insulating layer 31 to the inside of the through hole 31a provided in the insulating layer 31, and the via conductors are formed. 61. In the first layer 1 a , not only the side surfaces of the conductor pattern 11 but also the side surfaces of the via conductors 61 are integrally formed with the side surfaces of the conductor pattern 11 . Therefore, it is considered that the stress applied to the side surface of via conductor 61 is also distributed to the side surface of conductor pattern 11 such as via land 113 . As a result, peeling of via conductor 61 and insulating layer 31 may be suppressed.

As described above, the second layer 1b of the conductor pattern 11 is formed by pattern plating including electrolytic plating using the first layer 1a as a power supply layer. During the pattern plating, in areas where the conductive pattern 11 is not formed, the first layer 1a covering the side surfaces of the conductive pattern 11 is formed on a plating resist (not shown) used for pattern plating. That is, the first layer 1a is not formed on the surface 31s of the insulating layer 31 in areas where the conductor pattern 11 is not formed. Therefore, the portion of the surface 31s that is exposed without being covered with the conductive pattern 11 has not undergone the process of forming the first layer 1a thereon, and the conductive layer such as the first layer 1a is formed thereon. It is not the face from which the body was removed. Therefore, there is no concern about conductor residues. Therefore, wiring can be arranged in the conductor pattern 11 at a fine pitch, for example, like the wiring pattern 112 of the embodiment. For example, in the wiring pattern 112, the wiring width has a minimum value of 5.0 μm or less. Even if the wiring pattern 112 is formed with such a wiring width and a distance between the wirings, it is considered that there is no risk of causing a defect such as a short circuit between the wirings. In addition, wiring patterns 112 having a high aspect ratio can be formed. Therefore, the wiring pattern 112 with low resistance can be formed at high density on the conductor layer 1 .

In this embodiment, the upper surface 11s of the conductor layer 1 is a polished surface. The upper surface 11s is, for example, a polished surface polished by CMP (Chemical Mechanical Polishing) or sandblasting. That is, the upper surface 11s of the conductor layer 1 is a surface that has been polished in the manufacturing process of the wiring substrate 100, as will be described later. Therefore, even if unevenness occurs on the surface after formation of the conductive pattern 11 by electroplating, the top surface 11s is flattened by scraping the protrusions. If the upper surface 11s of the conductor layer 1 is a polished surface with few irregularities, for example, in the wiring pattern 112, good high-frequency transmission characteristics may be obtained.

Via conductors 62 formed integrally with the conductor layer 2 are formed in the insulating layer 32 covering the upper surface 11 s of the conductor layer 1 and the side surfaces of the conductor pattern 11 . The conductor layer 2 includes the lower layer 2a and the upper layer 2b as described above. The via conductor 62 is composed of a lower layer 2 a and an upper layer 2 b that are continuously formed from the surface 32 s of the insulating layer 32 to the inside of the through hole 32 a provided in the insulating layer 32 . In the present embodiment, the lower layer 2a of the conductor layer 2 is made of a metal film like the first layer 1a of the conductor layer 1, and constitutes the side surface of the conductor layer 2 and the lower surface, which is the surface on the insulating layer 32 side. . The upper layer 2b is made of an electrolytic plated film formed inside each conductor pattern 12 relative to the lower layer 2a. The side surface of upper layer 2b and the surface on the insulating layer 32 side are covered with lower layer 2a.

In the example of FIG. 2, the via conductors 62 and the via conductors 61 overlap in plan view. Therefore, when an external component (not shown) is mounted on the first surface 100 s of the wiring board 100 via connection pads (via lands 213 ), the conductor layers below the conductor layer 1 such as the conductor layer 3 and external components are connected by short paths. In addition, since the side surface of the conductor pattern 12 and the side surface of the via conductor 62 are integrally formed, it is considered that cracks or the like are unlikely to occur between the via land 213 on the insulating layer 32 and the via conductor 62 . . However, even if the conductor layer 2 is formed such that the lower layer 2a does not cover the side surface of the conductor pattern 12 of the conductor layer 2 and the upper layer 2b is exposed to the side surface of the conductor pattern 12, like the conductor layer 3 described later. good.

Note that the expression that the via conductors 62 and the via conductors 61 “overlap in plan view” means that the bottom portion of the via conductor 62 in contact with the upper surface 11s of the conductor layer 1 is the through hole 31 a at the interface between the insulating layer 31 and the conductor layer 1 . means that it fits within the opening of the Also, "planar view" means viewing the wiring board of the embodiment with a line of sight along its thickness direction.

The conductor layer 3 includes the lower layer 3a and the upper layer 3b as described above. In the present embodiment, the lower layer 3a of the conductor layer 3 is made of a metal film in the same manner as the first layer 1a of the conductor layer 1, and the side surfaces of the conductor patterns 13 such as the via lands 313 and the wiring patterns 312 of the conductor layer 3 and the insulating layers are formed. It constitutes the lower surface, which is the surface on the layer 33 side. The upper layer 3b is an electrolytic plated film formed inside each conductor pattern 13 relative to the lower layer 3a. The side surface of upper layer 3b and the surface on the insulating layer 33 side are covered with lower layer 3a. As described above, in the wiring board of the embodiment, a desired number of conductor layers including conductor patterns whose side surfaces are formed of metal films used as power supply layers during electroplating can be formed.

In this embodiment, via conductors 62 , 61 , and 63 are formed so as to be stacked, and a so-called stack via conductor is formed on the through-hole conductor 42 . In a wiring board on which stacked via conductors are formed, thermal stress or the like may cause stress to the stacked via conductors or distortion of the stacked via conductors. Interfacial peeling may occur at the interface between the via conductor and the insulating layer. However, in the present embodiment, since the side surface of the via conductor 61 and the side surface of the conductor pattern 11 are integrally formed in the via conductor 61, the stress can be dispersed. can be provided.

As described above, the conductor layer 1 is formed with the wiring patterns 112 arranged at a fine pitch. That is, as shown in FIG. 1, the spacing S1 between the wiring patterns 112 included in the conductor layer 1 (the distance between the upper surfaces 11s of the wiring patterns 112) is the same as that of the wiring patterns included in another conductor layer, for example, the conductor layer 3. It can be formed to be smaller than the interval S2 between the wiring patterns 312 (the distance between the upper surfaces 13s of the wiring patterns 312). Also, the wiring width L1 of the wiring pattern 112 (the wiring width on the upper surface 11s of the wiring pattern 112) may be smaller than the wiring width L2 of the wiring pattern 312 (the wiring width on the upper surface 13s of the wiring pattern 312). However, in this embodiment, the wiring patterns to be arranged at high density can be arranged at arbitrary positions and numbers on arbitrary conductor layers formed in the same manner as the conductor layer 1 . It is thought that a wiring board with high connection reliability including wiring patterns arranged at high density can be obtained.

In the wiring board 100 of the embodiment, the conductor pattern 11 of the conductor layer 1, the conductor pattern 12 of the conductor layer 2, and the conductor pattern 13 of the conductor layer 3 are arranged such that the side surfaces of the conductor patterns 11, 12, and 3 are directed inward toward the lower side (toward the core substrate 4). It has a tapered shape that slopes downward. Therefore, it is considered that the insulating layer 32 and the insulating layer 31 are less likely to be lifted due to the tapered shape, and therefore the peeling of the insulating layer 32 or the insulating layer 31 from the conductive pattern 11 and the conductive pattern 13 is less likely to occur. The conductor pattern 11, the conductor pattern 12, and the conductor pattern 13 are determined by selecting a suitable plating resist when forming the conductor layer 1, the conductor layer 2, and the conductor layer 3, and selecting a suitable exposure condition for the plating resist. can be formed by

Next, an example of a method for manufacturing the wiring board of the embodiment will be described with reference to FIGS. 3A to 3N using the wiring board 100 of FIG. 1 as an example.

As shown in FIG. 3A, a core substrate 4 including an insulating layer 34 and conductor layers 41 on both sides thereof is prepared, and insulating layers 33 are formed on both sides thereof. For example, a through-hole for forming a through-hole conductor 42 is formed in a double-sided copper-clad laminate, and a metal film is formed on the inner wall of the through-hole and the surface of the double-sided copper-clad laminate by electroless plating, sputtering, electroplating, or the like. be done. A through-hole conductor 42 made of a metal film integrated with the metal film is formed in the through-hole. For example, the inside of the through-hole conductor 42 is filled with the resin body 43 by injecting epoxy resin. Then, a metal film is further formed on the previously formed metal film and resin body 43 by electroless plating or electrolytic plating. Conductive layers 41 having a multi-layered structure having a predetermined conductive pattern are formed on both surfaces of the insulating layer 34 by patterning using a subtractive method. For example, the core substrate 4 is prepared in this manner, and the insulating layers 33 are formed on both surfaces of the core substrate 4 by laminating, for example, film-like epoxy resin and thermally compressing them. However, the film-like resin used for forming the insulating layer 33 may be a photosensitive resin, similarly to the insulating layer 31 to be described later.

As shown in FIG. 3B, through holes 33a are formed in the insulating layer 33 at positions where the via conductors 63 (see FIG. 1) are to be formed by, for example, carbon dioxide laser light irradiation. When insulating layer 33 is formed using a photosensitive resin, through holes 33a may be formed by exposure and development using an exposure mask having openings corresponding to through holes 33a. It should be noted that FIG. 3B and FIGS. 3C-3H and 3J-3N referenced below omit the illustration of conductive and insulating layers that may be formed on the opposite surface of one surface 34s of the insulating layer 34. and their explanations are also omitted. However, on the opposite side of the surface 34s, conductor layers and insulating layers may be formed in the same manner and number as on the surface 34s or different in manner and number than on the surface 34s. An insulating layer may not be formed.

A plating resist R1 is provided on the surface of the insulating layer 33, as shown in FIG. 3C. An opening R11 corresponding to the conductor pattern 13 (see FIG. 1) included in the conductor layer 3 is formed in the plating resist R1.

The plating resist R1 may be provided by laminating a dry film resist, for example, or may be provided by applying and drying a positive liquid resist. The opening R11 can be formed by exposure using an exposure mask having openings corresponding to the opening R11 and development. For example, a positive plating resist is used. The exposure conditions are adjusted to increase the amount of exposure on the surface side of the plating resist R1 so that the dissolution by the developer is greater on the surface side of the plating resist R1 than on the surface 33s side of the insulating layer 33, thereby performing plating. The opening R11 can be formed to have a cross-sectional shape in which the diameter of the opening on the surface side of the resist R1 is large and the diameter of the opening decreases toward the surface 33s. In a positive plating resist, wetting of the resist during development does not occur, so the opening R11 having a desired shape can be maintained even after development.

As shown in FIG. 3D, on the inner wall of the through-hole 33a and on the surface 33s of the insulating layer 33 not covered with the plating resist R1, on the surface of the plating resist R1 and on the inner wall of the opening R11 of the plating resist R1. Then, a metal film 3aa forming a lower layer 3a (see FIG. 1) of the conductor layer 3 is formed. The metal film 3aa is formed by sputtering or electroless plating, for example. Next, an electrolytic plated film 3bb forming an upper layer 3b (see FIG. 1) of the conductor layer 3 is formed on the metal film 3aa. Electroplated film 3bb is formed by electrolytic plating using metal film 3aa as a power supply layer.

As shown in FIG. 3D, the electrolytic plated film 3bb is also formed on the surface of the plating resist R1, specifically, on the metal film 3aa covering the surface of the plating resist R1. On the metal film 3aa on the surface 33s of the insulating layer 33, an electrolytic plated film 3bb having a thickness equal to or greater than the thickness required for at least the upper layer 3b of the conductor layer 3 is formed. Therefore, the opening R11 of the plating resist R1 may or may not be completely filled with the electrolytic plated film 3bb. On the other hand, electrolytic plated film 3bb completely fills through hole 33a of insulating layer 33 . As a result, via conductors 63 (see FIG. 1) are formed.

As shown in FIG. 3E, a portion of electrolytic plated film 3bb in the stacking direction is removed by polishing. Electroplated film 3bb is removed by, for example, CMP or sandblasting. This polishing also removes at least a portion of the metal film 3aa on the surface of the plating resist R1. The electrolytic plated film 3bb is polished together with the plating resist R1 until the thickness of the electrolytic plated film 3bb on the surface 33s of the insulating layer 33 reaches a predetermined thickness required for the upper layer 3b of the conductor layer 3 . A flat upper surface 13 s is obtained in the conductor layer 3 .

As shown in FIG. 3F, plating resist R1 is removed. As a result, a conductor layer 3 including conductor patterns 13 such as via lands 313 and a plurality of wiring patterns 312 is formed.

As shown in FIG. 3G, an insulating layer 31 is formed and a through hole 31a is formed in the insulating layer 31. As shown in FIG. The insulating layer 31 can be formed, for example, similarly to the insulating layer 33, by laminating a film-like resin containing epoxy resin or the like and applying heat and pressure.

When the conductor pattern 11 including the wiring patterns 112 arranged at a fine pitch is formed on the conductor layer 1 as in the example of FIG. 1, it may be preferable that the via conductors 61 are also formed at a fine pitch. A through-hole 31a with a small diameter needs to be formed in the insulating layer 31 . In such a case, the insulating layer 31 containing no inorganic filler may be preferable so that the small-diameter through-holes 31a can be easily formed.

A resin that does not contain an inorganic filler is unlikely to have a coefficient of thermal expansion close to that of a conductor layer made of metal, such as the conductor layer 1 . Therefore, when the insulating layer 31 does not contain an inorganic filler, it is considered preferable that the insulating layer 31 is not exposed to high temperatures during hardening of the insulating layer 31, for example. Therefore, the insulating layer 31 can be formed of a resin having a curing mechanism other than thermosetting, such as a photocurable resin. That is, the insulating layer 31 can be made of a photosensitive resin.

Therefore, the film-like resin used for forming the insulating layer 31 may be, for example, a photosensitive resin containing a photopolymerization initiator. A high temperature curing process for the insulating layer 31 can be avoided. Formation of the through holes 31a in the insulating layer 31 can be performed by, for example, irradiating carbon dioxide laser light or excimer laser light. When insulating layer 31 is formed using a photosensitive resin, through holes 31a may be formed by exposure and development using an exposure mask having openings corresponding to through holes 31a.

As shown in FIG. 3H, a plating resist R2 is provided on the surface of the insulating layer 31, similarly to the plating resist R1 described above. An opening R21 corresponding to the conductor pattern 11 (see FIG. 1) of the conductor layer 1 is formed in the plating resist R2, similarly to the opening R11 described above.

As shown in FIG. 3I, a metal film 1aa forming the first layer 1a (see FIG. 1) of the conductor layer 1 is formed. The metal film 1aa is formed by sputtering or electroless plating, for example. Incidentally, FIG. 3I shows the state after the formation of the metal film 1aa in the portion corresponding to the III portion shown in FIG. 3H. The metal film 1aa is formed on the inner wall of the through-hole 31a, on the surface 31s of the insulating layer 31 not covered with the plating resist R2, on the surface of the plating resist R2, and on the inner wall of the opening R21 of the plating resist R2. It is formed.

As shown in FIG. 3J, an electrolytic plated film 1bb forming the second layer 1b (see FIG. 1) of the conductor layer 1 is formed on the metal film 1aa in the same manner as the electrolytic plated film 3bb. The electrolytic plated film 1bb is formed on the metal film 1aa on the surface 31s of the insulating layer 31 so as to have a thickness equal to or greater than the thickness required for the second layer 1b of the conductor layer 1 at least. Through hole 31a of insulating layer 31 is completely filled with electrolytic plated film 1bb, and as a result, via conductor 61 is formed.

As shown in FIG. 3K, by a method similar to that described with reference to FIG. 3E, a portion of the electroplated film 1bb in the stacking direction is polished together with the metal film 1aa on the surface of the plating resist R2. removed. 11 s of flat upper surfaces are obtained also in the conductor layer 1. FIG. After that, the plating resist R2 is removed.

As shown in FIG. 3L, a conductor layer 1 including conductor patterns 11 such as via lands 113 and having a two-layer structure consisting of a first layer 1a and a second layer 1b is obtained. Since the conductor layer 1 including the conductor pattern 11 is formed without going through the step of removing the first layer 1a by etching, the wiring patterns 112 arranged at a fine pitch can be formed.

An insulating layer 32 is formed as shown in FIG. 3M. The insulating layer 32 can be formed, for example, by a method similar to the method for forming the insulating layer 31 described above. The insulating layer 32 may also be made of a photosensitive epoxy resin containing a photopolymerization initiator. A through hole 32 a is formed in the insulating layer 32 at the location where the via conductor 62 is formed. The through holes 32a can be formed by exposure and development when the insulating layer 32 is made of a photosensitive resin. The through-holes 32a may be formed by irradiating carbon dioxide laser light or excimer laser light.

A conductor layer 2 is formed by a method similar to the method for forming the conductor layer 1 described above. That is, as shown in FIG. 3M, a plating resist R3 having openings R31 corresponding to the conductor patterns 12 (see FIG. 1) of the conductor layer 2 is formed on the surface 32s of the insulating layer 32, and the lower layer 2a of the conductor layer 2 is formed. (see FIG. 1) is formed by, for example, sputtering or electroless plating. The metal film 2aa is formed on the inner wall of the through hole 32a, the surface 32s of the insulating layer 32, the surface of the plating resist R3, and the inner wall of the opening R31. Then, an electrolytic plated film 2bb constituting the upper layer 2b (see FIG. 1) of the conductor layer 2 is formed on the metal film 2aa by electrolytic plating using the metal film 2aa as a power supply layer. Electroplated film 2bb completely fills through hole 32a of insulating layer 32, and via conductor 62 is formed.

Thereafter, a portion of the electroplated film 2bb in the stacking direction is removed by polishing together with the plating resist R3. A flat top surface 12s (see FIG. 3N) is obtained in the conductor layer 2 . After that, the plating resist R2 is removed. The wiring board 100 shown in FIG. 1 is completed through the above steps.

The wiring substrates of the embodiments are not limited to those having the structures illustrated in each drawing, and the structures, shapes, and materials illustrated in this specification. As described above, the wiring board of the embodiment can have any laminated structure. For example, the wiring board of the embodiment may be a coreless board that does not include a core board. A wiring board of embodiments may have any number of conductor layers and insulating layers. For example, via conductors 62 in the example of FIG. 1 may be formed as conductor posts having a similar two-layer structure. Since the side surface of the protruding portion of the conductor post on the surface 32s of the insulating layer 32 is also covered with the lower layer 2a, the conductor post may be less likely to break due to external stress. Also, the insulating layer 32 may be provided as a solder resist. It is thought that the insulating layer 31 and the conductor layer 1 can be protected, and the short circuit between the conductor patterns 11 of the conductor layer 1 can be suppressed.

100 Wiring board 1 Conductor layer (first conductor layer)
11 conductor pattern 112 wiring pattern 113 via land (first via land)
1a First layer 1b Second layer 2 Conductor layer (second conductor layer)
2a Lower layer 2b Upper layer 3 Conductor layer (third conductor layer)
13 Conductor pattern 312 Wiring pattern 313 Via land 3a Lower layer 3b Upper layer 31 Insulating layer (first insulating layer)
31s surface 32 insulating layer (second insulating layer)
32s surface 61, 62, 63 via conductors 31a, 32a, 33a through hole L1 wiring width L2 of wiring pattern 112 wiring width S1 of wiring pattern 312 spacing S2 between wirings of wiring pattern 112 spacing between wirings of wiring pattern 312

Claims (8)

a first insulating layer;
a first conductor layer formed on the first insulating layer;
a second insulating layer covering the first insulating layer and the first conductor layer;
a second conductor layer formed on the second insulating layer;
a third conductor layer covered with the first insulating layer;
A wiring board comprising
The wiring board further comprises
a first via conductor formed inside a first through hole penetrating the first insulating layer and connecting the first conductor layer and the third conductor layer;
a second via conductor formed inside a second through hole penetrating the second insulating layer and connecting the first conductor layer and the second conductor layer;
The second insulating layer covers the surface of the first conductor layer opposite to the first insulating layer and the side surface of the first conductor layer,
a surface of the first conductor layer opposite to the first insulating layer is a polished surface;
The first conductor layer includes a first layer made of a metal film forming a side surface and a lower surface, which is a surface on the side of the first insulating layer, and a first layer made of an electrolytic plating film formed inside the first layer. 2 layers and
The second via conductor overlaps the first via conductor in plan view. 2. The wiring board according to claim 1, wherein the first layer and the second layer are formed continuously from the surface of the first insulating layer to the inside of the first through hole, and the first via conductor constitutes 2. The wiring board according to claim 1, wherein said first insulating layer contains a photosensitive resin. 4. The wiring board according to claim 3, wherein said second insulating layer contains a photosensitive resin. The wiring board according to claim 1,
A surface composed of the second conductor layer and the surface of the second insulating layer not covered with the second conductor layer is a component mounting surface. The wiring board according to claim 1,
The first conductor layer includes a first via land connected to the first via conductor,
The second conductor layer includes a second via land connected to the second via conductor. The wiring board according to claim 1,
The second conductor layer is composed of a lower layer forming a lower surface, which is the surface on the second insulating layer side, and an upper layer formed on the lower layer,
a side surface of the second conductor layer is covered with the lower layer;
A surface of the second conductor layer opposite to the second insulating layer is a polished surface. 8. The wiring board according to claim 7, wherein said lower layer and said upper layer are formed continuously from the surface of said second insulating layer to the inside of said second through-hole to constitute said second via conductor. there is

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