JP2023072494A - Driving circuit, power source control device, and switching power source - Google Patents

Abstract

To prevent simultaneous ON (penetration current) of an upper transistor and a lower transistor.SOLUTION: A driving circuit 12 is to complementarily turn on or off an upper transistor N1 and a lower transistor N2 in accordance with a pulse control signal PWM, and includes an upper pulse control signal generation circuit 123 that generates an upper pulse control signal HGCTL in accordance with the pulse control signal PWM, a lower pulse control signal generation circuit 124 that generates a lower pulse control signal LGCTL in accordance with the pulse control signal PWM, an upper gate driver 121 that turns on or off the upper transistor N1 in accordance with the upper pulse control signal HGCTL, and a lower gate driver 122 that turns on or off the lower transistor N2 in accordance with the lower pulse control signal LGCTL. The lower pulse control signal generation circuit 124 generates the lower pulse control signal LGCTL so that, once the lower transistor N2 is turned off, the off state is kept until the minimum off time passes.SELECTED DRAWING: Figure 4

Description

The invention disclosed in this specification relates to a drive circuit, a power supply control device, and a switching power supply.

In recent years, switching power supplies are widely used as power supply means for various applications.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

Japanese Patent Application Laid-Open No. 2018-57100

However, the conventional drive circuit for driving the switching power supply (especially the switch output stage thereof) has room for improvement in terms of preventing simultaneous turn-on of the upper transistor and the lower transistor (through current).

In view of the above problems found by the inventors of the present application, the invention disclosed in the present specification provides a drive circuit and a power supply that can prevent simultaneous ON (through current) of an upper transistor and a lower transistor. An object of the present invention is to provide a control device and a switching power supply.

For example, the drive circuit disclosed herein complementarily turns on/off an upper transistor and a lower transistor in response to a pulse control signal; an upper pulse control signal generation circuit configured to generate a signal; a lower pulse control signal generation circuit configured to generate a lower pulse control signal in response to said pulse control signal; and said upper pulse control an upper gate driver configured to turn on/off the upper transistor in response to a signal; and a lower gate driver configured to turn on/off the lower transistor in response to the lower pulse control signal. wherein the lower pulse control signal generation circuit generates the lower pulse control signal such that once the lower transistor is switched to an off state, the off state is maintained until a predetermined minimum off time elapses. do.

Other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description and accompanying drawings that follow.

According to the invention disclosed in this specification, it is possible to provide a drive circuit, a power supply control device, and a switching power supply that can prevent the upper transistor and the lower transistor from being turned on at the same time (through current). .

FIG. 1 is a diagram showing the overall configuration of a switching power supply. FIG. 2 is a diagram showing a first embodiment of the power control device. FIG. 3 is a diagram showing an example of switching drive in the first embodiment. FIG. 4 is a diagram showing a second embodiment of the power control device. FIG. 5 is a diagram showing an example of switching drive in the second embodiment. FIG. 6 is a diagram showing an example of the lower pulse control signal generation operation.

<Switching power supply>
FIG. 1 is a diagram showing the overall configuration of a switching power supply. The switching power supply 1 of this configuration example is a non-isolated step-down DC/DC converter (so-called BUCK converter) that steps down an input voltage Vin to generate an output voltage Vout. It comprises various discrete components (here inductor L1 and capacitor C1).

The power supply control device 10 is a semiconductor device that controls the switching power supply 1 . The power supply control device 10 has a plurality of external terminals (external terminals T1 to T4 in this figure) as means for establishing electrical connection with the outside of the device.

The external terminal T1 (PVIN pin) is connected to the application end of the input voltage Vin. The external terminal T2 (SW pin) is connected to the first end of the inductor L1. The external terminal T3 (FB pin) is connected to the application end of the output voltage Vout together with the second end of the inductor L1 and the first end of the capacitor C1. A voltage dividing circuit that generates a feedback voltage Vfb corresponding to the output voltage Vout may be provided between the terminal to which the output voltage Vout is applied and the external terminal T3. The external terminal T4 (PGND pin) and the second end of the capacitor C1 are both connected to the power system ground terminal (=ground voltage PGND application terminal).

The power supply control device 10 switches and drives a built-in switch output stage (not shown) so that the output voltage Vout (or the feedback voltage Vfb) fed back to the external terminal T3 matches a desired target value. As a result, a square-wave switch voltage Vsw is generated at the external terminal T2. The inductor L1 and the capacitor C1 function as a rectifying/smoothing circuit for rectifying and smoothing the switch voltage Vsw to generate the output voltage Vout.

<Power supply control device (first embodiment)>
FIG. 2 is a diagram showing a first embodiment of the power control device 10. As shown in FIG. A power control device 10 of this embodiment is formed by integrating a switch output stage 11, a drive circuit 12, a bootstrap circuit 13, and a controller 14. FIG.

Note that the power control device 10 may be provided with functional blocks other than those described above. For example, the power supply control device 10 includes an internal reference voltage generation circuit, a communication I/O [input/output] circuit, a clock generation circuit, a self-diagnosis circuit, and various abnormal protection circuits (UVLO [under voltage locked out], OCP [over current protection], OVD [over voltage detection], UVD [under voltage detection], SCP [short circuit protection] and TSD [thermal shutdown]) may be integrated.

The switch output stage 11 includes a transistor N1 (eg, an N-channel MOSFET [metal oxide semiconductor field effect transistor]) and a transistor N2 (eg, an N-channel MOSFET).

The drain of the transistor N1 is connected to the application terminal (PVIN pin) of the input voltage Vin. The source of the transistor N1 is connected to the switch voltage Vsw application terminal (SW pin). The gate of the transistor N1 is connected to the application terminal of the upper gate drive signal HG. The transistor N1 is turned on when the upper gate drive signal HG is at high level (≈Vbst), and turned off when the upper gate drive signal HG is at low level (≈Vsw). The transistor N1 functions as an upper transistor (=output transistor) of the switch output stage 11 .

The drain of the transistor N2 is connected to the switch voltage Vsw application terminal (SW pin). The source of transistor N2 is connected to the power system ground terminal (PGND pin). The gate of the transistor N2 is connected to the application terminal of the lower gate drive signal LG. The transistor N2 is turned on when the lower gate drive signal LG is at high level (≈Vin), and turned off when the lower gate drive signal LG is at low level (≈PGND). Transistor N2 functions as a lower transistor (=synchronous rectification transistor) of switch output stage 11 .

The transistors N1 and N2 are complementarily turned on/off according to the upper gate drive signal HG and the lower gate drive signal LG. As a result, a square-wave switch voltage Vsw pulse-driven between the input voltage Vin and the ground voltage PGND is generated.

The term "complementary" is used not only when the on/off states of the transistors N1 and N2 are completely reversed, but also when the transistors N1 and N2 are turned off simultaneously to prevent the generation of through current. It should be understood broadly to include the case where a period (so-called dead time) is provided.

Also, the rectification method of the switching power supply 1 is not necessarily limited to the synchronous rectification method, and a diode rectification method may be adopted. In that case, a rectifier diode may be used instead of the transistor N2.

The drive circuit 12 is a circuit block that drives the switch output stage 11 according to the pulse control signal PWM input from the controller 14. For example, the drive circuit 12 includes an upper gate driver 121, a lower gate driver 122, and an upper pulse control signal generator. A circuit 123 and a lower pulse control signal generation circuit 124 are included.

The upper gate driver 121 operates by being supplied with the bootstrap voltage Vbst and the switch voltage Vsw, and turns on/off the transistor N1 by generating the upper gate drive signal HG according to the upper pulse control signal HGCTL. For example, the upper gate drive signal HG becomes high level (≈Vbst) when the upper pulse control signal HGCTL is high level, and becomes low level (≈Vsw) when the upper pulse control signal HGCTL is low level. Become.

The lower gate driver 122 operates by receiving the supply of the input voltage Vin and the ground voltage PGND, and turns on/off the transistor N2 by generating the lower gate drive signal LG according to the lower pulse control signal LGCTL. . The lower gate drive signal LG becomes high level (≈Vin) when the lower pulse control signal LGCTL is at high level, and becomes low level (≈PGND) when the lower pulse control signal LGCTL is at low level. becomes.

The upper pulse control signal generation circuit 123 generates the upper pulse control signal HGCTL according to the pulse control signal PWM. For example, the upper pulse control signal HGCTL becomes high level when the pulse control signal PWM is high level, and becomes low level when the pulse control signal PWM is low level. The upper pulse control signal generation circuit 123 also functions as a level shifter that adapts the signal level of the upper pulse control signal HGCTL to the input dynamic range of the upper gate driver 121 .

The lower pulse control signal generation circuit 124 generates the lower pulse control signal LGCTL according to the pulse control signal PWM. Note that the lower pulse control signal generation circuit 124 may include, for example, an inverter INVa that inverts the logic level of the pulse control signal PWM to generate the lower pulse control signal LGCTL. In this case, the lower pulse control signal LGCTL becomes low level when the pulse control signal PWM is high level, and becomes high level when the pulse control signal PWM is low level.

Further, the upper pulse control signal generation circuit 123 and the lower pulse control signal generation circuit 124 generate the upper pulse control signal HGCTL and the lower pulse control signal LGCTL so as to provide a simultaneous OFF period (so-called dead time) for the transistors N1 and N2. It also has a function to adjust each logic switching timing.

The bootstrap circuit 13 is a circuit block that generates a bootstrap voltage Vbst higher than the switch voltage Vsw, and includes a transistor P2 (for example, a P-channel MOSFET) and a capacitor circuit CAP (=boot capacitor). .

The drain of the transistor P2 is connected to the application terminal (PVIN pin) of the input voltage Vin. The drain of the transistor P2 may be connected to the application end of the internal power supply voltage Vref (eg, 5V). The source and backgate of the transistor P2 are both connected to the application terminal (=BOOT node) of the bootstrap voltage Vbst. A bootstrap control signal S4 is input from the controller 14 to the gate of the transistor P2.

Note that the transistor P2 is basically turned on/off in synchronization with the transistor N2. More specifically, the transistor P2 is turned on during the on period of the transistor N2 (=low level period of the switch voltage Vsw), and turned off during the off period of the transistor N2 (=high level period of the switch voltage Vsw). Become.

Also associated with transistor P2 is a body diode BD3. Specifically, the drain of the transistor P2 corresponds to the anode of the body diode BD3, and the source of the transistor P2 corresponds to the cathode of the body diode BD3. When only the body diode BD3 is used as the rectifying element forming the bootstrap circuit 13, the gate and source of the transistor P2 should be shorted.

In addition, the capacitor circuit CAP is connected between the application end of the bootstrap voltage Vbst (=BOOT node) and the application end of the switch voltage Vsw (=SW pin). to store the charging voltage Vcap.

Therefore, the aforementioned bootstrap voltage Vbst is always higher than the switch voltage Vsw by the charging voltage Vcap (≈Vsw+Vcap). Specifically, during the high level period of the switch voltage Vsw (Vsw≈Vin, N1=ON, N2=OFF), Vbst≈Vin+Vcap. On the other hand, during the low level period of the switch voltage Vsw (Vsw≈PGND, N1=OFF, N2=ON), Vbst≈PGND+Vcap.

When the transistor P2 is turned on/off as the rectifying element of the bootstrap circuit 13, Vcap≈Vin-Vds (where Vds is the voltage between the drain and source of the transistor P2). On the other hand, when the transistor P2 is always turned off and only the body diode BD3 is used as the rectifying element of the bootstrap circuit 13, Vcap≈Vin-Vf (where Vf is the forward drop voltage of the body diode BD3).

The bootstrap voltage Vbst generated in this way is supplied to the drive circuit 12 (especially the upper gate driver 121) and is used as the high level of the upper gate drive signal HG (=gate voltage for turning on the transistor N1). Used. That is, during the ON period of the transistor N1, the high level (≈Vbst) of the upper gate drive signal HG is raised to a voltage value (≈Vin+Vcap) higher than the high level (≈Vin) of the switch voltage Vsw. Therefore, the gate-source voltage (=HG-SW) of the transistor N1 can be increased to reliably turn on the transistor N1.

By the way, if the capacitor circuit CAP is incorporated in the power supply control device 10, it becomes possible to reduce external discrete components. However, it is difficult to secure a sufficient capacitance value for the IC-embedded capacitor circuit CAP. Therefore, the capacitor circuit CAP may be configured as a so-called doubler capacitor (=voltage doubler) that can switch the capacitance value depending on whether the transistor N1 is turned on or off.

For example, if two capacitors are charged in parallel and then switched to series, the voltage VC across each capacitor can be doubled. That is, it is possible to raise the bootstrap voltage Vbst from (VC+Vsw) to (2VC+Vsw).

Of course, the configuration of the capacitor circuit CAP is not necessarily limited to the above, and any configuration that can realize m-fold boosting of the voltage VC between both ends (where m>1) may be used.

It is also possible to externally attach a discrete capacitor element to the power control device 10 instead of building the capacitor circuit CAP in the power control device 10 . In that case, the application end (=BOOT node) of the bootstrap voltage Vbst may be pulled out of the power supply control device 10 as a BOOT pin.

The controller 14 is supplied with an internal power supply voltage Vreg (eg, 5 V) and operates to generate a pulse control signal PWM so that a desired output voltage Vout is generated from the input voltage Vin. Any well-known technique (voltage mode control, current mode control, hysteresis control (ripple control), etc.) may be applied to the output feedback control method of the output voltage Vout, so detailed description thereof will be omitted.

<Study on Simultaneous ON (Through Current)>
FIG. 3 is a diagram showing an example of switching drive in the first embodiment. From the top, the pulse control signal PWM, the voltage between the gate and source of the transistor N1 (=HG-SW), and the gate/source voltage of the transistor N2. A source-to-source voltage (=LG-PGND) is depicted.

First, focusing on times t21 to t22, the behavior when the high level period of the pulse control signal PWM (=on period of the transistor N1) is relatively long will be described.

At time t21, the pulse control signal PWM rises to high level. At this time, the gate-source voltage (=HG-SW) of the transistor N1 rises to a high level with a delay of the delay time Td1. On the other hand, the gate-source voltage (=LG-PGND) of the transistor N2 falls to a low level more quickly than the gate-source voltage (=HG-SW) of the transistor N1.

At time t22, the pulse control signal PWM falls to low level. At this time, the gate-source voltage (=LG-PGND) of the transistor N2 rises to a high level with a delay of the delay time Td2. On the other hand, the gate-source voltage (=HG-SW) of the transistor N1 falls to a low level more quickly than the gate-source voltage (=LG-PGND) of the transistor N2.

By providing the delay times Td1 and Td2, the gate-source voltages of the transistors N1 and N2 are both at low level at the logic switching timing of the pulse control signal PWM. Simultaneous off periods can be provided.

Next, focusing on times t23 to t24, the behavior when the high level period of the pulse control signal PWM (=on period of the transistor N1) is relatively short will be described.

As shown in the figure, the gate-source voltage (=HG-SW) of the transistor N1 rises to a high level with a delay time Td1 behind the rising timing of the pulse control signal PWM. Further, the gate-source voltage (=LG-PGND) of the transistor N2 rises to a high level with a delay time Td2 behind the falling timing of the pulse control signal PWM. The provision of such delay times Td1 and Td2 is as described above.

However, if the high level period of the pulse control signal PWM is relatively short, as shown in the figure, the pulse control signal PWM becomes low before the delay time Td1 elapses after the pulse control signal PWM rises to high level. Levels may drop. In other words, a situation may occur in which the gate-source voltage (=HG-SW) of the transistor N1 rises to a high level after the pulse control signal PWM falls to a low level.

In particular, since the upper pulse control signal generation circuit 123 has a level shifter function, the signal delay (=delay time Td1) inside the circuit is large, so the above situation is likely to occur.

On the other hand, the gate-source voltage (=LG-PGND) of the transistor N2 rises to a high level with a delay time Td2 behind the falling timing of the pulse control signal PWM, as described above. As a result, as shown in the figure, there may occur a period during which the gate-source voltages of the transistors N1 and N2 are both at a high level, that is, a simultaneous ON period of the transistors N1 and N2.

If the transistors N1 and N2 are turned on at the same time, an excessive through current will flow through the switch output stage 11, causing the power control device 10 to malfunction. Therefore, as a general countermeasure, a high level period extension circuit may be introduced to extend the high level period of the pulse control signal PWM when it is short.

However, in the configuration that extends the high level period of the pulse control signal PWM, the minimum duty ratio of the switch output stage 11 (and the input/output voltage ratio of the switching power supply 1) is limited. In particular, in order to reliably prevent the transistors N1 and N2 from being turned on at the same time, it is necessary to set the amount of extension of the high level period to be relatively large in consideration of manufacturing variations and temperature characteristics of the high level period extension circuit. Therefore, the limitation of the above-described minimum duty ratio (input/output voltage ratio) becomes apparent.

In the following, in view of the above considerations, even if the high level period of the pulse control signal PWM (=the ON period of the transistor N1) is short, simultaneous turning-on of the transistors N1 and N2 (extending the occurrence of an excessive through current) is prevented. 2nd Embodiment of the power supply control apparatus 10 which can do is proposed.

<Power supply control device (second embodiment)>
FIG. 4 is a diagram showing a second embodiment of the power control device 10. As shown in FIG. The power supply control device 10 of the present embodiment is based on the first embodiment (FIG. 2) described above, and additionally has a timer CRT and a latch LAT as components of the lower pulse control signal generation circuit 124 .

The timer CRT delays the internal signal SA (=corresponding to the first internal signal corresponding to the lower pulse control signal LGCTL) output from the latch LAT to generate the internal signal SB (=corresponding to the second internal signal). do. For example, the internal signal SB rises to high level when the timer time TCR elapses after the internal signal SA rises to high level, and goes low when the timer time TCR elapses after the internal signal SB falls to low level. fall to the level. As the timer CRT, for example, a CR timer including a resistor and a capacitor may be used.

The latch LAT is a type of sequential circuit configured to receive the input of the pulse control signal PWM and the internal signal SB to switch the logic level of the internal signal SA, and includes NOR gates NORa and NORb and an inverter INVb.

NOR gate NORa receives inputs of internal signals SB and SD and outputs an internal signal SC (=third internal signal). Therefore, the internal signal SC becomes low level when at least one of the internal signals SB and SD is high level, and becomes high level when both of the internal signals SB and SD are low level.

The NOR gate NORb receives the input of the pulse control signal PWM and the internal signal SC, and outputs the internal signal SD (=corresponding to the fourth internal signal). Therefore, the internal signal SD becomes low level when at least one of the pulse control signal PWM and the internal signal SC is high level, and becomes high level when both the pulse control signal PWM and the internal signal SC are low level. .

Inverter INVb receives an input of internal signal SD, inverts the logic level of internal signal SD, and outputs internal signal SA. Therefore, the internal signal SA becomes low level when the internal signal SD is high level, and becomes high level when the internal signal SD is low level.

Once the transistor N2 is turned off, the lower pulse control signal generation circuit 124 of this configuration maintains the off state of the transistor N2 until a predetermined minimum off time (=corresponding to the aforementioned timer time TCR) elapses. The lower pulse control signal LGCTL is generated as follows.

FIG. 5 is a diagram showing an example of switching drive in the second embodiment. As in FIG. 3 described above, the pulse control signal PWM, the gate-source voltage (=HG-SW ), and the gate-source voltage (=LG-PGND) of the transistor N2. Regarding the gate-source voltage (=LG-PGND) of the transistor N2, the solid line indicates the behavior in the second embodiment (FIG. 4), and the broken line indicates the behavior in the first embodiment (FIG. 2). showing.

In the switching power supply 1 of the second embodiment, once the transistor N2 is switched to the off state, the off state of the transistor N2 is maintained until a predetermined minimum off time (=corresponding to the timer time TCR described above) elapses. .

Specifically, at times t21 and t23, after the pulse control signal PWM falls to high level, the gate-source voltage (=LG-PGND) of the transistor N2 temporarily changes to low level. After falling, the gate-source voltage (=LG-PGND) of the transistor N2 is maintained at a low level at least until the timer time TCR elapses.

With this configuration, the high level period of the pulse control signal PWM is relatively short, and the voltage between the gate and source of the transistor N1 (=HG-SW) becomes high level after the pulse control signal PWM falls to low level. Even if a rising condition occurs, the gate-source voltage (=LG-PGND) of the transistor N2 is maintained at a low level at least until the minimum off-time of the transistor N2 has elapsed. Therefore, it is possible to prevent the transistors N1 and N2 from being turned on at the same time (furthermore, the occurrence of an excessive through current).

In particular, in the switching power supply 1 of the second embodiment, the minimum off time of the transistor N2 is provided instead of extending the high level period of the pulse control signal PWM. Therefore, it is possible to prevent the transistors N1 and N2 from being turned on at the same time (and thus excessive through current) without sacrificing the minimum duty ratio of the switch output stage 11 (and thus the input/output voltage ratio of the switching power supply 1). can do.

FIG. 6 is a diagram showing an example of the lower pulse control signal generation operation, and depicts the pulse control signal PWM, the internal signals SA to SD, and the lower pulse control signal LGCTL in order from the top. For convenience of illustration, signal delays in NOR gates NORa and NORb and inverters INVa and INVb have been ignored.

First, focusing on times t31 to t33, the behavior when the high level period of the pulse control signal PWM (=on period of the transistor N1) is relatively long will be described. Incidentally, immediately before time t31, both the pulse control signal PWM and the internal signals SA to SC are at low level, and the internal signal SD and the lower pulse control signal LGCTL are at low level.

At time t31, when pulse control signal PWM rises to high level, internal signal SD falls to low level. Therefore, since the internal signal SA rises to high level, the lower pulse control signal LGCTL falls to low level. Also, when the internal signal SD falls to low level, the internal signal SC rises to high level. On the other hand, even if the internal signal SA rises to high level, the internal signal SB is maintained at low level until the timer time TCR elapses.

At time t32, when the timer time TCR elapses, the internal signal SB rises to high level. As a result, the internal signal SC falls to low level. Note that the internal signals SA and SD and the lower pulse control signal LGCTL are maintained at the previous logic levels (SA=H, SD=L, and LGCTL=L) unless the pulse control signal PWM falls to low level. ).

At time t33, when pulse control signal PWM falls to low level, internal signal SD rises to high level. Therefore, since the internal signal SA falls to low level, the lower pulse control signal LGCTL rises to high level. On the other hand, the internal signal SB is maintained at a high level until the timer time TCR elapses after the internal signal SA falls to a low level, and falls to a low level after the timer time TCR elapses. Note that the internal signal SC is maintained at the low level even after the pulse control signal PWM has fallen to the low level.

Next, focusing on times t34 to t36, the behavior when the high level period of the pulse control signal PWM (=on period of the transistor N1) is relatively short will be described. Incidentally, immediately before time t34, the pulse control signal PWM and the internal signals SA to SC are all at low level, and the internal signal SD and the lower pulse control signal LGCTL are at low level.

At time t34, when pulse control signal PWM rises to high level, internal signal SD falls to low level. Therefore, since the internal signal SA rises to high level, the lower pulse control signal LGCTL falls to low level. Also, when the internal signal SD falls to low level, the internal signal SC rises to high level. On the other hand, even if the internal signal SA rises to high level, the internal signal SB is maintained at low level until the timer time TCR elapses. Thus, the behavior at time t34 is the same as the behavior at time t31.

At time t35, the pulse control signal PWM falls to low level. However, since the timer time TCR has not elapsed at this time, the internal signal SB is maintained at the low level. At this time, the internal signal SC remains at high level, and the internal signal SD remains at low level. Therefore, since the internal signal SA is maintained at a high level, the lower pulse control signal LGCTL is maintained at a low level.

At time t36, when timer time TCR has elapsed, internal signal SB rises to a high level. Therefore, since the internal signal SC falls to low level, the internal signal SD rises to high level. As a result, since the internal signal SA falls to low level, the lower pulse control signal LGCTL rises to high level. The internal signal SB is maintained at high level until the timer time TCR elapses after the internal signal SA falls to low level, and falls to low level after the timer time TCR elapses.

Thus, once the pulse control signal PWM rises to high level, the internal signal SA is maintained at high level at least until the timer time TCR elapses. As a result, the lower pulse control signal LGCTL is maintained at low level. That is, the minimum off-time of the transistor N2 can be provided by the above series of lower pulse control signal generation operations.

In particular, the lower pulse control signal generation circuit 124 is configured as a timer latch circuit having a self-reset function by using a timer CRT and a latch LAT. Therefore, when the timer time TCR has elapsed, the lower pulse control signal generation circuit 124 is always reset by itself, so that the problem of freezing the lower gate driver 122 does not occur.

<Summary>
The following provides a general description of the various embodiments described above.

For example, the drive circuit disclosed herein complementarily turns on/off an upper transistor and a lower transistor in response to a pulse control signal; an upper pulse control signal generation circuit configured to generate a signal; a lower pulse control signal generation circuit configured to generate a lower pulse control signal in response to said pulse control signal; and said upper pulse control an upper gate driver configured to turn on/off the upper transistor in response to a signal; and a lower gate driver configured to turn on/off the lower transistor in response to the lower pulse control signal. wherein the lower pulse control signal generation circuit generates the lower pulse control signal such that once the lower transistor is switched to an off state, the off state is maintained until a predetermined minimum off time elapses. (first configuration).

In the drive circuit having the first configuration, the lower pulse control signal generation circuit is configured to generate a second internal signal by giving a delay to the first internal signal corresponding to the lower pulse control signal. and a latch configured to receive inputs of the pulse control signal and the second internal signal and switch the logic level of the first internal signal (second configuration). good.

In the drive circuit having the second configuration, the timer may be a CR timer (third configuration).

Further, in the drive circuit having the second or third configuration, the latch is a first logic gate configured to receive inputs of the second internal signal and the fourth internal signal and output a third internal signal. a second logic gate configured to receive the input of the pulse control signal and the third internal signal and output the fourth internal signal; and the first internal signal to receive the input of the fourth internal signal. and an inverter configured to output a signal (fourth configuration).

Further, in the drive circuit having any one of the first to fourth configurations, the upper pulse control signal generation circuit may be configured to function as a level shifter (fifth configuration).

Further, for example, the power supply control device disclosed in this specification controls a switching power supply that generates an output voltage from an input voltage, and includes a drive circuit having any one of the first to fifth configurations, A configuration (sixth configuration) includes a controller configured to generate the pulse control signal so that the desired output voltage is generated from the input voltage.

In the power supply control device according to the sixth configuration, the upper gate driver is an N-channel upper transistor connected between the input voltage application terminal and the switch voltage application terminal according to the upper pulse control signal. may be turned on/off (seventh configuration).

The power supply control device according to the seventh configuration further comprises a bootstrap circuit configured to generate a bootstrap voltage higher than the switch voltage by the charging voltage of the boot capacitor and supply the bootstrap voltage to the upper gate driver ( 8th configuration).

Further, in the power supply control device according to the eighth configuration, the bootstrap circuit may switch the capacitance value of the boot capacitor according to the on/off state of the upper transistor (ninth configuration). good.

Further, for example, the switching power supply disclosed in this specification has a configuration (tenth configuration) including the power supply control device according to any one of the sixth to ninth configurations.

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. For example, the mutual replacement of bipolar transistors with MOS field effect transistors and the logic level inversion of various signals are optional. That is, the above embodiments should be considered as examples in all respects and not restrictive, and the technical scope of the present invention is defined by the scope of the claims, It should be understood that all changes that come within the meaning and range of equivalency of the claims are included.

1 switching power supply 10 power control device (semiconductor device)
11 switch output stage 12 drive circuit 121 upper gate driver 122 lower gate driver 123 upper pulse control signal generation circuit 124 lower pulse control signal generation circuit 13 bootstrap circuit 14 controller BD3 body diode C1 capacitor CAP capacitor circuit (boot capacitor)
CRT Timer INVa, INVb Inverter L1 Inductor LAT Latch N1, N2 Transistor (N-channel MOSFET)
NOR1, NOR2 NOR gate P2 Transistor (P-channel MOSFET)
T1 to T4 external terminal

Claims (10)

A drive circuit configured to complementarily turn on/off upper and lower transistors in response to a pulse control signal,
an upper pulse control signal generation circuit configured to generate an upper pulse control signal in response to the pulse control signal;
a lower pulse control signal generation circuit configured to generate a lower pulse control signal in response to the pulse control signal;
an upper gate driver configured to turn on/off the upper transistor in response to the upper pulse control signal;
a lower gate driver configured to turn on/off the lower transistor in response to the lower pulse control signal;
with
The lower pulse control signal generation circuit generates the lower pulse control signal such that once the lower transistor is switched to an OFF state, the OFF state is maintained until a predetermined minimum OFF time elapses. . The lower pulse control signal generation circuit,
a timer configured to delay a first internal signal corresponding to the lower pulse control signal to generate a second internal signal;
a latch configured to accept inputs of the pulse control signal and the second internal signal and switch the logic level of the first internal signal;
2. The drive circuit of claim 1, comprising: 3. The driving circuit according to claim 2, wherein said timer is a CR timer. The latch is
a first logic gate configured to receive inputs of the second internal signal and the fourth internal signal and output a third internal signal;
a second logic gate configured to receive inputs of the pulse control signal and the third internal signal and output the fourth internal signal;
an inverter configured to receive the input of the fourth internal signal and output the first internal signal;
4. A drive circuit according to claim 2 or 3, comprising: 5. The drive circuit according to claim 1, wherein said upper pulse control signal generation circuit functions as a level shifter. A power control device configured to control a switching power supply that generates an output voltage from an input voltage,
a driving circuit according to any one of claims 1 to 5;
a controller configured to generate the pulse control signal such that the desired output voltage is generated from the input voltage;
A power control unit. 7. The upper gate driver according to claim 6, wherein the upper gate driver turns on/off an N-channel upper transistor connected between the input voltage application terminal and the switch voltage application terminal according to the upper pulse control signal. power control unit. 8. The power control device according to claim 7, further comprising a bootstrap circuit configured to generate a bootstrap voltage that is higher than the switch voltage by a boot capacitor charging voltage and supply the bootstrap voltage to the upper gate driver. 9. The power supply control device according to claim 8, wherein said bootstrap circuit can switch the capacitance value of said boot capacitor according to on/off of said upper transistor. A switching power supply comprising the power control device according to any one of claims 6 to 9.

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