JP2023045099A - semiconductor equipment - Google Patents

Abstract

A semiconductor device that suppresses an increase in wiring load capacitance of word lines and an increase in block size is provided. In this semiconductor device, two or more layers of first semiconductor chips and one or more layers of second semiconductor chips are stacked, and each of the first semiconductor chips includes a storage area and a first circuit area. and the second semiconductor chip includes a second circuit region, the first circuit region includes a high withstand voltage transistor having a withstand voltage of 15 V or more and 25 V or less, and a low withstand voltage transistor having a withstand voltage of 0.05 V or more and 3 V or less. The second circuit region does not include a transistor, and does not include a high-voltage transistor with a breakdown voltage of 15V or more and 25V or less, but includes a low-voltage transistor with a breakdown voltage of 0.05V or more and 3V or less. [Selection drawing] Fig. 1A

Description

The present invention relates to semiconductor devices.

A semiconductor device having a memory cell array is known. For example, there is a semiconductor device in which a plurality of chips including 3D-NAND memory cell arrays are stacked and a CMOS chip is further stacked. In this semiconductor device, a row decoder/driver circuit and a page buffer circuit are formed on a CMOS chip (see, for example, Japanese Unexamined Patent Application Publication No. 2002-200013).

U.S. Patent Specification No. 10600763

However, if the row decoder/driver circuit is provided in a CMOS chip separate from the chip containing the 3D NAND memory cell array, the row decoder/driver circuit in the CMOS chip will send a word to each chip containing the 3D NAND memory cell array. Since the lines are routed, the wiring load capacity of the word lines increases.

In addition, when the number of word lines from the row decoder/driver circuit increases, it is necessary to share the word lines among a plurality of chips including the 3D NAND memory cell array, resulting in an increase in block size.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device that suppresses an increase in wiring load capacitance of word lines and an increase in block size.

In this semiconductor device, two or more layers of first semiconductor chips and one or more layers of second semiconductor chips are stacked, and each of the first semiconductor chips includes a storage area and a first circuit area. , the second semiconductor chip includes a second circuit region, the first circuit region includes a high-voltage transistor with a breakdown voltage of 15 V or more and 25 V or less, and does not include a low-voltage transistor with a breakdown voltage of 0.05 V or more and 3 V or less. , the second circuit region does not include a high-voltage transistor with a breakdown voltage of 15V or more and 25V or less, but includes a low-voltage transistor with a breakdown voltage of 0.05V or more and 3V or less.

According to the disclosed technique, it is possible to provide a semiconductor device that suppresses an increase in wiring load capacitance of word lines and an increase in block size.

1 is a schematic diagram (part 1) illustrating a semiconductor device according to a first embodiment; FIG. FIG. 2 is a schematic diagram (part 2) illustrating the semiconductor device according to the first embodiment; FIG. 3 is a schematic diagram (part 3) illustrating the semiconductor device according to the first embodiment; 3 is a schematic cross-sectional view illustrating the 3D NAND memory cell array and main parts of the first circuit region; FIG. FIG. 3 is a diagram illustrating electrical connections between a 3D NAND memory cell array and main parts of a first circuit region; 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment; FIG. FIG. 4 is a diagram (part 1) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 2B is a diagram (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 3 is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 4 is a diagram (part 4) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 5) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 6) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 7) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 8) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 12 is a diagram (part 9) illustrating the manufacturing process of the semiconductor device according to the first embodiment; It is a schematic diagram which shows the application example of the semiconductor device which concerns on 1st Embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code|symbol may be attached|subjected to the same component part, and the overlapping description may be abbreviate|omitted.

<First Embodiment>
[Structure of entire semiconductor device]
FIG. 1A is a schematic diagram (Part 1) illustrating the semiconductor device according to the first embodiment. Referring to FIG. 1A, the semiconductor device 1 according to the first embodiment has a structure in which semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ , 30 ₄ , and 30 ₅ are stacked.

The semiconductor device 1 is, for example, a 3D-NAND flash memory device, but may be a 3D-ReRAM memory device or a 3D-MRAM memory device. Here, the following description will be given assuming that the semiconductor device 1 is a 3D-NAND flash memory device.

Each of the semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ , and 30 ₄ is a memory chip, and includes a 3D NAND memory cell array 310 which is a storage area constructed using a three-dimensional circuit, and a first circuit area 320. It has

The first circuit region 320 includes a CMOS circuit formed on a semiconductor substrate, wiring connected to the CMOS circuit, an insulating layer, and the like. In each semiconductor chip, the 3D NAND memory cell array 310 and the first circuit region 320 are electrically connected to each other. The semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ and 30 ₄ may have the same structure.

The semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ and 30 ₄ are representative examples of the first semiconductor chip according to the present invention. The first semiconductor chip may be laminated in at least two layers. Five or more layers of the first semiconductor chip can be stacked.

In the example of FIG. 1A, the first circuit region 320 is arranged below the 3D NAND memory cell array 310 in each of the semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ and 30 ₄ . This structure is a so-called CUA (CMOS Under Array).

However, the configuration of FIG. 1A is just an example, and the first circuit region 320 does not have to be arranged below the 3D NAND memory cell array 310 . For example, the first circuit region 320 may be arranged next to the 3D NAND memory cell array 310 and electrically connected to each other to form a so-called CNA (CMOS NEXT Array).

Alternatively, part of the first circuit region 320 may be arranged below the 3D NAND memory cell array 310 and the rest may be arranged next to the 3D NAND memory cell array 310 . In either case, the first circuit region 320 and the 3D NAND memory cell array 310 are arranged within the same chip. It should be noted that adopting CUA is more advantageous than adopting CNA in that the total area of semiconductor device 1 can be reduced.

The first circuit region 320 includes high-voltage transistors and does not include low-voltage transistors. That is, the transistors formed in the first circuit region 320 are only high voltage transistors. Here, the high voltage transistor is a transistor with a voltage resistance of 15 V or more and 25 V or less. A low-voltage transistor is a transistor with a voltage resistance of 0.05 V or more and 3 V or less. The area occupied by the high voltage transistor is about 100 times the area occupied by the low voltage transistor. The channel length of the high voltage transistor is, for example, about 1.5 to 2 μm.

A row decoder/driver circuit, for example, is formed in the first circuit region 320 . The row decoder/driver circuit is a circuit used when writing data to the 3D NAND memory cell array 310, and includes transistors forming a transfer transistor group Tr4, which will be described later. Each transistor constituting the transfer transistor group Tr4 is a high voltage transistor.

A charge pump circuit, for example, is formed in the first circuit region 320 . A charge pump circuit is a circuit that boosts an input voltage by connecting capacitors and diodes in multiple stages, and can boost 3.3V to 20V, for example. A high voltage transistor can be used as the diode.

In the semiconductor device 1 , in addition to the row decoder/driver circuit and the charge pump circuit, if a circuit using high-voltage transistors is required, it is formed in the first circuit region 320 .

The semiconductor chip ₃₀₅ is a second semiconductor chip stacked on the semiconductor chip ₃₀₄ , which is the first semiconductor chip in the uppermost layer. The semiconductor chip ₃₀₅ is a CMOS chip and has a second circuit area. The semiconductor chip ₃₀₅ has a semiconductor substrate, and the second circuit region includes a CMOS circuit formed on the semiconductor substrate, wiring connected to the CMOS circuit, an insulating layer, and the like. The second circuit area of the semiconductor chip ₃₀₅ does not include high-voltage transistors, but includes low-voltage transistors. In other words, the transistors formed on the semiconductor chip ₃₀₅ are only low-voltage transistors.

The semiconductor chip 30 ₅ is electrically connected to the semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ and 30 ₄ to each other. A page buffer circuit, for example, is formed in the second circuit region of the semiconductor chip ₃₀₅ . Also, in the second circuit region of the semiconductor chip ₃₀₅ , for example, a timing generation circuit is formed. Various circuits can be formed in the second circuit region of the semiconductor chip ₃₀₅ without using high-voltage transistors.

In the semiconductor device 1, it suffices that two or more layers of first semiconductor chips and one or more layers of second semiconductor chips are stacked, and the stacking position of the semiconductor chip ₃₀₅ , which is the second semiconductor chip, is not limited. . FIG. 1A shows an example in which the semiconductor device 1 includes a second semiconductor chip (semiconductor chip 30 ₅ ) stacked on the uppermost first semiconductor chip. For example, as shown in FIG. 1B, the semiconductor device 1 , a second semiconductor chip (semiconductor chip 30 ₅ ) arranged in the bottom layer. Alternatively, as shown in FIG. 1C, the semiconductor device 1 may include a second semiconductor chip (semiconductor chip 30 ₅ ) stacked between the first semiconductor chips.

Or you may combine these. For example, the semiconductor device 1 may include a second semiconductor chip stacked on the first semiconductor chip in the uppermost layer and a second semiconductor chip arranged in the lowermost layer. Alternatively, two or more layers of the second semiconductor chip may be continuously stacked. Alternatively, two or more second semiconductor chips having an area smaller than that of the first semiconductor chip may be arranged side by side on the same layer.

FIG. 2 is a schematic cross-sectional view illustrating the main parts of the 3D-NAND memory cell array and the first circuit region. FIG. 3 is a diagram exemplifying electrical connections between the 3D NAND memory cell array and main parts of the first circuit region.

As shown in FIGS. 2 and 3, the 3D NAND memory cell array 310 includes a plurality of cell strings CS arranged in a matrix, for example.

As shown in FIG. 3, each cell string CS includes a plurality of transistors connected in series between a bit line BL and a source line SL. For example, a selection transistor Tr1 connected to the bit line BL and a selection transistor Tr2 connected to the source line SL are arranged. 2 n (for example, 64) memory cell transistors Tr3 are connected in series between the select transistor Tr1 and the select transistor Tr2. The selection transistor Tr1, the memory cell transistor Tr3, and the selection transistor Tr2 are connected by a cell pillar CP (through electrode) shown in FIG.

A dummy cell may be arranged between the select transistor Tr1 and the select transistor Tr2. For example, several dummy cells, 2 n (for example, 64) memory cell transistors Tr3, and several dummy cells can be connected in series between the select transistor Tr1 and the select transistor Tr2. When the NAND memory cells are rewritten, the NAND memory cells near the bit line and source line are affected by hot electrons generated by the high voltage. By providing a dummy cell having the same structure as the NAND memory cell, which is not used as a memory element, the influence of hot electrons on the NAND memory cell can be reduced.

As shown in FIGS. 2 and 3, the 3D NAND memory cell array 310 includes select gate lines SGD, word lines WL, and select gate lines SGS. The select gate line SGD, the word line WL, and the select gate line SGS are, for example, plates that are arranged substantially parallel with a predetermined interval via an insulating layer. The word lines WL are stacked at predetermined intervals between the select gate lines SGS and SGD. The number of stacked word lines WL is the same as the number of memory cell transistors Tr3, which is 2 n (for example, 64).

As shown in FIG. 3, the first circuit region 320 is provided with a transfer transistor group Tr4 including a plurality of transistors. The transfer transistor group Tr4 is part of the row decoder/driver circuit. Each transistor constituting the transfer transistor group Tr4 is, for example, an N-type MOS transistor, and the gate electrodes of each transistor are connected to each other. Also, the drain or source of each transistor is connected to the select gate line SGD, word line WL, and select gate line SGS of the 3D NAND memory cell array 310 . The selection transistor Tr1 is controlled by a signal on the selection gate line SGD. The selection transistor Tr2 is controlled by a signal on the selection gate line SGS. Each memory transistor Tr3 is controlled by a signal on each word line WL.

Thus, in the semiconductor device 1, the 3D-NAND memory cell array 310 and the first circuit region 320 are arranged within the same chip. The first circuit region 320 includes high-voltage transistors and does not include low-voltage transistors. On the other hand, in the semiconductor device 1, the second circuit region including the low-voltage transistor and not including the high-voltage transistor is provided in the semiconductor chip ₃₀₅ of the uppermost layer.

That is, in the semiconductor device 1, the second circuit region including the low-voltage transistor and not including the high-voltage transistor is integrated in one chip (semiconductor chip 30 ₅ ) separate from the chip including the 3D NAND memory cell array 310. . As a result, since transistors with different design rules are not mixed, the semiconductor chip ₃₀₅ can be manufactured by a simple process at low cost. In addition, since the semiconductor chip ₃₀₅ does not include high-voltage transistors with a large area, a large number of low-voltage transistors can be laid out easily.

In addition, in the semiconductor device 1, since the high voltage transistors of the row decoder/driver circuit are arranged in the same chip as each chip including the 3D NAND memory cell array 310, the word line WL does not have to be routed long. An increase in the wiring load capacitance of the word line WL can be suppressed. As a result, high-speed operation of the semiconductor device 1 becomes possible. Further, even if the number of stacked chips including the 3D NAND memory cell array 310 is increased, routing of the word lines WL does not become difficult.

In the semiconductor device 1 , the high voltage transistors of the row decoder driver circuit are arranged in the same chip as each chip including the 3D NAND memory cell array 310 . Therefore, even if the number of stacked chips including the 3D NAND memory cell array 310 is increased, it is not necessary to share the word lines among a plurality of chips including the 3D NAND memory cell arrays. As a result, an increase in block size can be suppressed. In addition, since an increase in block size can be suppressed, the number of bits that need to be rewritten at one time does not increase, so the data rewrite time does not become long. That is, in the semiconductor device 1, even if the capacity of the memory is increased, the data rewrite time does not become long.

In addition, since the high voltage transistors of the charge pump circuit are arranged in the same chip as each chip including the 3D NAND memory cell array 310, the wiring of the charge pump circuit does not need to be routed. An increase in load capacity can be suppressed.

[Connection structure between semiconductor chips]
FIG. 4 is a cross-sectional view illustrating the semiconductor device according to the first embodiment, and schematically shows the semiconductor device 1 shown in FIG. 1A, etc., with a focus on through-wiring for connecting chips.

As shown in FIG. 4, the semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ , 30 ₄ , and 30 ₅ are sequentially stacked with their electrode pad formation sides facing in the same direction. It has a structure in which chips are directly electrically connected to each other. Although the semiconductor chips are connected without bumps in FIG. 4, they may be connected via bumps.

The semiconductor chip ₃₀₁ has a body 31 , a semiconductor integrated circuit 32 and electrode pads 33 . Each of the semiconductor chips 30 ₂ , 30 ₃ , 30 ₄ and 30 ₅ has a body 31 , a semiconductor integrated circuit 32 , electrode pads 33 , an insulating layer 36 and through electrodes 37 . The semiconductor integrated circuit 32 of each of the semiconductor chips 30 ₁ , 30 ₂ , 30 ₃ and 30 ₄ includes the 3D NAND memory cell array 310 and the first circuit region 320 shown in FIG. 1A. The semiconductor integrated circuit 32 of the semiconductor chip ₃₀₅ also includes the second circuit region shown in FIG. 1A. The thickness of each of the semiconductor chips 30 ₂ , 30 ₃ , 30 ₄ and 30 ₅ can be, for example, about 5 μm to 15 μm. The thickness of the semiconductor chip ₃₀₁ can be determined appropriately.

In the semiconductor chips 30 ₁ to 30 ₅ , the main body 31 is made of silicon, gallium nitride, silicon carbide, or the like. The semiconductor integrated circuit 32 includes diffusion layers (not shown), insulating layers (not shown), via holes (not shown), wiring layers (not shown), etc. formed on silicon, gallium nitride, silicon carbide, or the like. and is provided on one side of the main body 31 .

The electrode pad 33 is provided on the upper surface side of the semiconductor integrated circuit 32 via an insulating film (silicon oxide film, etc.) not shown. The electrode pads 33 are electrically connected to wiring layers (not shown) provided in the semiconductor integrated circuit 32 . The planar shape of the electrode pad 33 can be, for example, rectangular or circular. When the planar shape of the electrode pad 33 is circular, the diameter of the electrode pad 33 can be, for example, about 1 μm to 10 μm. The pitch of the electrode pads 33 can be, for example, about 2 μm to 20 μm.

As the electrode pad 33, for example, a layered body in which an Au layer, an Al layer, a Cu layer, or the like is layered on a Ti layer or a TiN layer can be used. As the electrode pad 33, a laminate obtained by laminating an Au layer on a Ni layer, a laminate obtained by sequentially laminating a Pd layer and an Au layer on a Ni layer, and a high-melting-point metal such as Co, Ta, Ti, TiN instead of Ni. A layered body in which a Cu layer or an Al layer is stacked on the same layer, or a wiring having a damascene structure may be used.

In the semiconductor chips 30 ₂ to 30 ₅ , an insulating layer serving as a barrier layer may be provided on the back surface of the main body 31 . In this case, for example, SiO ₂ , SiON, Si ₃ N ₄ or the like can be used as the material of the insulating layer. The thickness of the insulating layer can be, for example, about 0.05 μm to 0.5 μm. By forming an insulating layer (barrier layer) on the back side of the main body 31 of the semiconductor chips 30 ₁ to 30 ₅ , it is possible to reduce the risk of contamination of the semiconductor chips with metal impurities from the back side and to prevent the semiconductor chips from being placed in the lower layer. When placed, it can be insulated from the underlying semiconductor chip.

The vertically adjacent semiconductor chips are directly bonded without, for example, an adhesive layer or the like, but if necessary (for example, when the surface of the semiconductor integrated circuit 32 is not flat, etc.), an adhesive layer or the like may be interposed. . In each semiconductor chip except the bottom layer, a via hole is formed which penetrates through each semiconductor chip except the bottom layer and exposes the upper surface of the electrode pad 33 of the semiconductor chip ₃₀₁ serving as a base. is provided with an insulating layer 36 . As a material _of the insulating layer 36, for example, _SiO2 , SiON, _Si3N4 , or the like can be used. The thickness of the insulating layer 36 can be, for example, about 0.05 μm to 0.5 μm. A through electrode 37 is filled in the via hole so as to be in contact with the insulating layer 36 . Also, if an insulating layer is previously embedded in the main body 31 and the diameter of this insulating layer is larger than the diameter of the through electrode 37, the insulating layer 36 may not be used.

The planar shape of the through electrode 37 located in the insulating layer 36 is, for example, circular or polygonal. When the penetrating electrode 37 located in the insulating layer 36 has a circular planar shape, its diameter can be, for example, about 0.5 μm to 5 μm. The planar shape of the through electrode 37 located on the electrode pad 33 is, for example, circular or polygonal. When the through electrode 37 located on the electrode pad 33 has a circular planar shape, its diameter is, for example, the same as the diameter of the through electrode 37 located within the insulating layer 36, or for example, within the insulating layer 36. It can be made about 0.5 μm to 2 μm larger than the diameter of the through electrode 37 located there. The pitch of the through electrodes 37 can be, for example, about 1 μm to 12 μm. Since a plurality of through electrodes 37 may be provided in one electrode pad, the pitch of the through electrodes 37 can be made smaller than the pitch of the electrode pads.

The material of the through electrode 37 is copper, for example. The through electrode 37 may have a structure in which a plurality of metals are laminated. Specifically, for example, as the through electrode 37, a laminate obtained by laminating an Au layer, an Al layer, a Cu layer, or the like on a Ti layer or a TiN layer can be used. As the through electrode 37, a laminate obtained by laminating an Au layer on a Ni layer, a laminate obtained by sequentially laminating a Pd layer and an Au layer on a Ni layer, and a refractory metal such as Co, Ta, Ti, and TiN instead of Ni. A layered body in which a Cu layer or an Al layer is stacked on the same layer, or a wiring having a damascene structure may be used.

In this manner, the electrode pads 33 of the respective semiconductor chips are electrically connected to each other through the through electrodes 37 formed on the upper surfaces of the electrode pads 33 and further formed in the via holes with the insulating layer 36 interposed therebetween. . The electrode pad 33 and the portion of the through electrode 37 formed on the upper surface of the electrode pad 33 may be collectively referred to simply as the electrode pad. Further, the electrode pad 33 is connected to a transistor included in the semiconductor integrated circuit 32, and when the density of the through electrode 37 should be uniform in terms of processing of the through electrode 37, especially the transistor and the It can be installed even if there is no conduction between the upper and lower substrates. That is, there may be isolated electrode pads 33 and through electrodes 37 that are not electrically connected. Due to the presence of the isolated electrode pads 33 and through electrodes 37, heat dissipation can be improved.

Whether or not to form the electrode pads 33 connected to the transistors in the semiconductor chips 30 ₁ to 30 ₅ can be arbitrarily determined according to the specifications. Thereby, the through electrode 37 can be connected only to a desired semiconductor chip among the stacked semiconductor chips. For example, the same signal can pass through the semiconductor chip on the third layer and be supplied to the semiconductor chip on the fourth layer or the semiconductor chip on the second layer, or different signals or power can be supplied to the semiconductor chips on each layer.

[Lamination process of semiconductor chips]
Here, the manufacturing process of the semiconductor device 1 will be described by focusing on the stacking process of the semiconductor chips. However, the stacking process described here is just an example, and semiconductor chips may be stacked by other methods.

5 to 13 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. First, in the steps shown in FIGS. 5 and 6, an unthinned semiconductor substrate 30A is prepared. 5 is a plan view, and FIG. 6 is a sectional view. A plurality of product areas A and scribe areas B separating the product areas A are defined on the semiconductor substrate 30A. The product areas A are arranged vertically and horizontally, for example. C in the scribe area B indicates a position where the dicing blade or the like cuts the semiconductor substrate 30A (hereinafter referred to as "cutting position C"). Each product region A of the semiconductor substrate 30A becomes a semiconductor chip ₃₀₁ when singulated. The semiconductor substrate 30A has the main body 31 described with reference to FIG. 4, the semiconductor integrated circuit 32, and the electrode pads 33 (see FIG. 11), but the illustration of the electrode pads 33 is omitted here. ing.

Here, as an example, the semiconductor substrate 30A is assumed to be a silicon wafer. The semiconductor substrate 30A is circular, for example, and has a diameter φ1 of, for example, 6 inches (approximately 150 mm), 8 inches (approximately 200 mm), 12 inches (approximately 300 mm), or the like. The thickness of the semiconductor substrate 30A is, for example, 0.625 mm (when φ1=6 inches), 0.725 mm (when φ1=8 inches), and 0.775 mm (when φ1=12 inches).

Next, in the process shown in FIG. 7, a semiconductor substrate 30B having the same structure as the semiconductor substrate 30A is prepared, and a substrate 510 is bonded to the electrode pad forming side of the semiconductor substrate 30B via an adhesive layer 520. Next, as shown in FIG. As the substrate 510, a substrate that transmits light during alignment is preferably used, and for example, a quartz glass substrate or the like can be used. As the adhesive layer 520, for example, an adhesive that softens at a heating temperature (an adhesive that softens at about 200° C. or below) can be used in the process shown in FIG. The adhesive layer 520 can be formed on one surface of the substrate 510 by spin coating, for example. The adhesive layer 520 may be formed on one surface of the substrate 510 by using a method of attaching a film adhesive instead of the spin coating method.

Next, in the process shown in FIG. 8, the back side of the semiconductor substrate 30B is partially ground by a grinder or the like to thin the back side of the semiconductor substrate 30B. Then, an insulating layer may be formed on the back side of the thinned semiconductor substrate 30B by plasma CVD or the like. The thickness of the semiconductor substrate 30B after thinning can be, for example, about 5 μm to 15 μm. By setting the thickness of the semiconductor substrate 30B to about 5 μm to 15 μm, the processing time for via holes is greatly shortened, the aspect ratio is relaxed by thinning, and the embedding property and coverage are improved.

Next, in the process shown in FIG. 9, the back side of the semiconductor substrate 30B faces the electrode pad formation side of the semiconductor substrate 30A, and the semiconductor substrate 30B bonded to the substrate 510 is laminated on the semiconductor substrate 30A. The semiconductor substrate 30A and the semiconductor substrate 30B are bonded using, for example, surface activated bonding (SAB) if the semiconductor substrate 30A is flat, and thermosetting resin if the surface of the semiconductor substrate 30A is uneven. can. The thickness of the thermosetting resin can be changed according to the unevenness (step). For example, a thermosetting resin with a thickness of 2 to 5 μm can be used for a step of 1 μm.

Next, in the process shown in FIG. 10, the substrate 510 and the adhesive layer 520 shown in FIG. 9 are removed. As described above, as the adhesive layer 520, it is preferable to use an adhesive that softens at the temperature to be heated in the process shown in FIG. In the process shown in FIG. 10, a laminated body of the semiconductor substrate 30B and the semiconductor substrate 30A shown enlarged in FIG. 11 is formed. 11 to 13 below, description will be made with reference to one section of the product area A shown in FIGS. 5 and 6. FIG.

Next, in the process shown in FIG. 12, a via hole 30x is formed, an insulating layer 36 covering the inner wall surface of the via hole 30x is formed, and a through electrode 37 is formed in the via hole 30x.

The via holes 30x are formed so as to penetrate the electrode pads 33 of the semiconductor substrate 30B, the semiconductor integrated circuit 32, and the main body 31 and expose the surfaces of the electrode pads 33 of the semiconductor substrate 30A. The via hole 30x can be formed by dry etching or the like, for example. The via hole 30x is, for example, circular in plan view, and its diameter can be, for example, about 0.5 μm to 5 μm.

The insulating layer 36 is formed by forming an insulating layer continuously covering the inner wall surface of the via hole 30x and the upper surface of the electrode pad 33 exposed in the via hole 30x by, for example, a plasma CVD method or the like, thereby covering the inner wall surface of the via hole 30x. It can be formed by removing the portion other than the portion to be covered by RIE (Reactive Ion Etching) or the like. Also, if an insulating layer is previously embedded in the main body 31 and the diameter of this insulating layer is larger than the diameter of the through electrode 37, the insulating layer 36 may not be used.

The through electrode 37 can be formed in the via hole 30x by combining, for example, a sputtering method and a plating method. Specifically, for example, a metal such as Cu is formed into a film of about 200 nm to 500 nm by sputtering so as to continuously cover the inner wall surface of the via hole 30x and the upper surface of the electrode pad 33 exposed in the via hole 30x, and power is supplied. form a layer. Then, the inside of the via hole 30x is filled with a metal such as Cu by an electroplating method in which power is supplied via the power supply layer, thereby forming an electroplating layer protruding from the upper surface of the main body 31 . Then, the electrolytic plated layer protruding from the upper surface of the main body 31 is removed by CMP or the like. The upper surface of the electroplated layer filled in the via hole 30x and the upper surface of the main body 31 can be flush with each other, for example. As a result, the through electrode 37 can be formed by stacking the electroplated layer on the power supply layer.

Next, in the process shown in FIG. 13, the same processes as those shown in FIGS. 5 to 12 are repeated. That is, the semiconductor substrate 30C is laminated on the semiconductor substrate 30B. Then, the via hole 30x, the insulating layer 36, and the through electrode 37 are formed in the semiconductor substrate 30C, and the electrode pad 33 of the semiconductor substrate 30C is connected to the through electrode 37 of the semiconductor substrate 30B via the through electrode 37 of the semiconductor substrate 30C. electrically connected to the Further, a semiconductor substrate 30D is laminated on the semiconductor substrate 30C. Then, the via hole 30x, the insulating layer 36, and the through electrode 37 are formed in the semiconductor substrate 30D, and the electrode pad 33 of the semiconductor substrate 30D is connected to the through electrode 37 of the semiconductor substrate 30C via the through electrode 37 of the semiconductor substrate 30D. electrically connected to the Furthermore, the semiconductor substrate 30E is laminated on the semiconductor substrate 30D. Then, the via hole 30x, the insulating layer 36, and the through electrode 37 are formed in the semiconductor substrate 30E, and the electrode pad 33 of the semiconductor substrate 30E is connected to the through electrode 37 of the semiconductor substrate 30D via the through electrode 37 of the semiconductor substrate 30E. electrically connected to the

Through the above steps, the semiconductor substrates 30A to 30E, on which a plurality of product regions to be semiconductor chips are defined, are stacked with the electrode pad formation sides facing in the same direction, and substrates of different layers are directly connected to each other via the through electrodes 37. An electrically connected structure is created. In FIG. 13, it is also possible to further increase the number of stacked semiconductor chips. After that, the structure shown in FIG. 13 is cut at the cutting position C to singulate each product region, thereby completing a plurality of semiconductor devices 1 .

According to the chip stacking process described above, it is possible to easily increase the number of stacked semiconductor chips including the 3D-NAND memory cell array 310 and the first circuit region 320, and to cope with an increase in memory capacity. For example, in the semiconductor device 1 as a whole, the word lines WL can have 128 layers, 256 layers, or more than 256 layers.

[Application example of the semiconductor device 1]
FIG. 14 is a schematic diagram showing an application example of the semiconductor device according to the first embodiment. A semiconductor device 2 shown in FIG. 14 has an image sensor 40 , an A/D converter 50 , a RAM 60 and a ROM 70 .

In the semiconductor device 2, image data is input to the image sensor 40 (CCD sensor, CMOS sensor, etc.) as XY two-dimensional surface data. Directly below each pixel device of the image sensor 40, an A/D converter 50 for converting analog data of light amounts of the three primary colors of red, green, and blue into digital data is arranged. A RAM 60 is connected directly below the A/D converter 50 . The RAM 60 is, for example, an SRAM, but may be a DRAM. The SRAM stores the digitally converted light amount data. A ROM 70 is connected directly below the RAM 60 . The ROM 70 is, for example, a 3D NAND type flash memory device. That is, the semiconductor device 1 can be used as the ROM 70 .

By adopting the configuration shown in FIG. 14, image data can be stored in the ROM 70, which is a non-volatile memory, via the image sensor 40, the A/D converter 50, and the SRAM 60 while the image data is captured as plane data. . In addition, by using the semiconductor device 1 that can easily increase the capacity of the memory as the ROM 70, it is possible to store a large amount of data.

There are various uses as application examples of the semiconductor device 2 . For example, in sports, all data (Raw Data) of a 100m race such as the Olympics can be stored in the ROM 70, which is a non-volatile memory. Alternatively, as an application to medicine, when a single scan of MRI or CT is performed, the data of any part scanned can be output from the ROM 70, which is a non-volatile memory, as clear photographic data. Therefore, capturing the image data in terms of planes and storing them as plane data in the ROM 70, which is a non-volatile memory, without performing parallel to serial conversion, is not only useful for cultural development, but also for the development of science and technology. can make a big contribution to

Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments and the like without departing from the scope of the claims. can be added.

For example, in the above-described embodiments, a case where a semiconductor substrate (silicon wafer) having a circular shape in plan view is used has been described as an example, but the semiconductor substrate is not limited to a circular shape in plan view. You can use things.

Reference Signs List 1, 2 semiconductor device 30 ₁ , 30 ₂ , 30 ₃ , 30 ₄ , 30 ₅ semiconductor chip 30A, 30B, 30C, 30D, 30E semiconductor substrate 30x via hole 31 main body 32 semiconductor integrated circuit 33 electrode pad 36 insulating layer 37 through electrode 40 Image sensor 50 A/D converter 60 RAM
70 ROMs
310 3D NAND memory cell array 320 first circuit region 510 substrate 520 adhesion layer

Claims (14)

two or more layers of first semiconductor chips and one or more layers of second semiconductor chips are stacked,
each of the first semiconductor chips includes a storage area and a first circuit area;
the second semiconductor chip includes a second circuit area,
the first circuit region includes a high-voltage transistor with a withstand voltage of 15 V or more and 25 V or less, and does not include a low-voltage transistor with a withstand voltage of 0.05 V or more and 3 V or less;
The semiconductor device, wherein the second circuit region does not include a high withstand voltage transistor having a withstand voltage of 15 V or more and 25 V or less, and includes a low withstand voltage transistor having a withstand voltage of 0.05 V or more and 3 V or less. 2. The semiconductor device according to claim 1, further comprising said second semiconductor chip stacked on said first semiconductor chip in an uppermost layer. 3. The semiconductor device according to claim 1, comprising said second semiconductor chip arranged in the bottom layer. 4. The semiconductor device according to claim 1, comprising said second semiconductor chip stacked between said first semiconductor chips. 5. The semiconductor device according to any one of claims 1 to 4, wherein said storage area of each of said first semiconductor chips is composed of a 3D NAND memory cell array. each of the first semiconductor chips having a semiconductor substrate;
6. The semiconductor device according to claim 1, wherein said first circuit region of each said first semiconductor chip includes a CMOS circuit formed on said semiconductor substrate. 7. The semiconductor device according to claim 1, wherein said first circuit region is arranged below said memory region. The second semiconductor chip has a semiconductor substrate,
8. The semiconductor device according to claim 1, wherein said second circuit region includes a CMOS circuit formed on said semiconductor substrate. 9. The semiconductor device according to claim 1, wherein a row decoder/driver circuit is formed in said first circuit region. 10. The semiconductor device according to claim 1, wherein a charge pump circuit is formed in said first circuit region. 11. The semiconductor device according to claim 1, wherein a page buffer circuit is formed in said second circuit region. 12. The semiconductor device according to claim 1, wherein a timing generation circuit is formed in said second circuit region. 2. The first semiconductor chips are stacked with their electrode pad forming sides directed in the same direction, and the first semiconductor chips in different layers are directly and electrically connected to each other via through electrodes. 13. The semiconductor device according to any one of items 1 to 12. 14. The first semiconductor chip and the second semiconductor chip according to any one of claims 1 to 13, wherein the first semiconductor chip and the second semiconductor chip are stacked with their electrode pad forming sides directed in the same direction, and are directly and electrically connected via through electrodes. 10. The semiconductor device according to claim 1.

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