JP2023044599A - Integrated circuit and power supply circuit - Google Patents

Abstract

An integrated circuit and a power supply circuit capable of improving the power factor in the power supply circuit are provided.
In an AC-DC converter comprising an inductor to which a rectified voltage corresponding to an AC voltage is applied and a transistor for controlling the inductor current, a power factor correction IC for controlling switching of the transistor is provided, a first command value output circuit for turning on the transistor for a first period based on the difference between the corresponding first voltage and the reference voltage; an on-signal output circuit, a delay circuit that delays the on-signal for a predetermined period, and a second command value Vc2 for correcting the first command value Vc1 and turning on the transistor for a second period longer than the first period. A correction circuit and a drive circuit for turning on the transistor based on the delayed on-signal Son2 and turning off the transistor based on the second command value are provided.
[Selection drawing] Fig. 8

Description

The present invention relates to integrated circuits and power supply circuits.

As a power supply circuit, a power factor correction circuit (hereinafter referred to as a PFC (Power Factor Correction) circuit) that turns on a transistor after a predetermined period of time after an inductor current becomes zero is known (for example, Patent Documents 1 to 3).

JP 2008-199896 A U.S. Pat. No. 7,116,090 JP 2017-28778 A

In general, an integrated circuit that controls switching of transistors in a power factor correction circuit turns on the transistors at a timing when the voltage applied to the transistors is reduced after the inductor current becomes zero in order to reduce switching loss.

By the way, when the integrated circuit turns on the transistor after a predetermined period of time after the inductor current becomes zero, the switching loss is reduced, but the inductor current becomes negative, which deteriorates the power factor in the power supply circuit. There is

SUMMARY OF THE INVENTION The present invention has been made in view of the conventional problems as described above, and provides an integrated circuit and a power supply circuit capable of improving the power factor of the power supply circuit.

In order to solve the above-described problems, a first aspect of the present invention includes an inductor to which a rectified voltage corresponding to an alternating voltage is applied; and a transistor that controls an inductor current flowing through the inductor. an integrated circuit for controlling switching of the transistor of a power supply circuit for generating an output voltage of a target level from a first command value output circuit for outputting a first command value for turning on a period of time; and an on signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off. an on-signal output circuit, a delay circuit for delaying the on-signal for a predetermined period, and a second command value for correcting the first command value and outputting it as a second command value for turning on the transistor for a second period longer than the first period. and a driving circuit for turning on the transistor based on the delayed on signal and turning off the transistor based on the second command value. The correction circuit adjusts the first inductor current based on the ratio based on the third period and the second period from when the transistor is turned off until the inductor current reaches the predetermined value, and on the predetermined period. Correct the command value.

A second aspect of the present invention includes an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor that controls an inductor current flowing through the inductor, and generates an output voltage of a target level from the AC voltage. a first command for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage; an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off; a delay circuit for delaying a signal for a predetermined period; a correction circuit for correcting the first command value and outputting it as a second command value for turning on the transistor for a second period longer than the first period; a drive circuit for turning on the transistor based on the on signal and turning off the transistor based on the second command value; the first voltage; the second period; and a period after the transistor is turned off. and a second estimation circuit for estimating the rectified voltage based on a third period until the inductor current reaches the predetermined value. The correction circuit corrects the first command value based on the first voltage, the estimated rectified voltage, and the predetermined period.

In a third aspect of the present invention, there is provided a power supply circuit for generating an output voltage of a target level from an AC voltage, wherein an inductor to which a rectified voltage corresponding to the AC voltage is applied and an inductor current flowing through the inductor are controlled. and an integrated circuit for controlling switching of the transistor. The integrated circuit includes a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage; an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off; a delay circuit for delaying the on-signal for a predetermined period; a correction circuit for correcting the 1 command value and outputting it as a second command value for turning on the transistor for a second period longer than the first period; and turning on the transistor based on the delayed ON signal. and a driving circuit for turning off the transistor based on the second command value. The correction circuit adjusts the first inductor current based on the ratio based on the third period and the second period from when the transistor is turned off until the inductor current reaches the predetermined value, and on the predetermined period. Correct the command value.

In a fourth aspect of the present invention, there is provided a power supply circuit for generating an output voltage of a target level from an AC voltage, wherein an inductor to which a rectified voltage corresponding to the AC voltage is applied and an inductor current flowing through the inductor are controlled. and an integrated circuit for controlling switching of the transistor. The integrated circuit includes a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage; an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off; a delay circuit for delaying the on-signal for a predetermined period; a correction circuit for correcting the 1 command value and outputting it as a second command value for turning on the transistor for a second period longer than the first period; and turning on the transistor based on the delayed ON signal. a drive circuit for turning off the transistor based on the second command value; the first voltage; a third period from when the transistor is turned off until the inductor current reaches the predetermined value; and a second estimation circuit for estimating the rectified voltage based on two periods. The correction circuit corrects the first command value based on the first voltage, the estimated rectified voltage, and the predetermined period.

It is possible to provide an integrated circuit and power supply circuit capable of improving the power factor of the power supply circuit.

It should be noted that the above summary of the invention does not list all the necessary features of the invention. Subcombinations of these feature groups can also be inventions.

An example of a circuit diagram of a general AC-DC converter 10a is shown. An example of the configuration of a general power factor correction IC 35a is shown. 4 shows a conceptual diagram of the relationship among inductor current IL1, drain-source voltage Vds of NMOS transistor 36, and voltage Vo1. FIG. FIG. 10 shows the relationship between the inductor current IL1 and the input current Iin when there is no delay period with respect to the on-signal Son1. FIG. 10 shows the relationship when the inductor current IL1 and the input current Iin are controlled based on the delayed ON signal Son2 with respect to the ON signal Son1; 4 is a conceptual diagram showing the principle of correcting inductor current IL1 by the power factor correction IC according to the embodiment; FIG. 1 shows an example of a circuit diagram of an AC-DC converter 10b according to an embodiment. FIG. An example of the configuration of the power factor improvement IC 35b is shown. An example of the configuration of the correction circuit 64a is shown. 4 is a conceptual diagram of the relationship among inductor current IL2, drain-source voltage Vds of NMOS transistor 36, and voltage Vo2. FIG. An example of the configuration of the power factor improvement IC 35c is shown. An example of the configuration of the correction circuit 64b is shown. 1 shows an example of a circuit diagram of an AC-DC converter 10c according to an embodiment. FIG. An example of the configuration of the power factor improvement IC 35d is shown. An example of the configuration of the correction circuit 64c is shown. An example of the configuration of the power factor improvement IC 35e is shown. An example of the configuration of the power factor improvement IC 35f is shown. An example of the configuration of the power factor correction IC 35g is shown. An example of the configuration of the power factor correction IC 35h is shown. An example of the configuration of the rectified voltage estimating circuit 66a is shown. The operation of the rectified voltage estimating circuit 66a will be described. Main waveforms in the operation of the rectified voltage estimating circuit 66a will be described. An example of the configuration of the correction circuit 64d is shown. An example of the configuration of the rectified voltage estimating circuit 66b is shown. The operation of the rectified voltage estimating circuit 66b will be described. The operation in step S10 will be described. Waveforms for explaining the operation in step S10 are shown. An example of the configuration of the rectified voltage estimating circuit 66c is shown. An example of the configuration of the power factor correction IC 35i is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

In this specification, the term "connection" is used, and "connection" means "electrically connecting" unless otherwise specified. In this specification, with respect to voltages or signals, when the logic level is low, it is referred to as L level, and when the logic level is high, it is referred to as H level.

FIG. 1 shows an example of a circuit diagram of a typical AC-DC converter 10a. The AC-DC converter 10a is a step-up PFC circuit that generates an output voltage Vout of a target level from an AC voltage Vac of a commercial power supply. The output voltage Vout generated by the AC-DC converter 10a is used to drive the load 11.

The load 11 is, for example, a DC-DC converter or an electronic device that operates on a DC voltage.

<<Configuration of AC-DC converter 10a>>
AC-DC converter 10a includes full-wave rectifier circuit 30, capacitors 31 and 32, inductor 33, diode 34, power factor correction IC 35a, NMOS transistor 36, body diode 37, parasitic capacitor 38, and resistors 40-42.

== Input to full-wave rectifier circuit 30 ==
AC power supply 20 is a commercial AC power supply for supplying AC voltage Vac to full-wave rectifier circuit 30 . The AC voltage Vac is, for example, a voltage of 100 to 277 V and a frequency of 50 to 60 Hz.

The inductor 21 is a so-called power supply inductance that the AC power supply 20 has in the current Iin supplied from the AC power supply 20 to the full-wave rectifier circuit 30 . In the drawing, the inductor 21 is shown only on one of the paths connecting the AC power supply 20 and the full-wave rectifier circuit 30, but the power supply inductance on the other is omitted.

Capacitor 22 removes noise from current Iin supplied from AC power supply 20 to full-wave rectifier circuit 30 together with inductor 21 . Inductor 21 and capacitor 22 remove noise from current Iin supplied to full-wave rectifier circuit 30 .

== Configuration from full-wave rectifier circuit 30 to load 11 ==
Full-wave rectifier circuit 30 performs full-wave rectification on the input predetermined AC voltage Vac and outputs the rectified voltage Vr to capacitor 31 and inductor 33 . A rectified voltage Vr corresponding to the AC voltage Vac is applied to the inductor 33 .

Capacitor 31 smoothes rectified voltage Vr supplied from full-wave rectifier circuit 30 .

Capacitor 32 forms a boost chopper circuit together with inductor 33, diode 34 and NMOS transistor 36. FIG. As a result, the charged voltage of the capacitor 32 is boosted to the DC output voltage Vout and supplied to the load 11 .

A power factor improvement IC (Integrated Circuit; IC) 35a improves the power factor of the AC-DC converter 10a while controlling the switching of the NMOS transistor 36 so that the level of the output voltage Vout reaches a target level (eg, 400 V). It is an integrated circuit that

The power factor correction IC 35a includes terminals CS, FB and OUT. The power factor correction IC 35a has terminals other than the terminals CS, FB, and OUT (for example, a power supply terminal, a GND terminal, etc.), but the other terminals are omitted in the figure.

The NMOS transistor 36 is a power transistor for controlling power to the load 11 of the AC-DC converter 10a. NMOS transistor 36 controls inductor current IL1 flowing through inductor 33 .

Although the NMOS transistor 36 is an N-type (Metal Oxide Semiconductor) transistor, it may be a P-type transistor. Also, the NMOS transistor 36 may be another transistor such as a bipolar transistor.

A gate electrode of the NMOS transistor 36 is connected to the terminal OUT and controlled by the voltage Vo1 from the power factor correction IC 35a. NMOS transistor 36 also has a body diode 37 and a parasitic capacitor 38 .

The body diode 37 is a diode formed by a pn junction between the drain and source of the NMOS transistor 36, and is a parasitic diode. Body diode 37 contributes to reverse recovery characteristics. Body diode 37 acts as a parasitic element together with parasitic capacitor 38 when NMOS transistor 36 is turned off.

A parasitic capacitor 38 is a parasitic capacitance between the drain and source of the NMOS transistor 36 . In the AC-DC converter 10a, a parasitic capacitance that resonates with the inductance of the inductor 33 exists in the circuit when the NMOS transistor 36 is turned off. The parasitic capacitor 38 is an example of parasitic capacitance that resonates with the inductance of the inductor 33 .

Resistors 40 and 41 constitute a voltage dividing circuit that divides the output voltage Vout to generate the voltage Vfb. A voltage dividing circuit composed of resistors 40 and 41 applies the divided voltage Vfb as a feedback voltage to the terminal FB of the power factor correction IC 35a.

A resistor 42 is a resistor for detecting the inductor current IL1. A voltage Vcs corresponding to the inductor current IL1 is generated across the resistor 42 . One end of the resistor 42 is connected to the terminal CS of the power factor correction IC 35a.

Note that the AC-DC converter 10a corresponds to a "power supply circuit". The power factor correction IC 35a corresponds to an "integrated circuit". The voltage Vfb corresponds to the "first voltage".

<<Power factor improvement IC35a>>
FIG. 2 shows an example of the configuration of a general power factor improvement IC 35a. The power factor correction IC 35a includes ADCs 50 and 53 (Analog-to-Digital Converter), an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, and terminals CS and FB. , OUT.

ADC 50 converts voltage Vcs corresponding to inductor current IL1 applied to terminal CS into a digital value. Note that the digital value output from the ADC 50 is hereinafter described as the voltage Vcs for convenience.

Based on the voltage Vcs, the on-signal output circuit 51 detects that the inductor current IL1 is almost zero when the inductor current IL1 becomes equal to or less than a predetermined current value I0 (for example, several mA) slightly larger than zero. The on-signal output circuit 51 outputs an on-signal Son1 for turning on the NMOS transistor 36 when the inductor current IL1 becomes substantially zero (hereinafter, "substantially zero" is simply referred to as "0" (zero)). Output. As an example, the ON signal Son1 is an H level pulse signal.

The delay circuit 52 delays the on-signal Son1 by a predetermined period Tzcd and outputs the delayed on-signal Son2. Note that the period Tzcd will be described later.

The ADC 53 converts the voltage Vfb applied to the terminal FB into a digital value and outputs the digital value to the error amplifier circuit 54 . In addition, below, the digital value output from ADC53 is demonstrated as the voltage Vfb for convenience.

Error amplifying circuit 54 compares voltage Vfb and reference voltage Vref and amplifies their error. The error amplification circuit 54 outputs the amplified error to the first command value output circuit 55 .

First command value output circuit 55 outputs first command value Vc1 to drive circuit 56 based on the amplified error (that is, the difference between voltage Vfb and reference voltage Vref). The level of the first command value Vc1 (that is, the length of the period Ton1 in which the NMOS transistor 36 is turned on) is set so that the AC-DC converter 10a outputs the output voltage Vout at the target level.

The drive circuit 56 is a circuit that drives the NMOS transistor 36 based on the ON signal Son2 and the first command value Vc1. Specifically, when the ON signal Son2 is input, the driving circuit 56 outputs the voltage Vo1 at the H level for a period Ton1 corresponding to the first command value Vc1. As a result, the NMOS transistor 36 is turned on.

On the other hand, the driving circuit 56 outputs the L level voltage Vo1 when the period Ton1 corresponding to the first command value Vc1 has passed since the NMOS transistor 36 was turned on. As a result, the NMOS transistor 36 is turned off.

Although the details are omitted for convenience, as an example, the drive circuit 56 includes a circuit that outputs a drive signal for turning on the NMOS transistor 36 and a buffer circuit.

==Main Waveforms in AC-DC Converter 10a==
Here, main waveforms in the AC-DC converter 10a will be described in order to outline the operation of the general AC-DC converter 10a. FIG. 3 shows a conceptual diagram of the relationship between inductor current IL1, drain-source voltage Vds of NMOS transistor 36, and voltage Vo1. Here, it is assumed that the inductor current IL1 decreases to 0 (predetermined value) at time t0 after the NMOS transistor 36 is turned off.

At time t0, when inductor current IL1 decreases to 0, ON signal output circuit 51 in FIG. 2 outputs H level ON signal Son1. After time t0, the inductor current IL1 further decreases and becomes a negative value.

Here, the “positive inductor current IL1” is a current flowing from one end of the inductor 33 to which the full-wave rectifier circuit 30 and the inductor 33 are connected to the other end of the inductor 33 to which the inductor 33 and the NMOS transistor 36 are connected. It refers to the current flowing in the direction of The “negative direction inductor current IL1” refers to a current that flows from the other end of the inductor 33 to the one end of the inductor 33 .

By the way, at time t0, the NMOS transistor 36 is turned off, the inductor current IL1 in the positive direction decreases, and when it becomes 0, the inductor 33 and the parasitic capacitor 38 resonate. As a result, the drain-source voltage Vds of the NMOS transistor 36 decreases, and the inductor current IL1 in the negative direction (that is, the inductor current IL1 with a negative value) flows. In the figure, ILnp indicates the minimum value of the negative inductor current IL1.

Then, at time t1 after the delay period Tzcd has elapsed from time t0, the driving circuit 56 outputs the H-level voltage Vo1 based on the delayed ON signal Son2. Therefore, the NMOS transistor 36 is turned on.

The delay period Tzcd is set to a period from when the drain-source voltage Vds begins to drop until it reaches its lowest level, that is, a half period of the resonance period. As a result, power consumption when the NMOS transistor 36 is turned on can be reduced.

At time t1, the ON signal Son2 delayed by the delay circuit 52 becomes H level. When the NMOS transistor 36 turns on in response to the H-level on-signal Son2, the inductor current IL1 flowing through the inductor 33 increases.

Based on the first command value Vc1, the drive circuit 56 continues to turn on the NMOS transistor 36 from time t1 to time t2 when the period Ton1 elapses. At time t2, inductor current IL2 reaches a maximum value ILp1.

After that, at time t2, drive circuit 56 outputs L-level voltage Vo1. Therefore, the NMOS transistor 36 is turned off.

At time t3, the inductor current IL1 again decreases to zero. Here, the period from the time t2 to the time t3 when the NMOS transistor 36 is turned off until it indicates 0 is called a period Toff1.

Also, the period Ton1 corresponds to the "first period".

== About power factor improvement and dead angle ==
In the AC-DC converter 10a described above, power consumption can be reduced when the NMOS transistor 36 is turned on.

When the drive circuit 56 delays the on-signal Son1 by a predetermined period Tzcd, the inductor 33 carries a negative inductor current IL1 during the delay period Tzcd. During this time, when the NMOS transistor 36 is switched based on the signal So2 delayed by the drive circuit 56, the drain-source voltage Vds becomes lower than before the negative inductor current IL1 starts to flow, so the switching loss of the NMOS transistor 36 is reduced. and lower power consumption.

Also, in this case, the average value of the inductor current IL1 decreases by the amount by which the inductor current IL1 oscillates to the negative side during the period Tzcd. When the inductor current IL1 is low phase, the amplitude of the overall inductor current IL1 is small, so the negative oscillation of the inductor current IL1 contributes significantly to the average value of the inductor current IL1, and the positive contribution of the inductor current IL1 cancel out. This leads to deterioration of the power factor.

Hereinafter, it will be specifically described how the input current Iin in the AC-DC converter changes when there is no delay period and when there is a delay period. FIG. 4 shows the relationship between the inductor current IL1 and the input current Iin when there is no delay period with respect to the ON signal Son1. In the figure, the dashed line indicates the average value of the inductor current IL1.

===If there is no delay period===
Without the delay period, the AC power supply 20 operates in the so-called critical mode because the NMOS transistor 26 is turned on when the inductor current IL1 becomes zero. The period during which the NMOS transistor 26 is turned on is a fixed period corresponding to the target level.

In this case, the peak value of inductor current IL1 changes according to the rectified voltage. As a result, when the average value of the inductor current IL1 (broken line shown in the drawing of the inductor current IL1) is taken, the sinusoidal wave has a positively rectified shape. Note that even in the low phase of the inductor current IL1, the average value is sinusoidal, but the drive circuit 56 will switch when the drain-source voltage of the NMOS transistor 36 is at a high value, so the switching loss becomes larger.

===If there is a delay period===
FIG. 5 shows the relationship when the inductor current IL1 and the input current Iin are controlled based on the delayed ON signal Son2 with respect to the ON signal Son1. What is shown in FIG. 5 is an example of inductor current IL1 and input current Iin in AC-DC converter 10a.

As described with reference to FIG. 3, when the ON signal Son1 is delayed by a predetermined period Tzcd, a negative inductor current IL1 flows through the inductor 33 during the delay period Tzcd.

On the other hand, the positive contribution of the inductor current IL1 becomes smaller, especially at low phases (for example, near 0°). As a result, the negative contribution of the inductor current IL1 during the delay period cancels out the positive contribution of the inductor current IL1 during the period Ton1, and the average value of the inductor current IL1 flowing through the inductor 33 becomes a value close to zero.

An input current Iin input to the full-wave rectifier circuit 30 of FIG. 1 is input in a form drawn by the inductor current IL1. Therefore, in the region where the average value of the inductor current IL1 is near 0, the input current Iin is also near 0. As a result, a region in which the current value is close to 0 is generated in the region where the input current Iin has a low phase.

Thus, in the power factor correction IC, the region where the current value of the input current Iin is close to 0 in the low phase is called a dead angle. The wider the dead angle, the more the current waveform is distorted from a sine wave and the power factor is worse.

FIG. 6 is a conceptual diagram showing the principle of correcting the inductor current IL1 by the power factor correction IC according to the embodiment.

In the figure, IL1 indicates the inductor current related to the AC-DC converter 10a, and IL2 indicates the inductor current after correction by the AC-DC converters 10b and 10c of the embodiment described later with reference to FIGS. 7 and 12. FIG. Vo1 is the voltage applied to the terminal OUT before correction related to the AC-DC converter 10a and the gate electrode of the NMOS transistor 36, and Vo2 is the voltage applied to the terminal OUT and the NMOS transistor after correction by the AC-DC converters 10b and 10c of the embodiment described later. 36 shows the voltage applied to .

As already described with reference to FIG. 3, the delay circuit 52 delays the ON signal Son1 by the period Tzcd and outputs the ON signal Son2. As a result, the drive circuit 56 supplies the L-level voltage Vo1 for the period Tzcd in addition to the period Toff1 to turn off the NMOS transistor 36 .

As a result, the inductor current IL1 becomes lower by the minimum value ILnp, and a dead angle occurs in the input current Iin.

== Principle of improving the power factor while providing a delay period ==
As noted above, setting the delay period causes the inductor current IL1 to go negative. Therefore, if the period Ton2 during which the NMOS transistor 36 is turned on is lengthened in the switching period by the amount that cancels out the negative inductor current IL1, the decrease in the inductor current IL1 can be suppressed as a result.

In the AC-DC converter of the present embodiment, which will be described later, the period Ton during which the drive circuit 56 turns on the NMOS transistor 36 is set to a period Ton2 that is lengthened by the period ΔTon, and a current that cancels the negative swing of the inductor current IL1 is supplied during the period Tzcd. do.

As a result, the AC-DC converter of this embodiment supplies the inductor current IL2 corrected to the positive side so as to cancel out the current applied to the negative side.

In the inductor current IL2 of FIG. 6, the drive circuit 56 turns on the NMOS transistor 36 for a longer period by correcting the period Ton1 to the period Ton2. As a result, inductor current IL2 reaches maximum value ILp2 higher than maximum value ILp1 before correction at time t4.

Here, when the period Ton1 is corrected to the period Ton2, the period Toff is the period from when the NMOS transistor 36 is turned off until the inductor current IL2 indicates zero.

At time t4, the drive circuit 56 turns off the NMOS transistor 36, and the inductor current IL2 reaches 0 at time t5 after a period Toff longer than the period Toff1.

As a result, as the inductor current IL2, the integrated value in which the inductor current IL2 exhibits a negative value during the period Tzcd, the period ΔTon and the period Toff−Toff1 in the period in which the inductor current IL2 exhibits a positive value A current is provided which is canceled by the integral of the incremental inductor current IL2 of .

[Principle 1-1]
When the period Tzcd is the set value, the AC-DC converter of this embodiment derives the period Ton2 as follows. First, when the ON signal Son2 is delayed by a period Tzcd with respect to the ON signal Son1, the decrease value of the current is
ILnp×(2/π)=(Tzcd/L)×(Vout−Vr)×(2/π ² )
is represented by

On the other hand, the correction value ΔTon for the period Ton1 is
ΔTon=(2/π)×(L×ILnp)/Vr
∴ΔTon=(2/π ² )×Tzcd×[(Vout−Vr)/Vr]
is represented by

Also, the voltage ratio (Vout-Vr)/Vr is obtained from the periods Ton2 and Toff by (Vout-Vr)/Vr=Ton2/Toff
is estimated by Therefore, the period Ton2 can be calculated as follows.

First, the voltage ratio (Vout-Vr)/Vr is estimated from the periods Ton2 and Toff.
Ton2/Toff (1)
Next, the correction value ΔTon is calculated based on the ratio of equation (1) and the set value Tzcd.

ΔTon=(2/π ² )×Tzcd×(Ton2/Toff) (2)
A corrected period Ton2 is calculated using the correction value ΔTon in equation (2).

Ton2=Ton1+ΔTon (3)
Accordingly, an appropriate period can be calculated as the period Ton2.

[Principle 1-2]
Compared to principle 1-1, when the voltage Vout is the input value, the following estimated value Vres1 estimated from the periods Ton2 and Toff can be used as the rectified voltage Vr.

Vres1=Vout×[Toff/(Ton2+Toff)] (4)
A voltage ratio based on the voltage Vout and Vres is calculated using the estimated value Vres1 of Equation (4).

(Vout−Vres1)/Vres1 (5)
A correction value ΔTon is calculated based on the ratio of Equation (5) and the set value Tzcd.

ΔTon=(2/π ² )×Tzcd×(Vout−Vres1)/Vres1 (6)
A corrected period Ton2 is calculated using the correction value ΔTon in equation (6).

Ton2=Ton1+ΔTon (7)
Accordingly, an appropriate period can be calculated as the period Ton2.

[Principle 1-3]
Compared with the case of principle 1-2, when the voltages Vout and Vr are input values, the period Ton2 is calculated as follows. First, the voltage ratio is calculated.

(Vout−Vr)/Vr (8)
A correction value ΔTon is calculated based on the ratio of equation (8) and the set value Tzcd.

ΔTon=(2/π ² )×Tzcd×(Vout−Vr)/Vr (9)
A corrected period Ton2 is calculated using the correction value ΔTon in equation (9).

Ton2=Ton1+ΔTon (10)
Accordingly, an appropriate period can be calculated as the period Ton2.

[Principle 2]
The AC-DC converter records in the storage circuit the inductance L of the inductor 33 and the capacitance C of the capacitor (for example, the capacitance of the parasitic capacitor 38) that resonates the inductor currents IL1 and IL2 together with the inductance L of the inductor 33 as known values. , the following values can be used as the period Tzcd.

Tzcd=π×√(L·C) (11)
The period Ton2 can be calculated by using the period Tzcd in Equation (11) and performing calculations similar to Principles 1-1 to 1-3 in accordance with the input voltage and the like.

According to Principles 1-1 to 1-3, an appropriate period Ton2 corresponding to the value of period Tzcd can be calculated without recording the inductance L of the inductor 33 and the capacitance C of the capacitor as known values. Accordingly, the period Ton2 can be appropriately set according to the decrease value of the inductor current IL1.

According to Principle 2, the period Ton2 can be set according to the resonance period of the inductor current IL1 by the inductance L of the inductor 33 and the capacitance C of the capacitor that resonates the inductor current IL1 together with the inductance L. Accordingly, the period Ton2 can be appropriately set according to the decrease value of the inductor current IL1.

Therefore, according to Principles 1-1 and 1-2, the ON period Ton2 of the NMOS transistor 36 can be corrected just enough for the amount of decrease in the inductor current IL2 due to the delay of the ON signal Son1, and the power factor can be reduced. It can be improved. The ON period Ton2 according to the present embodiment can be corrected for each cycle from one ON period of the NMOS transistor 36 to the next ON period.

<<AC-DC converter 10b according to the first embodiment>>
FIG. 7 shows an example of the configuration of the AC-DC converter 10b of this embodiment. It should be noted that the configurations denoted by the same reference numerals as those of the AC-DC converter 10a in FIG. 1 correspond to the same configurations. The following mainly describes the differences between the AC-DC converter 10b and the AC-DC converter 10a.

AC-DC converter 10b includes full-wave rectifier circuit 30, capacitors 31 and 32, inductor 33, diode 34, power factor correction IC 35b, NMOS transistor 36, body diode 37, parasitic capacitor 38, and resistors 40-43. That is, the AC-DC converter 10b differs from the AC-DC converter 10a in that it has a power factor correction IC 35b and a resistor 43. FIG.

Also, the power factor correction IC 35b includes a terminal RT in addition to the terminals CS, FB, and OUT.

One end of the resistor 43 is connected to the terminal RT. The other end of resistor 43 is grounded. A voltage Vrt generated across the resistor 43 is applied to the terminal RT.

The power factor correction IC 35b sets the delay period Tzcd based on the voltage Vrt of the terminal RT, as will be described later with reference to FIGS. Furthermore, the power factor correction IC 35b appropriately sets the ON period of the NMOS transistor 36 based on the delay period Tzcd.

That is, in the power factor correction IC 35b, the period during which the voltage Vo2 applied to the NMOS transistor 36 through the OUT terminal exhibits the high logic level is different from that in the power factor correction IC 35a. As a result, even if the delay period Tzcd is set and the inductor current IL2 shows a negative value, the power factor correction IC 35b corrects the ON period of the NMOS transistor 36 to generate a positive inductor current IL2. period can be compensated. As a result, the power factor can be improved.

The terminal RT corresponds to the "first terminal". The voltage Vrt corresponds to the "second voltage".

<<Power factor correction IC 35b according to the first embodiment>>
FIG. 8 shows an example of the configuration of the power factor improvement IC 35b. In addition, the configurations denoted by the same reference numerals as the configuration of the power factor improving IC 35a in FIG. 2 correspond to the same configurations. In the following, differences from the power factor improvement IC 35a mainly in the configuration of the power factor improvement IC 35b will be described.

The power factor correction IC 35b includes ADCs 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, a current source 61, a delay period setting circuit 62, and a detection circuit 63. , a correction circuit 64a, and terminals CS, FB, OUT, RT. That is, the power factor correction IC 35b includes a terminal RT, a current source 61, a delay period setting circuit 62, a detection circuit 63, and a correction circuit 64a in addition to the configuration of the power factor correction IC 35a.

In this embodiment, the on-signal output circuit 51 outputs the on-signal Son1 to the delay circuit 52 and also outputs the on-signal Son1 to the detection circuit 63 .

Further, the delay circuit 52 outputs the delayed ON signal Son2 to the drive circuit 56, and outputs the data D (Tzcd) of the period Tzcd to the correction circuit 64a.

Further, the drive circuit 56 turns on the NMOS transistor 36 based on the delayed on-signal Son2, and keeps the NMOS transistor 36 on for a period Ton2 based on a second command value Vc2 described later. After that, the drive circuit 56 turns off the NMOS transistor 36 .

The drive circuit 56 of this embodiment supplies the voltage Vo<b>2 to the gate electrode of the NMOS transistor 36 and also to the detection circuit 63 . As will be described later, the detection circuit 63 is used to detect a period Toff that elapses from when the NMOS transistor 36 is turned off until the inductor current IL2 indicates 0 based on the voltage Vo2.

== Current source 61 and delay period setting circuit 62 (delay period setting) ==
Current source 61 is a bias current source that supplies a predetermined current to terminal RT. The current supplied by current source 61 produces a voltage Vrt across resistor 43 that is proportional to the current. Therefore, a voltage Vrt proportional to the current is applied to the terminal RT.

The delay period setting circuit 62 sets the predetermined period Tzcd in the delay circuit 52 based on the voltage Vrt applied to the terminal RT of the delay circuit 52 . That is, in the present embodiment, the period Tzcd is proportional to the resistance value of the resistor 43 and determined based on the voltage Vrt applied to the terminal RT.

On the other hand, a voltage Vrt corresponding to the predetermined period Tzcd is applied to the terminal RT.

==Detection circuit 63 and correction circuit 64a (output of second command value Vc2)==
The detection circuit 63 detects the timing at which the NMOS transistor 36 is turned off based on the voltage Vo2 supplied from the drive circuit 56 . Further, the detection circuit 63 detects the timing at which the inductor current IL2 becomes 0 after the NMOS transistor 36 is turned off, based on the ON signal Son1.

The detection circuit 63 detects the period Toff that elapses from turning off the NMOS transistor 36 to indicating 0 based on the timing at which the NMOS transistor 36 is turned off and the timing at which the inductor current IL2 becomes 0. Further, the detection circuit 63 outputs data D (Toff) corresponding to the period Toff to the correction circuit 64a.

The correction circuit 64a is a circuit that performs correction based on principle 1-1. That is, the correction circuit 64a corrects the first command value Vc1 and outputs it as a second command value Vc2 for turning on the period Ton2 longer than the period Ton1 corresponding to the first command value.

Specifically, the correction circuit 64a corrects the first command value Vc1 based on the data D (Tzcd) relating to the period Tzcd, the first command value Vc1, and the off-period data D (Toff) to obtain the second command value Vc1. Output as command value Vc2.

Further, the correction circuit 64a of the present embodiment has a ratio of the period Toff from when the NMOS transistor 36 is turned off until the inductor current becomes 0 to the period Ton2 based on the second command value Vc2, and the period Tzcd. Based on this, the first command value Vc1 is corrected.

The period Ton2 corresponds to the "second period". Also, the period Toff corresponds to the "third period".

The timing at which the NMOS transistor 36 is turned off corresponds to the "first timing". Also, the timing at which the inductor current IL2 becomes 0 after the NMOS transistor 36 is turned off corresponds to the "second timing".

===Details of Correction Circuit 64a===
The configuration and operation of the correction circuit 64a will be described in more detail below. The correction circuit 64a is a circuit that embodies the correction of the period Ton2 according to Principle 1-1.

FIG. 9 shows an example of the configuration of the correction circuit 64a. The correction circuit 64 a includes an arithmetic circuit 71 , a correction value output circuit 72 and a second command value output circuit 73 .

The arithmetic circuit 71 converts the period Ton2 to the period Toff based on the data D (Toff) corresponding to the period Toff input from the detection circuit 63 and the second command value Vc2 input from the second command value output circuit 73. Calculate the ratio divided by That is, the arithmetic circuit 71 calculates the ratio expressed by Equation (1).

Ton2/Toff (1)
Further, the arithmetic circuit 71 outputs the data D (Ton2/Toff) based on the ratio expressed by Equation (1) to the correction value output circuit 72 .

The correction value output circuit 72 is based on the data D (Tzcd) corresponding to the period Tzcd, the data D (Ton2/Toff), and the constant (2/π ² ) stored in the correction value output circuit 72. , to calculate the correction value ΔTon represented by the equation (2). Specifically, the correction value output circuit 72 calculates the correction value ΔTon for the period Ton1 by multiplying the constant (2/π ² ), the period Tzcd, and the ratio Ton2/Toff.

ΔTon=(2/π ² )×Tzcd×(Ton2/Toff) (2)
Further, the correction value output circuit 72 outputs data D (ΔTon) corresponding to the correction value ΔTon to the second command value output circuit 73 .

The second command value output circuit 73 calculates the period Ton2 represented by Equation (3). Specifically, the second command value output circuit 73 calculates the period Ton2 by correcting the period Ton1 with the correction value ΔTon based on the first command value Vc1 corresponding to the period Ton1 and the correction value ΔTon.

Ton2=Ton1+ΔTon (3)
Furthermore, the second command value output circuit 73 outputs to the drive circuit 56 a second command value Vc2 corresponding to the period Ton2. The second command value output circuit 73 also outputs the second command value Vc<b>2 to the arithmetic circuit 71 . Thereby, the second command value output circuit 73 can set an appropriate period Ton2 for the drive circuit 56 .

Note that the arithmetic circuit 71 corresponds to the "first arithmetic circuit".

<<Main waveforms in the AC-DC converter according to the embodiment>>
Here, main waveforms in the AC-DC converter 10a will be described in order to outline the operation of the AC-DC converter 10b according to the embodiment. FIG. 10 is a conceptual diagram of the relationship among inductor current IL2, drain-source voltage Vds of NMOS transistor 36, and voltage Vo2.

Corresponding to FIG. 3, it is assumed that the inductor current IL2 decreases to 0 at time t10 after the NMOS transistor 36 is turned off.

At time t10, when the inductor current IL2 decreases to 0, the on-signal output circuit 51 of FIG. 8 outputs an H-level on-signal Son1. After time t10, inductor current IL2 further decreases and becomes a negative value.

At time t10, the NMOS transistor 36 is turned off, the inductor current IL2 in the positive direction decreases, and when it becomes 0, resonance occurs in the inductor 33 and the parasitic capacitor 38. FIG. As a result, the drain-source voltage Vds of the NMOS transistor 36 decreases, causing a negative inductor current IL2 to flow.

At time t11 after the delay period Tzcd has elapsed from time t10, the driving circuit 56 outputs the H level voltage Vo2 based on the delayed ON signal Son2. Therefore, the NMOS transistor 36 is turned on.

When the NMOS transistor 36 turns on in response to the H-level on-signal Son2, the inductor current IL2 flowing through the inductor 33 increases.

Then, the driving circuit 56 turns on the NMOS transistor 36 based on the second command value Vc2 obtained by correcting the first command value Vc1 by the correction circuit 64c from the time t11 to the time t13 when the period Ton2=Ton1+ΔTon has passed. continue.

Note that FIG. 10 also shows a time t12 after the period Ton1 has elapsed from the time t11 in order to clarify the period ΔTon. At time t13, inductor current IL2 reaches a maximum value ILp2.

After time t13, the drive circuit 56 outputs the L level voltage Vo2. Therefore, the NMOS transistor 36 is turned off.

Furthermore, at time t14, the inductor current IL2 again decreases to zero. Here, a period Toff elapses from the time t13 to the time t14 when the NMOS transistor 36 is turned off until the inductor current IL2 indicates zero. At time t14, the ON signal output circuit 51 again outputs the H level signal Son1.

As described above, in the AC-DC converter 10b of the embodiment, the NMOS transistor 36 is turned on during the period from time t11 to time t13. This is a period ΔTon longer than the ON period of the NMOS transistor 36 of the AC-DC converter 10a of FIG.

As described above, in the AC-DC converter 10b of the embodiment, the NMOS transistor 36 is turned on for a long period of ΔTon, so that the positive current that cancels the contribution of the negative current value in the inductor current IL2 is ΔTon+(Toff−Toff1 ) for a long period of time. As a result, the period during which the current Iin indicates 0 is reduced, and the dead angle is eliminated.

As a result, the distortion from the sine wave of the waveform of the current Iin is eliminated and the power factor is improved.

<<Power factor correction IC 35c according to the second embodiment>>
FIG. 11 shows a power factor correction IC 35c. In the following, differences from the power factor improvement IC 35a mainly in the configuration of the power factor improvement IC 35b will be described. The power factor correction IC 35c includes a correction circuit 64b.

In the configuration of the AC-DC converter of the power factor correction IC 35c, in the configuration of the AC-DC converter 10b according to FIG. 7, the power factor correction IC 35b is replaced with the power factor correction IC 35c, and the other configurations are the same. . Therefore, the drawing of the AC-DC converter is omitted.

The ADC 53 of this embodiment inputs the converted digital value of the voltage Vfb to the correction circuit 64b.

The correction circuit 64b of this embodiment uses the voltage Vfb as an input value to derive the second command value Vc2.

===Details of Correction Circuit 64b===
Details of the calculation performed by the correction circuit 64b will be described below. The correction circuit 64b is a circuit that embodies the correction of the period Ton2 according to Principle 1-2.

FIG. 12 shows an example of the configuration of the correction circuit 64b. The correction circuit 64 b includes an estimation circuit 81 , an arithmetic circuit 82 , a correction value output circuit 83 and a second command value output circuit 84 .

The estimation circuit 81 calculates an estimated value Vres1 of the rectified voltage Vr represented by Equation (4). Specifically, the estimation circuit 81 calculates the estimated value Vres1 of the rectified voltage Vr based on the data D (Toff) corresponding to the period Toff, the second command value Vc2, and the voltage Vfb corresponding to the voltage Vout. calculate.

Vres1=Vout×[Toff/(Ton2+Toff)] (4)
Also, the estimation circuit 81 outputs an estimated value Vres1 based on the ratio represented by Equation (4) to the arithmetic circuit 82 .

Arithmetic circuit 82 calculates the voltage ratio represented by Equation (5). Specifically, arithmetic circuit 82 calculates a voltage ratio based on voltage Vout and estimated value Vres1 based on voltage Vfb corresponding to voltage Vout and estimated value Vres1.

(Vout−Vres1)/Vres1 (5)
The arithmetic circuit 82 also outputs data D[(Vout−Vres1)/Vres1] corresponding to the voltage ratio to the correction value output circuit 83 .

The correction value output circuit 83 outputs data D (Tzcd) corresponding to the period Tzcd, data D [(Vout−Vres1)/Vres1], and a constant (2/π ² ) stored in the correction value output circuit 83. , the correction value ΔTon represented by the equation (6) is calculated. Specifically, the correction value output circuit 83 multiplies the constant (2/π ² ), the period Tzcd, and the ratio (Vout−Vres1)/Vres1 to calculate the correction value ΔTon for the period Ton1.

ΔTon=(2/π ² )×Tzcd×(Vout−Vres1)/Vres1 (6)
Further, the correction value output circuit 83 outputs data D (ΔTon) corresponding to the correction value ΔTon to the second command value output circuit 84 .

The second command value output circuit 84 calculates the period Ton2 represented by Equation (7). Specifically, the second command value output circuit 84 calculates the period Ton2 by correcting the period Ton1 with the correction value ΔTon based on the first command value Vc1 corresponding to the period Ton1 and the correction value ΔTon.

Ton2=Ton1+ΔTon (7)
Further, the second command value output circuit 84 outputs to the drive circuit 56 a second command value Vc2 corresponding to the period Ton2.

As described above, the correction circuit 64b can also output the second command value Vc2 corrected for the period Ton1. As a result, the waveform of the inductor current IL2 similar to that of FIG. 10 can also be obtained by the power factor correction IC 35c.

Note that the arithmetic circuit 82 corresponds to a "second arithmetic circuit".

<<AC-DC converter 10c according to the third embodiment>>
FIG. 13 shows an example of a circuit diagram of an AC-DC converter 10c according to an embodiment. It should be noted that the structures denoted by the same reference numerals as the structure of the AC-DC converter 10b in FIG. 7 correspond to the same structures. The following mainly describes the differences between the AC-DC converter 10c and the AC-DC converter 10b.

The AC-DC converter 10c includes a power factor correction IC 35d and resistors 44 and 45 in addition to the components of the AC-DC converter 10b. Moreover, the power factor correction IC 35d includes a terminal RDIV in addition to the terminals CS, FB, OUT, and RT of the power factor correction ICs 35b and 35c.

One end of resistor 44 is connected to a node between capacitor 31 and inductor 33 , and the other end is connected to resistor 45 . Resistors 44 and 45 form a voltage dividing circuit that divides the rectified voltage Vr.

A node between resistors 44 and 45 is connected to terminal RDIV. A voltage Vrdiv obtained by dividing the rectified voltage Vr is applied to the terminal RDIV.

Here, the terminal RDIV corresponds to the "second terminal" and the voltage Vrdiv corresponds to the "third voltage".

<<Power factor correction IC 35d according to the third embodiment>>
FIG. 14 shows an example of the configuration of the power factor improvement IC 35d. Power factor correction IC 35 d includes correction circuit 64 c and ADC 65 .

ADC 65 converts voltage Vrdiv corresponding to rectified voltage Vr applied to terminal RDIV into a digital value. For convenience, the digital value output from the ADC 65 will be described below as the voltage Vrdiv. The ADC 65 inputs the digital value Vrdiv to the correction circuit 64c.

===Details of Correction Circuit 64c===
The configuration of the correction circuit 64c will be described in detail below. The correction circuit 64c is a circuit that embodies the correction of the period Ton2 according to Principle 1-3.

FIG. 15 shows an example of the configuration of the correction circuit 64c. Correction circuit 64 c includes arithmetic circuit 91 , correction value output circuit 92 , and second command value output circuit 93 .

Arithmetic circuit 91 calculates the ratio represented by Equation (8). Specifically, arithmetic circuit 91 calculates a voltage ratio based on voltage Vfb corresponding to voltage Vout and voltage Vrdiv corresponding to voltage Vr.

(Vout−Vr)/Vr (8)
The arithmetic circuit 91 also outputs data D[(Vout−Vr)/Vr] corresponding to the voltage ratio to the correction value output circuit 92 .

The correction value output circuit 92 outputs data D(Tzcd) corresponding to the period Tzcd, data D[(Vout−Vr)/Vr], and the constant (2/π ² ) stored in the correction value output circuit 72. , the correction value ΔTon represented by the equation (9) is calculated. Specifically, the correction value output circuit 92 multiplies the constant (2/π ² ), the period Tzcd, and the ratio (Vout−Vr)/Vr to calculate the correction value ΔTon for the period Ton1.

ΔTon=(2/π ² )×Tzcd×(Vout−Vr)/Vr (9)
Further, the correction value output circuit 92 outputs data D (ΔTon) corresponding to the correction value ΔTon to the second command value output circuit 93 .

The second command value output circuit 93 calculates the period Ton2 represented by Equation (10). Specifically, based on the first command value Vc1 corresponding to the period Ton1 input from the first command value output circuit 55 and the correction value ΔTon input from the correction value output circuit 92, the period Ton1 is set to the correction value. A period Ton2 corrected by ΔTon is calculated.

Ton2=Ton1+ΔTon (10)
Further, the second command value output circuit 93 outputs to the drive circuit 56 a second command value Vc2 corresponding to the period Ton2.

As described above, the correction circuit 64c can also output the second command value Vc2 in which the period Ton1 is corrected. As a result, the waveform of the inductor current IL2 similar to that of FIG. 10 can be obtained by the power factor correction IC 35d as well.

Note that the arithmetic circuit 91 corresponds to a "third arithmetic circuit".

<<Power factor correction IC 35e according to embodiment 4>>
FIG. 16 shows an example of the configuration of the power factor improvement IC 35e. The power factor correction IC 35 e includes a memory circuit 95 .

The power factor correction IC 35e includes a memory circuit 95 and has the same configuration as the power factor correction IC 35b except that the terminal RT, the current source 61 and the delay period setting circuit 62 are not included. Although the terminal RT of the power factor improving IC 35b is connected to the resistor 43, the power factor improving IC 35e does not include the terminal RT. 43 is not included.

The storage circuit 95 records the period Tzcd based on the inductance L of the inductor 33 and the capacitance C of the capacitor that resonates the inductor current IL2 together with the inductance L (for example, the capacitance of the parasitic capacitor 38). Based on the inductance L and the capacitance C, the storage circuit 95 records the period Tzcd that satisfies the following equation (11).

Tzcd=π×√(L·C) (11)
Based on the period Tzcd of equation (11), the delay circuit 52 delays the ON signal Son1 and outputs the ON signal Son2. In this embodiment, the correction by the correction circuit 64a is also performed by the same process as the process already described with reference to FIG. 9, based on the data D(Tzcd) corresponding to this period Tzcd. Further, this allows the power factor improvement IC 35e to correct the period Ton2 described in principle 2 of FIG.

In this embodiment, the storage circuit 95 is provided inside the power factor correction IC 35e. Delay circuit 52 is connected to storage circuit 95 .

However, the storage circuit 95 may be a storage device provided outside the power factor improvement IC 35e. In this case, the delay circuit 52 is connected to an external connection terminal (not shown) of the power factor correction IC 35e. An external connection terminal (not shown) is connected to a storage device outside the power factor correction IC 35e.

Note that the memory circuit 95 corresponds to the "first memory circuit".

<<Power factor correction IC 35f according to embodiment 5>>
FIG. 17 shows an example of the configuration of the power factor improvement IC 35f. Power factor correction IC 35 f includes a memory circuit 95 .

Power factor correction IC 35f has a configuration similar to that of power factor correction IC 35c except that it includes storage circuit 95 and does not include terminal RT, current source 61, and delay period setting circuit 62. FIG. Also, the AC-DC converter including the power factor correction IC 35f does not include the resistor 43 either.

The memory circuit 95 sets the period Tzcd that satisfies the equation (11) in the delay circuit 52 .
Tzcd=π×√(L·C) (11)
The delay circuit 52 uses the period Tzcd of equation (11) to output the ON signal Son2 and output the data D(Tzcd) to the correction circuit 64b. Based on this D(Tzcd), the correction circuit 64b outputs the second command value Vc2 through the same process as in FIG. Further, this allows the power factor improvement IC 35f to correct the period Ton2 described in principle 2 of FIG.

The storage circuit 95 of the present embodiment is provided inside the power factor improvement IC 35f, but may be a storage device provided outside the power factor improvement IC 35f.

<<Power factor correction IC 35g according to Example 6>>
FIG. 18 shows an example of the configuration of the power factor correction IC 35g. Power factor correction IC 35 g includes a memory circuit 95 .

The power factor correction IC 35g has a configuration similar to that of the power factor correction IC 35d except that it includes a memory circuit 95 and does not include the terminal RT, the current source 61, and the delay period setting circuit 62. FIG. Also, the AC-DC converter including the power factor correction IC 35g does not include the resistor 43 either.

The memory circuit 95 sets the period Tzcd that satisfies the equation (11) in the delay circuit 52 .
Tzcd=π×√(L·C) (11)
The delay circuit 52 outputs the ON signal Son2 using the period Tzcd of equation (11), and outputs the data D(Tzcd) to the correction circuit 64c. Based on this D(Tzcd), the correction circuit 64c outputs the second command value Vc2 through the same process as in FIG. Further, as a result, the power factor correction IC 35g can correct the period Ton2 described in principle 2 of FIG.

The storage circuit 95 of the present embodiment is provided inside the power factor improvement IC 35g, but may be a storage device provided outside the power factor improvement IC 35g.

In each of the power factor correction ICs 35b to 35g according to the embodiment, after the voltages Vcs, Vfb, Vrdiv are AD-converted by the ADCs 50, 53, 65, processing is performed until the voltage Vo2 is output. Here, in the power factor improvement ICs 35b to 35g, part or all of the processing performed after AD conversion by the ADCs 35, 53, 65 may be executed by software. Specifically, instead of the power factor correction IC 35a, it may be executed by a microcomputer, a DSP having a core and a memory, or the like.

<<Power factor correction IC 35h according to embodiment 7>>
FIG. 19 shows an example of the configuration of the power factor improvement IC 35h. The power factor correction IC 35h is an IC used in the AC-DC converter 10b of FIG. 7, like the power factor correction ICs 35b and 35c.

The power factor correction IC 35h includes ADCs 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, a current source 61, a delay period setting circuit 62, and a detection circuit 63. , a correction circuit 64 d and a rectified voltage estimation circuit 66 . Further, power factor correction IC 35h includes terminals RT, CS, FB, and OUT.

That is, the power factor correction IC 35h has a correction circuit 64d instead of the correction circuit 64b and a rectified voltage estimation circuit 66 in addition to the power factor correction IC 35b of FIG.

A rectified voltage estimation circuit 66 of the power factor improvement IC 35h estimates the rectified voltage Vr by a method different from that of the estimation circuit 81 of the correction circuit 64b of FIG. 12, and outputs an estimated value Vres2. The rectified voltage estimation circuit 66 estimates the rectified voltage Vr based on the voltage Vfb, the period Ton2, and the period Toff from when the NMOS transistor 36 is turned off until the inductor current IL becomes zero.

Further, the correction circuit 64d calculates a correction value ΔTon of the period Ton1 for turning on the NMOS transistor 36 based on the estimated value Vres2 estimated by the rectified voltage estimation circuit 66, and calculates the period Ton1 for turning on the NMOS transistor 36. A command value Vc2 corresponding to Ton2 is output.

Here, the rectified voltage estimating circuit 66 corresponds to a "second estimating circuit".

FIG. 20 shows an example of the configuration of the rectified voltage estimation circuit 66a. The rectified voltage estimation circuit 66a is one of the embodiments of the rectified voltage estimation circuit 66 of FIG.

===Overview of rectified voltage estimation circuit 66a===
Here, the rectified voltage Vr is a voltage obtained by full-wave rectifying the AC voltage Vac from which noise has been removed by the inductor 21 and the capacitor 22 in the AC-DC converter 10b of FIG. The rectified voltage Vr is represented by Vr=|Vrp×sin(ω×t+θ)| by the amplitude Vrp and the waveform sin(ω×t+θ) based on the frequency ω and the phase θ.

By the way, when ω×t+θ is a phase angle close to 180 m degrees (m is an integer), the waveform sin(ω×t+θ) becomes small. For example, when ±10+180 m degrees, the rectified voltage Vr and the input current Iin are "low phase".

In this case, the proportional relationship established between the L output voltage Vout and the rectified voltage Vr of the inductor 33 and the period Ton2 and the period Toff1 may deviate. For example, the resonance between the inductance L of the inductor 33 and the parasitic capacitance of the NMOS transistor 36 or the like may lengthen the period Toff, and the influence of the resonance becomes greater at low phases. As a result, a deviation may occur in relational expressions such as (Vout-Vr)/Vr=Ton2/Toff or Vres1=Vout×[Toff/(Ton2+Toff)].

On the other hand, when ω×t+θ is a phase angle close to 90+180 m, the difference between the relational expressions established between the output voltage Vout and the rectified voltage Vr and the periods Ton2 and Toff1 is small. For example, when 80 to 110+180 m degrees, the rectified voltage Vr and the input current Iin are "high phase".

Therefore, the rectified voltage estimation circuit 66a estimates the amplitude Vrp of the rectified voltage Vr when ω×t+θ is a phase angle close to 90+180 m degrees. In particular, the rectified voltage estimating circuit 66a estimates the amplitude Vrp of Vr when the period Toff indicates the peak value Toffp in the half cycle of the rectified voltage Vr.

The rectified voltage estimation circuit 66a multiplies the amplitude Vrp estimated by Equation (15) by the separately estimated waveform sin(ω×t+θ) at the peak value Toffp of the period Toff. As a result, the rectified voltage estimation circuit 66a can accurately estimate the rectified voltage Vr even when the rectified voltage Vr has a low phase.

===Configuration of rectified voltage estimation circuit 66a===
Rectified voltage estimation circuit 66 a includes peak determination circuit 111 a , amplitude estimation circuit 112 , frequency estimation circuit 113 a , phase output circuit 114 and output circuit 115 .

The peak determination circuit 111a detects the peak value of the period Toff corresponding to the command value Vc2 each time the period Toff reaches a peak, based on the data D (Toff) of the period Toff output by the detection circuit 63 in FIG. . The peak determination circuit 111a also outputs a pulse-like signal θinp that becomes H level each time the period Toff reaches a peak as a determination result.

Note that the peak determination circuit 111a determines, for example, an inflection point at which the time change of the period Toff changes from + to - as a peak.

Amplitude estimation circuit 112 estimates amplitude Vrp of rectified voltage Vr based on voltage Vfb, peak value Toffp, and command value Vc2 corresponding to period Ton2.

Here, when the NMOS transistor 36 is turned on for the period Ton2, the maximum value ILp2 (see FIG. 10) of the inductor current IL2 flowing through the inductor 33 of inductance L and the amplitude Vrp, which is the maximum value of the rectified voltage Vr, is , the relationship of equation (12) is established.
ILp2=(Vrp×Ton2)/L (12)

Furthermore, the NMOS transistor 36 is turned off during the peak value Toffp of the period Toff, and the inductor current IL2 becomes zero.

Here, the higher the phase angle of the rectified voltage Vr and the inductor current IL2, the longer the period Toff from when the NMOS transistor 36 is turned off until the inductor current IL2 becomes zero. For example, when the phase angle is 90 degrees (or 270 degrees, 450 degrees, etc.), the rectified voltage Vr exhibits the maximum amplitude Vrp. At this time, the inductor current IL2 also increases, so the period Toff from when the NMOS transistor 36 is turned off to when it becomes 0 also exhibits the peak value Toffp. Therefore, at the phase angle at which the rectified voltage Vr exhibits the amplitude Vrp, the period Toff also exhibits the peak value Toffp.

In this case, equation (13) holds between the peak value Toffp, the inductance L of the inductor 33, the maximum value ILp2 of the inductor current IL2, the output voltage Vout, and the amplitude Vrp of the rectified voltage Vr.
Toffp=(L×ILp2)/(Vout−Vrp) (13)

Based on equations (12) and (13), amplitude estimation circuit 112 estimates amplitude Vrp assuming that amplitude Vrp satisfies equation (14).
Vrp=Vout/(1+(Ton2/Toffp)) (14)

The frequency estimating circuit 113a estimates the frequency ω of the rectified voltage Vr by counting a period between a plurality of peak values Toffp based on the H level signal θinp. Here, the period between the peak values Toffp is a half cycle Tin corresponding to the phase angle of 180 degrees of the rectified voltage Vr. Although the details will be described later, the frequency estimating circuit 113a can time the half cycle Tin and estimate the frequency ω by the relational expression of frequency ω=2π/2Tin.

The phase output circuit 114 outputs the phase θ of the rectified voltage Vr based on the H level signal θinp and the estimated frequency ω.

Specifically, the phase output circuit 114 counts the elapsed time after the period Toff exhibits the peak value Toffp according to the H level signal θinp. The phase output circuit 114 calculates the phase angle of the rectified voltage Vr using the timing at which the peak value Toffp of the period Toff is indicated as the timing at which the phase angle of the rectified voltage Vr becomes 90±180 m degrees. In particular, in the phase output circuit 114, the phase angle of the rectified voltage Vr is (elapsed time/half cycle Tin)×180 degrees based on the elapsed time from the timing when the phase angle of the rectified voltage Vr becomes 90±180 m degrees. to calculate. Thereby, the phase output circuit 114 outputs information on the phase θ of the rectified voltage Vr.

Output circuit 115 outputs estimated value Vres2 of rectified voltage Vr based on estimated amplitude Vrp, estimated frequency ω and phase information. Further, output circuit 115 includes waveform output circuit 121 and multiplier circuit 122 .

Here, the waveform output circuit 121 outputs the waveform |sin(ω×t+θ)| of the rectified voltage Vr based on the estimated frequency ω and phase information. Furthermore, the multiplier circuit 122 outputs a rectified voltage Vr=|Vrp×sin(ω×t+θ)|, which is calculated by multiplying the estimated amplitude Vrp by the waveform |sin(ω×t+θ)|.

===Operation of rectified voltage estimation circuit 66a===
The operation of the rectified voltage estimating circuit 66a will be described with reference to FIGS. 21 and 22. FIG. FIG. 21 is a flow chart explaining the operation of the rectified voltage estimation circuit 66a, and FIG. 22 shows main waveforms in the operation of the rectified voltage estimation circuit 66a. For convenience of illustration, in FIG. 22, the peak value Toffp of the period Toff is shown as the same value.

In the following description, it is assumed that time t23 is after time t22 in FIG.

The peak values Toffp of Toff at times t21 and t22 are hereinafter referred to as peak values Toffpk-1 and Toffk. Here, Toffpk−1 is the k−1th peak value, and Toffk is the kth (k is a natural number equal to or greater than 2) peak value.

Amplitude estimation circuit 112 estimates amplitude Vrpk of rectified voltage Vr based on voltage Vfb corresponding to voltage Vout, second command value Vc2 corresponding to period Ton2, and peak value Toffk at time t22, for example ( S1). Here, since the amplitude Vrp satisfies Equation (14), the amplitude Vrpk at time t22 is estimated by Vrpk=Vout/(1+(Ton2/Toffpk)).

The frequency estimating circuit 113a calculates the frequency ωk of the rectified voltage Vr based on the period between the time t21 when the k-1-th peak value Toffpk is determined and the time t22 when the k-th peak value Toffpk is determined, for example. is estimated (S2).

Specifically, the frequency estimating circuit 113a starts timing according to the H level signal θinp, and clocks a period Tin until the next H level signal θinp is input.

Then, the frequency estimating circuit 113a calculates the k-th frequency ωk by ωk=2π/(2×Tink) using this period as the half cycle Tink of the k-th rectified voltage Vr, and outputs the data of the frequency ωk.

Here, each time the peak value is determined, the frequency estimating circuit 113a calculates the frequency ωk was supposed to be estimated, but it is not limited to this. For example, the frequency estimation circuit 113a may use an average value of a plurality of previously estimated frequencies as the estimation result.

Also, generally, the frequency of the AC voltage Vac is a predetermined specified frequency (eg, 50 Hz or 60 Hz). Therefore, the frequency estimation circuit 113a may select the prescribed frequency closest to the estimated frequency and output the selection result to the waveform output circuit 121 as the frequency ωk.

Phase output circuit 114 outputs information on phase θk of rectified voltage Vr at time t23 (S3).

Specifically, the phase output circuit 114 starts timing assuming that the phase angle of the rectified voltage Vr has reached 90+180 k degrees at time t22 in response to the H level signal θinp.

Here, the phase output circuit 114 can read the half cycle Tink from the frequency ωk output by the frequency estimation circuit 113a. Therefore, the phase output circuit 114 can calculate the phase angle of the rectified voltage Vr after time t22 as a phase angle of (elapsed time t/Tink)×180 degrees.

Thereby, the phase output circuit 114 outputs information on the phase θk of the rectified voltage Vr at time t23, for example.

Next, the waveform output circuit 121 outputs the waveform |sin(ωk×t+θk)| of the rectified voltage Vr based on the information on the wave number ωk and the phase θk (S4). Further, the multiplier circuit 122 outputs an estimated value Vres2=|Vrpk×sin(ωk×t+θk)| calculated by multiplying the amplitude Vrpk and the waveform |sin(ωk×t+θk)|. As a result, the rectified voltage estimation circuit 66a outputs the estimated value Vres2 (S5).

===Configuration of correction circuit 64d===
FIG. 23 shows an example of the configuration of the correction circuit 64d. Correction circuit 64 d includes arithmetic circuit 131 , correction value output circuit 132 , and second command value output circuit 133 .

Arithmetic circuit 131 calculates the ratio (Vout−Vres2)/Vres2 based on the estimated value Vres2 of the rectified voltage Vr and the voltage Vfb corresponding to the voltage Vout, and obtains data D[(Vout−Vres2)/Vres2 ] is output.

The correction value output circuit 132, based on the data D (Tzcd), the data D [(Vout-Vres2)/Vres2], and the constant (2/π ² ) stored in the correction value output circuit 132, A correction value ΔTon is calculated. The correction value output circuit 132 outputs a correction value ΔTon based on ΔTon=(2/π ² )×Tzcd×(Vout−Vres2)/Vres2.

The second command value output circuit 133 outputs a period Ton2 based on Ton2=Ton1+ΔTon based on the command value Vc1 corresponding to the period Ton1 and the correction value ΔTon.

Here, the arithmetic circuit 131 corresponds to the "third arithmetic circuit".

As described above, in the correction circuit 64d, the period Ton2 is calculated based on the estimated value Vres2 of the voltage Vr when the period Toff shows a peak and the phase angle is a value close to 90±180 m degrees. Therefore, even when the phase angle becomes low, an appropriate period Ton2 is set to cancel the negative value of the inductor current Il2 in FIG.

The drive circuit 56 of the power factor correction IC 35h in FIG. 19 can output the signal Vo2 for turning on the NMOS transistor 36 based on the period Ton2. As a result, the AC-DC converter including the power factor correction IC 35h can eliminate the dead angle of the inductor current IL2 and improve the power factor.

===Configuration of rectified voltage estimation circuit 66b===
FIG. 24 shows an example of the configuration of the rectified voltage estimation circuit 66b. The rectified voltage estimation circuit 66b is one of the embodiments of the rectified voltage estimation circuit 66 of FIG.

Rectified voltage estimation circuit 66b includes peak determination circuit 111b, amplitude estimation circuit 112, frequency estimation circuit 113b, phase output circuit 114, output circuit 115, and storage circuit . That is, the rectified voltage estimating circuit 66b includes a peak determining circuit 111b instead of the peak determining circuit 111a, a frequency estimating circuit 113b instead of the frequency estimating circuit 113a, and a storage circuit 116. 66a.

When the peak determination circuit 111b determines a new peak value (for example, the k-th peak value Toffpk) based on the recorded half-cycle Tin, it determines whether or not to use the new peak value Toffk for subsequent estimation. sorting process.

Here, let T2 be the timing corresponding to the peak value Toffpk, and let T1 be the timing corresponding to the previous (that is, k-th) peak value Toffpk−1.

The peak determination circuit 111b compares, for example, an average value Tave of a plurality of half-cycles Tin among a plurality of half-cycles Tin stored in a storage circuit 116, which will be described later, with T2-T1,
Determine the peak.

The peak determination circuit 111b determines to use the peak value Toffpk for subsequent estimation when T2-T1 is within a certain percentage (for example, 20%) of the average value Tave. On the other hand, if it is out of the range, the peak determination circuit 111b uses the value of the period Toff after the half cycle Tin from T1 instead of Toffpk as the peak value for later estimation.

Although the peak determination circuit 111b uses the average value Tave, it may use a half-cycle value corresponding to the specified frequency (50 Hz or 60 Hz) selected based on the average value Tave.

Every time the frequency estimation circuit 113b estimates the frequency, the half period of the period corresponding to the estimated frequency is stored in the storage circuit 116 as the half period Tin.

The storage circuit 116 records the half cycle Tin of the rectified voltage Vr. The operation of these circuits included in the rectified voltage estimating circuit 66b will be described in detail below with reference to FIGS. 25 to 27. FIG.

===Operation of rectified voltage estimation circuit 66b===
FIG. 25 explains the operation of the rectified voltage estimation circuit 66b. The flowchart of FIG. 25 differs from FIG. 21 in that S10 and S11 are included.

====Details of Step S10====
The operation of the rectified voltage estimating circuit 66a will be described with reference to FIGS. 26 and 27. FIG. FIG. 26 is a flowchart for explaining the operation of the rectified voltage estimating circuit 66a in step S10, and FIG. 27 shows waveforms for explaining the operation of the rectified voltage estimating circuit 66a.

For convenience of illustration, in FIG. 27, the peak value Toffp of the period Toff is shown as the same value except at t33. The peak value at time t31 is the k-2th peak value Toffpk-2, and the peak values at times t32 and t33 are the k-1th peak value Toffpk-1 and the k-th peak value Toffpk, respectively. (where k is a natural number of 3 or greater).

After determining the k-th peak value Toffpk, the peak determination circuit 111b determines timing T2 (time t33) of the peak value Toffpk and timing T1 at which the previous (that is, k−1)-th peak value Toffpk−1 is determined. (time t32) and the period T2-T1 is calculated (S21).

Here, the k-th peak value Toffk corresponds to the "first peak value", and the k-1-th peak value Toffpk-1 corresponds to the "second peak value".

The peak determination circuit 111b reads the values of the half-cycle Tin for the past peaks recorded from the storage circuit 116b, and calculates the average value Tave. Further, it is determined whether or not the period T2-T1 is within 20% of the period Tave (S22). That is, the peak determination circuit 111b determines whether 0.8Tave≤T2-T1≤1.2Tave is satisfied. If it is within the 20% range, proceed to S24, and if not within the 20% range, proceed to S23.

Note that in FIG. 27, the k-th peak value Toffpk is the peak Toffpk determined at t33. This peak is, for example, a peak that occurs when the AC voltage Vac or the state of the load 11 connected to the AC-DC converter suddenly changes.

Here, when time t33 is T2 and time T32 is T1, T2-T1 does not satisfy 0.8Tin≤T2-T1≤1.2Tin. Therefore, in the example of FIG. 27, the process proceeds to step S23.

Here, the ratio of 20% is an example, and this ratio is not limited to 20%, and may be set to 30% or 10%. In each of these cases, the peak determination circuit 111b determines whether the period T2-T1 is within the range of 0.7Tave≤T2-T1≤1.3Tave, or determines whether 0.9Tave≤T2-T1≤1. It is determined whether it is within the range of 1Tave. Note that 20% corresponds to the "predetermined ratio" from the "half cycle".

In the example of FIG. 27, 0.8Tin≦T2−T1≦1.2Tin is not satisfied, so peak determination circuit 111b does not output peak value Toffpk at time t33. Instead, the peak determination circuit 111b outputs Toff at time t34 after half cycle Tin has elapsed from time t33 (timing T1) as a peak value (S23).

As a result, the peak determination circuit 111b determines that the peak at t33 in FIG. 27 is an outlier peak due to noise or the like. In this manner, the peak determination circuit 111b can perform peak value selection processing in which outlier peak values are not output. After S23, the process S10 ends.

On the other hand, when 0.8Tin≦T2−T1≦1.2Tin is satisfied (not applicable in the example of FIG. 27), the peak determination circuit 111b outputs the peak value Toffpk (S24). After S24, the process S10 ends.

When the process S10 ends, the processes S1 and S2 in FIG. 25 are performed. These processes are the same as those of the steps referred to by the same reference numerals in FIG. However, in the example of FIG. 27, since Toff at time t34 is output as the peak value in S23, this value is also used as Toffpk in S1.

After S2, the frequency estimation circuit 113b stores the half period of the period corresponding to the estimated frequency ωk as a half period Tink in the storage circuit 116 (S11). S3 to S5 that are performed after this are the same as the processing of the steps referred to by the same reference numerals in FIG.

As described above, the rectified voltage estimating circuit 66b can exclude, for example, the peak value Toffpk caused by a sudden change in the AC voltage Vac or the load as an outlier. Therefore, in the rectified voltage estimating circuit 66b, the peak value Toffp of the period Toff is more accurately determined by the peak determining circuit 111b, and the rectified voltage Vr is also more accurately estimated based on the period Toffp.

As a result, the period Ton2 in which the correction circuit 64d turns on the NMOS transistor 36 can be appropriately set, so that the AC-DC converter including the power factor improvement IC 35h can improve the power factor.

===Configuration of rectified voltage estimation circuit 66c===
FIG. 28 shows an example of the configuration of the rectified voltage estimation circuit 66c. The rectified voltage estimation circuit 66c is one of the embodiments of the rectified voltage estimation circuit 66 of FIG.

Rectified voltage estimation circuit 66 c includes peak determination circuit 111 a , amplitude estimation circuit 112 , frequency estimation circuit 113 a , phase output circuit 114 , output circuit 115 and storage circuit 117 . That is, the rectified voltage estimating circuit 66c differs from the rectified voltage estimating circuit 66a in that it includes a storage circuit 117 connected to the waveform output circuit 121 .

In the rectified voltage estimating circuit 66c, the operation of the waveform output circuit 121 after the frequency estimating circuit 113a outputs the frequency ω and the phase output circuit 114 outputs the phase information differs from that of the rectified voltage estimating circuit 66a.

Storage circuit 117 records table TB|sin(ω×t+θ)| of waveform data |sin(ω×t+θ)| of rectified voltage Vr with normalized amplitude Vrp.

Therefore, the waveform output circuit 121 outputs the waveform data from the storage circuit 117 based on the frequency (for example, 50 Hz or 60 Hz) of the rectified voltage Vr and information on the input phase detected from the timing when the period Toff indicates the peak value Toffp. can be read out from the table TB|sin(ω*t+θ)|. Thereby, the waveform output circuit 121 can output the waveform data |sin(ω×t+θ)| of the rectified voltage Vr. Thus, the output circuit 115 outputs the estimated value Vres2 of the rectified voltage Vr using the waveform data |sin(ω×t+θ)|.

Other circuits of the rectified voltage estimating circuit 66c operate in the same manner as the rectified voltage estimating circuit 66a.

In the rectified voltage estimating circuit 66c, the waveform output circuit 121 can acquire waveform data from the storage circuit 117, so the amount of calculation in the power factor improvement IC 35h can be reduced.

The rectified voltage estimation circuit 66c also appropriately estimates the rectified voltage Vr, and the correction circuit 64d can set the period Ton2 based on the estimated value Vres2. Therefore, even if the rectified voltage estimation circuit 66c is used, the power factor of the AC-DC converter including the power factor improvement IC 35h can be improved.

Here, the memory circuit 117 corresponds to a "second memory circuit".

<<Power factor correction IC 35i according to embodiment 8>>
FIG. 29 shows an example of the configuration of the power factor improving IC 35i. The power factor correction IC 35i includes ADCs 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, a detection circuit 63, a correction circuit 64d, a storage circuit 95, and A rectified voltage estimation circuit 66 is included. Also, the power factor correction IC 35i includes terminals CS, FB, and OUT.

The power factor correction IC 35i can be used in an AC-DC converter similar to the power factor correction IC 35f of FIG. In the power factor improvement IC 35i, the memory circuit 95 sets the period Tzcd that satisfies the equation (11), similarly to the power factor improvement IC 35f.

The power factor improvement IC 35i includes a correction circuit 64d instead of the correction circuit 64b and a rectified voltage estimation circuit 66 in addition to the power factor improvement IC 35f. That is, in the power factor improvement IC 35i, the rectified voltage estimation circuit 66 estimates the rectified voltage Vr and outputs the estimated value Vres2, as in the power factor improvement IC 35h of FIG.

Furthermore, the correction circuit 64d calculates a correction value ΔTon for the period Ton1 for turning on the NMOS transistor 36 based on the estimated value Vres2, and outputs a command value Vc2 corresponding to the period Ton2 for turning on the NMOS transistor 36. do.

In the power factor correction IC 35i, the storage circuit 95 sets the period Tzcd that satisfies Equation (11) in the delay circuit 52, similarly to the power factor correction IC 35f in FIG.
Tzcd=π×√(L·C) (11)

In the power factor improvement IC 35i, even when the storage circuit 95 sets the delay period Tzcd, the correction circuit 64 can appropriately set the period Ton2 based on the estimated value Vres2, similarly to the power factor improvement IC 35h. Therefore, the AC-DC converter including the power factor correction IC 35i can also eliminate the dead angle of the inductor current IL2 and improve the power factor.

In each of the power factor correction ICs 35h and 35i, after the voltages Vcs and Vfb are AD-converted by the ADCs 50 and 53, processing is performed until the voltage Vo2 is output. Here, in the power factor improvement ICs 35h and 35i, part or all of the processing performed after AD conversion by the ADCs 35 and 53 may be executed by software.

===Summary===
The AC-DC converters 10b and 10c and the power factor improvement ICs 35b to 35g of the present embodiment have been described above.

In the power factor correction ICs 35b to 35g, the ON signal Son1 of the NMOS transistor 36 is delayed in order to reduce the switching loss in the NMOS transistor 36. FIG. According to the above configuration, the ON period Ton2 of the NMOS transistor 36 can be corrected just enough for the amount of decrease in the inductor current IL2 due to the delay of the ON signal Son1, and the power factor can be improved.

Further, the power factor correction ICs 35b to 35d include a terminal RT to which a voltage Vrt corresponding to the predetermined period Tzcd is applied, a delay period setting circuit 62 for setting the predetermined period Tzcd in the delay circuit 52 based on the voltage Vrt, Prepare.

Thereby, the period Tzcd can be appropriately set as a delay period for the delay period set according to the voltage Vrt generated at the terminal RT.

The power factor correction ICs 35b to 35d also include a current source 61, which is a bias current source that supplies a predetermined current Tzcd to a terminal RT, and a resistor 43 is connected to the terminal RT.

Thereby, the period Tzcd can be set as a delay period according to the resistance value of the resistor 43 provided outside the power factor correction ICs 35b to 35d.

In the power factor correction ICs 35e to 35g, the delay circuit 52 delays the ON signal Son1 for a predetermined period Tzcd determined based on the inductance L of the inductor 33 and the capacitance C of the parasitic capacitor 38 that resonates the inductor current IL2 together with the inductor 33. delay.

As a result, in the power factor correction ICs 35e to 35g, due to resonance based on the inductance L and the capacitance C, the ON period of the NMOS transistor 36 is properly controlled for the period Tzcd during which the drain-source voltage Vds of the NMOS transistor 36 exhibits a minimum value. Ton2 can be set. Therefore, it is possible to reduce the switching loss of the NMOS transistor 36 and improve the power factor of the AC-DC converter.

Power factor correction ICs 35e-35g also include a storage circuit 95 that records the period Tzcd corresponding to inductance L and capacitance C. FIG.

Thereby, the ON period Ton2 of the NMOS transistor 36 can be appropriately set for the period Tzcd based on the inductance L and the capacitance C recorded in the storage circuit 95 .

The power factor correction ICs 35b, 35c, 35e, and 35f also include a detection circuit 63 that detects the period Toff based on the timing at which the NMOS transistor 36 turns off and the timing at which the inductor current IL2 becomes zero.

This allows the power factor improvement ICs 35b, 35c, 35e, and 35f to detect the period Toff. Therefore, the power factor can be improved without using the voltage Vrdiv based on the rectified voltage Vr as the input to the correction circuits 64a and 64b.

Therefore, it is not necessary to provide a voltage dividing circuit or the like composed of the resistors 43 and 44 for inputting the voltage Vrdiv from the AC-DC converter 10b to the power factor improvement ICs 35b, 35c, 35e, and 35f. can be reduced. Also, the terminal RDIV can be omitted from the power factor improving ICs 35b, 35c, 35e, and 35f.

The correction circuit 64a also includes an arithmetic circuit 71 that divides the period Ton2 by the period Toff to calculate a ratio, and a correction value output circuit 72 that multiplies the predetermined period Tzcd by the ratio and outputs a correction value ΔTon. , and a second command value output circuit 73 that outputs a second command value Vc2 based on the first command value Vc1 and the correction value ΔTon.

Accordingly, the correction circuit 64a can calculate the second command value Vc2 for setting the period Ton2 in the drive circuit 56 without using the voltages Vfb and Vr as inputs to the correction circuit 64a.

Further, the correction circuit 64b calculates an estimation circuit 81 that calculates an estimated value Vres1 of the rectified voltage Vr based on the period Ton2 and the period Toff, and the voltage Vfb, and calculates the ratio based on the estimated value Vres1 and the voltage Vfb. a correction value output circuit 83 that multiplies the predetermined period Tzcd by a ratio to output a correction value ΔVon; and the second command value based on the first command value Vc1 and the correction value. and a second command value output circuit 84 that outputs

Accordingly, the correction circuit 64b can calculate the second command value Vc2 for setting the period Ton2 in the drive circuit 56 without using the voltage Vr as an input to the correction circuit 64b.

Further, the power factor correction ICs 35c and 35g are provided with a terminal RDIV to which a voltage Vrdiv corresponding to the rectified voltage Vr is applied, and the ratio is calculated based on the voltage Vfb and the voltage Vrdiv.

Thereby, the ratio based on the rectified voltage Vr and the output voltage Vout can be directly calculated based on the voltage Vfb and the voltage Vrdiv.

Further, the correction circuit 64c multiplies the predetermined period Tzcd by the arithmetic circuit 91 that calculates the ratio based on the voltage Vrdiv applied to the terminal RDIV and the voltage Vfb, and outputs the correction value ΔTon. and a second command value output circuit 93 that outputs a second command value Vc2 based on the first command value Vc1 and the correction value ΔTon.

In this manner, the arithmetic circuit 91 directly calculates the ratio based on the rectified voltage Vr and the output voltage Vout based on the voltage Vfb and the voltage Vrdiv, and the second specific ratio based on the arithmetic result of the arithmetic circuit 91 A configuration for outputting command value Vc2 is shown.

In another aspect of the present invention, the power factor correction ICs 35b, 35f, 35h, and 35i are based on the off period Toff of the NMOS transistor 36, the estimated value of the rectified voltage Vr in the AC-DC converter, and the voltage Vfb. Thus, the ON signal Son1 of the NMOS transistor 36 is delayed.

As a result, based on the period Toff, the estimated value of the rectified voltage Vr, and the voltage Vfb, the driving circuit 56 can turn on and off the NMOS transistor 36 at appropriate timings to improve the power factor.

In addition, the rectified voltage estimation circuits 66a, 66b, and 66c include a peak determination circuit 111a or 111b that determines a peak value Toffp of the period Toff based on the period Toff, a voltage Vfb, a peak value Toffp of the period Toff, and a period Ton2. , and an output circuit 115 that outputs an estimated value Vres2 of the rectified voltage Vr based on the estimated amplitude Vrp.

As a result, the rectified voltage estimation circuits 66a, 66b, 66c can provide the estimated value of the rectified voltage Vr without using the value of the period Toff when the rectified voltage Vr is in the low phase. Therefore, the rectified voltage estimation circuits 66a, 66b, 66c can more accurately estimate the rectified voltage Vr.

The rectified voltage estimating circuits 66a, 66b, 66c include frequency estimating circuits 113a, 113b for estimating the frequency ω of the rectified voltage Vr. The frequency estimating circuits 113a and 113b estimate the frequency ω of the rectified voltage Vr based on the determination results of the peak determining circuits 111a and 111b, and the output circuit 115 outputs the estimated frequency ω. Based on this, the rectified voltage Vr is output.

Thereby, the frequency estimating circuits 113a and 113b can time the period between the timings showing the peak value Toffp and estimate the half cycle Tin of the rectified voltage Vr. The output circuit 115 can output the waveform |sin(ω×t+θ)| of the rectified voltage Vr based on the period ω estimated by the frequency estimation circuits 113a and 113b.

Further, the rectified voltage estimation circuits 66a, 66b, 66c include a phase output circuit 114 for estimating the phase of the rectified voltage Vr based on the determination results of the peak determination circuits 111a, 111b and the estimated frequency ω. Circuit 115 outputs an estimated rectified voltage Vr based on the estimated phase.

As a result, the phase output circuit 114 sets the phase angle of the rectified voltage Vr at the peak value Toffp to 90+180 m degrees, and calculates the phase angle of the rectified voltage Vr based on the elapsed time after reaching the peak value Toffp and the half cycle Tin. can be estimated. Therefore, the waveform output circuit 121 can output the waveform |sin(ω×t+θ)| of the rectified voltage Vr based on the phase information output from the phase output circuit 114 .

If the period T2-T1 between the peak value Toffpk and the peak value Toffpk-1 immediately preceding the peak value Toffpk is within a range of 20% from the half cycle Tin of the rectified voltage Vr, the peak determination circuit 111b , the peak value Toffpk is output, and if the period T2-T1 is not within the range of 20% of the half-cycle Tin, the third period Toff after the half-cycle Tin from the peak value Toffpk-1 is output as a new peak value.

As a result, the rectified voltage estimating circuit 66b determines that the peak value Toffpk is an outlier due to erroneous detection due to noise or the like when the period T2-T1 between peaks largely deviates from the half-cycle Tin of the rectified voltage Vr. Therefore, the rectified voltage estimating circuit 66b can execute peak value selection processing that does not output outliers.

Further, the rectified voltage estimation circuit 66c includes a storage circuit 117 that records waveform data of the rectified voltage Vr with the normalized amplitude Vrp, and the output circuit 115 outputs the estimated rectified voltage Vr using the waveform data. do.

Thus, the rectified voltage estimation circuit 66c can estimate the rectified voltage Vr without detailed estimation of the waveform of the rectified voltage Vr and the frequency or phase for determining the waveform.

Further, the correction circuit 64d multiplies the calculation circuit 131 that calculates the ratio based on the estimated rectified voltage Vr and the voltage Vfb, the period Tzcd, and the ratio, and outputs the correction value ΔTon. It includes an output circuit 132 and a second command value output circuit 133 that outputs a second command value Vc2 based on the first command value Vc1 and the correction value ΔTon.

Thereby, the correction circuit 64d can calculate the correction value ΔTon without using the value of the period Toff when the rectified voltage Vr is in the low phase. Therefore, even when the rectified voltage Vr has a low phase, the period Ton2 for turning on the NMOS transistor 36 can be appropriately set.

In another aspect of the present invention, the AC-DC converters 10b and 10c that generate the output voltage Vout of the target level from the AC voltage Vac include an inductor 33 to which a rectified voltage Vr corresponding to the AC voltage Vac is applied. , an NMOS transistor 36 that controls an inductor current IL2 flowing through an inductor 33, and power factor correction ICs 35b-35g that control the switching of the NMOS transistor 36.

Thus, the AC-DC having an IC capable of correcting the ON period Ton2 of the NMOS transistor 36 just enough for the amount of decrease in the inductor current IL2 accompanying the delay of the ON signal Son1 and improving the power factor. The configuration of the converter is shown.

In another aspect of the present invention, the AC-DC converters 10b, 10c for generating the output voltage Vout of the target level from the AC voltage Vac include power factor correction ICs 35b, 35f, 35h, 35i. A DC converter 10b, 10c is provided. The power factor correction ICs 35b, 35f, 35h, and 35i output the ON signal Son1 of the NMOS transistor 36 based on the OFF period Toff of the NMOS transistor 36, the estimated value of the rectified voltage Vr in the AC-DC converter, and the voltage Vfb. are delaying.

As a result, based on the period Toff, the estimated value of the rectified voltage Vr, and the voltage Vfb, the drive circuit 56 causes the NMOS transistor 36 to turn on and off at appropriate timings, thereby improving the power factor. - Can provide a DC converter.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the scope of claims that the technical scope of the present invention can include such modifications or improvements and their equivalents without departing from the spirit of the present invention.

The execution order of each process such as actions, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly "before", "before etc., and it should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if the description is made using "first," "next," etc. for the sake of convenience, it means that it is essential to carry out in this order. not a thing

10a, 10b, 10c AC-DC converter 11 Load 20 AC power supply 21 Inductor 22 Capacitor 30 Full-wave rectifier circuit 31, 32 Capacitor 33 Inductor 34 Diode 35a, 35b, 35c, 35d, 35e, 35f, 35g, 35h, 35i Power factor Improved IC
36 NMOS transistor 37 body diode 38 parasitic capacitors 40 to 45 resistors 50, 53 ADC
51 ON signal output circuit 52 Delay circuit 54 Error amplifier circuit 55 First command value output circuit 56 Drive circuit 61 Current source 62 Delay period setting circuit 63 Detection circuits 64a, 64b, 64c, 64d Correction circuit 65 ADC
66, 66a, 66b, 66c Rectified voltage estimation circuit 71 Arithmetic circuit 72, 83, 92 Correction value output circuit 73, 84, 93 Second command value output circuit 81 Estimation circuit 82 Arithmetic circuit 91 Arithmetic circuit 95 Storage circuit 111a, 111b Peak Determination circuit 112 Amplitude estimation circuits 113a and 113b Frequency estimation circuit 114 Phase output circuit 115 Output circuit 116 Storage circuit 117 Storage circuit 121 Waveform output circuit 122 Multiplication circuit 131 Arithmetic circuit 132 Correction value output circuit 133 Second command value output circuit

Claims (19)

A power supply circuit comprising an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor for controlling an inductor current flowing through the inductor, and controlling switching of the transistor of a power supply circuit that generates an output voltage of a target level from the AC voltage. An integrated circuit that
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period;
a correction circuit that corrects the first command value and outputs a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
with
The correction circuit is
correcting the first command value based on a ratio based on a third period from when the transistor is turned off until the inductor current reaches the predetermined value and the second period, and on the predetermined period; ,
integrated circuit. The integrated circuit of claim 1, comprising:
a first terminal to which a second voltage corresponding to the predetermined period is applied;
a delay period setting circuit that sets the predetermined period in the delay circuit based on the second voltage;
comprising
integrated circuit. 3. The integrated circuit of claim 2, wherein
including a bias current source that supplies a predetermined current to the first terminal;
A resistor is connected to the first terminal,
integrated circuit. The integrated circuit of claim 1, comprising:
The delay circuit delays the ON signal for the predetermined period determined based on the inductance of the inductor and the capacitance of the capacitor that resonates the inductor current together with the inductor.
integrated circuit. 5. The integrated circuit of claim 4, wherein
a first storage circuit that records the predetermined time period corresponding to the inductance and the capacitance;
integrated circuit. An integrated circuit according to any one of claims 1 to 5,
a detection circuit that detects the third period based on a first timing at which the transistor is turned off and a second timing at which the inductor current is at the predetermined value;
integrated circuit. The integrated circuit of claim 6, comprising:
The correction circuit is
a first arithmetic circuit that divides the second period by the third period to calculate the ratio;
a correction value output circuit that multiplies the predetermined period and the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
including,
integrated circuit. The integrated circuit of claim 6, comprising:
The correction circuit is
an estimation circuit that calculates an estimated value of the rectified voltage based on the second period, the third period, and the first voltage;
a second arithmetic circuit that calculates the ratio based on the estimated value and the first voltage;
a correction value output circuit that multiplies the predetermined period and the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
including,
integrated circuit. An integrated circuit according to any one of claims 1 to 5,
A second terminal to which a third voltage corresponding to the rectified voltage is applied,
the ratio is calculated based on the first voltage and the third voltage;
integrated circuit. 10. The integrated circuit of claim 9, comprising:
The correction circuit is
a third arithmetic circuit that calculates the ratio based on the third voltage applied to the second terminal and the first voltage;
a correction value output circuit that multiplies the predetermined period and the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
including,
integrated circuit. A power supply circuit comprising an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor for controlling an inductor current flowing through the inductor, and controlling switching of the transistor of a power supply circuit that generates an output voltage of a target level from the AC voltage. An integrated circuit that
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period;
a correction circuit that corrects the first command value and outputs a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
a second estimation circuit for estimating the rectified voltage based on the first voltage, the second period, and a third period from when the transistor is turned off until the inductor current reaches the predetermined value; ,
with
The correction circuit is
correcting the first command value based on the first voltage, the estimated rectified voltage, and the predetermined period;
integrated circuit. 12. The integrated circuit of claim 11, comprising:
The second estimation circuit is
a peak determination circuit that determines a peak value of the third period in a half cycle of the rectified voltage based on the third period;
an amplitude estimation circuit that estimates the amplitude of the rectified voltage based on the first voltage, the peak value of the third period, and the second period;
an output circuit that outputs the estimated rectified voltage based on the estimated amplitude;
including,
integrated circuit. 13. The integrated circuit of claim 12, comprising:
The second estimation circuit is
including a frequency estimation circuit that estimates the frequency of the rectified voltage;
The peak determination circuit determines the peak value of the third period each time the third period reaches a peak,
The frequency estimation circuit estimates the frequency of the rectified voltage based on the determination result of the peak determination circuit,
The output circuit outputs the estimated rectified voltage based on the estimated frequency.
integrated circuit. 14. The integrated circuit of claim 13, comprising:
The second estimation circuit is
a phase output circuit for estimating the phase of the rectified voltage based on the determination result of the peak determination circuit and the estimated frequency;
The output circuit outputs the estimated rectified voltage based on the estimated phase.
integrated circuit. 15. An integrated circuit according to claim 13 or 14,
The peak determination circuit is
Output the first peak value when the period between the first peak value and the second peak value immediately before the first peak value is within a range of a predetermined ratio from the half cycle of the rectified voltage. and if the period is not within the range, outputting the third period after the half cycle from the second peak value as a new peak value;
integrated circuit. An integrated circuit according to any one of claims 12 to 15,
The second estimation circuit is
A second storage circuit for recording waveform data of the rectified voltage whose amplitude is normalized,
The output circuit is
Outputting the estimated rectified voltage using the waveform data;
integrated circuit. An integrated circuit according to any one of claims 11 to 16,
The correction circuit is
a third arithmetic circuit that calculates a ratio based on the estimated rectified voltage and the first voltage;
a correction value output circuit that multiplies the predetermined period and the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
including,
integrated circuit. A power supply circuit that generates an output voltage of a target level from an AC voltage,
an inductor to which a rectified voltage corresponding to the AC voltage is applied;
a transistor that controls an inductor current flowing through the inductor;
an integrated circuit that controls switching of the transistor;
with
The integrated circuit comprises:
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period;
a correction circuit that corrects the first command value and outputs a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
including
The correction circuit is
correcting the first command value based on a ratio based on a third period from when the transistor is turned off until the inductor current reaches the predetermined value and the second period, and on the predetermined period; ,
power circuit. A power supply circuit that generates an output voltage of a target level from an AC voltage,
an inductor to which a rectified voltage corresponding to the AC voltage is applied;
a transistor that controls an inductor current flowing through the inductor;
an integrated circuit that controls switching of the transistor;
with
The integrated circuit comprises:
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit for outputting an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period;
a correction circuit that corrects the first command value and outputs a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
a second estimation circuit for estimating the rectified voltage based on the first voltage, a third period from when the transistor is turned off until the inductor current reaches the predetermined value, and the second period; ,
including
The correction circuit is
correcting the first command value based on the first voltage, the estimated rectified voltage, and the predetermined period;
power circuit.

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