JP2023009745A - Semiconductor device, method for manufacturing semiconductor device, and electronic device - Google Patents

Abstract

To stably achieve a semiconductor device including a low-resistance semiconductor region connected to an electrode.SOLUTION: A semiconductor device 1 includes a semiconductor layer 10 including an active region AR1 and an inactive region AR2 adjacent to the active region, n-type semiconductor regions 21 and 22 provided in the active region AR1, and n-type semiconductor regions 61 and 62 provided in the inactive region AR2. A source electrode 40 and a drain electrode 50 are respectively connected to an n-type semiconductor region 21 and an n-type semiconductor region 22 of the active region AR1. Providing the n-type semiconductor regions 61 and 62 in the inactive region AR2 makes it possible to suppress speed-up of a growth rates of the n-type semiconductor regions 21 and 22 of the active region AR1 regrown together with them. This speed-up decreases an uptake quantity of dopant, thereby suppressing an increase in resistance. This stably achieves the semiconductor device 1 including sufficiently low-resistance n-type semiconductor regions 21 and 22 in the active region AR1.SELECTED DRAWING: Figure 5

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.

Regarding nitride semiconductor devices such as high electron mobility transistors (HEMTs), in order to obtain a low resistance value between the substrate and an electrode formed thereon, , a technique of protruding and forming a main electrode region in which an electrode is formed as an additional active layer portion is known. With regard to this technique, a mask layer formed on the main body of the active layer is provided with an opening for the main electrode region formation region and a dummy opening. Techniques have been proposed to grow additional active layer portions in the openings. It is said that this method does not cause film growth in the dummy opening due to the local loading effect.

JP 2008-85215 A

Regarding semiconductor devices, as a method of reducing the resistance between a semiconductor layer in an active region in which a transistor element is provided and an electrode that is ohmically connected to the semiconductor layer, a dopant of a predetermined conductivity type is introduced between the semiconductor layer and the electrode. There is a method of providing a semiconductor region that is contained to have a low resistance. Such a semiconductor region is formed, for example, by providing a mask having an opening on the semiconductor layer and growing a semiconductor crystal in the opening by using a metal organic chemical vapor deposition (MOCVD) method. re-growth). An electrode for ohmic connection is connected to the semiconductor region formed on the semiconductor layer.

In forming a semiconductor region using the MOCVD method, atoms of the main material of the semiconductor region to be formed are supplied not only on the semiconductor layer in the opening of the mask but also on the mask outside the opening. Atoms of the main material supplied on the mask can diffuse on the mask. Atoms of the primary material that diffuse on the mask can be consumed in the growth of semiconductor regions on the semiconductor layer as they move into the openings. When the atoms of the main material diffusing on the mask migrate to the openings and are consumed in the growth of the semiconductor region, the atoms of the main material diffusing on the mask do not migrate to the openings. The growth rate of the semiconductor regions grown in As the growth rate of the semiconductor region increases, the incorporation of atoms in the dopant source decreases and the resistance of the resulting semiconductor region increases. In this way, when the amount of dopant fluctuates due to the difference in the growth rate of the semiconductor region caused by the influence of the atoms of the main material diffusing on the mask, the semiconductor region connected to the electrode has a sufficiently low resistance. There is a possibility that the device cannot be stably realized.

An object of the present invention is to stably realize a semiconductor device having a low-resistance semiconductor region connected to an electrode.

In one aspect, a semiconductor layer, an active region provided in the semiconductor layer, an inactive region provided in the semiconductor layer and adjacent to the active region, and a semiconductor layer on the first surface side of the semiconductor layer in the active region a first semiconductor region provided, a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, and the first semiconductor region provided on the first surface side of the semiconductor layer; A semiconductor device is provided that includes a connected first electrode.

In another aspect, there are provided a method for manufacturing a semiconductor device as described above, and an electronic device including the semiconductor device as described above.

On one side, it is possible to stably realize a semiconductor device having a low-resistance semiconductor region connected to an electrode.

It is a figure explaining the example of a semiconductor device. It is a figure explaining an example of the formation method of a regrowth region. It is a figure explaining the difference of the growth rate of a regrowth area|region. FIG. 4 is a diagram showing an example of the relationship between the growth rate of a regrown region and the on-resistance of a transistor element; 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment; FIG. FIG. 10 is a diagram (part 1) illustrating an example of a semiconductor device according to a second embodiment; FIG. 10 is a diagram (part 2) illustrating an example of a semiconductor device according to a second embodiment; FIG. 10 is a diagram (part 1) illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 10 is a diagram (part 2) illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 13 is a diagram (part 3) illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 14 is a diagram (part 4) illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 15 is a diagram (No. 5) explaining an example of a method for forming a semiconductor device according to a second embodiment; FIG. 10 is a diagram (part 6) for explaining an example of a method for forming a semiconductor device according to a second embodiment; FIG. 15 is a diagram (No. 7) illustrating an example of a method for forming a semiconductor device according to a second embodiment; FIG. 10 is a diagram (part 8) explaining an example of a method for forming a semiconductor device according to a second embodiment; FIG. 10 is a diagram showing an example of the relationship between the growth rate of the regrown region and the on-resistance of the transistor element according to the second embodiment; FIG. 10 is a diagram (part 1) for explaining a modification of the semiconductor device according to the second embodiment; FIG. 11 is a diagram (part 2) illustrating a modification of the semiconductor device according to the second embodiment; FIG. 13 is a diagram (part 3) illustrating a modification of the semiconductor device according to the second embodiment; FIG. 11 is a diagram (part 1) illustrating an example of a semiconductor device according to a third embodiment; FIG. 12 is a diagram (part 2) illustrating an example of a semiconductor device according to a third embodiment; FIG. 11 is a diagram (part 1) illustrating an example of a semiconductor device according to a fourth embodiment; FIG. 12 is a diagram (part 2) illustrating an example of a semiconductor device according to a fourth embodiment; It is a figure explaining an example of the semiconductor package concerning a 5th embodiment. It is a figure explaining an example of the power factor improvement circuit based on 6th Embodiment. It is a figure explaining an example of the power supply device which concerns on 7th Embodiment. FIG. 22 is a diagram illustrating an example of an amplifier according to an eighth embodiment; FIG.

A so-called selective re-growth ohmic contact technique is known as a technique for reducing the resistance between a semiconductor layer and an electrode to realize an ohmic connection. In this technique, a low-resistance semiconductor region containing a dopant of a predetermined conductivity type is selectively grown (regrowed) in a predetermined portion of a semiconductor layer, and an electrode is connected to the semiconductor region. , of the electrodes to achieve an ohmic connection with the semiconductor layer. A semiconductor region provided between a semiconductor layer and an electrode is also called a regrowth region, a regrowth layer, or the like.

By the way, as one type of semiconductor device, one using a nitride semiconductor is known. A semiconductor device using a nitride semiconductor has been developed as a high withstand voltage and high output device by utilizing characteristics such as a high saturated electron velocity and a wide bandgap. As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors (FETs) such as HEMTs. As one HEMT, an AlGaN (aluminum gallium nitride) layer is used as an electron supply layer (also referred to as a "barrier layer"), and a GaN (gallium nitride) layer is used as an electron transit layer (also referred to as a "channel layer"). ) is known. In such a HEMT, a high concentration of two-dimensional Electron gas (Two Dimensional Electron Gas; 2DEG) is generated to realize high power devices. Therefore, HEMTs using GaN-based nitride semiconductors are expected to be applied to high-power amplifiers for communication and the like.

FIG. 1 is a diagram illustrating an example of a semiconductor device. FIG. 1A schematically shows a fragmentary cross-sectional view of a first example of a semiconductor device. FIG. 1B schematically shows a fragmentary cross-sectional view of a second example of a semiconductor device.

A semiconductor device 100A illustrated in FIG. 1A is an example of a HEMT. The semiconductor device 100A includes a semiconductor layer 110 and a gate electrode 120, a source electrode 130 and a drain electrode 140 provided thereon.

The semiconductor layer 110 includes an electron transit layer 111 and an electron supply layer 112 . For example, GaN is used for the electron transit layer 111 and AlGaN is used for the electron supply layer 112 . A 2DEG 1 a is generated in the vicinity of the bonding interface between the electron transit layer 111 and the electron supply layer 112 . 2DEG1a is generated in an active region 160 defined by an inactive region 150 provided in the semiconductor layer 110. FIG. The inactive region 150 is a region formed as an element isolation region by ion implantation of Ar (argon) into the semiconductor layer 110 or the like. The active region 160 is a region formed as a device region defined by such device isolation regions.

A gate electrode 120 is provided on the electron supply layer 112 of the semiconductor layer 110 in the active region 160 . A gate electrode 120 is provided on the electron supply layer 112 so as to function as a Schottky electrode. The source electrode 130 and the drain electrode 140 are provided on the electron supply layer 112 of the semiconductor layer 110 in the active region 160 so as to sandwich the gate electrode 120 . A source electrode 130 and a drain electrode 140 are formed on the electron supply layer 112 to function as ohmic electrodes.

During operation of the semiconductor device 100A, a predetermined voltage is supplied between the source electrode 130 and the drain electrode 140, and a predetermined gate voltage is supplied to the gate electrode 120. FIG. A channel through which carrier electrons are transported is formed in the electron transit layer 111 between the source electrode 130 and the drain electrode 140, and the transistor function of the semiconductor device 100A is realized.

In the semiconductor device 100A, electrons are generated between the channel, that is, the 2DEG1a generated in the electron transit layer 111 near the junction interface with the electron supply layer 112 and the source electrode 130 and the drain electrode 140 provided on the electron supply layer 112. A feed layer 112 is interposed. In the semiconductor device 100A, the resistance R1 between the 2DEG1a and the source electrode 130 and the drain electrode 140 is relatively high. Therefore, in the semiconductor device 100A, the on-resistance between the source electrode 130 and the drain electrode 140 via the channel of the transistor element included therein is relatively high. When the on-resistance increases, an increase in current flow between the source electrode 130 and the drain electrode 140 of the semiconductor device 100A is suppressed, and an increase in output power of the semiconductor device 100A is suppressed.

Therefore, the selective regrowth ohmic contact technique as described above is employed for connecting the source electrode 130 and the drain electrode 140 to the semiconductor layer 110 .
A semiconductor device 100B shown in FIG. 1B is an example of a HEMT that employs the selective re-growth ohmic contact technology. In the semiconductor device 100B, an n-type semiconductor region 181 and an n-type semiconductor region 182 (regrowth regions) are provided in the recesses 171 and 172 provided in the semiconductor layer 110, respectively, and the source electrode 130 and the drain electrode 140 are respectively provided thereon. It has a connected configuration. The semiconductor device 100B differs from the semiconductor device 100A in that it has such a configuration.

In the semiconductor device 100B, the recesses 171 and 172 penetrate the electron supply layer 112 to reach the electron transit layer 111, and the bottoms of the recesses 171 and 172 are deeper than the 2DEG1a generated in the electron transit layer 111. is provided so that An n-type semiconductor region 181 and an n-type semiconductor region 182 are grown (re-grown) in the recess 171 and the recess 172 using, for example, MOCVD, respectively. For example, n-type GaN is used for the n-type semiconductor regions 181 and 182 . A source electrode 130 and a drain electrode 140 are connected to the formed n-type semiconductor regions 181 and 182, respectively.

In the semiconductor device 100B, the 2DEG1a of the channel generated in the electron transit layer 111 is connected to the n-type semiconductor region 181 and the n-type semiconductor region 182 of relatively low resistance, and the 2DEG1a, the n-type semiconductor region 181 and the n-type semiconductor region are connected to each other. 182 becomes relatively low. A source electrode 130 and a drain electrode 140 are connected to the relatively low-resistance n-type semiconductor regions 181 and 182, respectively. Thereby, the resistance between the 2DEG1a and the source electrode 130 and the drain electrode 140 becomes relatively low. Therefore, in the semiconductor device 100B, the on-resistance between the source electrode 130 and the drain electrode 140 via the channel of the transistor element included therein is relatively low. Lowering the on-resistance enables a larger current to flow between the source electrode 130 and the drain electrode 140 of the semiconductor device 100B, thereby enabling a higher output of the semiconductor device 100B.

Here, an example of a method of forming a regrown region such as the n-type semiconductor region 181 and the n-type semiconductor region 182 will be described with reference to FIG.
FIG. 2 is a diagram explaining an example of a method of forming a regrown region. FIGS. 2A to 2D schematically show cross-sectional views of essential parts of each step of forming a regrown region.

First, as shown in FIG. 2A, a semiconductor layer 110 having an electron supply layer 112 provided on an electron transit layer 111 is prepared, and a mask 190 having an opening 190a is formed on the electron supply layer 112. be done.

The semiconductor layer 110 is prepared by growing an electron supply layer 112 such as AlGaN on an electron transit layer 111 such as GaN grown on a base substrate (not shown) by MOCVD, for example. . In the semiconductor layer 110, an inactive region 150 is formed by Ar ion implantation or the like, and an active region 160 defined by the inactive region 150 is formed. A mask 190 is formed on the semiconductor layer 110 as described above.

An insulating film such as SiN (silicon nitride) is used for the mask 190 . For example, a mask 190 such as SiN is formed on the electron supply layer 112 using plasma CVD or the like. Openings 190a corresponding to portions of the semiconductor layer 110 forming regrown regions are formed in the mask 190 by photolithography and dry etching such as RIE (Reactive Ion Etching) using F (fluorine) gas. is formed. The opening 190 a is formed in the semiconductor layer 110 in the active region 160 .

Next, as shown in FIG. 2B, the portion of the semiconductor layer 110 exposed through the opening 190a of the mask 190 is removed by a dry etching technique such as RIE using Cl (chlorine) gas, and the recess 170 ( (corresponding to the recess 171 or 172 in FIG. 1B) is formed. The recess 170 is formed, for example, through the electron supply layer 112 of the semiconductor layer 110 to reach the electron transit layer 111, and the bottom surface of the recess 170 is positioned deeper than the 2DEG1a generated in the electron transit layer 111. be.

Next, as shown in FIG. 2C, the recess 170 formed in the semiconductor layer 110 is formed with an n-type semiconductor region 180 such as n-type GaN as a regrowth region (see FIG. B) corresponding to the n-type semiconductor region 181 or the n-type semiconductor region 182) is regrown and formed. For example, when n-type GaN is regrown as the n-type semiconductor region 180, the MOCVD method uses tri-methyl-gallium (TMGa) and NH ₃ (ammonia) as main raw materials, and SiH ₄ (silane) and GeH ₄ (germane) are used.

After that, as shown in FIG. 2D, the mask 190 on the semiconductor layer 110 is removed by a wet etching technique using HF (hydrogen fluoride) or the like. As a result, a structure in which an n-type semiconductor region 180 is formed as a regrown region in the recess 170 formed in the semiconductor layer 110 of the active region 160 is obtained.

However, when forming such a regrown region, the growth rate of the n-type semiconductor region 180 may differ depending on the opening 190a of the mask 190 or the arrangement of the recess 170 formed therein. This point will be described with reference to FIG.

FIG. 3 is a diagram for explaining the difference in growth rate of regrown regions. FIG. 3 schematically shows a plan view of essential parts of a semiconductor layer on which a mask is formed.
For example, the case shown in FIG. 3, that is, the case where the mask 190 formed on the semiconductor layer 110 includes a region 191 in which the openings 190a are relatively dense and a region 192 in which the openings 190a are relatively sparse. think of. A group of recesses 170 is formed relatively densely in the semiconductor layer 110 in the region 191 where the group of openings 190a of the mask 190 is relatively dense. On the other hand, a group of recesses 170 is formed relatively sparsely in the semiconductor layer 110 in the region 192 where the group of openings 190a of the mask 190 is relatively sparse. A mask 190 including such regions 191 and 192 is formed, and the semiconductor layer 110 in which the recesses 170 are formed in the openings 190a is subjected to MOCVD as described above to form n-type GaN or the like. An n-type semiconductor region 180 is formed.

At that time, the atoms 183 of the main raw material of the n-type semiconductor region 180, such as Ga (gallium) atoms, are supplied not only on the semiconductor layer 110 in the opening 190a of the mask 190 but also on the mask 190 outside the opening 190a. be done. Atoms 183 of the primary material supplied on the mask 190 can diffuse on the mask 190 . Atoms 183 of the main material diffusing on the mask 190 move to the opening 190 a and can be consumed in the re-growth of the n-type semiconductor region 180 formed in the recess 170 of the semiconductor layer 110 . When the atoms 183 of the main material diffusing on the mask 190 move to the opening 190a and are consumed for the re-growth of the n-type semiconductor region 180, compared to the case where the atoms 183 do not move to the opening 190a, The growth rate of the n-type semiconductor region 180 regrown in the opening 190a is increased.

In a region 192 where the group of openings 190a of the mask 190 is relatively sparse, since the mask 190 exists in a relatively large area around the group of openings 190a, the light diffuses over the mask 190 and moves to the group of openings 190a. The amount of atoms 183 in the incoming main raw material tends to be relatively large. In a region 192 where the group of openings 190a is relatively sparse, the number of groups of openings 190a per unit area is small, so the amount of atoms 183 of the main raw material reaching each opening 190a also increases. easy. As a result, the growth rate of the n-type semiconductor region 180 regrown in the recess 170 is faster in the region 192 in which the group of openings 190a is relatively sparse than in the region 191 in which the group of openings 190a is relatively dense. easy to become

As the growth rate of the n-type semiconductor region 180 increases, the amount of atoms of the dopant material, such as Si (silicon) atoms and Ge (germanium) atoms, decreases, and the resistance of the resulting n-type semiconductor region 180 tends to increase. That is, the n-type semiconductor region 180 regrown in the region 192 where the openings 190a of the mask 190 are relatively sparse is the n-type semiconductor region regrowth in the region 191 where the openings 190a are relatively dense. Compared to 180, it tends to be regrown at a faster growth rate and tends to have a higher resistance.

When the n-type semiconductor region 180 is regrown using the MOCVD method, dopant material atoms such as Si atoms and Ge atoms can be supplied onto the mask 190 in addition to the main material atoms 183 such as Ga atoms. However, the atoms of the dopant raw material have a shorter stay (adsorption) time on the mask 190 and a shorter diffusion distance than the atoms 183 of the main raw material. Therefore, the probability that atoms of the dopant material supplied onto the mask 190 reach the openings 190a and are consumed for regrowth there is relatively low. As a result, in the n-type semiconductor region 180, the growth rate of which increases due to movement of the atoms 183 of the main material supplied and diffused onto the mask 190 to the openings 190a, the amount of atoms of the dopant material taken in decreases, and the resistance increases. easy to get high.

FIG. 4 is a diagram showing an example of the relationship between the growth rate of the regrown region and the on-resistance of the transistor element.
In FIG. 4, the horizontal axis represents the growth rate [nm/min] of the n-type semiconductor region (regrowth region) provided in the active region and connected to the electrode (ohmic electrode) of the transistor element, and the vertical axis represents the transistor element. on-resistance [Ω·mm]. As shown in FIG. 4, when the growth rate of the n-type semiconductor region increases, the on-resistance of the transistor element tends to increase.

As described above, when the regrown region is formed using the MOCVD method, the n-type semiconductor is formed as the regrown region in the semiconductor layer at the opening of the mask due to the influence of the atoms of the main raw material diffused on the mask. It can happen that the regions grow at different rates. The difference in the growth rate of the n-type semiconductor regions is not limited to different n-type semiconductor regions formed in one semiconductor layer, but can occur between n-type semiconductor regions formed in different semiconductor layers. . Differences in the growth rate of the n-type semiconductor regions lead to variations in the amount of incorporated n-type dopants, which causes differences in the resistance of the formed n-type semiconductor regions. As a result, it may not be possible to stably realize a semiconductor device having an n-type semiconductor region with sufficiently low resistance, which is connected to electrodes such as a source electrode and a drain electrode.

In view of the above points, here, a method shown as an embodiment below is used to suppress the difference in the growth rate of the semiconductor region regrown in the semiconductor layer for connection of the electrode. To stably realize a semiconductor device having a low-resistance semiconductor region connected to a

[First embodiment]
FIG. 5 is a diagram illustrating an example of the semiconductor device according to the first embodiment. FIG. 5 schematically shows a fragmentary cross-sectional view of an example of the semiconductor device according to the first embodiment.

A semiconductor device 1 shown in FIG. 5 is an example of a HEMT. The semiconductor device 1 includes a semiconductor layer 10, an n-type semiconductor region 21 and an n-type semiconductor region 22 provided in its active region AR1, a gate electrode 30, a source electrode 40 and a drain electrode 50. FIG. The semiconductor device 1 further includes an n-type semiconductor region 61 and an n-type semiconductor region 62 provided in the inactive region AR2 of the semiconductor layer 10 .

The semiconductor layer 10 includes an electron transit layer 11 and an electron supply layer 12 . For example, GaN is used for the electron transit layer 11 and AlGaN is used for the electron supply layer 12 . A 2DEG 1 a is generated in the vicinity of the bonding interface between the electron transit layer 11 and the electron supply layer 12 . 2DEG1a is generated in an active region AR1 defined by an inactive region AR2 provided in the semiconductor layer 10. FIG. The inactive region AR2 is a region formed as an element isolation region by ion implantation of Ar into the semiconductor layer 10 or the like. The active region AR1 is a region formed as an element region defined by such an element isolation region.

The n-type semiconductor region 21 and the n-type semiconductor region 22 are provided in recesses 71 and 72, respectively, provided on one surface (surface on the electron supply layer 12 side) 10a of the semiconductor layer 10 in the active region AR1. For example, the recesses 71 and 72 penetrate the electron supply layer 12 and reach the electron transit layer 11. be provided. The n-type semiconductor regions 21 and 22 are regrown in the recesses 71 and 72, respectively, by MOCVD, for example. For example, n-type GaN is used for the n-type semiconductor region 21 and the n-type semiconductor region 22 . The n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are also called regrowth regions, regrowth layers, and the like.

The gate electrode 30 is provided on the surface 10a side of the semiconductor layer 10 in the active region AR1. In the example of FIG. 5, the gate electrode 30 is provided on the surface 10a of the semiconductor layer 10 (the electron supply layer 12). The gate electrode 30 is located between the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1, and is connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 (and the source electrode provided thereon). 40 and drain electrode 50). A metal such as Ni (nickel) or Au (gold) is used for the gate electrode 30 . Gate electrode 30 is provided to function as a Schottky electrode.

The source electrode 40 and the drain electrode 50 are provided on the surface 10a side of the semiconductor layer 10 so as to sandwich the gate electrode 30 therebetween. The source electrode 40 is located on the n-type semiconductor region 21 provided in the recess 71 of the semiconductor layer 10 and is provided so as to be connected to the n-type semiconductor region 21 . The drain electrode 50 is located on the n-type semiconductor region 22 provided in the recess 72 of the semiconductor layer 10 and is provided so as to be connected to the n-type semiconductor region 22 . Metals such as Ti (titanium) and Al (aluminum) are used for the source electrode 40 and the drain electrode 50 . The source electrode 40 and the drain electrode 50 are provided to function as ohmic electrodes.

During operation of the semiconductor device 1 , a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50 and a predetermined gate voltage is supplied to the gate electrode 30 . A channel through which carrier electrons are transported is formed in the electron transit layer 11 between the source electrode 40 and the drain electrode 50, and the transistor function of the semiconductor device 1 is realized.

In the semiconductor device 1, the 2DEG 1a of the channel generated in the electron transit layer 11 is connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 having relatively low resistance, and the 2DEG 1a and the n-type semiconductor region 21 and the n-type semiconductor region are connected to each other. 22 is reduced. A source electrode 40 and a drain electrode 50 are connected to the relatively low-resistance n-type semiconductor regions 21 and 22, respectively. Thereby, the resistance between the 2DEG1a and the source electrode 40 and the drain electrode 50 becomes relatively low. Therefore, in the semiconductor device 1, the on-resistance between the source electrode 40 and the drain electrode 50 via the channel of the element having the transistor function (transistor element) is relatively low. Since the on-resistance is lowered, a large current can flow between the source electrode 40 and the drain electrode 50 of the semiconductor device 1, and the output of the semiconductor device 1 can be increased.

In the semiconductor device 1, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in an inactive region AR2 adjacent to and defining an active region AR1 in which a transistor element is formed. For the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2, n-type GaN is used, for example, like the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. . The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are also referred to as dummy regrowth regions, dummy regrowth layers, and the like.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in recesses 81 and 82, respectively, provided on the surface 10a side of the semiconductor layer 10 in the inactive region AR2. The recesses 81 and 82 are intermittently or continuously provided, for example, so as to surround the active region AR1. The recesses 81 and 82 are provided, for example, with the same or equivalent depths as the recesses 71 and 72 in which the n-type semiconductor regions 21 and 22 are provided, respectively. An n-type semiconductor region 61 and an n-type semiconductor region 62 are regrown in the recesses 81 and 82, respectively, using, for example, the MOCVD method. At this time, the n-type semiconductor region 61 and the n-type semiconductor region 62 are formed simultaneously with the n-type semiconductor region 21 and the n-type semiconductor region 22 . As will be described later, with respect to the surface 10a of the semiconductor layer 10, the end surfaces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the side of the surface 10a are the same as those of the n-type semiconductor region 21 and the n-type semiconductor region 22. , higher than the end face 21a and the end face 22a on the side of the surface 10a.

The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are provided so as to be positioned apart from the active region AR1. That is, the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the semiconductor layer 10 so as not to contact the active region AR1 (and the n-type semiconductor region 21 and the n-type semiconductor region 22 provided therein). be done. The n-type semiconductor region 61 and the n-type semiconductor region 62 (recess 81 and recess 82) are provided at positions where the distance D1 from the active region AR1 in the inactive region AR2 adjacent to the active region AR1 is 50 μm or more. is preferred. This is because if the n-type semiconductor region 61 and the n-type semiconductor region 62 are located in a range where the distance D1 from the active region AR1 is less than 50 μm, the following fears may occur. That is, due to the electrical action (capacitive coupling, etc.) between the n-type semiconductor regions 61 and 62 in the semiconductor layer 10 and the n-type semiconductor regions 21 and 22 of the active region AR1 and 2DEG1a, , the operation of the transistor element may be affected. However, as will be described later, the n-type semiconductor region 61 and the n-type semiconductor region 62 are separated from the n-type semiconductor region 21 and the n-type semiconductor region 22 (the recess 71 and the recess 72) provided in the active region AR1. In the example of 1), it is preferable that the distance D1 from the active region AR1 is within 500 μm.

When the n-type semiconductor region 21 and the n-type semiconductor region 22 and the n-type semiconductor region 61 and the n-type semiconductor region 62 of the semiconductor device 1 having the above configuration are regrown using the MOCVD method, on the surface 10a of the semiconductor layer 10, A mask is formed having openings where they will be regrown. Recesses 71 and 72 and recesses 81 and 82 are formed in the openings of this mask, and the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are respectively formed in these recesses. be grown. Atoms (such as Ga atoms) of the main material of the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are formed in the recesses 71 and 72 and the recesses 81 and 82 as well as the mask. Also supplied on top. Atoms of the main material supplied on the mask can diffuse on the mask.

Since the dopant material atoms stay on the mask for a shorter time and have a shorter diffusion distance than the main material atoms, they do not diffuse on the mask as much as the main material atoms.
Atoms of the main material diffusing on the mask corresponding to the inactive region AR2 move to a group of openings in the mask corresponding to the recesses 81 and 82 provided in the inactive region AR2, and move to the n-type semiconductor regions 61 and n-type semiconductor regions 61 and 82. It becomes easy to be consumed for the re-growth of the semiconductor region 62 . As a result, the atoms of the main material diffusing on the mask corresponding to the inactive region AR2 are prevented from moving to the openings of the mask corresponding to the recesses 71 and 72 provided in the active region AR1. Consumption for regrowth of the type semiconductor region 21 and the n-type semiconductor region 22 is suppressed. Therefore, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 is suppressed from increasing due to the influence of the atoms of the main material diffusing on the mask corresponding to the inactive region AR2. stabilized.

Atoms of the main material diffusing on the mask corresponding to the inactive region AR2 are easily consumed for regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62, and the n-type semiconductor region 21 and the n-type semiconductor region 22 The placement of the openings in the mask is adjusted to make it less likely to be consumed by regrowth. Thereby, the arrangement of the recesses 71 and 72 and the recesses 81 and 82 formed in the semiconductor layer 10 is adjusted. The recess 81 and the recess 82 (the n-type semiconductor region 61 and the n-type semiconductor region 62) are provided at positions within 500 μm from the recess 71 and the recess 72 (the n-type semiconductor region 21 and the n-type semiconductor region 22). is preferred. This is because when the distance of the recess 81 and the recess 82 from the recess 71 and the recess 72 exceeds 500 μm, the following occurs easily. That is, the atoms of the main material diffused on the mask corresponding to the inactive region AR2 move to the mask openings corresponding to the recesses 71 and 72, and the n-type semiconductor regions 21 and 22 are regenerated. This is because they are consumed for growth, and their growth rate tends to increase.

Atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 are easily consumed for regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62, and the n-type semiconductor region 21 and the n-type semiconductor region It becomes difficult to be consumed by 22 regrowth. Therefore, the growth rate of the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 is relatively higher than the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. significantly faster. As a result, with respect to the surface 10a of the semiconductor layer 10, the end surface 61a and the end surface 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the side of the surface 10a are the surfaces of the n-type semiconductor region 21 and the n-type semiconductor region 22. The position is higher than the end face 21a and the end face 22a on the 10a side.

As described above, the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are stabilized by suppressing an increase in their growth rate. As a result, the amount of dopant incorporated in the n-type semiconductor region 21 and the n-type semiconductor region 22 is prevented from decreasing, and the resistance thereof is prevented from increasing. As a result, the semiconductor device 1 having sufficiently low-resistance n-type semiconductor regions 21 and 22 connected to the source electrode 40 and the drain electrode 50 is stably realized.

Note that the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 having a faster growth rate than the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are the n-type semiconductor regions 21 and A smaller amount of dopant is taken in than in the n-type semiconductor region 22 .

As described above, the technique of providing an n-type semiconductor region (dummy regrowth region) in the inactive region and suppressing the growth rate of the n-type semiconductor region (regrowth region) provided in the active region is a This is effective when the arrangement of the semiconductor regions is sparse (when the growth rate tends to increase). However, the technique can be similarly applied to the case where the n-type semiconductor regions provided in the active region are densely arranged. By providing the n-type semiconductor region in the inactive region, the growth rate of the n-type semiconductor region provided in the active region can be reduced not only when the arrangement of the n-type semiconductor regions provided in the active region is sparse, but also when the arrangement of the n-type semiconductor regions provided in the active region is dense. It can be suppressed and stabilized.

Further, by providing an n-type semiconductor region (dummy regrowth region) in the inactive region, the growth rate of a plurality of n-type semiconductor regions (regrowth regions) provided in the active region is stabilized, and the growth rate of the plurality of n-type semiconductor regions (regrowth regions) provided in the active region is stabilized. It is possible to suppress the difference in growth rate between different n-type semiconductor regions. Furthermore, it is possible to suppress the difference in growth rate not only between the n-type semiconductor regions provided in the active regions of one semiconductor layer, but also between the n-type semiconductor regions provided in the active regions of different semiconductor layers.

[Second embodiment]
6 and 7 are diagrams for explaining an example of the semiconductor device according to the second embodiment. FIG. 6 schematically shows a plan view of essential parts of a semiconductor device according to the second embodiment. FIG. 7 schematically shows a fragmentary cross-sectional view of a semiconductor device according to the second embodiment. FIG. 7 is a schematic cross-sectional view taken along line VII-VII in FIG.

A semiconductor device 1A shown in FIGS. 6 and 7 is an example of a HEMT. As shown in FIGS. 6 and 7, the semiconductor device 1A includes a semiconductor layer 10A, an n-type semiconductor region 21 and an n-type semiconductor region 22 (regrowth regions) provided in its active region AR1, a gate electrode 30, a source It includes an electrode 40 and a drain electrode 50 . The semiconductor device 1A further includes an n-type semiconductor region 61 and an n-type semiconductor region 62 (dummy regrowth regions) provided in the inactive region AR2 of the semiconductor layer 10A.

The semiconductor layer 10A of the semiconductor device 1A includes a substrate 13, an initial layer 14, an electron transit layer 11, a spacer layer 15 and an electron supply layer 12, as shown in FIG.
Here, substrates such as SiC (silicon carbide), Si, sapphire, GaN, AlN (aluminum nitride), and diamond are used for the substrate 13 . The substrate 13 may have a single-layer structure of one type of substrate, or may have a laminated structure of two or more types of substrates.

The initial layer 14 is provided on one surface 13 a of the substrate 13 . A nitride semiconductor such as AlN, GaN, or AlGaN is used for the initial layer 14 . The initial layer 14 may have a single-layer structure of one kind of nitride semiconductor, or may have a laminated structure of two or more kinds of nitride semiconductors.

The electron transit layer 11 is provided on the surface 14a of the initial layer 14 opposite to the substrate 13 side. A nitride semiconductor such as GaN or AlGaN is used for the electron transit layer 11 . The electron transit layer 11 may have a single-layer structure of one kind of nitride semiconductor, or may have a laminated structure of two or more kinds of nitride semiconductors. For example, i-type GaN is used for the electron transit layer 11 .

The spacer layer 15 is provided on the surface 11a of the electron transit layer 11 opposite to the initial layer 14 side. A nitride semiconductor such as AlN or AlGaN is used for the spacer layer 15 . The spacer layer 15 may have a single layer structure of one kind of nitride semiconductor, or may have a laminated structure of two or more kinds of nitride semiconductors.

The electron supply layer 12 is provided on the surface 15a of the spacer layer 15 opposite to the electron transit layer 11 side. Nitride semiconductors such as AlGaN, InAlN (indium aluminum nitride), InAlGaN (indium aluminum gallium nitride), AlN, and ScAlN (scandium aluminum nitride) are used for the electron supply layer 12 . The electron supply layer 12 may have a single-layer structure of one kind of nitride semiconductor, or may have a laminated structure of two or more kinds of nitride semiconductors.

In the semiconductor device 1A, the 2DEG 1a is generated near the bonding interface between the electron transit layer 11 and the spacer layer 15 . 2DEG1a is generated in an active region AR1 defined by an inactive region AR2 provided in the semiconductor layer 10A. The inactive region AR2 is a region formed as an element isolation region by, for example, Ar ion implantation into the semiconductor layer 10A. The active region AR1 is a region formed as an element region defined by such an element isolation region. The inactive region AR2 is provided adjacent to the active region AR1 so as to surround the active region AR1. A transistor element having a transistor function is formed in the active region AR1 where the 2DEG1a is generated.

In the semiconductor layer 10A, for example, the MOCVD method is used to grow the initial layer 14 on the surface 13a of the substrate 13, the electron transport layer 11 is grown on the surface 14a, the spacer layer 15 is grown on the surface 11a, and the spacer layer 15 is grown on the surface 14a. It is formed by growing the electron supply layer 12 on the surface 15a.

Although illustration is omitted here, the semiconductor layer 10A includes a cap layer or the like using a nitride semiconductor such as GaN, which is provided on the surface 12a of the electron supply layer 12 opposite to the spacer layer 15 side. Other layers may also be included.

An n-type semiconductor region 21 and an n-type semiconductor region 22 are provided on the side of the surface 10a of the semiconductor layer 10A (the surface 12a of the electron supply layer 12 in this example) in the active region AR1. The n-type semiconductor region 21 and the n-type semiconductor region 22 are provided in recesses 71 and 72, respectively, provided on the surface 10a side of the semiconductor layer 10A in the active region AR1. The recesses 71 and 72 reach the electron transit layer 11 through the electron supply layer 12 and the spacer layer 15 as shown in FIG. It is provided so as to be deeper than the 2DEG1a. The n-type semiconductor regions 21 and 22 are regrown in the recesses 71 and 72, respectively, by MOCVD, for example. For example, n-type GaN is used for the n-type semiconductor region 21 and the n-type semiconductor region 22 .

The gate electrode 30 is provided on the surface 10a side of the semiconductor layer 10A. In the examples of FIGS. 6 and 7, the gate electrode 30 is provided on the surface 10a (electron supply layer 12) of the semiconductor layer 10A in the active region AR1 and the inactive region AR2. A part of the gate electrode 30 is located between the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. are provided so as not to be connected to the source electrode 40 and the drain electrode 50) provided in the . A metal such as Ni or Au is used for the gate electrode 30 . Gate electrode 30 is provided to function as a Schottky electrode. A gate insulating film (not shown) made of oxide, nitride, oxynitride, or the like may be interposed between the gate electrode 30 and the surface 10a of the semiconductor layer 10A.

The source electrode 40 and the drain electrode 50 are provided on the surface 10a side of the semiconductor layer 10A so as to sandwich the gate electrode 30 therebetween. The source electrode 40 is provided such that a portion thereof is located on the n-type semiconductor region 21 provided in the recess 71 of the semiconductor layer 10A and is connected to the n-type semiconductor region 21 . The drain electrode 50 is provided such that a portion thereof is located on the n-type semiconductor region 22 provided in the recess 72 of the semiconductor layer 10A and is connected to the n-type semiconductor region 22 . A metal such as Ti or Al is used for the source electrode 40 and the drain electrode 50 . The source electrode 40 and the drain electrode 50 are provided to function as ohmic electrodes.

During operation of the semiconductor device 1A, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. FIG. A channel through which carrier electrons are transported is formed in the electron transit layer 11 between the source electrode 40 and the drain electrode 50, and the transistor function of the semiconductor device 1A is realized.

In the semiconductor device 1A, the 2DEG 1a of the channel generated in the electron transit layer 11 is connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 having relatively low resistance, and the 2DEG 1a and the n-type semiconductor region 21 and the n-type semiconductor region are connected to each other. 22 is reduced. As a result, in the semiconductor device 1A, the resistance between the 2DEG 1a and the source electrode 40 and the drain electrode 50 connected via the n-type semiconductor regions 21 and 22 is reduced, and the on-resistance of the transistor element is reduced. reduced. In the semiconductor device 1A, an n-type semiconductor region 21 and an n-type semiconductor region 22 are provided so as to penetrate the electron supply layer 12 and the spacer layer 15 so as to be connected to the 2DEG 1a of the electron transit layer 11 . Even if the electron supply layer 12 and the spacer layer 15 are interposed between the 2DEG 1a and the surface 10a of the semiconductor layer 10A, the n-type semiconductor region 21 and the n-type semiconductor region 22 form the 2DEG 1a, the source electrode 40 and the drain. The resistance between electrodes 50 is effectively reduced.

In the semiconductor device 1, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in an inactive region AR2 adjacent to and defining an active region AR1 in which a transistor element is formed. For the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2, n-type GaN is used, for example, like the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. .

The n-type semiconductor region 61 and the n-type semiconductor region 62 are respectively provided in recesses 81 and 82 provided on the surface 10a side of the semiconductor layer 10A in the inactive region AR2. The recesses 81 and 82 are provided, for example, so as to surround the active region AR1. In the examples of FIGS. 6 and 7, recesses 81 and 82 which are U-shaped in plan view are provided on both sides of the inactive region AR2 with the active region AR1 interposed therebetween. For example, as shown in FIG. 7, the recesses 81 and 82 are provided with the same or equivalent depths as the recesses 71 and 72 in which the n-type semiconductor regions 21 and 22 are provided, respectively.

An n-type semiconductor region 61 and an n-type semiconductor region 62 are regrown in the recesses 81 and 82, respectively, using, for example, the MOCVD method. At this time, the n-type semiconductor region 61 and the n-type semiconductor region 62 are formed simultaneously with the n-type semiconductor region 21 and the n-type semiconductor region 22 . With respect to the surface 10a of the semiconductor layer 10A, the end surfaces 61a and 62a of the n-type semiconductor regions 61 and 62 on the surface 10a side are The position is higher than the end face 21a and the end face 22a.

The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are provided so as to be positioned apart from the active region AR1. The n-type semiconductor region 61 and the n-type semiconductor region 62 (recess 81 and recess 82) are preferably provided in the inactive region AR2 adjacent to the active region AR1, at a position separated from the active region AR1 by 50 μm or more. In the semiconductor layer 10A, an electrical action (capacitive coupling, etc.) between the n-type semiconductor region 61 and the n-type semiconductor region 62 and the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 and the 2DEG1a is suppressed, This is to suppress the influence of the electrical action on the operation of the transistor element. However, as will be described later, the n-type semiconductor region 61 and the n-type semiconductor region 62 (the recess 81 and the recess 82) are similar to the n-type semiconductor region 21 and the n-type semiconductor region 22 (the recess 71 and the recess 72) provided in the active region AR1. ) at a distance of 500 μm or less.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2 so as not to contact the gate electrode 30. As shown in FIG. As a result, the influence of the n-type semiconductor regions 61 and 62 on the gate electrode 30 is suppressed, and the influence of the influence on the gate electrode 30 on the operation of the transistor element is suppressed.

In the semiconductor device 1A having the above configuration, the n-type semiconductor region 21 and the n-type semiconductor region 22 connected to the source electrode 40 and the drain electrode 50 are provided in the active region AR1, and the n-type semiconductor region 22 is provided in the inactive region AR2. A region 61 and an n-type semiconductor region 62 are provided. By providing the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the growth rate during regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 together with them is reduced. Speeding up is suppressed. Details of the regrowth will be described later. By suppressing an increase in the growth rate during regrowth, a decrease in the amount of dopant incorporated in the n-type semiconductor regions 21 and 22 is suppressed, and an increase in resistance thereof is suppressed. Thereby, the semiconductor device 1A having sufficiently low-resistance n-type semiconductor regions 21 and 22 connected to the source electrode 40 and the drain electrode 50 is stably realized.

Next, a method for forming the semiconductor device 1A having the above configuration will be described.
8 to 15 are diagrams for explaining an example of a method for forming a semiconductor device according to the second embodiment. An example of each step of forming a semiconductor device will be described below in order with reference to FIGS. 8 to 15. FIG.

FIG. 8 is a diagram showing an example of the preparation process of the semiconductor layer. FIG. 8A schematically shows a plan view of essential parts of an example of the preparation process of the semiconductor layer. FIG. 8B schematically shows a fragmentary cross-sectional view of an example of a step of preparing a semiconductor layer. FIG. 8(B) is a schematic cross-sectional view taken along line VIII--VIII of FIG. 8(A).

For example, a semiconductor layer 10A as shown in FIGS. 8A and 8B is prepared. For example, using the MOCVD method, the initial layer 14 is grown on the surface 13a of the substrate 13, the electron transit layer 11 is grown on the surface 14a, the spacer layer 15 is grown on the surface 11a, and the electron supply layer is grown on the surface 15a. Layer 12 is grown. A 2DEG 1 a is generated in the vicinity of the bonding interface between the electron transit layer 11 and the spacer layer 15 .

FIG. 9 is a diagram showing an example of a process for forming an inactive region and an active region. FIG. 9A schematically shows a plan view of an essential part of an example of a process of forming an inactive region and an active region. FIG. 9B schematically shows a fragmentary cross-sectional view of an example of a process of forming an inactive region and an active region. FIG. 9B is a schematic cross-sectional view taken along line IX-IX of FIG. 9A.

After preparing the semiconductor layer 10A, for example, as shown in FIGS. 9A and 9B, an inactive region AR2 is formed, whereby an active region AR1 defined by the formed inactive region AR2 is formed.

For example, on the surface 10a of the semiconductor layer 10A, a resist pattern (not shown) having an opening in the portion of the semiconductor layer 10A that forms the inactive region AR2 is formed by photolithography. Ar ions are implanted into the portion of the semiconductor layer 10A exposed from the opening of the resist pattern. An inactive region AR2 is formed in the portion of the semiconductor layer 10A where Ar ions are implanted. Ar ion implantation is performed so as to extend to a position deeper than the 2DEG 1 a generated in the electron transit layer 11 . An active region AR1 defined by an inactive region AR2 is formed in a portion of the semiconductor layer 10A where Ar ion implantation has not been performed. After Ar ion implantation, the resist pattern is removed using an organic solvent or the like.

Instead of the Ar ion implantation, the inactive region may be formed by removing the portion of the semiconductor layer 10A exposed from the opening of the resist pattern by dry etching such as RIE using a Cl-based gas. can also

FIG. 10 is a diagram showing an example of a mask forming process. FIG. 10A schematically shows a plan view of essential parts of an example of a mask forming process. FIG. 10B schematically shows a fragmentary cross-sectional view of an example of a mask forming process. FIG. 10(B) is a schematic cross-sectional view taken along line XX of FIG. 10(A).

After forming the inactive region AR2 and the active region AR1, for example, as shown in FIGS. A mask 90 is formed having a The group of openings 90a of the mask 90 is provided at a portion of the semiconductor layer 10A where the n-type semiconductor region 21 and the n-type semiconductor region 22 (or the recess 71 and the recess 72) provided in the active region AR1 are formed. A group of openings 90a of the mask 90 are further provided at portions of the semiconductor layer 10A where the n-type semiconductor regions 61 and 62 (or the recesses 81 and 82) provided in the inactive region AR2 are to be formed.

An insulating film such as SiN is used for the mask 90 . For example, an insulating film such as SiN is formed on the surface 10a of the semiconductor layer 10A using the plasma CVD method. Next, on the insulating film, photolithographic technology is used to form the n-type semiconductor regions 21 and 22 of the semiconductor layer 10A and to form the n-type semiconductor regions 61 and 62. A resist pattern (not shown) having corresponding openings is formed. Then, the insulating film exposed from the openings of the resist pattern is removed by dry etching such as RIE using F-based gas. Thereby, a group of openings 90a of the mask 90 as shown in FIGS. 10A and 10B are formed.

Although illustration is omitted here, the resist pattern used when forming the group of openings 90a may remain on the mask 90 after forming the group of openings 90a.
FIG. 11 is a diagram showing an example of a recess forming process. FIG. 11A schematically shows a plan view of an essential part of an example of the recess forming process. FIG. 11B schematically shows a fragmentary cross-sectional view of an example of the recess forming process. FIG. 11(B) is a schematic cross-sectional view taken along line XI-XI of FIG. 11(A).

After forming the mask 90 having the group of openings 90a, as shown in FIGS. 11A and 11B, portions of the semiconductor layer 10A exposed from the group of openings 90a are subjected to RIE or the like using a Cl-based gas. is removed by dry etching. As a result, recesses 71 and 72 communicating with the openings 90a of the mask 90 are formed on the surface 10a side of the semiconductor layer 10A in the active region AR1. A recess 81 and a recess 82 communicating with the opening 90a of the mask 90 are formed on the surface 10a side of the semiconductor layer 10A in the inactive region AR2.

The recesses 71 and 72 of the active region AR1 penetrate the electron supply layer 12 and the spacer layer 15 of the semiconductor layer 10A to reach the electron transit layer 11, and the bottom surfaces of the recesses 71 and 72 are formed in the electron transit layer 11. It is formed so as to be deeper than 2DEG1a. As an example, the recess 71 and the recess 72 are formed such that their bottom surfaces are located at a depth of 60 nm or less from the surface 11a of the electron transit layer 11 toward the initial layer 14 side. The recesses 81 and 82 of the inactive region AR2 form the electron supply layer 12 and the spacer layer 15 of the semiconductor layer 10A in the inactive region AR2 simultaneously with the recesses 71 and 72 of the active region AR1 at the same or equivalent depths. It is formed so as to penetrate and reach the electron transit layer 11 .

After the formation of the recesses 71 and 72 and the recesses 81 and 82, if the resist pattern used for forming the openings 90a remains on the mask 90, the resist pattern may be removed using an organic solvent or the like. removed.

FIG. 12 is a diagram showing an example of a process for forming an n-type semiconductor region. FIG. 12A schematically shows a plan view of essential parts of an example of a process for forming an n-type semiconductor region. FIG. 12B schematically shows a fragmentary cross-sectional view of an example of a process for forming an n-type semiconductor region. FIG. 12(B) is a schematic cross-sectional view taken along line XII-XII of FIG. 12(A).

After forming the recesses 71 and 72 and the recesses 81 and 82, as shown in FIGS. A region 61 and an n-type semiconductor region 62 are formed.

For example, the MOCVD method is used to form the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and n in the recesses 71 and 72 and the recesses 81 and 82 exposed from the openings 90a of the mask 90. The type semiconductor regions 62 are each regrown. For example, n-type GaN is regrown as the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 . The n-type semiconductor region 21 and n-type semiconductor region 22 and the n-type semiconductor region 61 and n-type semiconductor region 62 are formed into recesses 71 and 72 and recesses 81 and 82, respectively, in the same regrowth process using the MOCVD method. be regrown.

When the n-type semiconductor region 21, the n-type semiconductor region 22 and the n-type semiconductor region 61, the n-type semiconductor region 62 are re-grown using the MOCVD method, the atoms of the main raw material are formed into the recesses 71 and 72 and the recesses 81 and 62. In addition to the recess 82, it is also supplied on the mask 90. FIG.

Since the dopant material atoms stay on the mask for a shorter time and have a shorter diffusion distance than the main material atoms, they do not diffuse on the mask as much as the main material atoms.
Atoms of the main material supplied onto the mask 90 corresponding to the inactive region AR2 and diffused thereon move to a group of openings 90a of the mask 90 corresponding to the recesses 81 and 82 of the inactive region AR2, and n It is likely to be consumed for regrowth of the type semiconductor region 61 and the n-type semiconductor region 62 . As a result, the atoms of the main material diffusing on the mask 90 corresponding to the inactive region AR2 move to the group of openings 90a of the mask 90 corresponding to the recesses 71 and 72 of the active region AR1, and the n-type semiconductor region 21 And consumption for regrowth of the n-type semiconductor region 22 is suppressed. Therefore, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 can be suppressed from increasing due to the influence of the atoms of the main material diffusing on the mask 90 corresponding to the inactive region AR2. .

Atoms of the main raw material diffused on the mask 90 corresponding to the inactive region AR2 are easily consumed for regrowth of the n-type semiconductor regions 61 and 62, and the n-type semiconductor regions 21 and 22 The arrangement of the openings 90a is adjusted in order to make it difficult to consume the regrowth (FIG. 10). Thereby, the arrangement of the recesses 71 and 72 and the recesses 81 and 82 is adjusted (FIG. 11). The recess 81 and the recess 82 (the n-type semiconductor region 61 and the n-type semiconductor region 62) are provided at positions within 500 μm from the recess 71 and the recess 72 (the n-type semiconductor region 21 and the n-type semiconductor region 22). is preferred. This is because when the distance of the recess 81 and the recess 82 from the recess 71 and the recess 72 exceeds 500 μm, the following occurs easily. That is, the atoms of the main material diffused on the mask 90 corresponding to the inactive region AR2 move to the group of openings 90a corresponding to the recesses 71 and 72, and the n-type semiconductor regions 21 and 22 are regenerated. This is because they are consumed for growth, and their growth rate tends to increase.

From this point of view, the arrangement of the group of openings 90a of the mask 90 is adjusted, and the arrangement of the recesses 71 and 72 and the recesses 81 and 82 is adjusted. In the recesses 71 and 72 and the recesses 81 and 82 whose arrangement is adjusted, the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 82 are formed in the same regrowth process using the MOCVD method. Semiconductor regions 62 are each regrown. This prevents the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 from increasing due to the influence of the main material atoms diffusing on the mask 90 corresponding to the inactive region AR2. and stabilized.

Atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2 are easily consumed for regrowth of the n-type semiconductor region 61 and the n-type semiconductor region 62, and the n-type semiconductor region 21 and the n-type semiconductor It becomes difficult to be consumed for the regrowth of the region 22 . Therefore, the growth rate of the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 is relatively higher than the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1. significantly faster. As a result, with respect to the surface 10a of the semiconductor layer 10A, the end surface 61a and the end surface 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 on the side of the surface 10a are the surfaces of the n-type semiconductor region 21 and the n-type semiconductor region 22. The position is higher than the end face 21a and the end face 22a on the 10a side.

As described above, an increase in the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 is suppressed and stabilized, so that the n-type semiconductor region 21 and the n-type semiconductor region 22 dopant incorporation is suppressed. By suppressing a decrease in the amount of dopant taken in, an increase in the resistance of the n-type semiconductor regions 21 and 22 is suppressed. Thereby, the n-type semiconductor region 21 and the n-type semiconductor region 22 with sufficiently low resistance are stably formed.

Note that the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 having a faster growth rate than the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are the n-type semiconductor regions 21 and A smaller amount of dopant is taken in than in the n-type semiconductor region 22 .

FIG. 13 is a diagram showing an example of the mask removing process. FIG. 13A schematically shows a plan view of essential parts of an example of the mask removing process. FIG. 13B schematically shows a fragmentary cross-sectional view of an example of the mask removing process. FIG. 13(B) is a schematic cross-sectional view taken along line XIII--XIII of FIG. 13(A).

After forming the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62, the mask 90 is removed as shown in FIGS. 13A and 13B. For example, the mask 90 is removed by wet etching using HF or the like.

14A and 14B are diagrams showing an example of a process of forming a source electrode and a drain electrode. FIG. 14A schematically shows a fragmentary plan view of an example of a process of forming a source electrode and a drain electrode. FIG. 14B schematically shows a fragmentary cross-sectional view of an example of a process of forming a source electrode and a drain electrode. FIG. 14(B) is a schematic cross-sectional view taken along line XIV-XIV of FIG. 14(A).

After removing the mask 90, the source electrode 40 and the drain electrode 50 are formed as shown in FIGS. 14A and 14B. For example, first, a resist pattern (not shown) having openings at portions where the source electrode 40 and the drain electrode 50 are to be formed is formed by photolithography. The openings of this resist pattern are provided to communicate with the n-type semiconductor regions 21 and 22 regrown in the recesses 71 and 72 of the semiconductor layer 10A in the active region AR1. After forming the resist pattern, a metal is vapor-deposited on the resist pattern and in its openings by a vacuum vapor deposition method. As an example, Ti is deposited to a thickness of 2 nm to 50 nm, and Al is deposited thereon to a thickness of 100 nm to 300 nm. After metal deposition, the lift-off technique removes the resist pattern along with the metal deposited thereon. Thereby, a source electrode 40 and a drain electrode 50 connected to the n-type semiconductor region 21 and the n-type semiconductor region 22, respectively, are formed. After that, heat treatment (alloying treatment) is performed at 500° C. to 900° C. in a nitrogen atmosphere to establish an ohmic connection between the source electrode 40 and the drain electrode 50 .

It should be noted that the source electrode 40 and the drain electrode 50 are partially connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1, respectively, even if the other portion is located in the inactive region AR2. good.

FIG. 15 is a diagram showing an example of the formation process of the gate electrode. FIG. 15A schematically shows a fragmentary plan view of an example of a step of forming a gate electrode. FIG. 15B schematically shows a fragmentary cross-sectional view of an example of a step of forming a gate electrode. FIG. 15(B) is a schematic cross-sectional view taken along line XV-XV of FIG. 15(A).

After forming the source electrode 40 and the drain electrode 50, the gate electrode 30 is formed as shown in FIGS. 15A and 15B. For example, first, a resist pattern (not shown) having an opening at a portion where the gate electrode 30 is to be formed is formed by photolithography. The opening of this resist pattern is provided so as to communicate with the semiconductor layer 10A (the gate insulating film when a gate insulating film is formed) in the active region AR1 between the source electrode 40 and the drain electrode 50. . After forming the resist pattern, a metal is vapor-deposited on the resist pattern and in its openings by a vacuum vapor deposition method. As an example, Ni with a thickness of 5 nm to 30 nm is evaporated, and Au with a thickness of 100 nm to 300 nm is evaporated thereon. After metal deposition, the lift-off technique removes the resist pattern along with the metal deposited thereon. Thereby, the gate electrode 30 is formed. Heat treatment may be performed after the formation of the gate electrode 30 .

It should be noted that the gate electrode 30 is not limited to be provided in the active region AR1, and may be extended outward from the active region AR1 and partially provided in the inactive region AR2.
Further, when a gate insulating film is interposed between the gate electrode 30 and the semiconductor layer 10A, the gate insulating film is formed before the gate electrode 30 is formed.

Through the above steps, the semiconductor device 1A having the configuration shown in FIGS. 15A and 15B is formed.
In the semiconductor device 1A, an increase in the growth rate of the n-type semiconductor regions 21 and 22 provided in the active region AR1 is suppressed (FIG. 12). As a result, the amount of dopant incorporated in the n-type semiconductor regions 21 and 22 is suppressed from decreasing, and the increase in resistance due to the decrease in the amount of dopant incorporated is suppressed. Thereby, the n-type semiconductor region 21 and the n-type semiconductor region 22 with sufficiently low resistance are stably formed. A source electrode 40 and a drain electrode 50 are connected to the sufficiently low-resistance n-type semiconductor regions 21 and 22, respectively, and the resistance between them and 2DEG1a is reduced. As a result, the semiconductor device 1A can be increased in current and output. According to the above method, the semiconductor device 1A having sufficiently low-resistance n-type semiconductor regions 21 and 22 connected to the source electrode 40 and the drain electrode 50 is stably realized.

FIG. 16 is a diagram showing an example of the relationship between the growth rate of the regrown region and the on-resistance of the transistor element according to the second embodiment.
In FIG. 16, the horizontal axis represents the growth rate [nm/min] of the n-type semiconductor region (regrowth region) provided in the active region and connected to the electrode (ohmic electrode) of the transistor element, and the vertical axis represents the transistor element. on-resistance [Ω·mm]. Part P in FIG. 16 shows the growth rate of the n-type semiconductor region (regrowth region) in the active region and the ON resistance of the transistor element when the n-type semiconductor region (dummy regrowth region) is provided in the inactive region. An example of the relationship is shown. For comparison, part Q in FIG. 16 shows an example of the relationship between the growth rate of the n-type semiconductor region in the active region and the on-resistance of the transistor element when the n-type semiconductor region is not provided in the inactive region. ing.

As shown in FIG. 16, when the n-type semiconductor region of the active region and the n-type semiconductor region of the inactive region are provided (part P), the n-type semiconductor region of the active region is higher than the case where the n-type semiconductor region of the inactive region is not provided (portion Q). The growth rate of the semiconductor region is reduced and the on-resistance of the transistor element is stabilized at a low value. According to the above method, the increase in the growth rate of the n-type semiconductor region of the active region is suppressed, the increase in resistance due to the increase in the growth rate is suppressed, and a semiconductor device having a transistor element with a low on-resistance is provided. It can be stably implemented.

Next, a modified example will be described.
17 to 19 are diagrams for explaining modifications of the semiconductor device according to the second embodiment. FIGS. 17A and 17B schematically show plan views of essential parts of examples of semiconductor devices according to modifications, and FIGS. 18A, 18B and 19 show Each of them schematically shows a main part cross-sectional view of an example of a semiconductor device according to a modification.

A semiconductor device 1Aa shown in FIG. 17A has a configuration in which an n-type semiconductor region 61 provided in an inactive region AR2 is divided into a plurality of segments 61b, and an n-type semiconductor region 62 is divided into a plurality of segments 62b. It is different from the semiconductor device 1A (FIG. 6, etc.) in this respect. For the segment 61b group and the segment 62b group of the inactive region AR2, the arrangement of the opening 90a group of the mask 90 is adjusted accordingly in the process of FIG. It is formed by performing the steps according to . After forming the segment 61b group and the segment 62b group, the source electrode 40, the drain electrode 50, and the gate electrode 30 are formed according to the example of the steps of FIGS. 14 and 15 above. For example, a semiconductor device 1Aa is obtained in this way.

In the semiconductor device 1Aa, the n-type semiconductor regions 21 and 22 of the active region AR1 and the segments 61b and 62b of the inactive region AR2 are formed in the regrowth process using the MOCVD method. (dummy regrowth regions) are formed. By forming the n-type semiconductor regions in the segment 61b group and the segment 62b group of the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 regrown together with them is increased. Speeding up is suppressed, and their resistance is suppressed from increasing.

As in the semiconductor device 1Aa, the inactive region AR2 may be provided with an n-type semiconductor region 61 in which a group of divided segments 61b are intermittently arranged. Intermittently arranged n-type semiconductor regions 62 may be provided.

Moreover, the semiconductor device 1Ab shown in FIG. 17B has a configuration in which a continuous n-type semiconductor region 63 surrounding the active region AR1 is provided in the inactive region AR2. 6, etc.). For the n-type semiconductor region 63 of the inactive region AR2, the arrangement of the openings 90a of the mask 90 is adjusted accordingly in the process of FIG. is formed by performing After the formation of the n-type semiconductor region 63, the source electrode 40, the drain electrode 50, and the gate electrode 30 are formed in accordance with the example of the steps shown in FIGS. For example, the semiconductor device 1Ab is obtained in this way.

In the semiconductor device 1Ab, in the regrowth process using the MOCVD method, the continuous n-type semiconductor regions 63 (dummy regrowth regions) of the inactive region AR2 are formed together with the n-type semiconductor regions 21 and 22 of the active region AR1. ) is formed. By forming the n-type semiconductor region 63 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 regrown together with the n-type semiconductor region 63 can be suppressed from increasing. The increase in the resistance of is suppressed.

In the semiconductor device 1Ab in which the continuous n-type semiconductor region 63 surrounding the active region AR1 is provided in the inactive region AR2, for example, as shown in FIG. In some cases, it may be necessary to intersect semiconductor regions 63 . In such a case, an insulating layer is provided on the n-type semiconductor region 63 at least at the intersection with the gate electrode 30 so that the insulating layer is interposed between the n-type semiconductor region 63 and the gate electrode 30 . Just do it. This avoids contact between the n-type semiconductor region 63 and the gate electrode 30 . By avoiding contact between the n-type semiconductor region 63 and the gate electrode 30, the influence of the n-type semiconductor region 63 on the gate electrode 30 is suppressed, and the influence on the operation of the transistor element due to the influence on the gate electrode 30 is reduced. suppressed.

The same can be applied to the source electrode 40 and the drain electrode 50 as well. That is, if the layout requires that the source electrode 40 and the drain electrode 50 intersect with the n-type semiconductor region 63 while avoiding contact in plan view, the source electrode 40 and the drain electrode 50 and the n-type semiconductor region 63 are arranged. An insulating layer may be interposed between them. This suppresses the influence of the n-type semiconductor region 63 on the source electrode 40 and the drain electrode 50 .

The semiconductor device 1Ac shown in FIG. 18A has a configuration in which a trench 64 is provided between the n-type semiconductor region 21 of the active region AR1 and the n-type semiconductor region 61 of the inactive region AR2. Furthermore, the semiconductor device 1Ac has a configuration in which a trench 65 is provided between the n-type semiconductor region 22 of the active region AR1 and the n-type semiconductor region 62 of the inactive region AR2. FIG. 18A shows an example in which trenches 64 and 65 are provided so as to divide the inactive region AR2. The semiconductor device 1Ac differs from the semiconductor device 1A (FIG. 7, etc.) in that it has such a configuration. The trenches 64 and 65 can be formed after any one of the steps of FIGS. 8-15. For example, after forming the inactive region AR2 in the process of FIG. 9, a predetermined portion of the inactive region AR2 is removed by dry etching such as RIE using a Cl-based gas to form trenches 64 and 65. . For example, a semiconductor device 1Ac is obtained in this manner.

In the semiconductor device 1Ac, the n-type semiconductor regions 21 and 22 of the active region AR1 and the n-type semiconductor regions 61 and 62 of the inactive region AR2 are formed in the re-growth process using the MOCVD method. be done. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 in the active region AR1 regrown together with them increases. is suppressed, and an increase in their resistance is suppressed.

In semiconductor device 1Ac, trench 64 is provided between n-type semiconductor region 21 and n-type semiconductor region 61 , and trench 65 is provided between n-type semiconductor region 22 and n-type semiconductor region 62 . As a result, electrical actions (capacitive coupling, etc.) between the n-type semiconductor regions 61 and 62 of the inactive region AR2 and the n-type semiconductor regions 21 and 22 of the active region AR1 and 2DEG1a are prevented. , can be effectively suppressed.

In the semiconductor device 1Ad shown in FIG. 18B, a recess 66 surrounding the active region AR1 is formed in the inactive region AR2, and the n-type semiconductor regions 61 and 62 are provided at the bottom of the recess 66. It is different from the semiconductor device 1A (see FIG. 7, etc.) in that it has a closed configuration. For example, in the process of FIG. 9, the portion of the semiconductor layer 10A exposed from the opening of the resist pattern (not shown) is subjected to RIE using a Cl-based gas instead of Ar ion implantation. It is formed by removing it by dry etching. The concave portion 66 is formed so that the bottom thereof is located deeper than the 2DEG 1 a formed in the electron transit layer 11 .

The semiconductor layer 10A in which the recess 66 is formed is subjected to the process according to the example of the processes of FIGS. That is, the formation of the mask 90, the formation of the recesses 71 and 72 of the active region AR1 and the recesses 81 and 82 of the recess 66 of the inactive region AR2, the n-type semiconductor regions 21 and 22, and the n-type semiconductor region 61 And the formation of the n-type semiconductor region 62 is performed. Then, the mask 90 is removed, the source electrode 40 and the drain electrode 50 are formed, and the gate electrode 30 is formed to obtain the semiconductor device 1Ad.

In the semiconductor device 1Ad, the n-type semiconductor regions 21 and 22 of the active region AR1 and the n-type semiconductor regions 61 and 22 of the inactive region AR2 are grown in the regrowth process using the MOCVD method. 62 are formed. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 in the active region AR1 regrown together with them increases. is suppressed, and an increase in their resistance is suppressed.

In the semiconductor device 1Ad, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in the recess 66 of the inactive region AR2. Therefore, in the semiconductor device 1Ad, the side surfaces of the n-type semiconductor regions 61 and 62 of the inactive region AR2 and the n-type semiconductor regions 21 and 22 of the active region AR1 face each other, It is possible to prevent the side surfaces from facing each other over a large area. As a result, electrical actions (capacitive coupling, etc.) between the n-type semiconductor regions 61 and 62 of the inactive region AR2 and the n-type semiconductor regions 21 and 22 of the active region AR1 and 2DEG1a are prevented. , can be effectively suppressed.

A semiconductor device 1Ae shown in FIG. 19 has a configuration in which n-type semiconductor regions 21 and 22 and n-type semiconductor regions 61 and 62 are provided on a surface 10a of a semiconductor layer 10A. In the semiconductor device 1Ae, the semiconductor layer 10A is not provided with the recesses 71 and 72 and the recesses 81 and 82 described above. The semiconductor device 1Ae differs from the semiconductor device 1A (FIG. 7, etc.) in that it has such a configuration.

For example, after the mask 90 is formed according to the example of the process of FIG. 10, the recesses 71, 72 and 81 and 82 shown in the process of FIG. The regrowth using the MOCVD method is performed according to the example of . That is, the MOCVD method is used to re-grow the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 on the surface 10a of the semiconductor layer 10A. 13 to 15, the mask 90 is removed, the source electrode 40 and the drain electrode 50 are formed, and the gate electrode 30 is formed. Formation is performed to obtain the semiconductor device 1Ae.

In the semiconductor device 1Ae, an n-type semiconductor region 21 and an n-type semiconductor region 22 are formed on the surface 10a of the semiconductor layer 10A in the active region AR1 in the regrowth process using the MOCVD method. Along with them, an n-type semiconductor region 61 and an n-type semiconductor region 62 are formed on the surface 10a of the semiconductor layer 10A in the inactive region AR2. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 in the active region AR1 regrown together with them increases. is suppressed, and an increase in their resistance is suppressed.

As in the semiconductor device 1Ae, the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 need not necessarily be provided in the recesses 71 and 72 and the recesses 81 and 82. do not do. If the source electrode 40 and the drain electrode 50 respectively connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 provided on the surface 10a of the semiconductor layer 10A are connected to the 2DEG 1a with sufficiently low resistance, the semiconductor device 1Ae can be obtained. A configuration such as the following may be adopted.

[Third Embodiment]
20 and 21 are diagrams illustrating an example of the semiconductor device according to the third embodiment. FIG. 20 schematically shows a plan view of essential parts of a semiconductor device according to the third embodiment. FIG. 21 schematically shows a fragmentary cross-sectional view of a semiconductor device according to the third embodiment. 21 is a schematic cross-sectional view taken along the line XXI-XXI of FIG. 20. FIG.

A semiconductor device 1B shown in FIGS. 20 and 21 is an example of a HEMT. In the semiconductor device 1B, the source electrode 40 connected to the n-type semiconductor region 21 provided in the active region AR1 extends to the inactive region AR2 and is connected to the n-type semiconductor region 61 provided in the inactive region AR2. have a configuration. As an example, the source electrode 40 is provided so as to cover the n-type semiconductor region 61 and partially overlap the n-type semiconductor region 61 in a plan view. Similarly, in the semiconductor device 1B, the drain electrode 50 connected to the n-type semiconductor region 22 provided in the active region AR1 extends to the inactive region AR2 and extends to the n-type semiconductor region 62 provided in the inactive region AR2. It has a connected configuration. As an example, the drain electrode 50 is provided so as to cover the n-type semiconductor region 62 and partially overlap the n-type semiconductor region 62 in plan view. The semiconductor device 1B differs from the semiconductor device 1A (FIGS. 6 and 7, etc.) described in the second embodiment in that it has such a configuration.

In the formation of the semiconductor device 1B, in the step of FIG. 14 described in the second embodiment, the source electrode 40 is formed in both the n-type semiconductor region 21 of the active region AR1 and the n-type semiconductor region 61 of the inactive region AR2. formed to be connected to A drain electrode 50 is formed to be connected to both the n-type semiconductor region 22 of the active region AR1 and the n-type semiconductor region 62 of the inactive region AR2. Other steps are performed according to the example of the steps of FIGS. 8 to 13 and 15 described in the second embodiment. By such a method, a semiconductor device 1B as shown in FIGS. 20 and 21 is obtained.

Note that, with respect to the surface 10a of the semiconductor layer 10A, the end surfaces 61a and 62a of the n-type semiconductor regions 61 and 62 are more dense than the end surfaces 21a and 22a of the n-type semiconductor regions 21 and 22. high position.

As an example in FIG. 20, the source electrode 40 covers the entire n-type semiconductor region 61 of the inactive region AR2 in plan view, and the drain electrode 50 covers the entire n-type semiconductor region 62 of the inactive region AR2 in plan view. shows a semiconductor device 1B having a layout covering the . In addition, the source electrode 40 may be laid out so as to cover part of the n-type semiconductor region 61 of the inactive region AR2 in plan view, and the drain electrode 50 may be laid out so as to cover the n-type semiconductor region of the inactive region AR2 in plan view. 62 may be partially covered.

In the semiconductor device 1B, in the same manner as described in the second embodiment, in the regrowth process using the MOCVD method, the inactive region is grown together with the n-type semiconductor regions 21 and 22 of the active region AR1. An n-type semiconductor region 61 and an n-type semiconductor region 62 of AR2 are formed. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 in the active region AR1 regrown together with them increases. is suppressed, and an increase in their resistance is suppressed.

Furthermore, in the semiconductor device 1B, the source electrode 40 covers the whole or part of the n-type semiconductor region 61 of the inactive region AR2 and is connected to the n-type semiconductor region 61 . A drain electrode 50 covers all or part of the n-type semiconductor region 62 of the inactive region AR2 and is connected to the n-type semiconductor region 62 .

Here, the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are provided at a position separated from the active region AR1, for example, at a position separated by 50 μm or more. Therefore, the n-type semiconductor region 61 of the inactive region AR2 connected to the source electrode 40 is electrically affected by the n-type semiconductor region 21 of the active region AR1 and the 2DEG1a in the semiconductor layer 10A. Influence on the operation of the transistor element can be suppressed. Similarly, the n-type semiconductor region 62 of the inactive region AR2 connected to the drain electrode 50 is electrically connected to the n-type semiconductor region 22 of the active region AR1 and the 2DEG1a in the semiconductor layer 10A so that the active region AR1 effect on the operation of the transistor element of In the semiconductor device 1B, the source electrode 40 is arranged to cover all or part of the n-type semiconductor region 61, and the drain electrode 50 is arranged to cover all or part of the n-type semiconductor region 62 by suppressing such an electrical action. It can be a layout that covers the part. By adopting a configuration like the semiconductor device 1B, it is possible to increase the degree of freedom in layout of the source electrode 40 and the drain electrode 50 and the degree of freedom in pattern design.

The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2 so as not to contact the gate electrode 30. As shown in FIG. As a result, the influence of the n-type semiconductor regions 61 and 62 on the gate electrode 30 is suppressed, and the influence of the influence on the gate electrode 30 on the operation of the transistor element is suppressed.

[Fourth Embodiment]
22 and 23 are diagrams illustrating an example of the semiconductor device according to the fourth embodiment. FIG. 22 schematically shows a plan view of essential parts of a semiconductor device according to the fourth embodiment. FIG. 23 schematically shows a fragmentary cross-sectional view of a semiconductor device according to the fourth embodiment. FIG. 23 is a schematic cross-sectional view taken along line XXIII--XXIII of FIG.

A semiconductor device 1C shown in FIGS. 22 and 23 is an example of a HEMT. The semiconductor device 1</b>C has a pair of source electrodes 40 , a drain electrode 50 provided between the source electrodes 40 , and gate electrodes 31 provided between the drain electrode 50 and each source electrode 40 . 30. Each part of the group of source electrodes 40, part of the drain electrode 50, and part of the gate finger portion 31 (FIG. 22) are provided in the active region AR1. The group of source electrodes 40 are respectively connected to the n-type semiconductor regions 21 and 22 provided in the active region AR1, extend to the inactive region AR2, and extend to the n-type semiconductor region provided in the inactive region AR2. 61 and n-type semiconductor region 62 . As an example, the group of source electrodes 40 covers the n-type semiconductor region 61 and the n-type semiconductor region 62, respectively, and each part of the group of source electrodes 40 overlaps the n-type semiconductor region 61 and the n-type semiconductor region 62, respectively, in plan view. So it is provided. Also, the drain electrode 50 is connected to the n-type semiconductor region 23 provided in the active region AR1, and is provided so as to extend to the inactive region AR2 (FIG. 22). The semiconductor device 1C differs from the semiconductor device 1A (FIGS. 6 and 7, etc.) described in the second embodiment in that it has such a configuration.

In forming the semiconductor device 1C, the n-type semiconductor region 21, the n-type semiconductor region 22 and the n-type semiconductor region 23 are formed in the active region AR1 in the steps of FIGS. 10 to 13 described in the second embodiment. , an n-type semiconductor region 61 and an n-type semiconductor region 62 are formed in the inactive region AR2. That is, a mask 90 having a group of openings 90a corresponding to these is formed, and recesses 71, 72 and 73 of the active region AR1 and recesses 81 and 82 of the inactive region AR2 are formed. A regrowth step is then performed. Mask 90 is then removed. 14 and 15 described in the second embodiment, a group of source electrodes 40 and a drain electrode 50 are formed in patterns as shown in FIGS. 22 and 23, Furthermore, a gate electrode 30 having gate fingers 31 is formed. A semiconductor device 1C as shown in FIGS. 22 and 23 is obtained by such a method.

Note that, with respect to the surface 10a of the semiconductor layer 10A, the end surfaces 61a and 62a of the n-type semiconductor regions 61 and 62 are the end surfaces 21a and 21a of the n-type semiconductor regions 21, 22 and 23, respectively. , the end surface 22a and the end surface 23a.

In addition, one of the source electrodes 40 may have a layout that covers a part of the n-type semiconductor region 61 of the inactive region AR2 in a plan view, and the other of the source electrodes 40 may also have a layout of n The layout may cover part of the semiconductor region 62 . This makes it possible to increase the degree of freedom in layout and the degree of freedom in pattern design and provide the group of source electrodes 40 .

In the semiconductor device 1C, the n-type semiconductor regions 21, 22 and 23 of the active region AR1 and the n-type semiconductor regions 61 and 61 of the inactive region AR2 are grown in the regrowth process using the MOCVD method. A mold semiconductor region 62 is formed. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, the n-type semiconductor region 21, the n-type semiconductor region 22 and the n-type semiconductor region 23 of the active region AR1 are regrown together with them. growth rate is suppressed, and their resistance is suppressed from increasing.

The semiconductor device 1C is applied to a source-grounded transistor in which the group of source electrodes 40 is grounded (GND), a discrete device, a microwave monolithic integrated circuit (MMIC), and the like. The n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are separated from the gate electrode 30 and the drain electrode 50 at positions separated from the gate electrode 30 and the drain electrode 50 used as signal transmission lines. and is provided. The n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in an inactive region AR2 directly below or part of the group of source electrodes 40 used as GND, or in an inactive region AR2 where other passive elements and the like are not provided. The n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are provided at a position separated from the active region AR1, for example, at a position separated by 50 μm or more, and the n-type semiconductor region 61 and the n-type semiconductor region 62 of the active region AR1 in the semiconductor layer 10A. Electric action with the region 21 and 2DEG1a is suppressed. Accordingly, by providing the n-type semiconductor region 61 and the n-type semiconductor region 62, the growth rate of the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23 of the active region AR1 is prevented from increasing. The influence on the operation of the element and signal transmission is suppressed.

The first to fourth embodiments have been described above.
The semiconductor devices 1, 1A, 1B, 1C, etc. having the configurations described in the first to fourth embodiments can be applied to various electronic devices. As an example, a case where the semiconductor device having the configuration described above is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier will be described below.

[Fifth Embodiment]
Here, an example of application of the semiconductor device having the above configuration to a semiconductor package will be described as a fifth embodiment.

FIG. 24 is a diagram illustrating an example of a semiconductor package according to the fifth embodiment. FIG. 24 schematically shows a plan view of essential parts of an example of a semiconductor package according to the fifth embodiment.

A semiconductor package 200 shown in FIG. 24 is an example of a discrete package. The semiconductor package 200 includes the semiconductor device 1A described in the second embodiment, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 sealing them.

The semiconductor device 1A is mounted, for example, on the die pad 210a of the lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. FIG. Pad 30a, pad 40a and pad 50a are respectively connected to gate lead 211, source lead 212 and drain lead 213 of lead frame 210 using wires 230 of Au, Al or the like. The lead frame 210, the semiconductor device 1A mounted thereon, and the wire 230 connecting them are sealed with a resin 220 so that the gate lead 211, the source lead 212, and the drain lead 213 are partially exposed.

An external connection electrode connected to the source electrode 40 is provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 30a connected to the gate electrode 30 and the pad 50a connected to the drain electrode 50 are provided. you can The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

For example, the semiconductor device 1A described in the second embodiment is used to obtain the semiconductor package 200 having such a configuration.
As described above, in the semiconductor device 1A (FIGS. 6 and 7, etc.), an n-type semiconductor region (regrowth region) connected to an electrode (source electrode 40 or drain electrode 50) is provided in the active region, and further , an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing the n-type semiconductor region in the inactive region, it is possible to prevent the growth rate of the n-type semiconductor region provided in the active region from increasing. As a result, a decrease in the amount of dopant taken in the n-type semiconductor region provided in the active region is suppressed, and an increase in resistance due to a decrease in the amount of dopant taken in is suppressed. A type semiconductor region is stably formed in the active region. As a result, the semiconductor device 1A having the sufficiently low-resistance n-type semiconductor region connected to the electrode in the active region can be stably realized. A high-performance semiconductor package 200 is realized by using such a semiconductor device 1A.

Although the semiconductor device 1A is used as an example here, it is possible to similarly obtain a semiconductor package by using other semiconductor devices 1, 1B, 1C, and the like.
[Sixth embodiment]
Here, an example of application of the semiconductor device having the configuration as described above to a power factor correction circuit will be described as a sixth embodiment.

FIG. 25 is a diagram illustrating an example of a power factor correction circuit according to the sixth embodiment. FIG. 25 shows an equivalent circuit diagram of an example of the power factor correction circuit according to the sixth embodiment.
A power factor correction (PFC) circuit 300 shown in FIG. 25 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360 and an alternating current power supply 370 (AC).

In the PFC circuit 300, the drain electrode of the switch element 310, the anode terminal of the diode 320 and one terminal of the choke coil 330 are connected. A source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350 . The other terminal of capacitor 340 and the other terminal of choke coil 330 are connected. The other terminal of capacitor 350 and the cathode terminal of diode 320 are connected. A gate driver is connected to the gate electrode of the switch element 310 . An alternating current power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360 , and a direct current power supply (DC) is taken out between both terminals of the capacitor 350 .

For example, the above semiconductor devices 1, 1A, 1B, 1C, etc. are used for the switch element 310 of the PFC circuit 300 having such a configuration.
As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and an n-type semiconductor region is provided in the inactive region. (dummy regrowth regions) are provided. By providing the n-type semiconductor region in the inactive region, it is possible to prevent the growth rate of the n-type semiconductor region provided in the active region from increasing. As a result, a decrease in the amount of dopant taken in the n-type semiconductor region provided in the active region is suppressed, and an increase in resistance due to a decrease in the amount of dopant taken in is suppressed. A type semiconductor region is stably formed in the active region. As a result, the semiconductor devices 1, 1A, 1B, 1C, etc. having sufficiently low-resistance n-type semiconductor regions connected to the electrodes in the active regions can be stably realized. Such semiconductor devices 1, 1A, 1B, 1C, etc. are used to realize a high-performance PFC circuit 300. FIG.

[Seventh embodiment]
Here, an example of applying the semiconductor device having the above configuration to a power supply device will be described as a seventh embodiment.

FIG. 26 is a diagram illustrating an example of a power supply device according to the seventh embodiment. FIG. 26 shows an equivalent circuit diagram of an example of the power supply device according to the seventh embodiment.
A power supply device 400 shown in FIG. 26 includes a primary circuit 410 , a secondary circuit 420 , and a transformer 430 provided between the primary circuit 410 and the secondary circuit 420 .

The primary side circuit 410 includes the PFC circuit 300 as described in the third embodiment and an inverter circuit, such as a full bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. be The full-bridge inverter circuit 440 includes a plurality of switch elements 441 , 442 , 443 and 444 , which are four here as an example.

The secondary circuit 420 includes a plurality of switch elements 421 , 422 and 423 , which are three here as an example.
For example, in the power supply device 400 having such a configuration, the switch element 310 of the PFC circuit 300 and the switch elements 441 to 444 of the full-bridge inverter circuit 440 included in the primary side circuit 410 are provided with the above semiconductor devices 1, 1A, and 1B. , 1C, etc. are used. For example, the switch elements 421 to 423 of the secondary side circuit 420 of the power supply device 400 use ordinary MIS (Metal Insulator Semiconductor) type FETs using silicon.

As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and an n-type semiconductor region is provided in the inactive region. (dummy regrowth regions) are provided. By providing the n-type semiconductor region in the inactive region, it is possible to prevent the growth rate of the n-type semiconductor region provided in the active region from increasing. As a result, a decrease in the amount of dopant taken in the n-type semiconductor region provided in the active region is suppressed, and an increase in resistance due to a decrease in the amount of dopant taken in is suppressed. A type semiconductor region is stably formed in the active region. As a result, the semiconductor devices 1, 1A, 1B, 1C, etc. having sufficiently low-resistance n-type semiconductor regions connected to the electrodes in the active regions can be stably realized. Using such semiconductor devices 1, 1A, 1B, 1C, etc., a high-performance power supply device 400 is realized.

[Eighth Embodiment]
Here, an application example of the semiconductor device having the configuration as described above to an amplifier will be described as an eighth embodiment.

FIG. 27 is a diagram explaining an example of an amplifier according to the eighth embodiment. FIG. 27 shows an equivalent circuit diagram of an example of the amplifier according to the eighth embodiment.
Amplifier 500 shown in FIG. 27 includes digital predistortion circuit 510 , mixer 520 , mixer 530 and power amplifier 540 .

Digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the nonlinear distortion-compensated input signal SI and the AC signal. Power amplifier 540 amplifies a signal obtained by mixing input signal SI with an AC signal. In the amplifier 500 , for example, by switching a switch, the output signal SO can be mixed with an AC signal in the mixer 530 and sent to the digital predistortion circuit 510 . Amplifier 500 can be used as a high frequency amplifier and a high power amplifier.

The semiconductor devices 1, 1A, 1B, 1C and the like are used for the power amplifier 540 of the amplifier 500 having such a configuration.
As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and an n-type semiconductor region is provided in the inactive region. (dummy regrowth regions) are provided. By providing the n-type semiconductor region in the inactive region, it is possible to prevent the growth rate of the n-type semiconductor region provided in the active region from increasing. As a result, a decrease in the amount of dopant taken in the n-type semiconductor region provided in the active region is suppressed, and an increase in resistance due to a decrease in the amount of dopant taken in is suppressed. A type semiconductor region is stably formed in the active region. As a result, the semiconductor devices 1, 1A, 1B, 1C, etc. having sufficiently low-resistance n-type semiconductor regions connected to the electrodes in the active regions can be stably realized. Using such semiconductor devices 1, 1A, 1B, 1C, etc., a high-performance amplifier 500 is realized.

Various electronic devices (semiconductor package 200, PFC circuit 300, power supply device 400, amplifier 500, etc. described in the fifth to eighth embodiments) to which the above semiconductor devices 1, 1A, 1B, 1C, etc. are applied can be It can be mounted on an electronic device or electronic device. For example, various electronic It can be mounted on an instrument or an electronic device.

The following supplementary remarks are disclosed with respect to the embodiment described above.
(Appendix 1) A semiconductor layer;
an active region provided in the semiconductor layer;
an inactive region provided in the semiconductor layer and adjacent to the active region;
a first semiconductor region provided on the first surface side of the semiconductor layer in the active region;
a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region;
and a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

(Note 2) The first semiconductor region is provided in a first recess provided on the first surface side of the semiconductor layer in the active region,
2. The semiconductor device according to claim 1, wherein the second semiconductor region is provided in a second recess provided on the first surface side of the semiconductor layer in the inactive region.

(Appendix 3) The semiconductor layer is
an electron supply layer provided on the first surface side;
an electron transit layer provided on the side opposite to the first surface side of the electron supply layer,
3. The semiconductor device according to Supplementary Note 1 or 2, wherein the first semiconductor region and the second semiconductor region reach the electron transit layer through the electron supply layer.

(Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein the second semiconductor region is positioned apart from the active region.
(Appendix 5) The semiconductor device according to any one of appendices 1 to 4, wherein the second semiconductor region is provided at a position at a distance of 50 μm or more from the active region.

(Appendix 6) The semiconductor device according to any one of appendices 1 to 5, wherein the second semiconductor region is provided at a position within 500 μm from the first semiconductor region.
(Additional Note 7) With respect to the first surface of the semiconductor layer, the first end surface of the first semiconductor region on the side of the first surface of the semiconductor layer is the first surface of the semiconductor layer of the second semiconductor region. 7. The semiconductor device according to any one of appendices 1 to 6, wherein the semiconductor device is located at a position lower than the second end surface on the first surface side.

(Note 8) The semiconductor device according to any one of notes 1 to 7, wherein the first electrode is connected to the first semiconductor region and the second semiconductor region.
(Additional Note 9) A second electrode provided on the first surface side of the semiconductor layer, at least a part of which is located in the active region, and which is separated from the first semiconductor region and the second semiconductor region. 9. The semiconductor device according to any one of appendices 1 to 8, characterized by:

(Appendix 10) forming an active region and an inactive region adjacent to the active region in a semiconductor layer;
forming a first semiconductor region on the first surface side of the semiconductor layer in the active region;
forming a second semiconductor region on the first surface side of the semiconductor layer in the inactive region;
and forming a first electrode connected to the first semiconductor region on the first surface side of the semiconductor layer.

(Appendix 11) In the step of forming the first semiconductor region and the step of forming the second semiconductor region,
forming a mask having a first opening communicating with the active region and a second opening communicating with the inactive region on the first surface side of the semiconductor layer;
11. The method according to claim 10, wherein the first semiconductor region and the second semiconductor region are grown in the first opening and the second opening of the mask, respectively, using metalorganic vapor phase epitaxy. and a method for manufacturing a semiconductor device.

(Supplementary Note 12) After forming the mask, the semiconductor layer in the first opening and the second opening is partially removed, and a first recess communicating with the first opening is formed in the semiconductor layer, and forming a second recess in communication with the second opening;
When growing the first semiconductor region and the second semiconductor region in the first opening and the second opening, respectively, the first recess communicating with the first opening and the second opening 12. The method of manufacturing a semiconductor device according to claim 11, wherein the first semiconductor region and the second semiconductor region are grown in the second recess communicating with the portion.

(Appendix 13) A semiconductor layer;
an active region provided in the semiconductor layer;
an inactive region provided in the semiconductor layer and adjacent to the active region;
a first semiconductor region provided on the first surface side of the semiconductor layer in the active region;
a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region;
and a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

1, 1A, 1Aa, 1Ab, 1Ac, 1Ad, 1Ae, 1B, 1C, 100A, 100B Semiconductor device 1a 2DEG
Reference Signs List 10, 10A, 110 semiconductor layer 10a, 11a, 12a, 13a, 14a, 15a surface 11, 111 electron transit layer 12, 112 electron supply layer 13 substrate 14 initial layer 15 spacer layer 21, 22, 23, 61, 62, 63 , 180, 181, 182 n-type semiconductor regions 21a, 22a, 23a, 61a, 62a end surfaces 30, 120 gate electrodes 30a, 40a, 50a pads 31 gate finger portions 40, 130 source electrodes 50, 140 drain electrodes 61b, 62b segments 64 , 65 trenches 66 recesses 71, 72, 73, 81, 82, 170, 171, 172 recesses 90, 190 masks 90a, 190a openings 150, AR2 inactive regions 160, AR1 active regions 183 atoms 191, 192 regions 200 semiconductor package 210 lead frame 210a die pad 211 gate lead 212 source lead 213 drain lead 220 resin 230 wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 switch element 320 diode 330 choke coil 340, 350 capacitor 360 diode bridge 370 AC power supply 400 Power supply device 410 Primary circuit 420 Secondary circuit 430 Transformer 440 Full bridge inverter circuit 500 Amplifier 510 Digital predistortion circuit 520, 530 Mixer 540 Power amplifier R1, R2 Resistor

Claims (9)

a semiconductor layer;
an active region provided in the semiconductor layer;
an inactive region provided in the semiconductor layer and adjacent to the active region;
a first semiconductor region provided on the first surface side of the semiconductor layer in the active region;
a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region;
and a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region. The semiconductor layer is
an electron supply layer provided on the first surface side;
an electron transit layer provided on the side opposite to the first surface side of the electron supply layer,
2. The semiconductor device according to claim 1, wherein said first semiconductor region and said second semiconductor region penetrate said electron supply layer to reach said electron transit layer. 3. The semiconductor device according to claim 1, wherein said second semiconductor region is provided at a position with a distance of 50 [mu]m or more from said active region. 4. The semiconductor device according to claim 1, wherein said second semiconductor region is provided at a position within 500 [mu]m from said first semiconductor region. With respect to the first surface of the semiconductor layer, the first end surface of the first semiconductor region on the first surface side of the semiconductor layer is the first surface of the second semiconductor region on the first surface side of the semiconductor layer. 5. The semiconductor device according to any one of claims 1 to 4, wherein the second end face is positioned lower than the second end face. 6. The semiconductor device according to claim 1, wherein said first electrode is connected to said first semiconductor region and said second semiconductor region. forming an active region and an inactive region adjacent to the active region in a semiconductor layer;
forming a first semiconductor region on the first surface side of the semiconductor layer in the active region;
forming a second semiconductor region on the first surface side of the semiconductor layer in the inactive region;
and forming a first electrode connected to the first semiconductor region on the first surface side of the semiconductor layer. In the step of forming the first semiconductor region and the step of forming the second semiconductor region,
forming a mask having a first opening communicating with the active region and a second opening communicating with the inactive region on the first surface side of the semiconductor layer;
8. The method according to claim 7, wherein the first semiconductor region and the second semiconductor region are grown in the first opening and the second opening of the mask, respectively, using metalorganic vapor phase epitaxy. A method of manufacturing the semiconductor device described. a semiconductor layer;
an active region provided in the semiconductor layer;
an inactive region provided in the semiconductor layer and adjacent to the active region;
a first semiconductor region provided on the first surface side of the semiconductor layer in the active region;
a second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region;
and a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region.

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