JP2022509249A - 半導体デバイス、接合構造および半導体デバイスを形成するための方法 - Google Patents
半導体デバイス、接合構造および半導体デバイスを形成するための方法 Download PDFInfo
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- JP2022509249A JP2022509249A JP2021530780A JP2021530780A JP2022509249A JP 2022509249 A JP2022509249 A JP 2022509249A JP 2021530780 A JP2021530780 A JP 2021530780A JP 2021530780 A JP2021530780 A JP 2021530780A JP 2022509249 A JP2022509249 A JP 2022509249A
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Abstract
Description
Claims (23)
- 複数の第1の相互接続部を備える第1の相互接続層、および
複数の第1のボンディングコンタクトを備える第1のボンディング層であって、前記第1の相互接続部の各々は、前記第1のボンディングコンタクトのそれぞれの1つに接触している、第1のボンディング層を備える、第1の半導体構造と、
複数の第2の相互接続部を備える第2の相互接続層、および
複数の第2のボンディングコンタクトを備える第2のボンディング層であって、前記第2のボンディングコンタクトのうちの少なくとも1つは、前記第2の相互接続部のそれぞれの1つに接触しており、前記第2のボンディングコンタクトのうちの少なくとも別の1つは、前記第2の相互接続部から分離される、第2のボンディング層を備える、第2の半導体構造と、
前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面とを備え、
前記第1のボンディングコンタクトの各々は、前記ボンディング界面において前記第2のボンディングコンタクトのうちの1つと接触している、半導体デバイス。 - 前記第1のボンディングコンタクトの数は、前記第1の相互接続部の数と同じである、請求項1に記載の半導体デバイス。
- 前記第1のボンディングコンタクトの数は、前記第2のボンディングコンタクトの数よりも少ない、請求項2に記載の半導体デバイス。
- 前記第1のボンディングコンタクトの各々は、名目上同じ臨界寸法を有する、請求項1~3のいずれか一項に記載の半導体デバイス。
- 前記第1のボンディングコンタクトおよび前記第2のボンディングコンタクトは、前記ボンディング界面において互いに接触するボンディングコンタクトの対を含み、前記ボンディングコンタクトの対は、前記第1の相互接続部および前記第2の相互接続部のそれぞれの対を電気的に接続する、請求項1~4のいずれか一項に記載の半導体デバイス。
- 前記第1のボンディングコンタクトおよび前記第2のボンディングコンタクトは、前記ボンディング界面において互いに接触するダミーボンディングコンタクトの対を含み、前記ダミーボンディングコンタクトの対は、それぞれの第1の相互接続部に電気的に接続され、ただし、第2の相互接続部には接続されない、請求項1~5のいずれか一項に記載の半導体デバイス。
- 前記第2のボンディングコンタクトのうちの少なくとも1つは、前記ボンディング界面において前記第1のボンディングコンタクトから分離される、請求項1~6のいずれか一項に記載の半導体デバイス。
- 前記第2のボンディングコンタクトのうちの少なくとも1つは、第1の臨界寸法を有する第1の部分と、前記第1の臨界寸法とは異なる第2の臨界寸法を有する第2の部分とを備える、請求項1~7のいずれか一項に記載の半導体デバイス。
- 前記第1のボンディング層は、第1の誘電体をさらに備え、前記第2のボンディング層は、前記ボンディング界面において前記第1の誘電体と接触する第2の誘電体をさらに備える、請求項1~8のいずれか一項に記載の半導体デバイス。
- 前記第1の半導体構造および前記第2の半導体構造のうちの一方は、NANDメモリストリングを有するデバイス層をさらに備え、前記第1の半導体構造および前記第2の半導体構造のうちのもう一方は、周辺デバイスを有するデバイス層をさらに備える、請求項1~9のいずれか一項に記載の半導体デバイス。
- ボンディング界面と、
前記ボンディング界面において互いに接触している機能的ボンディングコンタクトの対であって、前記機能的ボンディングコンタクトの対は、前記ボンディング界面の両側の対向する相互接続部の対にそれぞれ接触している、機能的ボンディングコンタクトの対と、
前記ボンディング界面において互いに接触しているダミーボンディングコンタクトの対であって、前記ダミーボンディングコンタクトの対は、前記ボンディング界面の一方の側の相互接続部と接触し、前記ボンディング界面の反対側のどの相互接続部からも分離される、ダミーボンディングコンタクトの対とを備える、接合構造。 - 前記ボンディング界面において互いに接触する誘電体の対をさらに備える、請求項11に記載の接合構造。
- 前記ボンディング界面にある、前記ボンディング界面のいずれかの側のどの相互接続部からも分離された別のダミーボンディングコンタクトをさらに備える、請求項11または12に記載の接合構造。
- 半導体デバイスを形成するための方法であって、
第1の基板の上方に、複数の第1の相互接続部を備える第1の相互接続層を形成することと、
複数の第1のボンディングコンタクトを備える第1のボンディング層を、前記第1の相互接続部の各々が前記第1のボンディングコンタクトのそれぞれの1つと接触するように、前記第1の相互接続層の上方に形成することと、
第2の基板の上方に、複数の第2の相互接続部を備える第2の相互接続層を形成することと、
複数の第2のボンディングコンタクトを備える第2のボンディング層を、前記第2のボンディングコンタクトのうちの少なくとも1つが前記第2の相互接続部のうちのそれぞれの1つと接触し、前記第2のボンディングコンタクトのうちの少なくとも別の1つが前記第2の相互接続部から分離されるように、前記第2の相互接続層の上方に形成することと、
前記第1の基板および前記第2の基板を、前記第1のボンディングコンタクトの各々がボンディング界面において前記第2のボンディングコンタクトのうちの1つと接触するように、フェイスツーフェイス方式で接合することとを含む、方法。 - 前記第1のボンディング層を形成することは、単一回のパターニングプロセスによって前記第1のボンディングコンタクトを形成することを含む、請求項14に記載の方法。
- 前記第2のボンディング層を形成することは、2回のパターニングプロセスによって前記第2のボンディングコンタクトを形成することを含む、請求項14または15に記載の方法。
- 前記第2のボンディング層を形成することは、
前記2回のパターニングプロセスのうちの1回によって前記第2の相互接続部の上方に第2のボンディングコンタクトの第1の部分を形成することと、
前記2回のパターニングプロセスのうちのもう1回によって第2のボンディングコンタクトの前記第1の部分の上方に第2のボンディングコンタクトの第2の部分を形成することであって、前記第2のボンディングコンタクトの前記第2の部分の数は、前記第2のボンディングコンタクトの前記第1の部分の数よりも多い、第2のボンディングコンタクトの第2の部分を形成することとを含む、請求項16に記載の方法。 - 前記第1のボンディングコンタクトの数は、前記第1の相互接続部の数と同じである、請求項14~17のいずれか一項に記載の方法。
- 前記第1のボンディングコンタクトの各々は、名目上同じ臨界寸法を有する、請求項14~18のいずれか一項に記載の方法。
- 前記第1のボンディング層を形成することは、前記第1のボンディング層内に第1の誘電体を形成することを含み、
前記第2のボンディング層を形成することは、前記第2のボンディング層内に第2の誘電体を形成することを含み、
前記第1の誘電体は、前記接合後に前記ボンディング界面において前記第2の誘電体と接触している、請求項14~19のいずれか一項に記載の方法。 - NANDメモリストリングを有する第1のデバイス層を、前記第1の相互接続層と前記第1の基板との間に形成することと、
周辺デバイスを有する第2のデバイス層を、前記第2の相互接続層と前記第2の基板との間に形成することとをさらに含む、請求項14~20のいずれか一項に記載の方法。 - 周辺デバイスを有する第1のデバイス層を、前記第1の相互接続層と前記第1の基板との間に形成することと、
NANDメモリストリングを有する第2のデバイス層を、前記第2の相互接続層と前記第2の基板との間に形成することとをさらに含む、請求項14~20のいずれか一項に記載の方法。 - 前記接合がハイブリッド接合を含む、請求項14~22のいずれか一項に記載の方法。
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