JP2022149664A - Display device - Google Patents

Abstract

To provide a display device capable of reducing power consumption.SOLUTION: A display device comprises: a display area 4 having a plurality of divided areas arranged in a matrix; a pixel array 10 which has a plurality of sub-arrays each arranged in the plurality of divided areas and in which each of the plurality of sub-arrays has a plurality of pixels; a plurality of scanning lines provided in each of the plurality of sub-arrays and extending in a first direction; a plurality of signal lines provided in the pixel array 10 so as to be commonly connected to a sub-array group of each column and extending in a second direction; a plurality of gate drivers GD each arranged in the plurality of divided areas and each connected to the plurality of scanning lines; a source driver 12 connected to the plurality of signal lines; and a control circuit 15 capable of controlling the plurality of gate drivers GD and the source driver 12 to individually drive the plurality of sub-arrays.SELECTED DRAWING: Figure 2

Description

The present invention relates to display devices.

An active matrix liquid crystal display device using thin film transistors (TFTs) as active elements, or an organic EL (electroluminescence) display device includes a substrate (called a TFT substrate) on which TFTs are arranged in a matrix. . The TFT substrate has a plurality of signal lines, each extending in the column direction, to which image signals are input, and a plurality of scanning lines, each extending in the row direction.

In recent years, gate drivers for driving scanning lines have been formed on TFT substrates to reduce the cost of driver ICs and narrow the frame of display panels. In addition, forming the gate driver on the TFT substrate eliminates restrictions on routing wiring of the scanning lines, so this technology is also useful for irregular-shaped display panels that are highly demanded for vehicles. Such technology is called GIP (Gate driver in panel) or GOA (Gate driver on array).

GIP or GOA is a very important technology for realizing narrow-frame and free-form display panels at low cost. However, in the configuration in which the circuit is arranged in the frame, there is a limit to how narrow the frame can be because a circuit arrangement area is required. Also, given the reliability issues (especially light leaks), we have to accept some frame.

Under such circumstances, a technique for mounting a gate driver within the display area has been proposed. This technology has been developed for the purpose of connecting multiple panels by narrowing the frame and for forming a foldable display structure. This technique is attracting attention as a technique to be applied to a narrow bezel and a deformed display associated therewith.

Japanese Patent No. 6077704 JP 2019-91516 A

The present invention provides a display device capable of reducing power consumption.

According to the first aspect of the present invention, a display area having a plurality of divided areas arranged in a matrix and a plurality of sub-arrays respectively arranged in the plurality of divided areas, each of the plurality of sub-arrays comprising: a pixel array having a plurality of pixels; a plurality of scanning lines provided in each of the plurality of sub-arrays and extending in a first direction; a plurality of signal lines extending in a second direction intersecting the first direction; a plurality of gate drivers respectively arranged in the plurality of divided regions and connected to the plurality of scanning lines; and the plurality of signal lines. A display device is provided comprising a line-connected source driver and a control circuit capable of controlling the plurality of gate drivers and the source driver and individually driving the plurality of sub-arrays.

According to the second aspect of the present invention, a display area having a plurality of divided areas arranged in a matrix, a non-display area provided in at least one of the plurality of divided areas and having no pixels arranged thereon, a pixel array having a plurality of sub-arrays arranged in the remaining divided regions, each of the plurality of sub-arrays having a plurality of pixels; and a plurality of sub-arrays provided in each of the plurality of sub-arrays extending in the first direction. , a plurality of signal lines provided in the pixel array so as to be commonly connected to the sub-array groups of each column and extending in a second direction intersecting the first direction, and the remaining divided regions, respectively. a plurality of gate drivers arranged and each connected to the plurality of scanning lines; a source driver connected to the plurality of signal lines; a plurality of gate drivers and the source drivers; and a control circuit capable of individually driving the .

A third aspect of the present invention provides the display device according to the first or second aspect, wherein the control circuit sequentially drives sub-array groups arranged in the column direction.

According to a fourth aspect of the present invention, there is provided the display device according to any one of the first to third aspects, wherein the control circuit simultaneously drives sub-array groups arranged in the row direction.

According to a fifth aspect of the present invention, there is provided the display device according to any one of the first to fourth aspects, wherein a start signal for starting scanning is commonly input to the gate driver group of each row.

According to a sixth aspect of the present invention, there is provided the display device according to any one of the first to fifth aspects, wherein the clock signal is commonly input to the gate driver group of each row.

According to a seventh aspect of the present invention, there is provided the display device according to any one of the first to fifth aspects, wherein the clock signal is commonly input to the gate driver group for each column.

An eighth aspect of the present invention provides the display device according to the fifth aspect, wherein a clear signal for stopping scanning is input to each of the plurality of gate drivers.

According to the ninth aspect of the present invention, the control circuit inputs the clear signal immediately after inputting the start signal to the first gate driver to rewrite data to the sub-array connected to the first gate driver. There is provided a display device according to an eighth aspect, which stops.

According to the 10th aspect of the present invention, each of the plurality of gate drivers includes a shift register having a plurality of cascaded core circuits, each of the plurality of core circuits outputting an output signal of a preceding core circuit. an input for transferring a corresponding input signal to a first node; a first inverter circuit enabled by a first frame signal and holding an inverted signal of said first node at a second node; and said first frame signal. A display device according to any one of the first to ninth aspects is provided, comprising a second inverter circuit enabled by a complementary second frame signal and holding the inverted signal of the first node at a third node. .

According to an eleventh aspect of the present invention, the core circuit includes an output section, the output section includes an output transistor and a capacitor, the output transistor having a gate connected to the first node and a clock having a first terminal for receiving a signal and a second terminal connected to a scanning line;
A display device according to a tenth aspect is provided, wherein the capacitor has a first electrode connected to the first node and a second electrode connected to the scanning line.

According to a twelfth aspect of the present invention, according to the eleventh aspect, the odd-numbered core circuits receive a first clock signal, and the even-numbered core circuits receive a second clock signal complementary to the first clock signal. Such a display device is provided.

According to the present invention, it is possible to provide a display device capable of reducing power consumption.

FIG. 1 is a schematic layout diagram of a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a block diagram of a liquid crystal display device. FIG. 3 is a schematic diagram of the display area. FIG. 4 is a schematic diagram of the pixel array shown in FIG. FIG. 5 is a schematic diagram of the gate driver group shown in FIG. FIG. 6 is a circuit diagram of the subarray shown in FIG. FIG. 7 is a block diagram of a shift register included in the gate driver. FIG. 8 is a circuit diagram of the core circuit shown in FIG. FIG. 9 is a schematic diagram for explaining the arrangement area of the gate driver. FIG. 10 is a layout diagram of the register section. FIG. 11 is a layout diagram of the output section and the clear section. FIG. 12 is a layout diagram of the input section. FIG. 13 is a layout diagram of the pull-down section. FIG. 14 is a diagram for explaining wiring of a plurality of divided areas. FIG. 15 is a schematic diagram illustrating an example of the display area. FIG. 16 is a timing chart for explaining the scanning operation of the divided areas. FIG. 17 is a timing chart for explaining the scanning stop operation of the divided areas. FIG. 18 is a schematic diagram for explaining drive pattern 1 of the liquid crystal display device. FIG. 19 is a schematic diagram for explaining drive pattern 2 of the liquid crystal display device. FIG. 20 is a timing diagram explaining the operation of the shift register. FIG. 21 is a schematic diagram for explaining the inverter operation of the core circuit during the selection period. FIG. 22 is a diagram illustrating wiring of a plurality of divided regions according to the second embodiment. FIG. 23 is a timing chart for explaining the scanning operation of the divided areas. FIG. 24 is a timing chart for explaining the operation of stopping scanning of divided areas. FIG. 25 is a schematic diagram of a display area according to the third embodiment. FIG. 26 is a schematic diagram for explaining drive pattern 1 of the liquid crystal display device. FIG. 27 is a schematic diagram for explaining drive pattern 2 of the liquid crystal display device.

Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and proportions of each drawing are not necessarily the same as the actual ones. Also, even when the same parts are shown in the drawings, there are cases in which the dimensional relationships and ratios are shown differently. In particular, several embodiments shown below are examples of apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention can be is not specified. In the following description, elements having the same functions and configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.

In this embodiment, a liquid crystal display device will be described as an example of a display device. The liquid crystal display device of this embodiment has a configuration in which a gate driver is arranged within the display area.

[1] First Embodiment [1-1] Configuration of Liquid Crystal Display Device 1 FIG. 1 is a schematic layout diagram of a liquid crystal display device 1 according to a first embodiment of the present invention. In FIG. 1, the X direction is the row direction in which the scanning lines GL extend, and the Y direction is the column direction in which the signal lines SL extend. The liquid crystal display device 1 includes a TFT substrate 2 , an integrated circuit (IC) 3 , a pixel array 10 and a gate driver group 11 .

The TFT substrate 2 is composed of a transparent insulating substrate, such as a glass substrate or a plastic substrate. A pixel array 10 , a gate driver group 11 , and an integrated circuit 3 are provided on the TFT substrate 2 . A counter substrate (not shown) is arranged above the TFT substrate 2, and a liquid crystal layer (not shown) is arranged between the TFT substrate 2 and the counter substrate.

The pixel array 10 is provided with a plurality of scanning lines GL each extending in the X direction and a plurality of signal lines SL each extending in the Y direction. The area where the pixel array 10 is arranged corresponds to the display area.

The gate driver group 11 is arranged within the display area. Part of the gate driver group 11 is arranged in the peripheral area around the display area. The peripheral area corresponds to the picture frame. The gate driver group 11 is connected to multiple scanning lines GL.

The integrated circuit 3 is connected to a plurality of signal lines SL. The integrated circuit 3 is also connected to a gate driver group 11 . The integrated circuit 3 is composed of an IC chip.

FIG. 2 is a block diagram of the liquid crystal display device 1. As shown in FIG. The liquid crystal display device 1 includes a pixel array 10 , a gate driver group 11 , a source driver 12 , a common electrode driver 13 , a voltage generator circuit 14 and a control circuit 15 . The integrated circuit 3 shown in FIG. 1 includes the source driver 12, common electrode driver 13, voltage generator circuit 14, and control circuit 15 shown in FIG.

The pixel array 10 has a plurality of pixels arranged in a matrix. The pixel array 10 has a plurality of sub-arrays arranged in a matrix. A specific configuration of the subarray will be described later. The pixel array 10 is provided with a plurality of scanning lines GL each extending in the X direction and a plurality of signal lines SL each extending in the Y direction. Pixels are arranged in intersection regions between the scanning lines GL and the signal lines SL.

The gate driver group 11 is electrically connected to multiple scanning lines GL. The gate driver group 11 includes a plurality of gate drivers provided corresponding to the plurality of sub-arrays described above. A specific configuration of the gate driver will be described later. The gate driver group 11 sends scanning signals for turning on/off switching elements included in the pixels to the pixel array 10 based on control signals sent from the control circuit 15 .

The source driver 12 is electrically connected to multiple signal lines SL. The source driver 12 receives control signals and display data from the control circuit 15 . The source driver 12 sends a gradation signal (driving voltage) corresponding to display data to the pixel array 10 based on the control signal.

A common electrode driver 13 generates a common voltage Vcom and supplies the common voltage Vcom to common electrodes in the pixel array 10 . A common electrode is an electrode provided so as to face a plurality of pixel electrodes provided for each of a plurality of pixels with a liquid crystal layer interposed therebetween.

The voltage generation circuit 14 generates various voltages necessary for the operation of the liquid crystal display device 1 and supplies these voltages to corresponding circuits.

The control circuit 15 comprehensively controls the operation of the liquid crystal display device 1 . The control circuit 15 receives image data DT and a control signal CNT from the outside. The control circuit 15 generates various control signals based on the image data DT and sends these control signals to the corresponding circuits.

[1-1-1] Configuration of Display Area 4 The area of the TFT substrate 2 where the pixel array 10 is provided constitutes the display area 4 . FIG. 3 is a schematic diagram of the display area 4. As shown in FIG.

The display area 4 includes a plurality of divided areas DI_(1,1) to DI_(m,n) arranged in a matrix (m rows×n columns). "m" and "n" are each an integer of 2 or more. The number of divided areas DI included in the display area 4 can be set arbitrarily. In this embodiment, the description of the reference sign DI with the suffixes (m, n) omitted is commonly applied to a plurality of divided areas. The same is true for other subscripted reference signs.

Each division area DI is provided with a sub-array SA and a gate driver GD.

FIG. 4 is a schematic diagram of the pixel array 10 shown in FIG. The pixel array 10 includes a plurality of subarrays SA_(1,1) to SA_(m,n) arranged in a matrix (m rows×n columns). A plurality of sub-arrays SA_(1,1) to SA_(m,n) are provided in divided areas DI_(1,1) to DI_(m,n), respectively.

Each subarray SA includes a plurality of pixels PX arranged in a matrix. A plurality of scanning lines GL are arranged in one subarray SA. That is, the plurality of subarrays SA can be scanned individually. A plurality of sub-arrays SA included in each column (that is, a plurality of sub-arrays SA arranged in the column direction) are connected to a common signal line SL.

FIG. 5 is a schematic diagram of the gate driver group 11 shown in FIG. The gate driver group 11 includes a plurality of gate drivers GD_(1,1) to GD_(m,n) arranged in a matrix (m rows×n columns). Gate drivers GD_(1,1) to GD_(m,n) are provided in divided areas DI_(1,1) to DI_(m,n), respectively. Each gate driver GD is connected to a plurality of scanning lines GL arranged in the corresponding sub-array SA and scans the plurality of scanning lines GL. FIG. 5 schematically shows how a plurality of circuit elements forming the gate driver GD are dispersedly arranged in the divided area DI.

FIG. 6 is a circuit diagram of subarray SA shown in FIG. A plurality of scanning lines GL1 to GLi and a plurality of signal lines SL1 to SLj are arranged in the sub-array SA. "i" and "j" are each an integer of 2 or more.

The pixel PX includes a switching element (active element) 16, a liquid crystal capacitor (liquid crystal element) Clc, and a storage capacitor Cs. As the switching element 16, for example, a TFT (Thin Film Transistor) or an n-channel TFT is used. Note that although the source and drain of a transistor change depending on the direction of current flowing through the transistor, an example of the connection state of the transistor will be described below. However, it goes without saying that the source and drain are not fixed as the name suggests.

The TFT 16 has a source connected to the signal line SL, a gate connected to the scanning line GL, and a drain connected to one electrode of the liquid crystal capacitor Clc. A liquid crystal capacitor Clc as a liquid crystal element is composed of a pixel electrode, a common electrode, and a liquid crystal layer sandwiched therebetween. A common electrode driver 13 applies a common voltage Vcom to the other electrode of the liquid crystal capacitor Clc.

One electrode of the storage capacitor Cs is connected to one electrode of the liquid crystal capacitor Clc. The other electrode of the storage capacitor Cs is connected to a storage capacitor line (also called a storage electrode) CsL. The storage capacitor Cs has a function of suppressing the potential fluctuation occurring in the pixel electrode and holding the drive voltage applied to the pixel electrode until the drive voltage corresponding to the next signal is applied. The storage capacitor Cs is composed of a pixel electrode, a storage capacitor line CsL, and an insulating film sandwiched therebetween. A voltage generation circuit 14 applies a storage capacitor voltage Vcs to the storage capacitor line CsL. The storage capacitor voltage Vcs is set to the same voltage as the common voltage Vcom, for example.

[1-1-2] Configuration of Gate Driver GD Next, the configuration of the gate driver GD will be described. The gate driver GD has a shift register SR. FIG. 7 is a block diagram of the shift register SR included in the gate driver GD.

The shift register SR includes a plurality of core circuits RG1-RGi. Core circuits RG1 to RGi are provided corresponding to scanning lines GL1 to GLi, respectively.

A plurality of core circuits RG1-RGi are cascade-connected. Each core circuit RG functions as a register that temporarily stores input data. The shift register SR operates in synchronization with a clock signal to sequentially shift input data (pulse signal).

Each core circuit RG is configured to output a pulse signal according to the conditions of a plurality of signals input thereto. Each core circuit RG has an input terminal V_IN, an output terminal OUT, a frame terminal Fr_o, a frame terminal Fr_e, a clock terminal CLK, a clear terminal CR, and a reset terminal RST_IN.

A plurality of core circuits RG1 to RGi are cascade-connected such that the output terminal OUT of an arbitrary core circuit RG is connected to the input terminal V_IN of the subsequent core circuit RG. A start signal ST is input to the input terminal V_IN of the first-stage core circuit RG1.

A frame signal Frame_o is input to the frame terminals Fr_o of the core circuits RG1 to RGi. A frame signal Frame_e is input to the frame terminals Fr_e of the core circuits RG1 to RGi. A clear signal CLR is input to clear terminals CR of the core circuits RG1 to RGi.

A clock signal ClkA is input to the clock terminals CLK of the odd-numbered core circuits RG1, RG3, . A clock signal ClkB is input to the clock terminals CLK of the even-numbered core circuits RG2, RG4, . Clock signal ClkA and clock signal ClkB have a complementary phase relationship.

An output terminal OUT of an arbitrary core circuit RG is connected to the reset terminal RST_IN of the previous core circuit RG. A clear signal CLR is input to the reset terminal RST_IN of the core circuit RGi at the final stage.

Output terminals OUT of the plurality of core circuits RG1 to RGi are connected to scanning lines GL1 to GLi, respectively. A capacitor connected to each scanning line GL in FIG. 7 represents a simplified capacitance of a pixel connected to the scanning line.

The control circuit 15 generates the aforementioned frame signal Frame_o, frame signal Frame_e, clock signal ClkA, clock signal ClkB, and clear signal CLR, and supplies these signals to the shift register SR.

[1-1-3] Specific Configuration of Core Circuit RG Next, a specific configuration of the core circuit RG will be described. FIG. 8 is a circuit diagram of the core circuit RG shown in FIG. The core circuit RG includes an input section 20 , a register section 21 , an output section 22 , a pull-down section 23 and a clear section 24 . The core circuit RG is composed of N-channel TFTs. Hereinafter, the TFT may be simply referred to as a transistor. In this specification, one of the source and drain of the transistor may be called the first terminal, and the other may be called the second terminal.

The input section 20 is a circuit for receiving an input signal VIN. The input section 20 comprises two transistors M2, M5. An input signal VIN is input to the gate of the transistor M2 via the input terminal V_IN. The input signal VIN corresponds to the output signal of the preceding core circuit RG. The drain of transistor M2 is connected to its gate. That is, the transistor M2 is diode-connected. The source of transistor M2 is connected to node An. The transistor M2 transfers the input signal VIN to the node An when the input signal VIN is at high level, and is turned off when the input signal VIN is at low level.

A reset signal RST is input to the gate of the transistor (also called a reset transistor) M5 via a reset terminal RST_IN. The reset signal RST corresponds to the output signal of the subsequent core circuit RG. The drain of transistor M5 is connected to node An. A source of the transistor M5 is connected to a power supply terminal to which a voltage Vgl is supplied. The voltage Vgl is a reference voltage for setting the signal to low level, and is lower than the high level voltage of the signal. Voltage Vgl is, for example, a negative voltage lower than ground voltage GND, and is set in the range of -10V to -20V.

The register section 21 is a circuit for holding the voltage applied to the capacitor Cb in the selected state and the non-selected state. The register unit 21 includes two inverter circuits 21o and 21e and a transistor M1b.

The inverter circuit 21o includes three transistors M1o, M6o and M7o. A frame signal Frame_o is input to the gate of the transistor M1o via the frame terminal Fr_o. The drain of transistor M1o is connected to its gate. The source of transistor M1o is connected to node Bno. The transistor M1o transfers the frame signal Frame_o to the node Bno when the frame signal Frame_o is at high level, and is turned off when the frame signal Frame_o is at low level. That is, the inverter circuit 21o is enabled when the frame signal Frame_o is at high level.

The gate of transistor M6o is connected to node Bno. The drain of transistor M6o is connected to node An. The source of the transistor M6o is connected to the power supply terminal supplied with the voltage Vgl. The transistor M6o has a function of pulling down the potential of the node An.

The gate of transistor M7o is connected to node An. The drain of transistor M7o is connected to node Bno. The source of the transistor M7o is connected to the power supply terminal to which the voltage Vgl is supplied. The transistor M7o has a function of pulling down the potential of the node Bno.

The inverter circuit 21e has three transistors M1e, M6e, and M7e. A frame signal Frame_e is input to the gate of the transistor M1e via the frame terminal Fr_e. The drain of transistor M1e is connected to its gate. The source of transistor M1e is connected to node Bne. The transistor M1e transfers the frame signal Frame_e to the node Bne when the frame signal Frame_e is at high level, and turns off when the frame signal Frame_e is at low level. That is, the inverter circuit 21e is enabled when the frame signal Frame_e is at high level.

The gate of transistor M6e is connected to node Bne. The drain of transistor M6e is connected to node An. The source of the transistor M6e is connected to the power supply terminal supplied with the voltage Vgl. The transistor M6e has a function of pulling down the potential of the node An.

The gate of transistor M7e is connected to node An. The drain of transistor M7e is connected to node Bne. The source of the transistor M7e is connected to the power supply terminal supplied with the voltage Vgl. The transistor M7e has a function of pulling down the potential of the node Bne.

The gate of transistor M1b is connected to node An. One end of the current path of transistor M1b is connected to node Bno. The other end of the current path of transistor M1b is connected to node Bne. The transistor M1b connects the node Bno and the node Bne when the node An is at high level.

The output unit 22 is a circuit for outputting an output signal to the scanning line GL. The output unit 22 includes a transistor (also referred to as an output transistor) M3 and a capacitor Cb. The gate of transistor M3 is connected to node An. A clock signal Clk is input to the drain of the transistor M3. The clock signal Clk is either one of the clock signals ClkA and ClkB, the clock signal ClkA for the odd-numbered core circuits RG, and the clock signal ClkB for the even-numbered core circuits RG. The source of transistor M3 is connected to node Qn.

One electrode of capacitor Cb is connected to node An, and the other electrode of capacitor Cb is connected to node Qn. Node Qn is connected to corresponding scanning line GL.

The pull-down section 23 is a circuit for pulling down the potential of the node Qn. The pull-down section 23 includes two transistors (also referred to as pull-down transistors) M4o and M4e. The gate of transistor M4o is connected to node Bno. The drain of transistor M4o is connected to node Qn. A source of the transistor M4o is connected to a power supply terminal supplied with a voltage Vgl.

The gate of transistor M4e is connected to node Bne. The drain of transistor M4e is connected to node Qn. The source of the transistor M4e is connected to the power supply terminal supplied with the voltage Vgl.

The clearing unit 24 is a circuit for clearing the node An and the node Qn. The clear section 24 comprises two transistors M8 and M9. A clear signal CLR is input to the gate of the transistor M8 via a clear terminal CR. The drain of transistor M8 is connected to node Qn. The source of the transistor M8 is connected to the power supply terminal supplied with the voltage Vgl.

A clear signal CLR is input to the gate of the transistor M9 through a clear terminal CR. The drain of transistor M9 is connected to node An. A source of the transistor M9 is connected to a power supply terminal to which a voltage Vgl is supplied.

[1-2] Arrangement of Gate Driver GD Next, the arrangement of the gate driver GD will be described. FIG. 9 is a schematic diagram for explaining the arrangement area GA of the gate driver GD.

A region between the pixels PX adjacent in the X direction and a region between the pixels PX adjacent in the Y direction are used as the gate driver arrangement region GA.

The gate driver GD comprises a plurality of circuit elements (active elements) AE. The circuit element AE is composed of a transistor (TFT) and a capacitor. The circuit element AE is arranged in the gate driver arrangement area GA.

In the example of FIG. 9, the gate driver arrangement area GA is provided with wirings (referred to as An lines) forming the nodes An and power supply lines (referred to as Vgl lines) for supplying the voltage Vgl.

The arrangement of the register section 21, the output section 22, the clear section 24, the input section 20, and the pull-down section 23 included in the core circuit RG will be described below in this order.

[1-2-1] Arrangement of Register Unit 21 FIG. 10 is a layout diagram of the register unit 21. As shown in FIG. FIG. 10 shows seven pixels PX connected to one scanning line GL and a gate driver arrangement area GA for one row.

Transistors M1b, M1e, M1o, M6e, M6o, M7e, and M7o forming the register section 21 are arranged in the gate driver arrangement area GA. In addition, in the gate driver placement area GA, there are an An line, a Vgl line, a wire forming a node Bne (referred to as a Bne line), a wire forming a node Bno (referred to as a Bno line), and a wire supplying a frame signal Frame_e (Frame_e line). ), and a wiring for supplying a frame signal Frame_o (referred to as a Frame_o line). The connection relationship of the plurality of transistors forming the register section 21 is the same as in FIG.

Note that the width of the gate driver arrangement area GA is limited. Therefore, a transistor having one function is formed by connecting a plurality of transistors in parallel. In this manner, the size of each transistor is designed so that each transistor fits within the gate driver arrangement area GA.

[1-2-2] Arrangement of Output Unit 22 and Clear Unit 24 FIG. 11 is a layout diagram of the output unit 22 and the clear unit 24 . FIG. 11 shows ten pixels PX connected to two scanning lines GL and two rows of gate driver arrangement areas GA.

In the gate driver arrangement area GA, a transistor M3 and a capacitor Cb forming the output section 22 and transistors M8 and M9 forming the clear section 24 are arranged. Further, in the gate driver arrangement area GA, there are an An line, a Vgl line, a wiring for supplying a clock ClkA (referred to as a ClkA line), a wiring for supplying a clock ClkB (referred to as a ClkB line), and a wiring for supplying a clear signal CLR (CLR line) is arranged. The connection relationship of the plurality of elements forming the output section 22 and the clear section 24 is the same as in FIG.

Since the capacitor Cb is large in size, it is configured by connecting a plurality of capacitors in parallel. Although illustration is omitted, since the size of the output transistor M3 is also large, a plurality of transistors are connected in parallel.

Clocks ClkA and clocks ClkB are alternately supplied to a plurality of core circuits RG. FIG. 11 shows the output section 22 to which the clock ClkA is supplied and the output section 22 to which the clock ClkB is supplied.

[1-2-3] Arrangement of Input Unit 20 FIG. 12 is a layout diagram of the input unit 20. As shown in FIG. FIG. 12 shows six pixels PX connected to two scanning lines GL and two rows of gate driver arrangement areas GA.

The transistors M2 and M5 forming the input section 20 are arranged in the gate driver arrangement area GA. In the gate driver arrangement area GA, An lines, Vgl lines, wirings for supplying input signals VIN (called VIN lines), and wirings for supplying reset signals RST (called RST lines) are arranged. be. The connection relationship of the plurality of transistors forming the input section 20 is the same as in FIG.

An arbitrary scanning line GL is connected to the transistor M2 included in the subsequent input section 20 using the VIN line. An arbitrary scanning line GL is connected to the transistor M5 included in the input section 20 of the previous stage using the RST line.

[1-2-4] Arrangement of Pull-Down Section 23 FIG. 13 is a layout diagram of the pull-down section 23. As shown in FIG. FIG. 13 shows three pixels PX connected to one scanning line GL and a gate driver arrangement area GA for one row.

A transistor M4e forming the pull-down section 23 is arranged in the gate driver arrangement area GA. Also, An lines and Vgl lines are arranged in the gate driver arrangement area GA. Similarly to the transistor M4e, the transistor M4o forming the pull-down section 23 is also arranged in the gate driver arrangement area GA. The connection relationship of the plurality of transistors forming the pull-down section 23 is the same as in FIG.

[1-3] Wiring of Plurality of Divided Areas DI Next, the wiring of the plurality of division areas DI will be described.

FIG. 14 is a diagram illustrating wiring of a plurality of divided areas DI. A case where the display area 4 is composed of 9 (=3×3) divided areas DI_(1,1) to DI_(3,3) will be described below as an example.

Wiring to a plurality of divided areas DI is performed as follows.
- A gate driver GD is arranged for each divided area DI.
・Use only the Vgl line for the power supply wiring.
- The Frame_e line and the Frame_o line are wired as common signals for all screens.
・CLR lines are routed for each divided area DI.
The ST line (wiring for supplying the start signal ST), the ClkA line, and the ClkB line are wired for each divided area DI in the scanning line direction (X direction).

The start signal ST is composed of three start signals ST1 to ST3. The start signals ST1-ST3 are supplied using three lines ST1-ST3, respectively.

The clock signal ClkA is composed of three clock signals ClkA1 to ClkA3. The clock signals ClkA1-ClkA3 are provided using three ClkA1-ClkA3 lines, respectively.

The clock signal ClkB is composed of three clock signals ClkB1 to ClkB3. The clock signals ClkB1-ClkB3 are provided using three ClkB1-ClkB3 lines, respectively.

The clear signal CLR is composed of nine clear signals CLR11 to CLR33. The clear signals CLR11-CLR33 are provided using nine lines CLR11-CLR33.

The start signal ST1 is input to the divided areas DI_(1,1), DI_(1,2), and DI_(1,3) in the first row. The start signal ST2 is input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) in the second row. The start signal ST3 is input to the divided areas DI_(3,1), DI_(3,2), and DI_(3,3) on the third row. The nine divided areas DI_(1,1) to DI_(3,3) can be start-controlled on a row-by-row basis.

Clock signals ClkA1 and ClkB1 are input to the divided areas DI_(1,1), DI_(1,2), and DI_(1,3) in the first row. Clock signals ClkA2 and ClkB2 are input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) in the second row. Clock signals ClkA3 and ClkB3 are input to the divided areas DI_(3,1), DI_(3,2), and DI_(3,3) in the third row. The nine divided areas DI_(1,1) to DI_(3,3) can be clock-controlled in row units.

The nine clear signals CLR11 to CLR33 are input to the nine divided areas DI_(1,1) to DI_(3,3), respectively. Nine divided areas DI_(1,1) to DI_(3,3) stop scanning individually using nine clear signals CLR11 to CLR33 to prevent data from being rewritten (display ) is possible.

A frame signal Frame_e is input to all the divided areas DI. A frame signal Frame_o is input to all the divided areas DI. The Vgl line is wired to all divided areas DI.

[1-4] Example of Display Area 4 Next, an example of the display area 4 will be described. FIG. 15 is a schematic diagram illustrating an example of the display area 4. As shown in FIG. Let the row number m of the divided area DI, the column number n of the divided area DI, and the scanning line number i within the divided area DI be.

The display area 4 has, for example, (480×640) pixels. The display area 4 has nine divided areas DI_(1,1) to DI_(3,3).

Each divided area DI has 160 scanning lines. The number of columns of the divided areas DI in the first column is 213 . The number of columns of the divided areas DI in the second column is 214. The number of columns of the divided areas DI in the third column is 213. The number of columns in the divided regions DI corresponds to the number of source lines SL.

[1-5] Operation The operation of the liquid crystal display device 1 configured as described above will be described.

[1-5-1] Scanning Operation of Display Area 4 First, the scanning operation of one divided area DI will be described. FIG. 16 is a timing chart for explaining the scanning operation of the divided area DI.

Control circuit 15 receives signal Vsync from the outside. A period from when the signal Vsync once becomes low level to when it becomes low level again (or a period during which the signal Vsync is high level) is one frame. One frame is a period during which all scanning lines included in the sub-array SA are scanned once, and a period during which one image is displayed in the divided area DI.

Clock signals ClkAm, ClkBm, start signal STm, and clear signal CLRmn are input to an arbitrary divided area DI_(m, n).

In response to the low level of the signal Vsync, the control circuit 15 inputs the start signal STm to the divided area DI_(m,n). In response to the start signal STm, the gate driver GD_(m,n) starts scanning operation.

The control circuit 15 inputs the clock signals ClkAm and ClkBm to the divided areas DI_(m,n). Clock signal ClkAm and clock signal ClkBm have a complementary phase relationship. In response to the clock signals ClkAm and ClkBm, the gate driver GD_(m,n) performs a scanning operation, that is, turns a plurality of scanning lines GL to high level in sequence.

After the last scanning line GLi becomes high level, the control circuit 15 makes the clear signal CLRmn high level. As a result, the shift register SR of the gate driver GD_(m,n) is cleared, that is, the output of the shift register SR becomes low level. In this way, the data in the divided area DI_(m,n) is rewritten.

Next, the scanning stop operation for one divided area DI will be described. FIG. 17 is a timing chart for explaining the scanning stop operation of the divided area DI. FIG. 17 shows the operation of a divided area in which data is not rewritten among the divided areas in the same row to which the start signal STm is input.

In response to the low level of the signal Vsync, the control circuit 15 inputs the start signal STm to the divided area DI_(m,n). Subsequently, the control circuit 15 inputs the clear signal CLRmn to the divided area DI_(m,n) immediately after the start signal STm. As a result, the start signal STm can be substantially invalidated. After that, no pulse is input to the scanning line GL. In this case, the divided area DI_(m,n) is not scanned and is kept displayed.

[1-5-2] Drive Pattern Next, the drive pattern of the liquid crystal display device 1 will be described. As an example, m=3 and n=3, that is, the operation of nine divided areas DI_(1,1) to DI_(3,3) will be described below.

FIG. 18 is a schematic diagram for explaining the drive pattern 1 of the liquid crystal display device 1. As shown in FIG. The control circuit 15 validates (high level) the start signal ST1 in the first frame. The control circuit 15 enables (high level) the clear signals CLR11, CLR12, and CLR13 at the time when the first frame ends. As a result, the scanning operation of the divided areas DI_(1,1) to DI_(1,3) in the first row is performed.

The control circuit 15 validates the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR21, CLR22, and CLR23 at the time when the second frame ends. As a result, the scanning operation of the divided areas DI_(2,1) to DI_(2,3) in the second row is performed.

The control circuit 15 validates the start signal ST3 in the third frame following the second frame. The control circuit 15 enables the clear signals CLR31, CLR32, and CLR33 at the time when the third frame ends. As a result, the scanning operation of the divided areas DI_(3,1) to DI_(3,3) in the third row is performed.

19A and 19B are schematic diagrams for explaining the drive pattern 2 of the liquid crystal display device 1. FIG. The control circuit 15 validates the start signal ST1 in the first frame. The control circuit 15 validates the clear signals CLR12 and CLR13 immediately after the start signal ST1. This stops the scanning of the divided areas DI_(1,2) and DI_(1,3). The control circuit 15 validates the clear signal CLR11 at the time when the first frame ends. In this way, the scanning operation of the divided area DI_(1,1) is executed, and the data of the divided area DI_(1,1) is rewritten. Also, the divided areas DI_(1,2) and DI_(1,3) hold the display.

The control circuit 15 validates the start signal ST2 in the second frame following the first frame. The control circuit 15 validates the clear signals CLR22 and CLR23 immediately after the start signal ST2. This stops the scanning of the divided areas DI_(2,2) and DI_(2,3). The control circuit 15 validates the clear signal CLR21 at the time when the second frame ends. In this way, the scanning operation of the divided area DI_(2,1) is executed, and the data of the divided area DI_(2,1) is rewritten. Also, the divided areas DI_(2,2) and DI_(2,3) hold the display.

Similarly, the start signal STm is activated, and any divided area DI included in the m row performs the scanning operation. Also, the clear signal CLR corresponding to the remaining divided areas DI included in the m row is validated, and the scanning of the remaining divided areas DI is stopped.

As a result, the first to ninth frames are driven in order, and the data in the divided areas DI_(1,1) to DI_(3,3) are rewritten.

Note that FIGS. 18 and 19 show an example of rewriting the data of all the divided areas DI. By controlling the start signal ST and the clear signal CLR, it is possible to display an image in the display area 4 by skipping the scanning of an arbitrary divided area DI.

[1-5-3] Operation of Shift Register SR Next, the operation of the shift register SR will be described. FIG. 20 is a timing chart explaining the operation of the shift register SR. As shown in FIG. 7, frame signals Frame_o and Frame_e are input to the shift register SR.

The frame signals Frame_o and Frame_e are alternately enabled (high level) every arbitrary frame, with the minimum unit being one frame. The two inverter circuits 21o and 21e alternately operate according to the frame signals Frame_o and Frame_e. The control circuit 15 switches the states of the frame signals Frame_o and Frame_e while the signal Vsync is at low level.

As an example, it is assumed that the frame signal Frame_o is validated (high level). The frame signal Frame_e is at low level. When the frame signal Frame_o becomes high level, the transistor M1o of the inverter circuit 21o is turned on and the inverter circuit 21o is enabled. The transistor M1e of the inverter circuit 21e is turned off, and the inverter circuit 21o is disabled.

After the frame signal Frame_o becomes high level, the start signal ST is made high level. As a result, the input signal VIN of the first-stage core circuit RG1 becomes high level. Then, the transistor M2 of the input section 20 is turned on, and the node An becomes high level.

When the node An becomes high level, the transistor M7o of the inverter circuit 21o is turned on, and the node Bno becomes low level. That is, the inverter circuit 21o holds the inverted data of the node An at the node Bno. As a result, the transistor M4o of the pull-down section 23 is turned off, and the pull-down operation of the node Qn stops.

Further, when the node An becomes high level, the transistor M3 of the output section 22 is turned on. Subsequently, the clock signal ClkA becomes high level. Then, the scanning line GL1 becomes high level.

The second-stage core circuit RG2 receives an output signal from the preceding-stage core circuit RG1 as an input signal VIN. Subsequently, the clock signal ClkB becomes high level. Then, the core circuit RG2 turns the scanning line GL2 to high level.

The core circuit RG1 of the first stage receives the output signal of the core circuit RG2 of the second stage as the reset signal RST. A reset signal RST is input to the gate of the transistor M5 of the input section 20 . Then, the transistor M5 is turned on and the node An becomes low level.

When the node An becomes low level, the transistor M7o of the inverter circuit 21o is turned off, and the node Bno becomes high level. That is, the inverter circuit 21o holds the inverted data of the node An at the node Bno. When the node Bno becomes high level, the transistor M6o turns on and the node An is held low level. As a result, the transistor M4o of the pull-down section 23 is turned on, and the node Qn becomes low level.

Further, when the node An becomes low level, the transistor M3 of the output section 22 is turned off. As a result, the scanning line GL1 becomes low level.

As a detailed design, adjacent core circuits RG are prevented from operating at the same time. For this reason, the edges of the clock signal ClkA and the pulses of the clock signal ClkB are spaced apart so that they do not overlap.

Similarly, core circuits RG3 to RGi sequentially output pulse signals.

After the final-stage core circuit RGi outputs the pulse signal, the clear signal CLR is set to high level. When the clear signal CLR becomes high level, the transistors M8 and M9 of the clear section 24 are turned on. Then, the node Qn and the node An become low level. As a result, the core circuit RGi sets the scanning line GLi to low level.

After that, the frame signal Frame_e is set to high level, and the frame signal Frame_o is set to low level. Then, the inverter circuit 21e of the core circuit RG is enabled. After that, the scanning operation by the shift register SR is repeated.

Such an operation can eliminate a transistor to which a positive bias is continuously applied in the core circuit RG. As a result, it is possible to suppress the deterioration of the characteristics of the transistors forming the core circuit RG. In particular, when a TFT is used as a transistor, the threshold voltage Vth shifts when a positive bias is continuously applied. However, in this embodiment, it is possible to suppress deterioration of TFT characteristics.

[1-5-4] Operation of Core Circuit RG Next, the operation of the core circuit RG included in the shift register SR will be described. The selection period is a period during which the scanning line is selected and a period during which the scanning line outputs a pulse signal. The non-selection period is a period other than the selection period, and is a period during which the scanning line does not output the pulse signal.

FIG. 21 is a schematic diagram for explaining the inverter operation of the core circuit RG during the selection period. As an example, it is assumed that the frame signal Frame_o is enabled (high level (“Hi” in FIG. 21)) and the inverter circuit 21o performs inverter operation. The frame signal Frame_e is at low level (“Lo” in FIG. 21).

An input signal VIN at a high level ("ON" in FIG. 21) is input to the gate of the transistor M2 from the core circuit RG in the previous stage. Therefore, the transistor M2 is turned on, and the node An becomes high level ("Hi" in FIG. 21).

A high-level frame signal Frame_o is input to the gate of the transistor M1o. Therefore, the transistor M1o is turned on, and the inverter circuit 21o is enabled.

Since node An is at a high level, transistor M7o is turned on and node Bno is pulled down. Arrows in FIG. 21 represent currents.

Furthermore, the transistor M7e of the inverter circuit 21e can also be operated for the inverter operation during the selection period. That is, since the node An is at high level, the transistors M1b and M7e are on. Therefore, node Bno is also pulled down through the path of transistor M1b, node Bne, and transistor M7e. This ensures that node Bno is set to a low level.

The drive capability of the transistor M6o is set to be greater than the drive capability of the transistor M7o. During the non-selection period, the node An is pulled down by the transistor M6o, and the node An can be reliably set to a low level.

As conditions for realizing the inverter operation, the transistors M6 and M7 are set to satisfy the following conditions. The transistor M6 means the transistors M6o and M6e respectively, and the transistor M7 means the transistors M7o and M7e respectively. Channel widths of the transistors M6 and M7 are denoted as W6 and W7, respectively. Channel width is also called gate width.

W7≦W6≦2×W7
By setting “W6≦2×W7”, the combined drive capability of the transistors M7o and M7e becomes greater than the drive capability of the transistor M6o (or the transistor M6e). This ensures that the node Bno is set to a low level during the selection period.

By setting “W7≦W6”, the drive capability of the transistor M6 becomes greater than the drive capability of the transistor M7. As a result, the node An can be reliably set to a low level during the non-selection period.

Focus on the inverter circuit included in the core circuit RG near the final stage. The potential of the node Bne of the invalidated inverter circuit (for example, the inverter circuit 21e) among the inverter circuits 21o and 21e decreases due to the leakage current of the transistor M1e. Therefore, in the core circuit RG near the final stage, the transistor M1b is turned on during the selection period, so that the node Bno on the enabled side becomes conductive with the node Bne. It's becoming

[1-6] Effect of First Embodiment In the first embodiment, the display area 4 is divided into a plurality of divided areas DI arranged in a matrix. A sub-array SA and a gate driver GD are arranged in each of the plurality of divided regions DI. Thereby, the liquid crystal display device 1 capable of narrowing the frame can be realized. Further, the display area 4 can be divided and driven for each divided area DI. In addition, scanning can be freely performed for each divided area DI.

In addition, by scanning each divided area DI, the frame frequency can be lowered compared to scanning the entire screen as one frame. This reduces power consumption due to charging and discharging by the clock signal. Furthermore, since the writing time for writing data (driving voltage) to the pixel can be extended, the current for driving the TFT included in the pixel can be reduced, and the size of the TFT can be reduced. As a result, the current supplied to the scanning line GL and the signal line SL can be reduced, so that power consumption can be reduced.

Further, the clock signals ClkA and ClkB can be driven by time division for each divided area DI. As a result, power consumption can be reduced compared to the case where the clock signal is supplied to the entire screen.

Each core circuit RG includes two inverter circuits 21o and 21e, and the inverter circuits 21o and 21e are alternately enabled according to frame signals Frame_o and Frame_e. Therefore, it is possible to prevent the voltage from being continuously applied to the transistors (for example, TFTs) forming the shift register SR. As a result, a gate driver GD with a high withstand voltage can be realized.

[2] Second Embodiment The second embodiment is another example regarding the wiring of the display area 4 . In the second embodiment, a different clock signal is wired for each column of the divided areas DI.

[2-1] Wiring of Multiple Divided Areas DI FIG. 22 is a diagram for explaining the wiring of multiple divided areas DI according to the second embodiment. A case where the display area 4 is composed of 9 (=3×3) divided areas DI_(1,1) to DI_(3,3) will be described below as an example.

Wiring to a plurality of divided areas DI is performed as follows.
- A gate driver GD is arranged for each divided area DI.
・Use only the Vgl line for the power supply wiring.
- The Frame_e line and the Frame_o line are wired as common signals for all screens.
・CLR lines are routed for each divided area DI.
・The ST line is wired for each divided area DI in the scanning line direction (X direction).
- The ClkA line and the ClkB line are wired for each divided area DI in the signal line direction (Y direction).

The start signal ST is composed of three start signals ST1 to ST3. The start signals ST1-ST3 are supplied using three lines ST1-ST3, respectively.

The clock signal ClkA is composed of three clock signals ClkA1 to ClkA3. The clock signals ClkA1-ClkA3 are provided using three ClkA1-ClkA3 lines, respectively.

The clock signal ClkB is composed of three clock signals ClkB1 to ClkB3. The clock signals ClkB1-ClkB3 are provided using three ClkB1-ClkB3 lines, respectively.

The clear signal CLR is composed of nine clear signals CLR11 to CLR33. The clear signals CLR11-CLR33 are provided using nine lines CLR11-CLR33.

The start signal ST1 is input to the divided areas DI_(1,1), DI_(1,2), and DI_(1,3) in the first row. The start signal ST2 is input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) in the second row. The start signal ST3 is input to the divided areas DI_(3,1), DI_(3,2), and DI_(3,3) on the third row. The nine divided areas DI_(1,1) to DI_(3,3) can be start-controlled on a row-by-row basis.

The clock signals ClkA1 and ClkB1 are input to the divided areas DI_(1,1), DI_(2,1), and DI_(3,1) in the first column. The clock signals ClkA2 and ClkB2 are input to the divided areas DI_(1,2), DI_(2,2) and DI_(3,2) in the second column. The clock signals ClkA3 and ClkB3 are input to the divided areas DI_(1,3), DI_(2,3), and DI_(3,3) in the third column. The nine divided areas DI_(1,1) to DI_(3,3) can be clock-controlled in column units.

The nine clear signals CLR11 to CLR33 are input to the nine divided areas DI_(1,1) to DI_(3,3), respectively. Nine divided areas DI_(1,1) to DI_(3,3) stop scanning individually using nine clear signals CLR11 to CLR33 to prevent data from being rewritten (display ) is possible.

A frame signal Frame_e is input to all the divided areas DI. A frame signal Frame_o is input to all the divided areas DI. The Vgl line is wired to all divided areas DI.

[2-2] Scanning Operation of Display Area 4 Next, the scanning operation of one divided area DI will be described. FIG. 23 is a timing chart for explaining the scanning operation of the divided area DI.

Control circuit 15 receives signal Vsync from the outside. Clock signals ClkAm, ClkBm, start signal STm, and clear signal CLRmn are input to an arbitrary divided area DI_(m, n). The scanning operation of the divided area DI is the same as in FIG. 16 of the first embodiment.

Next, the scanning stop operation for one divided area DI will be described. FIG. 24 is a timing chart for explaining the scanning stop operation of the divided area DI. FIG. 24 shows the operation of a divided area in which data is not rewritten among the divided areas in the same row to which the start signal STm is input.

In response to the low level of the signal Vsync, the control circuit 15 inputs the start signal STm to the divided area DI_(m,n). Subsequently, the control circuit 15 inputs the clear signal CLRmn to the divided area DI_(m,n) immediately after the start signal STm. As a result, the start signal STm can be substantially invalidated. After that, no pulse is input to the scanning line GL. In this case, the divided area DI_(m,n) is not scanned and is kept displayed.

Divided areas DI adjacent in the row direction operate with different clock signals ClkA (and different clock signals ClkB). As shown in FIG. 24, the clock signal is not input to the divided areas in which the data is not rewritten among the divided areas adjacent to each other in the row direction.

Also in the liquid crystal display device 1 according to the second embodiment, the drive pattern described in the first embodiment can be executed. The effect of the second embodiment is also the same as that of the first embodiment.

[3] Third Embodiment In the third embodiment, some of the plurality of divided areas obtained by dividing the display area 4 are configured as non-display areas in which no image is displayed.

FIG. 25 is a schematic diagram of the display area 4 according to the third embodiment. FIG. 25 shows an example in which the display area 4 has nine divided areas.

The display area 4 includes one or more non-display areas ND. FIG. 25 shows an example in which the display area 4 includes three non-display areas ND. Pixels and gate drivers are not provided in the non-display area ND.

The display area 4 includes six divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3). ). A sub-array SA and a gate driver GD are arranged in the divided area DI.

FIG. 26 is a schematic diagram for explaining the drive pattern 1 of the liquid crystal display device 1. As shown in FIG. In FIG. 26, for example, it is assumed that the wiring of the display area 4 in the first embodiment is provided. No signal line is wired in the non-display area ND.

The control circuit 15 validates (high level) the start signal ST1 in the first frame. The control circuit 15 enables (high level) the clear signals CLR12 and CLR13 at the time when the first frame ends. Thereby, the scanning operation of the divided areas DI_(1,2) and DI_(1,3) in the first row is performed.

The control circuit 15 validates the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR21 and CLR23 at the time when the second frame ends. Thereby, the scanning operation of the divided areas DI_(2,1) and DI_(2,3) in the second row is performed.

The control circuit 15 validates the start signal ST3 in the third frame following the second frame. The control circuit 15 enables the clear signals CLR31 and CLR32 at the time when the third frame ends. As a result, the scanning operation of the divided areas DI_(3,1) and DI_(3,2) in the third row is performed.

27A and 27B are schematic diagrams for explaining the drive pattern 2 of the liquid crystal display device 1. FIG. In FIG. 27, for example, it is assumed that the wiring of the display area 4 in the second embodiment is provided. No signal line is wired in the non-display area ND.

The control circuit 15 validates the start signal ST2 in the first frame. The control circuit 15 validates the clear signal CLR23 immediately after the start signal ST2. This stops the scanning of the divided area DI_(2,3). The control circuit 15 validates the clear signal CLR21 at the time when the first frame ends. In this way, the scanning operation of the divided area DI_(2,1) is executed, and the data of the divided area DI_(2,1) is rewritten. Also, the divided area DI_(2,3) holds the display.

The control circuit 15 validates the start signal ST3 in the second frame following the first frame. The control circuit 15 validates the clear signal CLR32 immediately after the start signal ST3. This stops the scanning of the divided area DI_(3,2). The control circuit 15 validates the clear signal CLR31 at the time when the second frame ends. In this way, the scanning operation of the divided area DI_(3,1) is executed, and the data of the divided area DI_(3,1) is rewritten. Also, the divided area DI_(3,2) holds the display.

Similarly, the start signal STm is activated, and any divided area DI included in the m row performs the scanning operation. Also, the clear signal CLR corresponding to the remaining divided areas DI included in the m row is validated, and the scanning of the remaining divided areas DI is stopped.

As a result, six divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3) are The data of the divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3) and DI_(2,3) are driven in order. can be rewritten.

The non-display area ND is always displayed in black, for example. Alternatively, the non-display area ND may be displayed in a color other than black by arranging a color filter of a desired color in the non-display area ND.

In the third embodiment, a gate driver GD is arranged for each divided area DI. Therefore, even if a non-display area ND is provided between the divided areas DI in the column direction, all the divided areas DI can be scanned using the gate driver GD.

Also, in the third embodiment, a non-rectangular non-rectangular display can be realized. In addition, irregular shaped displays can be optimally driven.

In each of the above-described embodiments, the case where all the transistors are N-type transistors has been described. However, not limited to this, by inverting the polarities of the power supply voltage and the clock signal, it is possible to configure all the transistors with P-type transistors.

Also, the shift register SR included in the gate driver GD is not limited to the configuration described in each of the above embodiments. It is also possible to use other types of shift registers capable of sequentially outputting pulses to a plurality of scanning lines GL.

Further, in each of the above embodiments, a liquid crystal display device is described as an example of a display device. However, it is not limited to this, and can be applied to other display devices such as an organic EL display device.

The present invention is not limited to the above-described embodiments, and can be modified in various ways without departing from the scope of the present invention at the implementation stage. Further, each embodiment may be implemented in combination as appropriate, in which case the combined effect can be obtained. Furthermore, various inventions are included in the above embodiments, and various inventions can be extracted by combinations selected from a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, if the problem can be solved and effects can be obtained, the configuration with the constituent elements deleted can be extracted as an invention.

Reference Signs List 1 Liquid crystal display device 2 TFT substrate 3 Integrated circuit 4 Display area 10 Pixel array 11 Gate driver group 12 Source driver 13 Common electrode driver 14 Voltage generating circuit 15 Control circuit 16 Switching element 20 Input unit 21 Register unit 21e, 21o Inverter circuit 22 Output unit 23 Pull-down unit 24 Clear unit SR Shift register RG Core circuit .

Claims (12)

a display area having a plurality of divided areas arranged in a matrix;
a pixel array having a plurality of sub-arrays respectively arranged in the plurality of divided regions, each of the plurality of sub-arrays having a plurality of pixels;
a plurality of scanning lines provided in each of the plurality of sub-arrays and extending in a first direction;
a plurality of signal lines provided in the pixel array so as to be commonly connected to the sub-array groups in each column and extending in a second direction intersecting the first direction;
a plurality of gate drivers respectively arranged in the plurality of divided regions and each connected to the plurality of scanning lines;
a source driver connected to the plurality of signal lines;
a control circuit capable of controlling the plurality of gate drivers and the source drivers and individually driving the plurality of sub-arrays;
A display device comprising: a display area having a plurality of divided areas arranged in a matrix;
a non-display area provided in at least one divided area among the plurality of divided areas and in which no pixels are arranged;
a pixel array having a plurality of sub-arrays arranged respectively in the remaining divided regions, each of the plurality of sub-arrays having a plurality of pixels;
a plurality of scanning lines provided in each of the plurality of sub-arrays and extending in a first direction;
a plurality of signal lines provided in the pixel array so as to be commonly connected to the sub-array groups in each column and extending in a second direction intersecting the first direction;
a plurality of gate drivers respectively arranged in the remaining divided regions and each connected to the plurality of scanning lines;
a source driver connected to the plurality of signal lines;
a control circuit capable of controlling the plurality of gate drivers and the source drivers and individually driving the plurality of sub-arrays;
A display device comprising: 3. The display device according to claim 1, wherein the control circuit sequentially drives sub-array groups arranged in the column direction. 4. The display device according to any one of claims 1 to 3, wherein the control circuit simultaneously drives sub-array groups arranged in the row direction. 5. The display device according to any one of claims 1 to 4, wherein a start signal for starting scanning is commonly input to the gate driver group of each row. 6. The display device according to any one of claims 1 to 5, wherein a clock signal is commonly input to a group of gate drivers in each row. 6. The display device according to any one of claims 1 to 5, wherein a clock signal is commonly input to a group of gate drivers for each column. The display device according to claim 5, wherein a clear signal for stopping scanning is input for each of the plurality of gate drivers. 9. The display according to claim 8, wherein the control circuit inputs the clear signal immediately after inputting the start signal to the first gate driver to stop rewriting data to the sub-array connected to the first gate driver. Device. each of the plurality of gate drivers includes a shift register having a plurality of cascaded core circuits;
each of the plurality of core circuits,
an input unit that transfers an input signal corresponding to the output signal of the preceding core circuit to the first node;
a first inverter circuit enabled by a first frame signal and holding an inverted signal of the first node at a second node;
and a second inverter circuit enabled by a second frame signal complementary to said first frame signal and holding at a third node the inverted signal of said first node. Display device as described. The core circuit includes an output section,
the output unit includes an output transistor and a capacitor;
the output transistor has a gate connected to the first node, a first terminal for receiving a clock signal, and a second terminal connected to a scan line;
11. The display device according to claim 10, wherein the capacitor has a first electrode connected to the first node and a second electrode connected to the scanning line. The odd-numbered core circuits receive the first clock signal,
12. The display device of claim 11, wherein even-numbered core circuits receive a second clock signal that is complementary to the first clock signal.

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