JP2022147402A - Nitride semiconductor device - Google Patents

Abstract

To provide a nitride semiconductor device that can be suppressed from varying in threshold voltage while suppressing a gate insulation film from decreasing dielectric breakdown voltage.SOLUTION: A nitride semiconductor device comprises a gallium nitride layer, a gate insulation film provided on the gallium nitride layer, and a gate electrode provided on the gate insulation film. The gate insulation film has a first insulation film provided on the gallium nitride layer, a second insulation film provided on the first insulation film, and a third insulation film provided on the second insulation film. The first insulation film is an aluminum nitride film. The second insulation film is an AlxSiyO film (x>y≥0). The third insulation film is an Alx'Siy'O film (0≤x'<y').SELECTED DRAWING: Figure 2

Description

The present invention relates to nitride semiconductor devices.

In order to realize a GaN-MOSFET with excellent electrical characteristics, it is important to suppress variations in threshold voltage. However, in the conventional method, Ga—O bonds are formed at the interface between gallium nitride (GaN) and the gate insulating film, resulting in many hole traps, making it difficult to suppress fluctuations in threshold voltage. .

Also, in HEMTs, a technique of forming a thin aluminum nitride (AlN) film on GaN and forming an aluminum oxide (Al ₂ O ₃ ) film or a silicon oxide (SiO ₂ ) film thereon is known (for example, , Patent Document 1). However, when the Al ₂ O ₃ film is formed on the AlN film, the dielectric breakdown voltage of the gate insulating film may decrease. In addition, when forming a _SiO2 film on AlN, an interface level is formed at the interface between AlN and _SiO2 , which may result in insufficient reduction of hole traps.

JP 2016-143842 A

In a GaN-MOSFET, there is a demand for a technique capable of suppressing variations in threshold voltage while suppressing a decrease in dielectric breakdown voltage of a gate insulating film.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a nitride semiconductor device capable of suppressing variations in threshold voltage while suppressing a decrease in dielectric breakdown voltage of a gate insulating film. With the goal.

To solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer, a gate insulating film provided on the gallium nitride layer, and a gate provided on the gate insulating film. an electrode; The gate insulating film includes a first insulating film provided on the gallium nitride layer, a second insulating film provided on the first insulating film, and a third insulating film provided on the second insulating film. a membrane; The first insulating film is an aluminum nitride film. The second insulating film is an AlxSiyO film (x>y≧0). The third insulating film is an Alx'Siy'O film (0≤x'<y').

ADVANTAGE OF THE INVENTION According to this invention, the nitride semiconductor device which can suppress the fluctuation|variation of a threshold voltage can be provided, suppressing the fall of the dielectric breakdown voltage resistance of a gate insulating film.

FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 1 of the present invention. FIG. 3 is a flow chart showing the manufacturing method of the GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 4 is a model diagram showing the bonding state of atoms according to Embodiment 1 of the present invention, and is a model diagram showing the bonding state of atoms among GaN, AlN and Al ₂ O ₃ . FIG. 5 is a diagram showing energy bands at the AlN/Al ₂ O ₃ interface shown in FIG. FIG. 6 is a model diagram showing the bonding state of atoms according to a comparative example of the present invention, and is a model diagram showing the bonding state of atoms among GaN, AlN and SiO ₂ . FIG. 7 is a diagram showing energy bands at the AlN/SiO ₂ interface shown in FIG. FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 2 of the present invention. FIG. 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 3 of the present invention.

Embodiments of the present invention are described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it goes without saying that there are portions with different dimensional relationships and ratios between the drawings.

In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction or Y-axis direction is a direction parallel to the surface 12a of the GaN layer 12 . The X-axis direction, the Y-axis direction, or both the X-axis direction and the Y-axis direction may be called horizontal directions. The Z-axis direction is the normal direction of the surface 12 a of the GaN layer 12 . The Z-axis direction is also the thickness direction of the GaN layer 12 . The X-axis direction, Y-axis direction and Z-axis direction are orthogonal to each other.

Further, in the following description, the direction of the Z-axis arrow may be referred to as "up", and the direction opposite to the Z-axis arrow may be referred to as "down". "Upper" and "lower" do not necessarily mean perpendicular to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely expedient expressions specifying relative positional relationships among regions, layers, films, substrates, etc., and do not limit the technical idea of the present invention. For example, if the paper surface is rotated 180 degrees, it goes without saying that "top" becomes "bottom" and "bottom" becomes "top".

Also, in the following description, p or n means that holes or electrons are the majority carriers, respectively. Moreover, + and - attached to p and n mean semiconductor regions having relatively high or low impurity concentrations, respectively, compared to semiconductor regions not marked with + and -. However, even if the semiconductor regions are given the same p and p (or n and n), it does not mean that the impurity concentration of each semiconductor region is exactly the same.

<Embodiment 1>
(Configuration example)
FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device 100 according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing a configuration example of the GaN semiconductor device 100 according to Embodiment 1 of the present invention. FIG. 2 shows a cross section of the plan view of FIG. 1 taken along line X1-X'1.
A GaN semiconductor device 100 shown in FIGS. 1 and 2 is, for example, a power semiconductor device, and includes a gallium nitride substrate (hereinafter referred to as a GaN substrate) 10 and a plurality of vertical MOSFETs 1 provided on the GaN substrate 10 . In the GaN semiconductor device 100, vertical MOSFETs 1 are repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeating unit structure, and these unit structures are arranged side by side in one direction (for example, the X-axis direction).

A region provided with a plurality of unit structures is called an active region. Although not shown, an edge termination structure is provided around the active region to prevent electric field crowding in the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure and a JTE (Junction On Termination On ExtenSiOn) structure.
As shown in FIGS. 1 and 2, the vertical MOSFET 1 includes a gate insulating film 5 provided on a GaN substrate 10, a gate electrode 6 provided on the gate insulating film 5, and a gate electrode 6 provided on the GaN substrate 10. It has a source electrode 7 and a drain electrode 8 .

The GaN substrate 10 has, for example, a GaN single crystal substrate 11 and a GaN layer 12 (an example of the “gallium nitride layer” of the present invention) provided on the GaN single crystal substrate 11 . As shown in FIG. 1, surface 12a of GaN layer 12 is also surface 10a of GaN substrate 10 . A back surface 12 b of the GaN layer 12 opposite to the front surface 12 a is in contact with the GaN single crystal substrate 11 . Back surface 11 b of GaN single crystal substrate 11 is also back surface 10 b of GaN substrate 10 .
The conductivity type of the GaN single crystal substrate 11 is, for example, the n+ type. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements selected from Si (silicon), O (oxygen) and Ge (germanium). The impurity concentration of O in the GaN single crystal substrate 11 is 2×10 ¹⁸ /cm ³ or more.

The GaN single crystal substrate 11 may be a low dislocation free-standing substrate having a dislocation density of less than 1E+7/cm ² . Since the GaN single crystal substrate 11 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Further, by using a low-dislocation self-supporting substrate for the GaN single-crystal substrate 11, even when a large-area power device is formed on the GaN single-crystal substrate 11, leakage current in the power device can be reduced. As a result, the manufacturing apparatus can manufacture power devices with a high non-defective product rate. Further, in the heat treatment, it is possible to prevent the ion-implanted impurities from diffusing deeply along the dislocations. Note that E+ is exponential notation. For example, 1E+7 means 1×10 ⁷ .

GaN layer 12 is provided on GaN single crystal substrate 11 . The GaN layer 12 is an n− type GaN single crystal layer, and is a layer formed on the GaN single crystal substrate 11 by an epitaxial growth method. The n-type dopant (n-type impurity) contained in the GaN layer 12 is one or more elements selected from Si (silicon), O (oxygen), and Ge (germanium).
A p − type well region 13 , an n + type source region 14 , and a p + type contact region 16 are provided on the surface 12 a side of the GaN layer 12 . A region of the GaN layer 12 where the well region 13, the source region 14 and the contact region 16 are not provided may be called a drift region. The drift region functions as a current path between GaN single crystal substrate 11 and well region 13 .

The well region 13 is formed by ion-implanting a p-type dopant (p-type impurity) from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. A p-type dopant is, for example, magnesium (Mg). Well region 13 faces surface 12 a of GaN layer 12 . Also, the well region 13 has a first side surface adjacent to the source region 14 and a second side surface adjacent to the drift region immediately below the gate insulating film 5 in the horizontal direction. In the well region 13, the channel of the vertical MOSFET 1 is formed between the first side and the second side and at the contact interface with the gate insulating film 5 and its vicinity. A region in which a channel is formed in the well region 13 is hereinafter referred to as a channel region CR.

For example, the channel region CR is located within 20 nm from the surface 12a in contact with the gate insulating film 5 toward the back surface 12b. The concentration of the p-type dopant (for example, Mg) in the channel region CR is higher than that of the n-type dopant contained in the channel region CR, for example 1E+16/cm ³ or more.

The source region 14 is formed by ion-implanting an n-type dopant from the surface 12a side of the GaN layer 12 and activating the n-type dopant by heat treatment. The n-type dopant is, for example, one or more of Si, O and Ge. Source region 14 faces surface 12 a of GaN layer 12 and is located inside well region 13 . The sides and bottom of source region 14 contact well region 13 . The source region 14 and the well region 13 are in contact with each other in the X-axis direction, the Y-axis direction, and the Z-axis direction.

The p+ type contact region 16 is formed by ion-implanting a p-type dopant from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. A p-type dopant is, for example, Mg. Contact region 16 faces surface 12 a of GaN layer 12 and is located inside well region 13 . At least the bottom of contact region 16 is in contact with well region 13 . The contact region 16 and the well region 13 are in contact with each other in the Z-axis direction.

As shown in FIG. 2, the gate insulating film 5 includes a first insulating film 51 provided on the GaN layer 12, a second insulating film 52 provided on the first insulating film 51, and a second insulating film 52. and a third insulating film 53 provided thereon. That is, first insulating film 51 is in contact with surface 12 a of GaN layer 12 including well region 13 . The second insulating film 52 is located between the first insulating film 51 and the gate electrode 6 and is in contact with the surface of the first insulating film 51 . The third insulating film 53 is located between the second insulating film 52 and the gate electrode 6 and is in contact with the surface of the second insulating film 52 . The first insulating film 51 , the second insulating film 52 and the third insulating film 53 are stacked in this order to form the gate insulating film 5 .

The first insulating film 51 is an aluminum nitride (AlN) film. For example, the AlN film is formed with a thickness of 0.5 nm or more and 5 nm or less by an ALD (Atomic Layer Deposition) method, and is formed with a thickness of 2 nm, for example. The thickness of the AlN film is preferably 5 nm or less because cracks may occur if the AlN film is too thick.

The second insulating film 52 is an AlxSiyO film (x>y≧0), for example, an aluminum oxide (Al ₂ O ₃ ) film. For example, the Al ₂ O ₃ film is formed with a thickness of 2 nm by the ALD method.
The third insulating film 53 is an Alx'Siy'O film (0≤x'<y'), for example, a silicon oxide ( _SiO2 ) film. For example, the SiO ₂ film is formed with a thickness of 100 nm by CVD (Chemical Vapor Deposition).

A gate electrode 6 is provided on the gate insulating film 5 . The gate electrode 6 is a planar electrode provided on the flat gate insulating film 5 . The gate electrode 6 is made of, for example, Al or an Al--Si alloy. Alternatively, the gate electrode 6 may be composed of impurity-doped polysilicon.

The source electrode 7 is continuously provided from the n + -type source region 14 to the p + -type contact region 16 and is electrically connected to the source region 14 and the contact region 16 respectively. Although not shown, the source electrode 7 may be provided so as to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al--Si alloy.
The drain electrode 8 is provided on the back surface 11 b side of the GaN single crystal substrate 11 and electrically connected to the GaN single crystal substrate 11 . The drain electrode 8 is made of, for example, Al or an Al--Si alloy.

(Production method)
Next, a method for manufacturing the GaN semiconductor device 100 will be described. FIG. 3 is a flow chart showing the manufacturing method of the GaN semiconductor device 100 according to Embodiment 1 of the present invention in order of steps. The GaN semiconductor device 100 is manufactured using various devices such as a cleaning device, a film forming device, a heat treatment device, an exposure device, and an etching device. Hereinafter, these devices are collectively referred to as manufacturing devices.

At step ST1 in FIG. 3, the manufacturing equipment forms the p− type well region 13 (see FIG. 2) on the surface 12a side of the GaN layer 12. As shown in FIG. For example, the p-type well region 13 is formed by partially ion-implanting magnesium (Mg) as a p-type impurity into the surface 12a side of the GaN layer 12, and heat-treating the entire substrate including the GaN layer 12 to activate Mg. It is formed by

Next, in step ST2 in FIG. 3, the manufacturing equipment forms an n + -type source region 14 (see FIG. 2) and a p + -type contact region 16 (see FIG. 2) on the surface 12a side of the GaN layer 12, respectively. do. For example, the n + -type source region 14 is formed by partially ion-implanting silicon (Si) as an n-type impurity into the surface side of the well region 13 and heat-treating the entire substrate including the well region 13 to activate Si. It is formed by The p+ type contact region 16 is formed by partially ion-implanting Mg as a p-type impurity into the surface side of the well region 13 and heat-treating the entire substrate including the well region 13 to activate Si. . The heat treatment for forming the n + -type source region 14 and the heat treatment for forming the p + -type contact region 16 are, for example, the same step.

Next, at step ST3 in FIG. 3, the manufacturing equipment forms the first insulating film 51 on the surface 12a of the GaN layer 12 in which the well region 13, the source region 14 and the contact region 16 are formed. The manufacturing apparatus forms an AlN film with a thickness of 2 nm as the first insulating film 51 by ALD, for example.
Next, in step ST4 in FIG. 3, the manufacturing equipment forms the second insulating film 52 on the surface of the first insulating film 51. As shown in FIG. The manufacturing apparatus forms an Al ₂ O ₃ film with a thickness of 2 nm as the second insulating film 52 by ALD, for example.

The process of forming the AlN film shown in step ST3 of FIG. 3 and the process of forming the Al ₂ O ₃ film shown in step ST4 of FIG. It is preferable to use This is because if the process of forming the AlN film in step ST3 and the process of forming the Al ₂ O ₃ film in step ST4 are performed in the same chamber, the film forming gas (including oxygen) used in the process of step ST4 is This is because it may remain in the chamber and affect the next lot.

For example, it is assumed that the film-forming gas containing oxygen used in the process of step ST4 remains in the chamber even after the process of step ST4 is completed. When the wafers of the next lot are put into the chamber where the oxygen gas remains, the wafers put in are exposed to the residual oxygen gas, and the surface 12a of the GaN layer 12 is oxidized before the AlN film is formed ( That is, there is a possibility that a Ga—O bond is generated on the surface 12a). To reduce this possibility, the process of step ST3 and the process of step ST4 are preferably performed in separate chambers.

Next, in step ST5 of FIG. 3, the manufacturing equipment forms the third insulating film 53 on the surface of the second insulating film 52. As shown in FIG. The manufacturing apparatus forms a SiO ₂ film with a thickness of 100 nm as the third insulating film 53 by, for example, the CVD method.
Next, in step ST6 in FIG. 3, the manufacturing equipment forms the gate electrode 6 (see FIG. 2) on the third insulating film 53. As shown in FIG. For example, the manufacturing apparatus forms a gate electrode film on the third insulating film 53 . The gate electrode film is made of Al or an Al—Si alloy, and is deposited by vapor deposition. Alternatively, the gate electrode film may be made of polysilicon doped with impurities, and the film may be formed by the CVD method. Next, the manufacturing equipment forms the gate electrode 6 by patterning the gate electrode film.

Next, in step ST7 in FIG. 3, the manufacturing equipment forms the source electrode 7 (see FIG. 2) on the surface 12a side of the GaN layer 12. Next, in FIG. The source electrode 7 is formed by forming a film of Al or an Al--Si alloy by vapor deposition and patterning the formed Al or Al--Si alloy.
Next, in step ST8 in FIG. 3, the manufacturing equipment forms the drain electrode 8 (see FIG. 2) on the back surface 10b side of the GaN substrate 10. Next, in FIG. The drain 8 is formed by forming a film of Al or an Al--Si alloy by vapor deposition and patterning as necessary. Through the above steps, the GaN semiconductor device 100 shown in FIGS. 1 and 2 is completed.

Note that the flowchart shown in FIG. 3 is merely an example of the manufacturing method. The method for manufacturing the GaN semiconductor device 100 is not limited to the flow chart shown in FIG. For example, in the flowchart shown in FIG. 3, the order of execution of the step of forming the source electrode 7 (step ST7) and the step of forming the drain electrode 8 (step ST8) may be changed. The step of forming the n + -type source region 14 and the p + -type contact region 16 (step ST2) may be performed between steps ST6 and ST7 instead of between steps ST1 and ST3. The GaN semiconductor device 100 shown in FIG. 2 can be manufactured even with such an order of execution.

(interface state)
(1) Embodiment FIG. 4 is a model diagram showing the bonding state of atoms according to Embodiment 1 of the present invention, and is a model diagram showing the bonding state of atoms among GaN, AlN and Al ₂ O ₃ . As shown in FIG. 4, AlN does not contain oxygen (O). Therefore, the surface of GaN is difficult to oxidize, and Ga--O bonds are difficult to form. At the GaN/AlN interface, formation of interface states due to Ga—O bonds is suppressed.
FIG. 5 is a diagram showing energy bands at the AlN/Al ₂ O ₃ interface shown in FIG. The vertical axis of FIG. 5 indicates energy (eV), and the horizontal axis of FIG. 5 indicates symmetric points in the wavenumber space. As shown in FIG. 5, the formation of interface states is suppressed at the AlN/Al ₂ O ₃ interface.

(2) Comparative Example FIG. 6 is a model diagram showing the bonding state of atoms according to a comparative example of the present invention, and is a model diagram showing the bonding state of atoms among GaN, AlN and SiO ₂ . Al--Si--O bonds are formed at the AlN/ _SiO.sub.2 interface.
FIG. 7 is a diagram showing energy bands at the AlN/SiO ₂ interface shown in FIG. The vertical axis of FIG. 7 indicates energy (eV), and the horizontal axis of FIG. 7 indicates symmetric points in the wavenumber space. As shown in FIG. 7, at the AlN/SiO ₂ interface, an interface level is formed within the bandgap due to oxygen (O) resulting from the Al--O--Si bond. This interface state can be the source of hole traps.

(Effect of Embodiment 1)
As described above, the GaN semiconductor device 100 according to Embodiment 1 of the present invention includes the GaN layer 12, the gate insulating film 5 provided on the GaN layer 12, and the gate electrode provided on the gate insulating film 5. 6 and . The gate insulating film 5 includes a first insulating film 51 provided on the GaN layer 12 , a second insulating film 52 provided on the first insulating film 51 , and a third insulating film 52 provided on the second insulating film 52 . and an insulating film 53 . The first insulating film 51 is an aluminum nitride film (AlN). The second insulating film 52 is an AlxSiyO film (x>y≧0). The third insulating film 53 is an Alx'Siy'O film (0≤x'<y').

According to this, the first insulating film 51 is positioned between the GaN layer 12 and the second insulating film 52 . Since the first insulating film 51 is AlN and does not contain oxygen (O), the formation of Ga—O bonds is suppressed at the interface (for example, the GaN/AlN interface) between the first insulating film 51 and the GaN layer 12. . At the GaN/AlN interface, formation of interface states due to Ga—O bonds is suppressed.

A second insulating film 52 is positioned between the first insulating film 51 and the third insulating film 53 . The second insulating film 52 is an AlxSiyO film (x>y≧0), such as an Al ₂ O ₃ film. The third insulating film 53 is an Alx'Siy'O film (0≤x'<y') such as an _SiO2 film. As shown in FIGS. 5 and 7, the AlN/Al ₂ O ₃ interface suppresses the formation of interface states compared to the AlN/SiO ₂ interface.
Furthermore, the presence of Al ₂ O ₃ between AlN and SiO ₂ keeps the SiO ₂ film away from the GaN/AlN interface. This can reduce the influence of interface states formed by contact with the SiO ₂ film on the GaN/AlN interface.

As a result, the GaN semiconductor device 100 can reduce the hole traps due to the interface states, and can suppress fluctuations in the threshold voltage of the vertical MOSFET 1 .
In addition, the SiO ₂ film has a larger dielectric breakdown electric field than the AlN film and the Al ₂ O ₃ film, and can increase the dielectric breakdown voltage. Since the gate insulating film 5 has the third insulating film 53 exemplified by the SiO ₂ film, it is possible to suppress a decrease in dielectric breakdown voltage.

(Evaluation results)
Table 1 shows the results of evaluating the amount of threshold voltage shift and the dielectric breakdown voltage between Embodiment 1 of the present invention and Comparative Examples 1 to 3. As shown in FIG. 2, the vertical MOSFET 1 according to the first embodiment has, as the gate insulating film 5, an insulating film in which an AlN film, an _Al2O3 film _, and an _SiO2 film are laminated in this order. On the other hand, although not shown, the vertical MOSFET according to Comparative Example 1 has an insulating film in which an Al ₂ O ₃ film and a SiO ₂ film are laminated in this order as a gate insulating film. The vertical MOSFET according to Comparative Example 2 has an insulating film in which an AlN film and a SiO ₂ film are laminated in this order as a gate insulating film. A vertical MOSFET according to Comparative Example 3 has an insulating film in which an AlN film and an Al ₂ O ₃ film are laminated in this order as a gate insulating film.

In Table 1, the shift amount of the threshold voltage indicates the shift amount of the threshold voltage after applying a negative bias to the gate electrode as a relative value. The reference value of the shift amount is that of the first embodiment. In Table 1, the shift amount of the first embodiment is set to 1, and the shift amounts of Comparative Examples 1 to 3 are shown as relative values with respect to the first embodiment. As shown in Table 1, the shift amount of the threshold voltage was 3 times in Comparative Example 1, 2.5 times in Comparative Example 2, and 1 time in Comparative Example 3, as compared with Embodiment 1. From this result, it was confirmed that the fluctuation of the threshold voltage was suppressed by placing the AlN film and the Al ₂ O ₃ film between the GaN layer and the SiO ₂ film.
Further, as shown in Table 1, the dielectric breakdown voltage of the gate insulating film was 100 V in the first embodiment and the comparative examples 1 and 2, whereas it was 50 V in the third comparative example. From this result, it was confirmed that the decrease in dielectric breakdown voltage can be suppressed by arranging the SiO ₂ film as part of the gate insulating film.

<Embodiment 2>
In the first embodiment described above, the vertical MOSFET included in the GaN semiconductor device 100 is of planar type. However, in the embodiments of the present invention, the vertical MOSFET included in the GaN semiconductor device is not limited to the planar type, and may be of the trench gate type.

FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to Embodiment 2 of the present invention. As shown in FIG. 8, a GaN semiconductor device 100A according to Embodiment 2 has a trench H provided in a GaN substrate 10. As shown in FIG. The trench H is open on the surface 10a side of the GaN substrate 10 . The trench H is formed deeper than the p-type well region 13, and the bottom of the trench H reaches the n-type GaN layer 12 (drift region).

Inside the trench H, a gate insulating film 5 and a gate electrode 6 are arranged. The inner side and bottom surfaces of trench H are covered with first insulating film 51 of gate insulating film 5 . Also, the gate electrode 6 is embedded in the trench H with the gate insulating film 5 interposed therebetween. In the trench gate type vertical MOSFET, the region of the well region 13 facing the gate electrode 6 via the gate insulating film 5 provided on the side surface of the trench H becomes the channel region CR.

As with the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100A according to the second embodiment includes, as the gate insulating film 5, a first insulating film 51 provided on the GaN layer 12 and a first insulating film 51 It has a second insulating film 52 provided thereon and a third insulating film 53 provided on the second insulating film 52 . The first insulating film 51 , the second insulating film 52 and the third insulating film 53 are stacked in this order to form the gate insulating film 5 .

The first insulating film 51 is an AlN film formed to a thickness of 2 nm by ALD, for example. The second insulating film 52 is an AlxSiyO film (x>y≧0), eg, an Al ₂ O ₃ film with a thickness of 2 nm formed by ALD. The third insulating film 53 is an Alx'Siy'O film (0≤x'<y'), and is, for example, a _SiO2 film having a thickness of 100 nm formed by CVD.

According to this, similarly to the GaN semiconductor device 100, the GaN semiconductor device 100A can suppress fluctuations in the threshold voltage while suppressing a decrease in dielectric breakdown voltage of the gate insulating film 5. FIG.
In addition, in the GaN semiconductor device 100A, since the vertical MOSFET adopts the trench gate structure, the channel regions CR can be arranged more densely, which facilitates miniaturization of the device.

<Embodiment 3>
In the first and second embodiments described above, the MOSFETs provided in the GaN semiconductor devices 100 and 100A are vertical MOSFETs. However, in the embodiments of the present invention, the MOSFET included in the GaN semiconductor device may be of horizontal type instead of vertical type.

FIG. 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100B according to Embodiment 3 of the present invention. As shown in FIG. 9, a GaN semiconductor device 100B according to Embodiment 3 has an n + -type drain region 15 provided on the surface 12a side of the GaN layer 12 . The drain electrode 8 is provided on the surface 12 a of the GaN layer 12 and electrically connected to the n + -type drain region 15 . In the lateral MOSFET, a region sandwiched from both sides by the source region 14 and the drain region 15 and facing the gate electrode 6 with the gate insulating film 5 interposed therebetween serves as the channel region CR.

In the GaN semiconductor device 100B according to Embodiment 3, as in the GaN semiconductor device 100 according to Embodiment 1, a first insulating film 51 provided on the GaN layer 12 and a first insulating film 51 are provided as the gate insulating film 5. It has a second insulating film 52 provided thereon and a third insulating film 53 provided on the second insulating film 52 . The first insulating film 51 , the second insulating film 52 and the third insulating film 53 are stacked in this order to form the gate insulating film 5 . Each configuration of the first insulating film 51, the second insulating film 52, and the third insulating film 53 is the same as that of the GaN semiconductor device 100 according to the first embodiment.
According to this, similarly to the GaN semiconductor device 100, the GaN semiconductor device 100B can suppress fluctuations in the threshold voltage while suppressing a decrease in dielectric breakdown voltage of the gate insulating film 5. FIG.

<Modification>
In Embodiments 1 to 3 described above, the second insulating film 52 forming the gate insulating film 5 is an AlxSiyO film (x>y≧0), and is an Al ₂ O ₃ film as an example. However, in the embodiment of the present invention, the second insulating film 52 may be an AlxSiyO film (x>y>0). That is, the second insulating film 52 may have a composition that necessarily contains Si. As a result, the composition and bonding state between atoms of the second insulating film 52 can be brought close to the composition and bonding state between atoms of the third insulating film 53 , so that the second insulating film 52 and the third insulating film 53 It is possible to reduce the interface state formed at the interface of

Further, in Embodiments 1 to 3 described above, the third insulating film 53 constituting the gate insulating film 5 is an Alx'Siy'O film (0≤x'<y'), and as an example, is an _SiO2 film. explained. However, in the embodiment of the present invention, the third insulating film 53 may be an Alx'Siy'O film (0<x'<y'). That is, the third insulating film 53 may have a composition that necessarily contains Al. As a result, the composition of the third insulating film 53 can be brought close to the composition of the second insulating film 52, so that the interface level formed at the interface between the second insulating film 52 and the third insulating film 53 can be reduced. is possible・

<Other embodiments>
As described above, the present invention has been described through embodiments and variations, but the statements and drawings forming part of this disclosure should not be understood to limit the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.
For example, the p-type dopant used for vertical MOSFET 1 is not limited to magnesium (Mg). The p-type dopant may be beryllium (Be), zinc (Zn) or cadmium (Cd). For example, the channel region CR may contain one or more of Mg, Be, Zn, and Cd at a concentration of 1E+16/cm ³ or more as a p-type dopant.

Further, in FIG. 2, an n-type JFET region may be provided in the drift region immediately below the gate insulating film 5 . The JFET region is a region with a higher n-type dopant concentration and lower electrical resistance than the rest of the drift region. The on-resistance of the vertical MOSFET 1 may be reduced by providing the JFET region.

Moreover, in the above embodiment, the GaN layer 12 was exemplified as the "gallium nitride layer" of the present invention, but the "gallium nitride layer" is not limited to the GaN layer. For example, the "gallium nitride layer" may be a bulk GaN substrate. In addition, the "gallium nitride layer" contains GaN as a main component, and may further contain one or more elements selected from aluminum (Al) and indium (In).

Thus, the present invention naturally includes various embodiments and the like not described here. At least one of various omissions, replacements, and modifications of components can be made without departing from the gist of the embodiments and modifications described above. Moreover, the effects described in this specification are only examples and are not limited, and other effects may also occur. The technical scope of the present invention is defined only by the matters specifying the invention according to the valid scope of claims based on the above description.

1 Vertical MOSFET
5 gate insulating film 6 gate electrode 7 source electrode 8 drain electrode 10 GaN substrates 10a, 12a front surfaces 10b, 11b, 12b rear surface 11 GaN single crystal substrate 12 GaN layer 13 well region 14 source region 15 drain region 16 contact region 51 first insulation Film 52 Second insulating film 53 Third insulating film 100, 100A, 100B GaN semiconductor device H Trench

Claims (8)

a gallium nitride layer;
a gate insulating film provided on the gallium nitride layer;
a gate electrode provided on the gate insulating film;
The gate insulating film is
a first insulating film provided on the gallium nitride layer;
a second insulating film provided on the first insulating film;
a third insulating film provided on the second insulating film;
the first insulating film is an aluminum nitride film,
the second insulating film is an AlxSiyO film (x>y≧0),
The nitride semiconductor device, wherein the third insulating film is an Alx'Siy'O film (0≤x'<y'). 2. The nitride semiconductor device according to claim 1, wherein said _AlxSiyO film (x>y≧0) is an _Al2O3 film. 2. The nitride semiconductor device according to claim 1, wherein said AlxSiyO film (x>y≧0) is an AlxSiyO film (x>y>0). 4. The nitride semiconductor device according to claim 1, wherein said Alx'Siy'O film (0≤x'<y') is a _SiO2 film. The nitriding according to any one of claims 1 to 3, wherein the Alx'Siy'O film (0≤x'<y') is an Alx'Siy'O film (0<x'<y'). object semiconductor device. 6. The nitride semiconductor device according to claim 1, wherein said first insulating film has a film thickness of 0.5 nm or more and 5 nm or less. a MOSFET provided in the gallium nitride layer,
7. The nitride semiconductor device according to claim 1, wherein said gate insulating film and said gate electrode are included in a MOSFET. 8. The nitride semiconductor device according to claim 7, wherein said MOSFET is a vertical MOSFET.

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