JP2021132514A - Circuit for switching power source - Google Patents

Abstract

To enable favorable switching between PWM control and light-load control.SOLUTION: In a switching power source device that generates output voltage (VOUT) from input voltage (VIN), an output transistor (M1) is subjected to PWM control on the basis of error voltage (VCMP) based on a difference between reference voltage (VREF) and feedback voltage (VFB) based on the output voltage and slope voltage (VSLP) based on current flowing in the output transistor. A skip signal (SKP) is generated based on a result of comparing the error voltage and predetermined skip determination voltage (VSKP). In a light load time, light-load control to switch the output transistor according to the skip signal is performed. The skip determination voltage is varied depending on the duty of the output transistor or the input voltage.SELECTED DRAWING: Figure 1

Description

The present invention relates to a switching power supply circuit for forming a switching power supply device.

FIG. 27 shows a configuration example of the switching power supply device 900 that operates in the current mode. The switching power supply device 900 is a step-down DC / DC converter that obtains an output voltage Vout by switching an input voltage Vin with an output transistor 911. An inductor 912 is arranged between the output transistor 911 and the output capacitor 913 to which the output voltage Vout is applied. In the switching power supply device 900, the error voltage Vcmp is generated by the error amplifier 914 according to the difference between the feedback voltage Vfb corresponding to the output voltage Vout and the reference voltage Vref, and the error voltage Vcmp and the current information of the output transistor 911 (thus, the inductor). By controlling the output transistor 911 using the current information of 912), the output voltage Vout is stabilized to a desired target voltage.

In the switching power supply device 900 of FIG. 27, a set signal set that specifies the turn-on of the output transistor 911 is generated in synchronization with the clock signal clk. Then, when the slope voltage Vslp corresponding to the current flowing through the output transistor 911 reaches the error voltage Vcmp, a reset signal rst is issued and the output transistor 911 is turned off.

Japanese Unexamined Patent Publication No. 2016-11184

In the switching power supply device 900 that operates in the current mode, in principle, the error voltage Vcmp fluctuates according to the current of the load that receives the output voltage Vout. Then, in a situation where the load is determined to be light based on the error voltage Vcmp, it is possible to stop the switching operation (PWM control) of the synchronized output transistor 911 of the clock signal clk and perform the light load control instead. .. Light load control makes it possible to reduce switching loss during light load.

FIG. 28 shows a configuration of a switching power supply device 900a capable of switching and executing PWM control and light load control. In the switching power supply device 900a, the error voltage Vcmp is lowered at the time of light load, and when the error voltage Vcmp is lower than the skip determination voltage Vtskp, the light load control is started. When a decrease in the output voltage Vout is detected after the shift to the light load control, the output transistor 911 is turned on under the light load control.

In a switching power supply device such as the switching power supply device 900a that can switch and execute PWM control and light load control, it is required that the control switching be performed stably and seamlessly. Apart from this, it is also required to increase the efficiency (power conversion efficiency) of the switching power supply device as much as possible during light load control. With conventional switching power supply devices, there was room for improvement in meeting these demands.

On the other hand, in many switching power supply devices, a soft start operation is performed in which the output voltage is gradually increased at startup. However, in a switching power supply device such as the switching power supply device 900a that can switch and execute PWM control and light load control, care must be taken when realizing the soft start operation, and the soft start with a good skip determination voltage Vtskp. It is necessary to devise so as not to interfere with the operation.

A first object of the present invention is to provide a switching power supply circuit that realizes good control switching or contributes to improvement of efficiency. A second object of the present invention is to provide a switching power supply circuit that realizes a good soft start operation.

The switching power supply circuit according to the present invention is a switching power supply circuit that generates an output voltage from an input voltage by a switching operation of an output transistor, and obtains an error voltage according to the difference between the feedback voltage corresponding to the output voltage and the reference voltage. It has an error amplifier to generate and a slope voltage generator that generates a slope voltage according to the current flowing through the output transistor, and performs the switching operation in synchronization with the clock signal based on the error voltage and the slope voltage. A control unit capable of executing PWM control is provided, and the control unit generates a skip comparator that generates a skip signal based on a comparison result between the error voltage and the skip determination voltage, and a skip determination voltage generation that generates the skip determination voltage. It is possible to switch and execute the PWM control or the light load control that performs the switching operation according to the change in the height relationship between the error voltage and the skip determination voltage based on the skip signal. The skip determination voltage generation unit has a configuration (first configuration) in which the skip determination voltage is variable according to the input voltage or the duty of the output transistor.

In the switching power supply circuit according to the first configuration, in the PWM control, the error voltage changes in the first direction as the current of the load receiving the output voltage becomes larger, and the load As the current becomes smaller, the error voltage changes in the second direction opposite to the first direction, and in the skip comparator, the error voltage is on the first direction side of the skip determination voltage. When the skip signal is set to the first level, the skip signal is set to the second level when the error voltage is on the second direction side of the skip determination voltage, and the control unit sets the skip signal to the first level. The PWM control is executed when the voltage is maintained at, and when the skip signal changes from the first level to the second level, the PWM control is stopped and the control shifts to the light load control (second configuration). It may be.

In the switching power supply circuit according to the second configuration, the slope voltage changes in the first direction as the current flowing through the output transistor increases, and the error amplifier causes the output voltage to decrease. The error voltage is configured to change in the first direction accordingly, and in the PWM control, after the output transistor is turned on in synchronization with the clock signal, the comparison result between the error voltage and the slope voltage is obtained. In the light load control, the error voltage changes in the first direction as the output voltage decreases, so that the skip signal changes from the second level to the first level. When the transition occurs, the output transistor may be turned on in response to the transition, and then the output transistor may be turned off based on the comparison result between the error voltage and the slope voltage (third configuration).

In the switching power supply circuit according to the second or third configuration, the skip determination voltage generation unit shifts the skip determination voltage in the first direction as the input voltage decreases or the duty of the output transistor increases. It may be a configuration to be changed (fourth configuration).

In the switching power supply circuit according to any one of the second to fourth configurations, the control unit further includes a soft start voltage generation unit that generates a soft start voltage, and the soft start voltage generation unit further includes the switching. At the time of starting the power supply circuit, the soft start voltage is gradually changed in the first direction across the reference voltage, and in the error amplifier, the soft start voltage is on the first direction side of the reference voltage. When it is, the error voltage is generated according to the difference between the feedback voltage and the reference voltage, and when the soft start voltage is on the second direction side of the reference voltage, the feedback voltage and the soft start The error voltage is generated according to the difference from the voltage, and the skip determination voltage generation unit gradually changes the skip determination voltage toward the first direction at the time of starting the switching power supply circuit, and then gradually changes the skip determination voltage toward the first direction. , The voltage corresponding to the input voltage or the voltage corresponding to the duty of the output transistor may be set as the skip determination voltage (fifth configuration).

In the switching power supply circuit according to the fifth configuration, the skip determination voltage generation unit uses the soft start voltage to gradually change the skip determination voltage toward the first direction (sixth configuration). ) May be.

In the switching power supply circuit according to any one of the first to sixth configurations, when an inductor is connected in series to the output transistor and the output transistor is in the ON state, the input voltage is reached through the output transistor and the inductor. It may be a configuration in which a current based on the current flows (seventh configuration).

The other switching power supply circuit according to the present invention is a switching power supply circuit that generates an output voltage from an input voltage by the switching operation of the output transistor, and has an error according to the difference between the feedback voltage corresponding to the output voltage and the reference voltage. It has an error amplifier that generates a voltage and a slope voltage generator that generates a slope voltage according to the current flowing through the output transistor, and the switching operation is synchronized with a clock signal based on the error voltage and the slope voltage. A control unit capable of executing PWM control for performing PWM control is provided, and the control unit includes a skip comparator that generates a skip signal based on a comparison result between the error voltage and the skip determination voltage, and a skip determination that generates the skip determination voltage. It is possible to switch and execute the PWM control or the light load control in which the switching operation is performed according to the change in the height relationship between the error voltage and the skip determination voltage based on the skip signal by further having a voltage generation unit. The control unit further includes a soft start voltage generation unit that generates a soft start voltage, and the soft start voltage generation unit straddles the reference voltage when the switching power supply circuit is started. Is gradually changed in the first direction, and when the soft start voltage is on the first direction side of the reference voltage, the error amplifier causes the error according to the difference between the feedback voltage and the reference voltage. When a voltage is generated and the soft start voltage is on the second direction side of the reference voltage, the error voltage is generated according to the difference between the feedback voltage and the soft start voltage, and the first direction and the said. The second directions are opposite to each other, and the skip determination voltage generation unit gradually changes the skip determination voltage toward the first direction when the switching power supply circuit is started (eighth configuration). Is.

In the switching power supply circuit according to the eighth configuration, in the PWM control, the error voltage changes toward the first direction as the current of the load receiving the output voltage becomes larger, and the error voltage is changed. As the load current becomes smaller, the error voltage changes toward the second direction, and the skip comparator outputs the skip signal when the error voltage is on the first direction side of the skip determination voltage. When the error voltage is set to one level and the error voltage is on the second direction side of the skip determination voltage, the skip signal is set to the second level, and the control unit sets the skip signal to the first level. The PWM control may be executed, and when the skip signal changes from the first level to the second level, the PWM control may be stopped and the control may be shifted to the light load control (nineth configuration).

In the switching power supply circuit according to the ninth configuration, the slope voltage changes in the first direction as the current flowing through the output transistor increases, and the error amplifier causes the output voltage to decrease. The error voltage is configured to change in the first direction accordingly, and in the PWM control, after the output transistor is turned on in synchronization with the clock signal, the comparison result between the error voltage and the slope voltage is obtained. In the light load control, the error voltage changes in the first direction as the output voltage decreases, so that the skip signal changes from the second level to the first level. When the transition occurs, the output transistor may be turned on in response to the transition, and then the output transistor may be turned off based on the comparison result between the error voltage and the slope voltage (tenth configuration).

In the switching power supply circuit according to any one of the eighth to tenth configurations, the skip determination voltage generation unit gradually changes the skip determination voltage toward the first direction by using the soft start voltage. It may be the configuration (the eleventh configuration).

In the switching power supply circuit according to any one of the eighth to eleventh configurations, when an inductor is connected in series to the output transistor and the output transistor is in the ON state, the input voltage is reached through the output transistor and the inductor. It may be a configuration in which a current based on the current flows (12th configuration).

According to the present invention, it is possible to provide a switching power supply circuit that realizes good control switching or contributes to improvement of efficiency. Further, according to the present invention, it is possible to provide a switching power supply circuit that realizes a good soft start operation.

It is an overall block diagram of the switching power supply device which concerns on 1st Embodiment of this invention. It is an external view of the power supply IC which concerns on 1st Embodiment of this invention. FIG. 5 is a relationship diagram between a plurality of signals according to the first embodiment of the present invention. According to the first embodiment of the present invention, there is a configuration diagram (a) of a slope voltage generation unit and an explanatory diagram (b) of a slope voltage. It is explanatory drawing of the clock signal and the set signal which concerns on 1st Embodiment of this invention. It is a timing chart of the basic switching control according to the 1st Embodiment of this invention. It is a figure which shows the state of the waveform variation with the decrease of the load current which concerns on 1st Embodiment of this invention. It is a timing chart for demonstrating the pulse skip control which concerns on 1st Embodiment of this invention. It is a timing chart for demonstrating the reference return control according to 1st Embodiment of this invention. FIG. 5 is a relationship diagram between a plurality of signals related to a one-shot pulse according to the first embodiment of the present invention. FIG. 5 is an explanatory diagram of an operation associated with the generation of a one-shot pulse according to the first embodiment of the present invention. FIG. 5 is a signal waveform diagram according to the first embodiment of the present invention under specific conditions. It is a timing chart for demonstrating the operation which concerns on 2nd Embodiment of this invention. It is a figure which shows the input voltage dependence of the on-time of an output transistor in PWM control according to the 3rd Embodiment of this invention. It is explanatory drawing of the on time of the output transistor in light load control which concerns on 3rd Embodiment of this invention. It is a figure which shows the relationship between the on-time of an output transistor, the control to be executed, and an input voltage according to the 3rd Embodiment of this invention (provided that a skip determination voltage is fixed). It is a figure which shows the relationship between the on-time of an output transistor, the control to be executed, and an input voltage according to the 3rd Embodiment of this invention (provided that the 1st improvement technique is applied). It is a characteristic explanatory drawing of the switching power supply device which concerns on 3rd Embodiment of this invention. FIG. 5 is a configuration diagram of a portion related to a soft start operation according to a third embodiment of the present invention. FIG. 5 is a timing chart related to a soft start operation according to a third embodiment of the present invention. It is a figure which shows the state of the change of the output voltage at the time of starting of a switching power supply device which concerns on 3rd Embodiment of this invention. It is a circuit diagram of the skip determination voltage generation part which concerns on 3rd Embodiment of this invention. FIG. 22 is a timing chart related to the skip determination voltage generation unit of FIG. It is a figure which shows the result of the 1st simulation which concerns on 3rd Embodiment of this invention. It is a figure which shows the result of the 2nd simulation which concerns on 3rd Embodiment of this invention. It is explanatory drawing of the deformation technique which concerns on 3rd Embodiment of this invention. It is an overall block diagram of the switching power supply device which concerns on the related technique of this invention. It is an overall block diagram of the switching power supply device which concerns on the related technique of this invention.

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for the sake of simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, an element or a part, etc., the information, a signal, a physical quantity, an element or a part corresponding to the symbol or the code is described. Etc. may be omitted or abbreviated. For example, the output transistor referred to by "M1" described later (see FIG. 1) may be referred to as the output transistor M1 or may be abbreviated as the transistor M1, but they are all the same. Point to.

First, some terms used in the description of this embodiment will be described.
The ground refers to a conductive portion having a reference potential of 0 V (zero volt) or refers to the reference potential itself. In each embodiment, the voltage shown without any particular reference represents the potential seen from ground. Level refers to the level of potential, where a high level has a higher potential than a low level for any signal or voltage. For any signal or voltage, a signal or voltage at a high level means that the signal or voltage level is at a high level, and a signal or voltage at a low level means that the signal or voltage level is at a low level. Means that it is in. A level for a signal is sometimes referred to as a signal level, and a level for a voltage is sometimes referred to as a voltage level.
For any signal or voltage, switching from low level to high level is called up edge, and timing of switching from low level to high level is called up edge timing. Similarly, for any signal or voltage, switching from high level to low level is referred to as down edge, and timing of switching from high level to low level is referred to as down edge timing.
For any transistor configured as a FET (Field Effect Transistor) including a MOSFET, the on state means that the drain and source of the transistor are in a conductive state, and the off state means the drain of the transistor. And it means that there is a non-conduction state (interruption state) between the sources. The same applies to transistors that are not classified as FETs. Unless otherwise specified, the MOSFET may be understood as an enhancement type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Hereinafter, the on state and the off state may be simply expressed as on and off. For any transistor, switching from the off state to the on state is expressed as turn-on, and switching from the on state to the off state is expressed as turn-off.

<< First Embodiment >>
The first embodiment of the present invention will be described. FIG. 1 is an overall configuration diagram of the switching power supply device AA according to the first embodiment. The switching power supply device AA of FIG. 1 is configured as a step-down DC / DC converter that generates an output voltage V _{OUT lower than the input voltage V IN} from the input voltage V _IN. The input voltage V _IN and the output voltage V _OUT are positive DC voltages. The switching power supply device AA includes a power supply IC1 as a switching power supply circuit, an inductor L1 provided outside the power supply IC1, an output capacitor C1, and feedback resistors R1 and R2.

FIG. 2 shows an example of the appearance of the power supply IC 1. The power supply IC1 is an electronic component (semiconductor device) formed by enclosing a semiconductor integrated circuit in a housing (package) made of resin, and each circuit constituting the power supply IC1 is integrated with a semiconductor. Has been done. The housing of the electronic component as the power supply IC1 is provided with a plurality of external terminals exposed from the housing with respect to the outside of the IC1. The number of external terminals shown in FIG. 2 is merely an example.

External terminals TM1 to TM4 are shown in FIG. 1 as a part of a plurality of external terminals provided on the power supply IC1. The input voltage _VIN is input to the external terminal TM1. The external terminal TM2 is connected to the node ND1 described later. The external terminal TM3 is connected to the ground. _{A feedback voltage VFB,} which will be described later, is applied to the external terminal TM4.

The power supply IC 1 is provided with an output transistor M1, a synchronous rectification transistor M2, a control unit 10, and an internal power supply circuit 30. A block (reset circuit, protection circuit, etc.) that does not belong to the control unit 10 and is different from the internal power supply circuit 30 may be further included in the power supply IC 1, but the illustration and functional description of the block are omitted here unless necessary. .. Transistors M1 and M2 are configured as N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors). However, it is possible to modify the transistor M1 as a P-channel MOSFET.

The switching power supply device AA performs DC-DC conversion by a synchronous rectification method using the output transistor M1 and the synchronous rectification transistor M2. However, the transistor M2 can be replaced with a diode, and in this case, the switching power supply device AA performs DC-DC conversion by an asynchronous rectification method. For any transistor including the transistors M1 and M2, the section in which the transistor is in the on state may be referred to as an on section, and the section in which the transistor is in the off state may be referred to as an off section. ..

The drain of the transistor M1 is connected to the external terminal TM1 and therefore receives the input of the _{input voltage VIN.} The source of the transistor M1 and the drain of the transistor M2 are commonly connected at the node ND1. The source of the transistor M2 is connected to the external terminal TM3, that is, connected to the ground. The voltage generated at the node ND1 is referred to as a switch voltage and is represented by the _{symbol “V SW”.} One end of the inductor L1 is connected to the external terminal TM2, and the other end of the inductor L1 is connected to the node ND2. An output voltage V _OUT is generated at the node ND2. The output capacitor C1 is connected between the node ND2 and the ground. Further, a series circuit of feedback resistors R1 and R2 is provided between the node ND2 and the ground. _{Therefore, a feedback voltage V FB,} which is a voltage divider of the _{output voltage V OUT} , is generated at the connection node between the feedback resistors R1 and R2. By connecting the connection node between the feedback resistors R1 and R2 to the external terminal TM4, the feedback voltage _VFB is applied to the external terminal TM4. When the transistor M1 is configured as a P-channel MOSFET, the relationship between the source and drain of the transistor M1 is reversed (that is, the source and drain of the transistor M1 are connected to the external terminal TM1 and the node ND1, respectively. Will be connected).

In FIG. 1, “LD” represents a load connected between node ND2 and ground. The load LD is an arbitrary load (microcomputer or the like) that is driven based on the _{output voltage V OUT.} The current consumption of the load LD flowing from the no ND2 to the load LD is referred to as a load current and is represented by the _{symbol "ILD".} Further, the current flowing through the inductor L1 is referred to as an inductor current and is represented by the _{symbol “IL”.}

The control unit 10 turns on / off the transistors M1 and M2 by controlling the gate voltage of the transistors M1 and M2 based on _{the feedback voltage VFB and the slope voltage VSLP} described later according to the current flowing through the output transistor M1. Is controlled, thereby _{stabilizing the output voltage V OUT} to a predetermined target voltage V _TG (for example, 5 V). The control unit 10 of FIG. 1 can drive the transistors M1 and M2 by a so-called current mode control method. The internal power supply circuit 30 generates a predetermined internal power supply voltage V _{REG from the input voltage V IN.} Each circuit in the control unit 10 is driven based on the _{internal power supply voltage VREG.}

The internal configuration of the control unit 10 will be described. The control unit 10 includes an error amplifier 11, a reference voltage source 12, a resistor 13, a capacitor 14, a slope voltage generation unit 15, a main comparator 16, a set signal generation unit 17, a control signal generation unit 18, a gate driver 19, and a backflow detection unit 20. , A skip comparator 21, a one-shot pulse generation unit 22, and a skip determination voltage generation unit 23. For convenience of explanation, first, the existence of the skip comparator 21, the one-shot pulse generation unit 22, and the skip determination voltage generation unit 23 in the control unit 10 will be ignored, and other parts will be described.

The error amplifier 11 is a current output type transconductance amplifier. _{The feedback voltage VFB} applied to the external terminal TM4 is supplied to the inverting input terminal of the error amplifier 11. The reference voltage source 12 produces a _{reference voltage V REF,} which is a predetermined positive DC voltage. The reference voltage V _REF is input to the non-inverting input terminal of the error amplifier 11. The output terminal of the error amplifier 11 is connected to the line LN1 which is the wiring in the power supply IC1. When the power supply IC 1 is provided with the soft start function, the soft start voltage is also input to the error amplifier 11, but the function will be described later, and the function is ignored here.

The error amplifier 11 generates an _{error voltage V CMP} according to the difference between the negative side target voltage and the positive side target voltage. When the soft start function is ignored, the negative side target voltage and the positive side target voltage are the feedback voltage V _FB and the reference voltage V _REF , respectively. The error amplifier 11 causes an _{error voltage V CMP} in the line LN1 by inputting / outputting an electric charge due to an error current signal corresponding to the difference between the negative side target voltage and the positive side target voltage to the line LN1. Specifically, the error amplifier 11 outputs a current due to an error current signal toward the line LN1 so that the _{error voltage V CMP} becomes higher when the positive side target voltage is higher than the negative side target voltage, and the negative side target voltage becomes When the voltage is higher than the positive target voltage, the current due to the error current signal is drawn from the line LN1 toward the error amplifier 11 so that the _{error voltage V CMP becomes low.} As the absolute value of the difference between the negative target voltage and the positive target voltage increases, so does the magnitude of the current due to the error current signal.

A series circuit of a resistor 13 and a capacitor 14 is connected between the line LN1 and the ground. The series circuit functions as a phase compensation unit and cooperates with the error amplifier 11 to generate an _{error voltage V CMP in the line LN1.} Specifically, one end of the resistor 13 is connected to the line LN1, and the other end of the resistor 13 is connected to the ground via the capacitor 14. By appropriately setting the resistance value of the resistor 13 and the capacitance value of the capacitor 14, _{the signal phase of the error voltage V CMP} can be compensated and the oscillation of the output feedback loop can be prevented. Both or one of the resistor 13 and the capacitor 14 may be provided outside the power supply IC1 and externally connected to the power supply IC1.

_{The slope voltage generation unit 15 generates a slope voltage V SLP} according to the current flowing through the output transistor M1 in the on section of the output transistor M1 (that is, the section in which the output transistor M1 is in the on state).

The main comparator 16 compares the slope voltage V _SLP with the error voltage V _CMP and outputs a signal RST indicating the comparison result. Of the output signal RST of the main comparator 16, only the high level signal RST functions as a reset signal, and the low level signal RST does not correspond to the reset signal. Hereinafter, the output of the high-level signal RST from the main comparator 16 may be referred to as the issuance or output of a reset signal. The main comparator 16 functions as a reset signal generation unit that issues a reset signal based on the _{slope voltage V SLP} and the error voltage V _CMP.

The set signal generation unit 17 outputs the signal SET to the control signal generation unit 18. Of the output signal SETs of the set signal generation unit 17, only the high-level signal SET functions as a set signal, and the low-level signal SET does not correspond to the set signal. Hereinafter, the output of the high-level signal SET from the set signal generation unit 17 may be referred to as the issuance or output of the set signal. The set signal generation unit 17 can periodically issue a set signal, and can also control the output / non-output of the set signal based on the signals SKP and OSHT described later, but the details will be described later.

The control signal generation unit 18 is composed of a logic circuit such as a flip flip, and sets the on / off states of the transistors M1 and M2 based on the signal SET from the set signal generation unit 17 and the signal RST from the main comparator 16. Generates and outputs the specified control signal CNT. The gate driver 19 controls the gate signal G1 of the transistor M1 and the gate signal G2 of the transistor M2 based on the control signal CNT.

FIG. 3 shows the relationship between the signals SET, RST, CNT, G1 and G2. Each of the signals SET, RST, CNT, G1 and G2 is a binary signal having either a high level or a low level.

When a high-level signal SET is input to the control signal generator 18 (that is, when a set signal is issued) while the signal RST is low level, the control signal CNT becomes high level, and thereafter, the high level signal. The control signal CNT is held at a high level until the RST is input to the control signal generation unit 18 (that is, until the reset signal is issued).
When a high-level signal RST is input to the control signal generator 18 (that is, when a reset signal is issued) while the signal SET is low-level, the control signal CNT becomes low-level, and thereafter, a high-level signal. The control signal CNT is held at a low level until the SET is input to the control signal generation unit 18 (that is, until the set signal is issued).
In the section where both the signal SET and RST are at low level, the control signal CNT is maintained at the held level. The signals SET and RST do not become high level at the same time in the control unit 10.

The block composed of the transistors M1 and M2 is referred to as an output stage for convenience. The state of the output stage is one of an output high state, an output low state, and a HiZ state. In the output high state, the transistors M1 and M2 are in the on state and the off state, respectively. In the low output state, the transistors M1 and M2 are in the off state and the on state, respectively. In the Hi-Z state, both the transistors M1 and M2 are in the off state. In the section where the control signal CNT is high level, the gate driver 19 sets the gate signals G1 and G2 to high level and low level, respectively, so that the output stage is in the output high state and the control signal CNT is at low level. In a certain section, the gate signals G1 and G2 are set to low level and high level, respectively, so that the output stage is set to the output low state. However, even in the section where the control signal CNT is low level, when the high level backflow detection signal ZXOUT is output from the backflow detection unit 20, the gate driver 19 changes the output stage from the output low state to the Hi-Z state. After switching, the output stage is maintained in the Hi-Z state until the control signal CNT is switched to the high level.

The backflow detection unit 20 detects _{the presence or absence of a backflow current to the transistor M2 by comparing the switch voltage VSW} with the ground potential during the ON section of the transistor M2, and outputs a backflow detection signal ZXOUT indicating the detection result. Generate. The backflow detection signal ZXOUT is supplied to the gate driver 19. The backflow current refers to the current flowing from the node ND1 to the ground via the transistor M2. Level of reverse current detection signal ZXOUT the switch voltage V _SW goes low when lower than the potential of the ground, a high level when the switch voltage V _SW is higher than the potential of the ground. In other words, the level of the reverse current detection signal ZXOUT becomes a low level when the inductor current I _L flows toward the inductor L1 via the transistor M2 from the ground, the inductor current I _L from the inductor L1 to ground through the transistor M2 High level when backflowing. When the backflow current is detected, the output stage is set to the Hi-Z state to cut off the backflow current, so that the efficiency at the time of a light load can be improved.

The control unit 10 configured as described above _{alternately turns the transistors M1 and M2 on and off based on the feedback voltage VFB} and the slope voltage _{VSLP (} that is, sets the output stage between the output high state and the output low state). By performing the switching operation (switching), the output voltage V _OUT can be stabilized at the target voltage V _{TG corresponding to the reference voltage V REF} , and the load response can be improved by using the current information from the _{slope voltage V SLP.} Can be done. The method of controlling the transistors M1 and M2 by using the current information in addition to the output voltage V _OUT information (that is, in addition to the feedback voltage V _FB ) is called the current mode control method, and the control is called the current mode control. NS.

In the switching operation, turning the transistors M1 and M2 on and off alternately (that is, switching the output stage between the output high state and the output low state) means that the transition from the output low state to the output high state is performed. It is a concept including the intervention of a Hi-Z state based on the backflow detection signal ZXOUT. Further, when switching the state of the output stage between the output high state and the output low state, a dead time is inserted in which the transistors M1 and M2 are turned off at the same time in order to suppress the generation of a through current through the transistors M1 and M2. Is also good.

Due to the switching operation, a rectangular wavy voltage whose level fluctuates _{substantially between the input voltage V IN level and the ground level appears as the switch voltage V SW} , and the switch voltage V _SW is generated by the inductor L1 and the output capacitor C1. By smoothing, a DC output voltage V _OUT can be obtained.

The explanation of the slope voltage V _{SLP is supplemented.} Current flowing through the output transistor M1 during the on period of the output transistor M1, since equal to the inductor current I _L during the ON period of the output transistor M1, the slope voltage V _SLP is the inductor current I _L during the ON period of the output transistor M1 Shows information. That is, the slope voltage V _SLP includes the current information of the output transistor M1 or the inductor L1 during the on section of the output transistor M1. Any known method can be used as a method for generating the _{slope voltage VSLP} including the current information.

FIG. 4A shows an example of the configuration of the slope voltage generation unit 15, and FIG. 4B shows waveforms of the current and voltage involved _{in the slope voltage V SLP.} The slope voltage generation unit 15 of FIG. 4A includes an IV conversion unit 15a, a lamp voltage generation unit 15b, and an addition unit 15c. IV conversion unit 15a by converting the voltage (the inductor current I _L during the ON period of the words output transistor _M1) current flowing through the output transistor M1 during the on period of the output transistor M1, a sense voltage proportional to the current Generate V _{SNS. The lamp voltage generation unit 15b generates a sawtooth-shaped lamp voltage V RMP} that gradually increases starting from 0 V during the ON section of the output transistor M1. The addition unit 15c generates _{the sum of the sense voltage V SNS} and the lamp voltage V _RMP as the slope voltage V _{SLP. The slope voltage V SLP} is 0 V in a section other than the on section of the output transistor M1 (however, it may have a predetermined bias voltage value). As is well known, the oscillation of the output feedback loop in the current mode control can be suppressed by adding the _{lamp voltage V RMP.}

[Basic switching control]
Next, the basic switching control that can be executed by the control unit 10 when _{the load current ILD is relatively large will be described.} The state in which the load current _ILD is relatively large here corresponds to the state in which the output signal SKP of the skip comparator 21 is maintained at a low level, and in this state, the skip comparator 21 and the one-shot pulse generator 22 are significantly Doesn't work. Therefore, the basic switching control will be described by ignoring the existence of the skip comparator 21 and the one-shot pulse generation unit 22.

As shown in FIG. 5A, the set signal generation unit 17 includes _{a clock generation unit 17a that generates a clock signal CLK having a predetermined reference frequency f CLK} , and includes a state in which basic switching control is executed. Can generate and output a signal SET based on the clock signal CLK. As shown in FIG. 5B, the clock signal CLK is a _{signal in which a pulse is generated at the reference frequency f CLK} , and a pulse having a high level for a short time is generated in the clock signal CLK for each cycle of the clock signal CLK. In the clock signal CLK, the interval between high-level sections _{coincides with the time T P1} for one cycle of the clock signal CLK, that is, the reciprocal of the reference frequency f _CLK. When the signal SET is generated based on the clock signal CLK, the signal SET becomes high level for a predetermined minute time triggered by the down edge of the clock signal CLK. That is, when the signal SET is generated based on the clock signal CLK, the signal SET is a signal obtained by shifting the clock signal CLK in the time delay direction by the minute time.

The minute time described for pulses and the like does not have a particularly significant length in the present invention. Therefore, in the following description, the minute time is appropriately regarded as zero as it is a sufficiently short time. Further, although the signal SET is generated from the clock signal CLK here, the clock signal CLK itself may be supplied to the control signal generation unit 18 as a signal SET in the basic switching control. Further, in the basic switching control, it may be considered that the generation of the down edge of the clock signal CLK corresponds to the issuance of the set signal.

FIG. 6 shows a timing chart of basic switching control. The basic switching control will be described starting from the _{timing t A0} at which the output stage is in the output low state and the clock signal CLK is at the low level. In the basic switching control, the slope voltage V _SLP is 0V at the _{timing t A0 , and then when a pulse is generated in the clock signal CLK at the timing t A1} , the signal SET is raised to a high level for a short time with the down edge of the clock signal CLK as a trigger. That is, a set signal is issued. When the control signal CNT is switched from the low level to the high level in response to the issuance of the set signal, the output stage is switched from the output low state to the output high state. The interval output stage is the output high state, the inductor current I _L Yuki gradually increased, slide into rising slope voltage V _SLP gradually in conjunction with this. When the slope voltage _{V SLP} was less than the error voltage _{V CMP} reaches at a timing _{t A2} to the error voltage _{V CMP,} the output signal RST of the main comparator 16 changes over from the low level to the high level, i.e., the reset signal is issued Will be done. When the control signal CNT is switched from the high level to the low level in response to the issuance of the reset signal, the output stage is switched from the output high state to the output low state. When the output stage is in the low output state, the slope voltage V _SLP quickly drops to 0 V, so that the signal RST returns to the low level. After that, the same operation is repeated.

As described above, in the basic switching control, the set signal is issued in response to the down edge of the clock signal CLK having the _{reference frequency f CLK} , so that the transistors M1 and M2 are PWM controlled at the _{reference frequency f CLK.} Will be. That is, in the basic switching control, the output voltage V _OUT is obtained by _{pulse width modulation of the input voltage V IN} at the reference frequency f _CLK. "PWM" is an abbreviation for pulse width modulation.

FIG. 7 shows the waveform change when the _{load current ILD} decreases while the basic switching control is being executed. 7, the solid line waveform 311, 312 and 313, respectively, represents the load current _{I LD} of magnitude inductor current _{I L} when the first is the magnitude error voltage _{V CMP,} the slope voltage _{V SLP} waveform , dashed line waveform 314, 315, 316, respectively, the load current _I inductor current when the magnitude of the _LD is decreased to a second size from the first magnitude _{I L,} the error voltage _{V CMP,} the slope voltage V Represents the waveform of _SLP. In FIG. 7, the waveform 313 and the waveform 316 overlap each other in the section where _{the switch voltage V SW is at a low level.}

As understood from the circuit configuration described above, the magnitude of the load current I _LD as a basic switching control is a type of current mode control error voltage V _CMP varies according to the load current I _LD, shown in FIG. 7, for example There decreasing the second magnitude from the first magnitude, the error voltage V _CMP with an average value of the inductor current I _L decreases is reduced. _{If there is no change in the error voltage V CMP} with respect to the decrease in the load current I _LD, the amount of charge to the output capacitor C1 _{becomes excessive with respect to the load current I LD} , and the output voltage V _OUT rises. The error voltage V _CMP acts to decrease.

[Pulse skip control]
Next, the pulse skip control that can be executed when _{the load current ILD is relatively small will be described.} The skip comparator 21 is used to realize the pulse skip control. _{The error voltage V CMP} and the skip determination voltage V _TSKP are input to the inverting input terminal and the non-inverting input terminal of the skip comparator 21, respectively. The skip determination voltage V _TSKP is generated by the skip determination voltage generation unit 23. The skip determination voltage generation unit 23 has _{a function of changing the skip determination voltage VTSKP} according to the duty of the input voltage _VIN or the output transistor M1 and a function of gradually increasing the _{skip determination voltage VTSKP when the power supply IC1 is started.} However, those functions will be described later in the third embodiment, and here, it is assumed that the skip determination voltage _VTSKP is fixed at a predetermined positive DC voltage. The skip comparator 21 compares the error voltage V _CMP with the skip determination voltage V _TSKP and outputs a skip signal SKP based on the comparison result. Specifically, the skip comparator 21, the skip determination voltage _{V TSKP} outputs a skip signal SKP of high level is higher than the error voltage _{V CMP,} low level skip if the error voltage _{V CMP} is higher than the skip determination voltage _{V TSKP} Output the signal SKP. When the error voltage V _CMP and the skip determination voltage V _TSKP match, the level of the skip signal SKP is either low level or high level. The set signal generation unit 17 can perform pulse skip control when the skip signal SKP is at a high level.

The pulse skip control will be described with reference to FIG. In the operation example of FIG. 8, the skip signal SKP is maintained at a low level because “V _CMP > V _{TSKP ” after the timing t A2} and immediately before the timing t _A3. In the section where the skip signal SKP is at a low level (in FIG. 8, _{the section immediately before the timing t A3} ), the above-mentioned basic switching control can be performed. Therefore, in the operation example of FIG. 8, the operations _{from timing t A0} to t _A2 are as described above, and the basic switching control is executed until immediately before _{timing t A3.}

In the operation example of FIG. 8, with a decrease of the load current _{I LD,} which it is assumed that the error voltage _{V CMP} decreases monotonically from the timing _{t A0} after the timing _{t A3,} after the timing _{t A2,} the clock signal The error voltage V _{CMP falls} below the skip determination voltage V _{TSKP at the timing t A3} before the next pulse is generated in CLK, and as a result, the skip signal SKP switches from the low level to the high level at _{the timing t A3.} Set signal generation unit 17, when the skip signal SKP is switched to the high level at a timing t _A3, performing pulse skip control in a section where the skip signal SKP is maintained at a high level.

In the pulse skip control, the basic switching control synchronized with the clock signal CLK is stopped. Specifically, in the pulse skip control, a signal that masks the clock signal CLK is issued in the set signal generation unit 17 based on the high level skip signal SKP, and as a result, the signal SET is maintained at the low level. .. Therefore, after the timing t _A3 , as long as the skip signal SKP is maintained at a high level, the signal SET is maintained at a low level, so that the output transistor M1 is kept off. In FIG. 8, the broken line pulse 333 represents the pulse of the masked clock signal CLK, and the broken line pulses 334 and 335 represent the pulses that would have occurred in the signals SET and RST if pulse skip control had not been performed. The broken line waveforms 331 and 332 represent the waveforms of the voltages that would have been included in the _{switch voltage V SW} and the slope voltage V _SLP if the pulse skip control had not been performed. The pulse skip control described above reduces switching loss and improves efficiency at light loads.

[Reference return control]
Next, the reference return control will be described as the control for returning from the pulse skip control. FIG. 9 is an explanatory diagram of the reference return control. In the reference return control, the mask of the clock signal CLK is released in response to the switching of the skip signal SKP from the high level to the low level, and thereafter, the above-mentioned basic switching control is simply restarted.

Since a decrease in the output voltage V _{OUT causes an increase in the error voltage V CMP} , switching from the high level to the low level of the skip signal SKP means a decrease in the _{output voltage V OUT.} When the target voltage _{V TG} viewed from the output voltage _{V OUT} drops, but can quickly return the output voltage _{V OUT} to the target voltage _{V TG} is required, since the clock signal CLK and the skip signal SKP is asynchronous, reference When the return control is used, a relatively large time may elapse between the time when the skip signal SKP is switched to the low level and the time when the next set signal is issued. _{As a result, when the reference return control is used, the output voltage V OUT} may drop significantly with respect to the target voltage V _TG after the mask of the clock signal CLK is released and before the set signal is issued.

Since the output voltage V _OUT should be stabilized at the target voltage V _{TG , it is not preferable that the output voltage V OUT} drops significantly with respect to the target voltage V _TG , and the clock signal CLK when the reference return control is used. The fluctuation of the output voltage V _OUT after the mask is released may be large (that is, _{the ripple of the output voltage V OUT} may be large). After unmasking the clock signal CLK, a method of continuously issuing a set signal multiple times in order to quickly return _{the output voltage V OUT} to the target voltage V _{TG is also conceivable, but even if this method is used, the output voltage} There is no change in the fact that the ripple of V _{OUT can be large.}

[Improved return control]
Therefore, as a control for returning from the pulse skip control, the control unit 10 can execute the improved return control. The one-shot pulse generation unit 22 (hereinafter, may be abbreviated as the generation unit 22) of FIG. 1 is used for the improved return control. The generation unit 22 generates a one-shot pulse in response to the down edge of the skip signal SKP when a down edge occurs in the skip signal SKP (that is, when the skip signal SKP is switched from the high level to the low level). Then, the one-shot pulse is included in the signal OSHT and output to the set signal generation unit 17. In the following, the generation (generation) of a one-shot pulse may be referred to as the issuance of a one-shot pulse.

FIG. 10 shows the relationship between the signals SKP, SKPIN and OSHT. The circuit that refers to the skip signal SKP (for example, the generation units 17 and 22) is provided with a filter for removing the noise of the skip signal SKP, and the skip signal SKP after removing the noise corresponds to the signal SKPIN. Circuits that refer to the skip signal SKP (eg, generators 17 and 22) operate based on the signal SKPIN. Specifically, in principle, the above filter sets the signal SKPIN to a low level if the skip signal SKP is low level, and sets the signal SKPIN to a high level if the skip signal SKP is high level. After generating a down edge in the signal SKPIN in response to the down edge, the signal SKPIN is maintained at a low level for a predetermined low holding time regardless of the level of the skip signal SKP. Since the down edge of the signal SKPIN is generated in conjunction with the down edge of the skip signal SKP, it can be considered that the down edge of the skip signal SKP and the down edge of the signal SKPIN are equivalent.

The generation unit 22 maintains the signal OSHT at a low level in principle, and only when the down edge of the skip signal SKP occurs, the down edge of the skip signal SKP is used as a trigger (actually, the down edge of the signal SKPIN is used as a trigger). ) Set the signal OSHT to a high level for a short time. A pulse signal that can be included in the signal OSHT and has a high level for a short time is a one-shot pulse.

FIG. 11 shows a timing chart of the improved return control. After the pulse skip control is started through the basic switching control by the flow from the timing t _A0 to the timing t _{A3 described above (see FIG. 8), the error voltage V CMP,} which is lower than the _{skip determination voltage V TSKP} , increases and the timing It is _assumed that the skip determination voltage V _{TSKP is reached at t A4.} Then, at the timing t _A4 , a down edge is generated in the signals SKP and SKPIN, and a one-shot pulse (corresponding to “pulse 351” in FIG. 11) is generated in the signal OSHT triggered by the down edge of the signals SKP and SKPIN.

The set signal generation unit 17 raises the signal SET to a high level for a short time in response to the occurrence of a one-shot pulse in the signal OSHT, that is, issues a set signal. Since an upedge occurs in the control signal CNT triggered by the issuance of the set signal, the state of the output stage is switched from the output low state or the HiZ state to the output high state. In practice there is a delay in signal, etc., but here, with the down-edge signal SKP and SKPIN at the timing t _A4, at a timing t _A4, generating the one-shot pulse, the issuance of a set signal, and, of the output stage It is considered that switching to the output high state will occur.

After the timing t _A4 , when the rising slope voltage V _SLP reaches the error voltage V _CMP at the timing t _A5 , a reset signal (that is, a high level signal RST) is issued, so that the control signal CNT is changed from the high level. It is switched to the low level, and the state of the output stage is switched from the output high state to the output low state. Although not shown, after the timing _{t A5,} the reverse current detection signal ZXOUT high level occurs, the output stage is switched to the Hi-Z state.

Further, the set signal generation unit 17 sets the generation timing of the one-shot pulse, that is, the timing t _A4 as the operation start timing of the internal clock signal. In order to distinguish the internal clock signal whose timing t _A4 is set at the operation start timing from the above-mentioned clock signal CLK, the clock signal CLK2 is referred to. It can be understood that the above-mentioned clock signal CLK corresponds to the internal clock signal before the pulse skip control is performed. The clock signal CLK2 has a predetermined frequency f _CLK2 (for example, 300 kHz). The clock signal CLK2 is a _{signal in which a pulse is generated at the frequency f CLK2} , and a pulse having a high level for a minute time is generated in the clock signal CLK2 for each cycle of the clock signal CLK2 (see also FIG. 13 described later). In the clock signal CLK2, the interval between high-level sections _{coincides with the time T P2} for one cycle of the clock signal CLK2, that is, the reciprocal of the frequency f _CLK2. The first pulse is generated in the clock signal CLK2 at the timing when the time T _P2 elapses from the timing t _A4 , and thereafter, a pulse is periodically generated in the clock signal CLK2 at _{the frequency f CLK2.} The low holding time in the signal SKPIN may be determined based on the clock signal CLK2. In FIG. 11, the clock signal CLK2 is set to the clock signal CLK2 at the timing t _{A6 in which the time T P2} equal to the inverse of the frequency f _{CLK2 elapses from the timing t A4.} A pulse is generated, and the pulse triggers an upedge of the signal SKPIN (however, here, it is assumed that an upedge occurs in the signal SKP after the timing t _{A4 and before the timing t A6.} ).

As described above, in the improved return control, the output transistor M1 is immediately turned on in response to the transition from the high level to the low level of the skip signal SKP, asynchronously with the clock signal CLK in the basic switching operation. Accordingly, it is possible to supply charge to the to quickly output capacitor C1 in response to a decrease in the output voltage V _OUT, can be suppressed to be low ripple of the output voltage V _OUT in comparison to when adopting the reference return control Become.

The operation of the control unit 10 and the like will be described. When the skip signal SKP is at the first level (for example, low level), the control unit 10 can perform basic switching control that executes a switching operation in synchronization with the clock signal CLK (see FIGS. 6 and 8). ), When the skip signal SKP changes to the second level (for example, high level) during basic switching control, pulse skip control that stops the switching operation synchronized with the clock signal CLK can be performed (see FIG. 8). .. After that, when the skip signal SKP transitions from the second level (for example, high level) to the first level (for example, low level), the control unit 10 turns on the output transistor M1 asynchronously with the clock signal CLK in the basic switching control. (See FIG. 11).

More specifically, in the switching power supply device AA, in the basic switching control, the error voltage V _CMP changes in the first direction (for example, the ascending direction) as _{the load current I LD increases, and the load current I The} feedback control loop is formed so that the error voltage V _CMP changes in the second direction (for example, the downward direction) opposite to the first direction as the LD becomes smaller. Further, the skip comparator 21 sets the skip signal SKP to the first level when the high-low relationship between the _{error voltage V CMP} and the skip determination voltage V _{TSKP is reversed due to a change in the error voltage V CMP} in the second direction (for example, a decreasing direction). High and low between the _{error voltage V CMP} and the skip determination voltage V _TSKP due to the change from (for example, low level) to the second level (for example, high level) and the change of the error voltage V _CMP in the first direction (for example, ascending direction). When the relationship is reversed, the skip signal SKP is configured to change from a second level (eg, high level) to a first level (eg, low level).

In addition, the error amplifier 11 is configured such that the error voltage V _CMP changes in the first direction (for example, the ascending direction) as _{the output voltage V OUT decreases.} Therefore, after the start of the pulse skip control based on the second level (for example, high level) skip signal SKP, the error voltage V _CMP changes in the first direction (for example, the ascending direction) as _{the output voltage V OUT decreases.} As a result, when the skip signal SKP transitions from the second level (for example, high level) to the first level (for example, low level), the control unit 10 turns on the output transistor M1 asynchronously with the clock signal CLK in the basic switching control. This is the case (see FIG. 11).

The first level and the second level in the skip signal SKP are low level and high level, respectively, in the switching power supply device AA of FIG. 1, but the first and second levels are high level and low level, respectively. The switching power supply device AA may be modified as described above (the same applies to any other embodiment described later). Strictly speaking, the skip signal SKP being the first level and the second level means that the skip signal level is the first level and the second level (the same applies to other signals). It is considered that the first level skip signal SKP is a skip signal SKP having a first logical value, and the second level skip signal SKP is a skip signal SKP having a second logical value different from the first logical value. It can also be done (as well as for other signals). Further, in the switching power supply device AA of FIG. 1, the first direction and the second direction as the change direction of the _{error voltage V CMP are the ascending direction and the descending direction, respectively, but the first direction and the second direction are} The switching power supply device AA may be modified so as to be in a downward direction and an upward direction, respectively (the same applies to any other embodiment described later).

The control unit 10 has a specific signal generation unit that generates a specific signal in response to a transition from the second level (for example, high level) of the skip signal SKP to the first level (for example, low level), and is based on the specific signal. Turn on the output transistor M1. The one-shot pulse generation unit 22 is an example of a specific signal generation unit, and the one-shot pulse is an example of a specific signal. In the present invention, the form of the specific signal is not limited to the pulse signal.

Then, the control unit 10 turns on the output transistor M1 based on the specific signal (here, one-shot pulse), and then turns off the output transistor M1 based on the comparison result between the _{error voltage V CMP} and the slope voltage V _{SLP by the main comparator 16.} The timing may be determined ( _{see timing t A5 in} FIG. 11).

FIG. 12 _{shows a timing chart in a case where the load current ILD} is relatively small and skip control and improved return control are alternately repeated. In FIG. 12, 371, 372 and 373 represent three one-shot pulses generated in the signal OSHT, and 381, 382 and 383 are issued in response to the one-shot pulses 371, 372 and 373, respectively. Represents a set signal. In the case of FIG. 12, a one-shot pulse (for example, 371) is issued in response to the down edge of the skip signal SKP, and the skip signal SKP returns to a high level when _{the output voltage V OUT rises.} After that, when the output voltage V _OUT gradually decreases, a one-shot pulse (for example, 372) is issued again in response to the down edge again in response to the skip signal SKP. Hereinafter, the same operation is repeated. In the case as shown in FIG. 12, the _{operation is realized so that the error voltage V CMP} stabilizes in the vicinity of the skip judgment voltage V _{TSKP , and the slope voltage V SLP} slope constant when the control signal CNT is at a high level. Therefore, the high level section of the control signal CNT for each issuance of the one-shot pulse becomes substantially constant. Therefore, in the case of FIG. 12, it can be said that the control substantially equivalent to the constant on-time control is performed.

Issuance interval of the one-shot pulse depends on the load current I _LD, issuance interval of the one-shot pulse with increasing load current I _LD narrows. When the issuance interval is narrowed to a predetermined interval, the process may shift to PWM control in which a set signal is issued in synchronization with the clock signal CLK2. This PWM control is the same as the basic switching control described above, except that the set signal is issued in synchronization with the clock signal CLK2.

<< Second Embodiment >>
A second embodiment of the present invention will be described. The second embodiment and the third and fourth embodiments described later are embodiments based on the first embodiment, and the matters not particularly described in the second to fourth embodiments are the first unless there is a contradiction. The description of the embodiment also applies to the second to fourth embodiments. In interpreting the description of the second embodiment, the description of the second embodiment may be prioritized for matters that conflict between the first and second embodiments (the same applies to the third and fourth embodiments described later). .. As long as there is no contradiction, any plurality of embodiments may be combined among the first to fourth embodiments.

FIG. 13 shows a control timing chart according to the second embodiment. _{The timing t B1} in FIG. 13 corresponds to the timing t _A4 (see FIG. 11) described in the first embodiment, and the operation before the _{timing t B1 may be as described in the first embodiment.} At the timing t _B1 , a down edge is generated in the signals SKP and SKPIN, and a one-shot pulse 411 is generated in the signal OSHT triggered by the down edge of the signals SKP and SKPIN. The set signal generation unit 17 raises the signal SET to a high level for a short time in response to the occurrence of the one-shot pulse 411 in the signal OSHT, that is, issues a set signal 431. When the set signal 431 is issued, the output stage is switched to the output high state, and when the slope voltage V _SLP reaches the error voltage V _CMP after that, the output stage is in the output low state through the issuance of the reset signal. Switching to is as described in the first embodiment (the same applies to other set signals described later).

The set signal generation unit 17 sets the generation timing of the one-shot pulse 411, that is, the timing t _B1, to the operation start timing of the internal clock signal. In the example of FIG. 13, _{the internal clock signal whose timing t B1} is set to the operation start timing is referred to as the clock signal CLK2. As described in the first embodiment, the clock signal CLK2 has a predetermined frequency f _CLK2 (for example, 300 kHz), and a pulse is generated in the clock signal CLK2 every cycle of the clock signal CLK2. Therefore, a pulse 422 is generated in the clock signal CLK2 at the timing t _{B2 when the time T P2} for one cycle of the clock signal CLK2 _{elapses from the timing t B1,} and then the clock signal CLK2 becomes the clock signal CLK2 at the timing t _{B3 when the time T P2 further elapses.} Pulse 423 is generated.

Although different from the situation shown in FIG. 13, after the generation of the one-shot pulse 411 in response to the down edge of the skip signal SKP and before the pulse 422 is generated, the reset signal is issued and the skip signal SKP passes through the up edge of the skip signal SKP. Consider a case where another down edge is generated in response to the skip signal SKP and another one-shot pulse is generated in response to the down edge. In other words, this case is a case in which the skip signal SKP has another down edge within a predetermined time (that is, within one cycle of the clock signal CLK2) from _{the timing t B1 of the down edge of the skip signal SKP.} .. In this case, the set signal generation unit 17 may issue a set signal in response to another one-shot pulse (re-down edge of the skip signal SKP), thereby outputting in response to another one-shot pulse. The stage is in the output high state.

The above case corresponds to the case of FIG. In the case of FIG. 12, after the generation of the one-shot pulse 371, the skip signal SKP is reissued through the issuance of the reset signal and the up edge of the skip signal SKP by _{the time T P2 for one cycle of the clock signal CLK2 elapses.} The one-shot pulse 372 is generated due to the occurrence of the down edge. Therefore, the set signal generation unit 17 issues the set signal 382 in response to the one-shot pulse 372. In the case shown in FIG. 12, the load current _ILD is relatively small, and the output capacitor C1 is sufficiently charged by issuing one shot pulse once (that is, the output voltage V _{OUT rises} to the target voltage V _TG). Corresponds to the case).

In contrast, the case shown in FIG. 13, the timing t _B1 load current I _LD is relatively large from around, of once the issuance of a one-shot pulse corresponds to the case where the output capacitor C1 is not charged sufficiently, the timing t _{After B1} , the skip signal SKP is maintained at a low level including the timings t _B2 and t _B3.

In the case of FIG. 13, the set signal generation unit 17 switches the clock mask signal XCLKMSK from the low level to the high level, triggered by the generation of the pulse 422 at the clock signal CLK2 at the _{timing t B2.} The signal XCLKMSK is a signal that specifies whether or not to issue a set signal based on the clock signal CLK2, and is generated by the set signal generation unit 17. When the skip signal SKP is at high level, the signal XCLKMSK is at low level. When the skip signal SKP does not have a down edge again within a predetermined time from the timing of the down edge of the skip signal SKP (that is, within the time for one cycle of the clock signal CLK2), an up edge occurs in the signal XCLKMSK.

Only when the signal XCLKMSK is at a high level, a set signal is issued based on the clock signal CLK2. Therefore, in the case of FIG. 13, the set signal 432 is issued at _{the timing t B2 in synchronization with the pulse 422 at the clock signal CLK2, and at the timing t B3,} the set signal 433 is synchronized with the pulse 423 at the clock signal CLK2. Is issued. Strictly speaking, when the signal XCLKMSK is at a high level, a set signal is issued in synchronization with the down edge of the clock signal CLK2. After that, the same operation is repeated.

Although not specifically shown in FIG. 12, in the case of FIG. 12, it is assumed that the signal XCLKMSK is maintained at a low level. When the signal XCLKMSK is low level, a set signal is issued based on the one-shot pulse. A selector for issuing a set signal by selectively using either a one-shot pulse or a clock signal CLK2 according to the signal XCLKMSK can be provided in the set signal generation unit 17.

In this way, the control unit 10 does _{not generate another down edge of the skip signal SKP within a predetermined time from the timing t B1} of the down edge of the skip signal SKP (that is, within the time of one cycle of the clock signal CLK2). At that time, _{it is determined that the load current ILD} is relatively large, and the PWM control of the output stage synchronized with the clock signal CLK2 is started _{from the timing t B2 at} which the predetermined time has elapsed from _{the timing t B1.} This enables seamless control switching. In the PWM control synchronized with the clock signal CLK2, the PWM frequency (frequency of pulse width modulation) is _{fixed at the frequency f CLK2} , and the output duty of the output stage is determined depending on the _{error voltage V CMP} and the slope voltage V _SLP. That is, the PWM control performed after _{the timing t B2} is the PWM control in the current mode with the _{frequency f CLK2 as the PWM frequency.} The output duty of the output stage refers to the ratio of the on section of the output transistor M1 to one cycle of PWM control.

<< Third Embodiment >>
A third embodiment of the present invention will be described. In the third embodiment, the improved technique applicable to the first and second embodiments will be described. The PWM control described in the present embodiment corresponds to PWM control synchronized with the clock signal CLK (that is, the above-mentioned basic switching control) or PWM control synchronized with the clock signal CLK2.

The control unit 10 in the power supply IC 1 can execute the above-mentioned PWM control when the load LD is relatively heavy (that is, when the load current I _LD is relatively large), and when the load LD is relatively light (that is, when the load current I LD is relatively large). Light load control can be performed (when the _{LD is relatively small).} Light load control refers to switching control executed in response to the skip signal SKP, as shown in FIG.

A more specific description will be given starting from a state in which basic switching control, which is an example of PWM control, is being executed. The control unit 10 executes the basic switching control when the skip signal SKP is maintained at the low level, and stops the basic switching control when the skip signal SKP transitions from the low level to the high level to perform pulse skip control (FIG. 8). Perform light load control including).

In the basic switching control, after the output stage is set to the output high state in synchronization with the clock signal CLK (that is, after the output transistor M1 is turned on), the output is performed at the timing based on the comparison result between the _{feedback voltage VFB} and the slope voltage _VSLP. The stage is set to the output low state (that is, the output transistor M1 is turned off). The output stage refers to a block composed of transistors M1 and M2 as described above.

On the other hand, in the light load control in which the skip signal SKP shifts to a high level, the output voltage V _OUT is expected to decrease due to the pulse skip control. However, in the light load control, as shown in FIG. 12, when the skip signal SKP transitions from a high level to a low level due to an increase in the error voltage V _{CMP as the output voltage V OUT decreases, it responds to the transition.} The output stage is set to the output high state (that is, the output transistor M1 is turned on), and then the output stage is set to the output low state (that is, the output transistor M1 is set to the output low state) at a timing based on the comparison result between the _{feedback voltage VFB} and the slope voltage _VSLP. Turn off). In the case where the light load control is maintained, the output voltage V _{OUT rises until “V CMP} <V TSKP” is reached by the turn-on of the output transistor M1 triggered by the down edge of the skip signal SKP, and as a result, the skip signal SKP is high. Return to level (see Figure 12). After the skip signal SKP returns to the high level, the above operation is repeated.

As described above, in the light load control, the switching operation is performed according to the change in _{the level of the skip signal SKP (according to the change in the height relationship between the error voltage V CMP} and the skip determination voltage V _TSKP). More specifically, in light load control,
Operation a: Decrease _{in output voltage V OUT} when the skip signal SKP is at a high level,
Operation b: Transition of the skip signal SKP to the low level due to "V _CMP > V _{TSKP " due to the increase in the error voltage V CMP} due to the decrease in the _{output voltage V OUT.}
Operation c: Turn-on of the output transistor M1 accompanying the transition of the skip signal SKP to the low level,
Operation d: Turn-off of the output transistor M1 based on the comparison result between the _{feedback voltage V FB} and the slope voltage V _{SLP,
Operation e: Return} of the skip signal SKP to a high level by becoming _{"V CMP} <V TSKP" through a decrease _{in the error voltage V CMP} accompanying the turn-on of the output transistor M1.
Will be executed repeatedly.

When the light load control is continuously executed, as shown in FIG. 12, the error voltage V _{CMP fluctuates} around the skip judgment voltage V TSKP, and the error voltage V _CMP is roughly referred to as the skip judgment voltage V _TSKP. Can be considered equal.

By the way, although I was not particularly conscious of it so far, the input voltage _VIN can fluctuate within a predetermined voltage range. The variation range of the input voltage V _IN, hereinafter sometimes referred to as the input voltage range. For example, the input voltage V _IN is allowed to fluctuate within the input voltage range from the predetermined lower limit voltage V _INL to the predetermined upper limit voltage V _INH , and stable operation within the input voltage range is a power source. Required for IC1. Here, "0 <V _INL <V _INH ", for example, the lower limit voltage V _INL and the upper limit voltage V _INH are 12V and 36V, respectively.

In PWM control such as basic switching control, the output duty of the output stage (the ratio of the on section of the output transistor M1 to one cycle of PWM control) _{depends on the input voltage VIN} , and therefore, in each cycle of PWM control. The on-time of the output transistor M1 also depends on the _{input voltage VIN.} The ON time of the output transistor M1 in each period of PWM control is represented _{by "TON_PWM".} Expressed in "freq" the PWM frequency in the PWM control, in a situation where the output voltage _{V OUT} is desired target voltage _{V TG} is _{stabilized, "T ON_PWM = (V OUT} / V IN) (1 / freq)" It becomes. FIG. 14 conceptually shows the relationship between the on-time T _{ON_PWM when the input voltage V IN} is relatively low and the on-time T _{ON_PWM} when the input voltage V _{IN is relatively high.}

On the other hand, _{assuming that the load current ILD} is constant, the output transistor M1 is periodically turned on even in the light load control, similar to the PWM control. The ON time of the output transistor M1 per time in light load control is _{represented by "TON_LLM} ". When the light load control is continuously executed, the error voltage V _CMP is approximately equal to the skip determination voltage V _TSKP, and the output transistor M1 is turned off when the slope voltage V _SLP reaches the error voltage V _{CMP. Therefore} , the ON time T ON_LLM in the light load control is substantially proportional to the skip determination voltage _VTSKP (see FIG. 15).

In the design stage of the power supply IC1, the on-time T _{ON_PWM} and T _{ON_LLM} under various conditions are set and adjusted, and under certain conditions, the on-time T _{ON_PWM} and T _{ON_LLM} generally match. Here, it is assumed that the specific condition includes "V _IN = V _{IN H} ". That is, in certain conditions regarding the load current _{I LD} and the target voltage _{V TG,} the power IC1 to the on-time _{T ON_PWM} and _{T ON_LLM} is good agreement is designed when the input voltage _{V IN} is consistent with the upper limit voltage _{V INH} (However, the above specific conditions may be optional).

In this case, consider the behavior when the _{input voltage V IN} drops from the upper limit _{voltage V IN H} to the lower limit voltage V _INL. In PWM control, _{a decrease in the input voltage VIN} results in an increase in the on-time T _{ON_PWM.} As a result, as shown in FIG. 16, _{assuming that the skip determination voltage V TSKP} is fixed, when the input voltage V _IN is the lower limit voltage V _INL , the on-time T _{ON_PWM is relatively larger} than the on-time T ON_LLM. Will also be longer.

In switching from light load control to PWM control or switching from PWM control to light load control, it is ideal for stable or seamless control switching that the on-time is about the same before and after the switching. In a state where the phase compensation constants for PWM control is optimized, the on-time T _{ON_LLM} is too far from the on-time T _{ON_PWM,} may be oscillated in the feedback loop in the light load control occurs.

[First improved technology]
The first improved technique in consideration of this is applied to the power supply IC1 according to the third embodiment. In the first improved technique, the skip determination voltage V _TSKP is made variable _{according to the input voltage V IN.} More specifically, the skip determination voltage V _TSKP is increased as the input voltage V _{IN decreases.} As a result, the on-time _{TON_LLM tends} to increase as _{the input voltage VIN decreases.} As a result, as shown in FIG. 17, the difference between the on-time T _{ON_PWM} and T _{ON_LLM when the input voltage V IN} is relatively low is smaller than that when the skip determination voltage V _TSKP is fixed (FIG. 16). , Stable and seamless control switching can be realized.

Further, under a certain load condition, a _{small on-time TON_LLM} means that the switching frequency in the light load control becomes relatively high. An increase in the switching frequency increases the switching loss and leads to a decrease in the efficiency of the switching power supply device AA. According to the first improved technique, the on-time T _{ON_LLM when the input voltage V IN} is relatively low increases as compared with the case where the _{skip determination voltage V TSKP} is fixed, so that the switching frequency in light load control decreases. As a result, efficiency can be expected to improve. Strictly speaking, in light load control, switching is not always performed periodically, and therefore it can be said that the switching frequency cannot be defined. However, for convenience of explanation, the down edge of the skip signal SKP is present in light load control. It is assumed that it occurs at a constant cycle and switching is performed periodically.

In the switching power supply device AA, the target voltage _{VTG of the output voltage V OUT} can also be adjusted by adjusting the ratio of the resistance values of the feedback resistors R1 and R2. Skip always to match the on-time _{T ON_PWM} and _{T ON_LLM} hard throughout the adjustable range of the fluctuation range and the target voltage _{V TG} of the input voltage _{V IN,} corresponding to the input voltage _{V IN} according to the first improved technology Through the adjustment of the determination voltage _VTSKP , it is possible to bring the ratio between the _{on-time T ON_PWM} and T _{ON_LLM close to "1" under various conditions.}

Figure 18 shows a simulation of the ratio results between feasible on time _{T ON_PWM} and _{T ON_LLM} at first improved technology. In FIG. 18, each of the broken line waveforms 451 to 453 shows the relationship between _{the ratio of the on-time T ON_LLM} to the on-time T _{ON_PWM} and the input voltage V _IN. However, the broken line waveform 451, the target voltage _{V TG} of the output voltage _{V OUT} that has a higher voltage value than 5.0V is assumed. In dashed line waveform 452, the target voltage _{V TG} of the output voltage _{V OUT} that has the following voltage values and 5.0V or 3.3V is assumed. In dashed line waveform 453, the target voltage _{V TG} of the output voltage _{V OUT} that has the following voltage values and 2.4V or 1.0V is assumed.

Assuming that the fluctuation range of the input voltage V _IN is 12 V to 36 V, the ratio "T _{ON_LLM} / T _{ON_PWM} " is approximately 80% to 100% with _{respect to the target voltage V TG} of 3.3 V or more and 5.0 V or less. It is possible to design it so that it fits within the range. Also the target voltage _{V TG} of 5.0V greater and 1.0 V, the deviation from 100% the ratio _{"T ON_LLM /} T _{ON_PWM"} can be suppressed to up to about 40%. 3.3V and 5.0V are voltages that are adopted and regarded as important as power supply voltages and the like in many electronic devices. Therefore, although the ratio with respect to the target voltage _{V TG} of 3.3V and 5.0V _{"T ON_LLM /} T _{ON_PWM"} may be designed to supply IC1 to close to 1, whereas the other target voltage _{V TG} It is also possible to design the power supply IC1 so that the ratio "T _{ON_LLM} / T _{ON_PWM" approaches 1.}

[Second improved technology]
A second improved technique is also applied to the power supply IC 1 according to the third embodiment in addition to the first improved technique. First, the soft start operation, which is the premise of the second improved technology, will be described. The power supply IC 1 realizes a soft start operation in which _{the output voltage V OUT} is gradually increased from 0 V toward the target voltage V _TG when the switching power supply device AA is started. It should be noted that the operations shown in the first and second embodiments may be understood as operations after the signal SSEND, which will be described later, has reached a high level.

To achieve the soft-start operation, the control unit 10, provided with a circuit 52 for generating a signal SSEND corresponding to the soft start voltage generator 51 and the voltage V _SS to produce the soft-start voltage V _SS, as shown in FIG. 19 In addition, the error amplifier 11 is provided with first and second non-inverting input terminals as non-inverting input terminals. _{A soft start voltage V SS} and a reference voltage V _REF are applied to the first and second non-inverting input terminals of the error amplifier 11, respectively. _{The feedback voltage VFB} is applied to the inverting input terminal of the error amplifier 11 as described above.

_{As described above, the error amplifier 11 generates an error voltage V CMP} according to the difference between the negative side target voltage and the positive side target voltage, but the lower voltage of the soft start voltage _VSS and the reference voltage V _REF. Is used as the positive target voltage. The negative target voltage is the feedback voltage V _FB . Therefore, in the section where the soft start voltage V _SS is lower than the reference voltage V _REF , the error amplifier 11 generates an error voltage V CMP according to the difference between the _{feedback voltage V FB} and the soft start voltage V _{SS, and the soft start voltage V CMP.} the higher section than V _SS reference voltage _{V REF,} and generates an error voltage _{V CMP} according to a difference between the feedback voltage _{V FB} with a reference voltage _{V REF.} When "V _SS = V _REF ", either the soft start voltage V _SS or the reference voltage V _REF is the positive target voltage.

FIG. 20 is a timing chart at the time of starting the switching power supply device AA. _{It is assumed that the input voltage VIN} supplied to the power supply IC1 rises from 0 V (zero volt) to a predetermined positive DC voltage at the timing t _C1. Then, the power supply IC1 is activated at a timing _{t C1,} generator 51, starting from the timing _{t C1,} gradually increased toward the soft-start voltage _{V SS} from 0V to a predetermined positive predetermined voltage _{V SSMAX} .. For example, it is possible to generate a voltage V _SS at capacitor charged at a constant current circuit and a constant current for generating a constant current, the capacitor for generating a voltage V _SS is externally connected to the power supply IC1 You may. At the timing t _C3 after the timing t _C1 , the voltage V _SS just reaches the predetermined voltage V _SSMAX , and thereafter, the voltage V _SS is maintained at the predetermined voltage V _SSMAX. At timing _{t C2} between timing _{t C1} and _{t C3,} just voltage _{V SS} reaches a low predetermined voltage _{V SSEND} than the predetermined voltage _{V SSMAX.} Circuit 52, a voltage _{V SS} to output a low level signal SSEND when less than the predetermined voltage _{V SSEND,} outputs a high level signal SSEND when the voltage _{V SS} to the predetermined voltage _{V SSEND} more. The high level signal SSEND means the completion of the soft start operation. Here, "0 <V _REF <V _SSEND <V _SSMAX " is established. However, it may be "V _REF = V _SSEND".

Thus, generator 51, (at the time of startup of the words power IC1) switching power supply device AA of at the time of startup, toward the higher potential _{(V SSMAX)} reference voltage _{V REF} from lower than the reference voltage _{V REF} potential gradual potential to generate a soft-start voltage V _SS to rise, thereby providing the soft start operation to continue a gradual increase of the output voltage V _OUT toward from 0V to the target voltage V _TG to.

When the output voltage V _OUT is in the vicinity of 0V, it is required to shorten the on-time of the output transistor M1 and gradually increase the _{output voltage V OUT.} Starting from the timing t _{C1 , the error voltage V CMP} gradually rises from 0V (zero volt) due to the current supplied from the error amplifier 11 to the line LN1, but it is assumed that the skip is determined immediately after _{the timing t C1.} If the voltage V _TSKP has a large voltage value, the _{pal skip control is activated until the error voltage V CMP} reaches the skip determination voltage V TSKP, and the output transistor M1 is not turned on for a long time. When the error voltage _{V CMP} reaches the skip determination voltage _{V TSKP,} large on-time period corresponding to a large skip determination voltage _{V TSKP,} the output voltage _{V OUT} output Toranjisusuta M1 is turned on so possibly rapidly increases be. Such an operation may impair the smoothness of the rise of _{the output voltage V OUT.} That is, as shown in FIG. 21, _{the waveform of the output voltage V OUT} at the time of startup may be a broken line waveform 461 deviating from the ideal solid line waveform 462. When the skip determination voltage V _{TSKP is increased as the input voltage V IN} decreases by applying the first improved technique, such a possibility may become particularly apparent.

_{In consideration of this, in the second improved technique, the potential of the skip determination voltage VTSKP} is gradually increased from the initial potential at the time of starting the switching power supply device AA (that is, at the time of starting the power supply IC1), and then becomes the final potential. (In other words, the voltage with the final potential is set to the _{skip judgment voltage V TSKP). As a result, the output voltage V OUT} can be gradually increased when the switching power supply device AA is started (that is, when the power supply IC 1 is started).

The initial potential of the skip determination voltage V _TSKP may be 0V or may be different from 0V. Final potential of the skip determination voltage _{V TSKP} is arbitrary is higher than the initial potential of the skip determination voltage _{V TSKP.} The initial potential and final potential of the skip determination voltage V _TSKP may be a first predetermined potential (predetermined first fixed potential) and a second predetermined potential (predetermined second fixed potential), respectively. Both the first improved technique and the second improved technique may be applied to the power supply IC 1. In this case, at least the final potential of the _{skip determination voltage V TSKP is a potential corresponding to the input voltage V IN} (input voltage V). _{The lower the IN, the} higher the final potential of the skip determination voltage V _{TSKP is set).} Also the initial potential of the skip determination voltage _{V TSKP} may be a potential corresponding to the input voltage _{V IN} (the initial potential of the skip determination voltage _{V TSKP} lower the input voltage _{V IN} can be set higher).

[Skip judgment voltage generator]
FIG. 22 shows a circuit configuration example of the skip determination voltage generation unit 23 that realizes both the first and second improved techniques. The skip determination voltage generation unit 23 of FIG. 22 includes resistors 111 to 117, transistors 121 to 133, an operational amplifier 141, and a capacitor 142. Figure skip decision voltage generator 23 of 22, in addition to receiving an input voltage _{V IN} via terminal TM1 (see FIG. 1), receives the above-mentioned soft start voltage _{V SS} and a predetermined positive DC voltage Vreg1～Vreg3. DC voltage Vreg1~Vreg3 may be a voltage generated by the internal power supply circuit 30 of FIG. 1, or, based on the internal power supply voltage _{V REG} generated by the internal power supply circuit 30 is generated by the power supply within IC1 good. For example, the DC voltages Vreg1 to Vreg3 are 3.3V, 1.1V, and 0.2V, respectively. The above-mentioned predetermined voltage V _SSMAX (see FIG. 20) is higher than the DC voltage Vreg2.

Transistors 121, 127 and 133 are configured as N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors), and transistors 122-126 and 128-132 are configured as P-channel MOSFETs.

_{An input voltage V IN} is applied to one end of the resistor 111, and the other end of the resistor 111 is connected to the ground via the resistor 112. The connection node between the resistors 111 and 112 is connected to the non-inverting input terminal of the operational amplifier 141 and is connected to the ground via the capacitor 142. The inverting input terminal of the operational amplifier 141 is connected to the source of the transistor 121 and is connected to the ground via the resistor 113. The gate of the transistor 121 is connected to the output terminal of the operational amplifier 141. The drain of the transistor 121 is commonly connected to each gate of the transistors 122 to 124 and the drain of the transistor 122.

A DC voltage Vreg1 is commonly applied to each source of the transistors 122 to 124 and 129 to 132. The drain of the transistor 123 is connected to each source of the transistors 125 and 126 and the gate of the transistor 127. Each drain of transistors 125 and 126 is connected to ground. The gate of the transistor 125 is a DC voltage Vreg2 is applied, the soft-start voltage _{V SS} to the gate of the transistor 126 is applied.

The drain of the transistor 124 is connected to the gate of the transistor 133 and is connected to the source of the transistor 128 via the resistor 114. The drain of the transistor 128 is connected to the ground, and a DC voltage Vreg3 is applied to the gate of the transistor 128.

The drain of the transistor 127, the drain and the gate of the transistor 129, the gate of the transistor 130, and the drain of the transistor 131 are commonly connected to each other. The source of transistor 127 is connected to ground via resistor 115. The drain of the transistor 130 is connected to the ground via a resistor 117. The drain of the transistor 133, the drain and the gate of the transistor 132, and the gate of the transistor 131 are commonly connected to each other. The source of transistor 133 is connected to ground via resistor 116.

The transistors 122 to 124 form a first current mirror circuit in which the transistors 122 are on the current input side and the transistors 123 and 124 are on the current output side. The transistors 129 and 130 form a second current mirror circuit in which the transistor 129 is the current input side and the transistor 130 is the current output side. The transistors 131 and 132 form a third current mirror circuit in which the transistor 132 is the current input side and the transistor 131 is the current output side. Here, it is assumed that the current input / output ratio is set to "1: 1" in each of the first to third current mirror circuits.

The drain current of the transistor 121 and 124 - the (drain current flowing between the source), _{respectively,} "I S1", together represent at _{"I S2",} the drain current of the transistor 127,132,130, respectively, _{"I A ","} expressed by _{I B "," I O "} . Further, the resistance value of the resistor 113 and 114, _{respectively,} "R S1", together represent at _{"R S2",} the resistance value of the resistor 115, 116, and 117, _{respectively, "R A", "R} B", It is represented by _"RO". In addition, the expressed at a voltage of a connection node between the resistors 111 and 112 _{"V INS",} representing the gate voltage of the transistor 127 in the _{"V P".} The voltage _{V INS} is the partial pressure of the input voltage _{V IN.} The voltage at the connection node between the drain of the transistor 130 and the resistor 117 (that is, the voltage between both terminals of the resistor 117) is used as the _{skip determination voltage VTSKP.}

Some relational expressions related to the configuration of FIG. 22 will be described. In the configuration of FIG. 22, the following equation (1) is established, and assuming that the current input / output ratio of the current mirror circuit composed of the transistors 122 and 124 is “1: 1” as described above, the following equation (2) is established. do.
_IS1 = V _INS / R _S1 ... (1)
_IS1 = _IS2 ... (2)

Here, it is assumed that the resistance values of the resistors 113 and 114 are set to be equal. That is, it is assumed that the following equation (3) holds. Then, the equation (4) is established from the equations (1) to (3). Further, it is assumed that the resistance values of the resistors 115 and 116 are set to be equal. That is, it is assumed that the following equation (5) holds. Here, the resistance values R _S1 , R _S2 , _RA and R _B are all equal and set to, for example, 1500 kΩ.
R _S1 = R _S2 ... (3)
_IS2・ R _S2 = V _INS・ ・ ・ (4)
_{R A = R B ··· (5} )

FIG. 23 shows a timing chart at the time of starting of the switching power supply device AA including the skip determination voltage generation unit 23 of FIG. _{It is assumed that the input voltage VIN} supplied to the power supply IC1 rises from 0 V (zero volt) to a predetermined positive DC voltage at the timing t _D1. Then, the power supply IC1 is started at the timing _{t D1,} starting from the timing _{t D1,} the soft-start voltage _{V SS} is slide into rising gradually toward from 0V to a predetermined positive predetermined voltage _{V SSMAX.} At the timing t _D3 after the timing t _D1 , the voltage V _SS just reaches the predetermined voltage V _SSMAX , and thereafter, the voltage V _SS is maintained at the predetermined voltage V _SSMAX.

In the process of the soft-start voltage V _SS rises from 0V, the voltage V _P slide into rise in conjunction with the rise of the soft-start voltage V _SS. However, increase in the voltage _{V P} is terminated at a timing _{t D2,} in the subsequent timing _{t D2,} the voltage _{V P} is fixed by the voltage corresponding to the voltage Vreg2 (approximately equal to Vreg2). The timing t _D2 is a timing after the timing t _D1 and before the timing _{t D3.} At elevated course of voltage _{V P,} the current _{I A} increases with increasing voltage _{V P,} with an increase in the current _{I A,} the skip determination voltage _{V TSKP} through increase in current _{I O} increases.

Current _{I S2} is also dependent on the voltage _{V INS} current _{I B} so depends on the voltage _{V INS,} current through the action of the current mirror circuit composed of the current mirror circuit and the transistors 129 and 130 consisting of transistors 131 and 132 _{I A} and _{I O Will} also depend on the voltage V INS. Thus, the skip determination voltage _{V TSKP,} in between time _{t D1} and _{t D2,} with increasing soft-start voltage _{V SS} while dependent on the input voltage _{V IN} Yuki rises gradually toward the initial potential to a final potential After the timing t _D2 , it will be fixed at the final potential depending on the input voltage _VIN.

The skip determination voltage V _TSKP after the timing t _D2 is expressed by the following equation (6). According to the second term on the right side of the equation (2), an increase in the skip determination voltage V _TSKP (first improved technique) is realized as _{the input voltage V IN decreases.} In between time _{t D1} and _{t D2,} skip decision voltage _{V TSKP} such as hand side of first term "Vreg2" is replaced by _{"V SS"} of the formula (2) is obtained (where _{the V TSKP} is negative No), the second improved technology is realized.
_{V TSKP = (Vreg2-Vreg3)} · R O / R A -V INS · R O / R A
... (6)

24 and 25 show the results of the first and second simulations related to the switching power supply device AA. In the first simulation corresponding to FIG. 24, it is assumed that the input voltage V _IN is 12 V and the output voltage V _OUT is 5 V (that is, the target voltage V _TG is 5 V). In the second simulation corresponding to FIG. 25, it is assumed that the input voltage V _IN is 12 V and the output voltage V _OUT is 3.3 V (that is, the target voltage V _TG is 3.3 V).

The broken line waveform 471 and the solid line waveform 472 in FIG. 24 and the broken line waveform 481 and the solid line waveform 482 in FIG. 25 _{represent the relationship between the load current ILD} and the efficiency of the switching power supply device. However, the broken line waveforms 471 and 481 represent the load current dependence of the efficiency in the virtual switching power supply to which the first improved technology is not applied, and the solid line waveforms 472 and 482 represent the switching power supply AA to which the first improved technology is applied (specifically). Shows the load current dependence of efficiency in the switching power supply device AA) including the skip determination voltage generation unit 23 of FIG. 22. The virtual switching power supply unit, in terms of the input voltage _{V IN} is designed when the ratio _{"T ON_LLM /} T _{ON_PWM"} is approximately 1 so as to match the upper limit voltage _{V INH} (here 36V is), the input voltage _{V IN} On the other hand, the skip determination voltage V _TSKP is invariant. Except for the application of the first improved technology, the conditions of the first simulation are the same between the virtual switching power supply and the switching power supply AA, and the conditions of the second simulation are also the same between the virtual switching power supply and the switching power supply AA. It is the same.

The broken line circle 473 in FIG. 24 and the broken line circle 483 in FIG. 24 represent switching points between the light load control and the PWM control in the virtual switching power supply device, and the broken line circle 474 in FIG. 24 and the broken line circle 484 in FIG. 24 are the first. It represents a switching point between light load control and PWM control in the switching power supply device AA to which the improved technology is applied. Although not clear from FIGS. 24 and 25, the waveforms 471 and 472 are partially overlapped and the waveforms 481 and 482 are partially overlapped in the current region where the _{load current ILD is larger than these switching points.} By applying the first improved technology, the efficiency in light load control is improved.

[Transformation of the first improved technology]
The above-mentioned first improved technique, that is, the first improved technique in which the skip determination voltage V _{TSKP is variable according to the input voltage V IN} , is referred to as a basic first improved technique for convenience. _{In the first improved technique, the skip determination voltage V TSKP} may be changed according to the duty of the output transistor M1. _{Hereinafter, for convenience of explanation, the technique of changing the skip determination voltage V TSKP} according to the duty of the output transistor M1 is referred to as a modified first improved technique, and the duty of the output transistor M1 is referred to as a duty DTY.

In the modified first improved technique, the skip determination voltage generation unit 23 _{variably sets the skip determination voltage VTSKP} according to the duty DTY as shown in FIG. 26A, and at this time, the duty DTY is derived. The duty lead-out unit 24 is added to the power supply IC1. The duty derivation unit 24 may be built in the skip determination voltage generation unit 23 as a component of the skip determination voltage generation unit 23.

The duty DTY represents "the ratio of the on-time of the output transistor M1 to the sum of the on-time and the off-time of the output transistor M1".
The on-time of the output transistor M1 represents the length of the on-section of the output transistor M1.
The off time of the output transistor M1 represents the length of the off section of the output transistor M1.

When PWM control is performed, "the ratio of the on-time of the output transistor M1 to the sum of the on-time and off-time of the output transistor M1" is the ratio (ratio) of the on-section of the output transistor M1 to one cycle of PWM control. ).

Since switching is not always performed periodically when light load control is performed, the switching cycle is indefinite, but even when light load control is performed, "on time and off of output transistor M1" The ratio of the on-time of the output transistor M1 to the sum of the times can be defined (except for the situation where the switching of the output transistor M1 is stopped due to _{the load current ILD being zero).}

For example, the duty derivation unit 24 may derive the duty DTY based on the ratio of _{the output voltage V OUT} and the input voltage V _IN. This is because in a step-down DC / DC converter such as the switching power supply AA, the ratio (V _OUT / V _IN ) is considered to substantially match the duty DTY in the steady state. As shown in FIG. 26B, a method of deriving the duty DTY based on _{the ratio (V OUT} / V _{IN) is referred to as a first deriving method.} In FIG. 26B, the duty out-licensing unit 24 that employs the first out-licensing method is shown as the duty out-licensing unit 24a. The duty DTY derived by the first derivation method is represented by the _{symbol "DTY 1" for convenience.} Duty DTY ₁ is represented by "DTY ₁ = V _OUT / V _IN ". When the first derivation method is adopted, an output monitoring terminal (not shown) connected to the node ND2 (see FIG. 1) _{to receive the output voltage V OUT} is provided in the power supply IC1 as an external terminal of the power supply IC1. You should leave it.

Further, for example, the duty derivation unit 24 may derive the duty DTY based on the _{switch voltage V SW.} As described above, a rectangular wavy voltage whose level fluctuates substantially between the input voltage V _{IN level and the ground level due to the switching operation appears as the switch voltage V SW} . For example, the voltage (V _IN / The switch voltage V _SW is binarized based on 2). In this case, the length of the section where the switch voltage V _SW is equal to _{or higher than the voltage (V IN} / 2) is regarded as the on-time of the output transistor M1 and the length of the section where the switch voltage V _SW is less than the voltage (V _IN / 2). The duty DTY may be derived by regarding the above as the off time of the output transistor M1.
Alternatively, for example, the duty derivation unit 24 may derive the duty DTY based on the gate signal G1 or the control signal CNT. In this case, the length of the high-level section of the gate signal G1 is regarded as the on-time of the output transistor M1 and the length of the low-level section of the gate signal G1 is regarded as the off-time of the output transistor M1 to derive the duty DTY. Alternatively, the duty DTY may be derived by regarding the length of the high-level section of the control signal CNT as the on-time of the output transistor M1 and the length of the low-level section of the control signal CNT as the off-time of the output transistor M1.
The method of deriving the duty DTY based on the switch voltage V _SW , the gate signal G1 or the control signal CNT is called the second derivation method, and the duty DTY derived by the second derivation method is represented by the symbol "DTY ₂ " for convenience. show.

When the first derivation method is used, the skip determination voltage V _TSKP at that timing may be determined and controlled _{based on the ratio (V OUT} / V _{IN) at a certain timing.} This also applies to the basic first improvement method, and in the basic first improvement method, the skip determination voltage _VTSKP at a certain timing may be determined and controlled _{based on the input voltage VIN at that timing.}

Even when the second derivation method is used, the skip determination voltage V _TSKP is adjusted in real time _{based on the duty DTY 2 at that time, but the derivation of the duty DTY 2} is performed by 1 of the output transistor M1. Strictly speaking, the current skip determination voltage _VTSKP is determined _{based on the past duty DTY 2} because switching for a cycle or more is required. That is, when the second derivation method is used _{, the duty DTY 2} in the first section is derived and derived _{based on the switch voltage V SW} , the gate signal G1 or the control signal CNT in an arbitrary first section. Based on the duty DTY ₂ in the section, the skip determination voltage _VTSKP in the second section after the first section is variably set.

Since the average voltage of the switch voltage V _{SW should correspond to the output voltage V OUT} , the following third derivation method can also be adopted. In the third derivation method, the duty DTY is derived based on the ratio of _{the average voltage of the switch voltage V SW} (in other words, the DC component of the _{switch voltage V SW ) and the input voltage V IN.} FIG. 26C shows a configuration example of the duty out-licensing unit 24 that employs the third out-licensing method as the duty out-licensing unit 24b. Duty deriving unit 24b 'and the filter block 24b_1 for generating a voltage _{V OUT'} voltage _{V OUT} corresponding to the average voltage of the switch voltage _{V SW} by averaging the switch voltage _{V SW} duty based on and _{V IN} DTY It is provided with a derivation block 24b_2 for deriving the above. Filter block 24b_1 is, for example, a low-pass filter consisting of resistors and capacitors are formed by a plurality of stages connected in series, is arbitrary as long as having a structure that can be derived average voltage of the switch voltage V _SW. Filter block 24b_1 can be regarded as a circuit for generating a DC component of the switch voltage _{V SW} as the voltage _{V OUT} 'by reducing the alternating current component of the switch voltage _{V SW.} The duty DTY derived by the third derivation method is represented by the _{symbol "DTY 3" for convenience.} Duty DTY ₃ is represented by "DTY ₃ = V _OUT '/ V _IN ".

When the third derivation method is used, the skip determination voltage at _{a certain timing is based on the ratio (V OUT} '/ V _IN ) at a certain timing, which is the same as the first derivation method and different from the second derivation method. _VTSKP can be determined and controlled. When the load current _ILD becomes completely zero, the output transistor M1 is not switched, so that the on-time of the output transistor M1 cannot be detected. However, the output voltage V _OUT by the output monitoring terminal receiving the output voltage V _OUT (not shown) if provided in the power supply IC1 is for detecting the voltage of the "I _{LD = 0"} is a also an output monitor terminal It is possible to obtain the information of the output voltage V _{OUT even when “ILD} = 0” according to the configuration as shown in FIG. 26 (c).

In the basic first improved technique, as described above, the skip determination voltage V _TSKP is increased as _{the input voltage VIN decreases.} Since a decrease in the input voltage V _IN causes an increase in the duty DTY, when the modified first improved technique is used, the skip determination voltage generation unit 23 is accompanied by an increase in _{the duty DTY (DTY 1} , DTY ₂ or DTY _{3). It is preferable} to increase the skip determination voltage V TSKP. As a result, the same effect as that of the basic first improved technique can be obtained. For example, the skip determination voltage V _TSKP may be determined based on the equation “V _TSKP = k ₁ · DTY + k _2”. In this equation, DTY is DTY ₁ , DTY ₂ or DTY ₃ , and k ₁ is a coefficient having a positive predetermined value. k ₂ has a positive or negative predetermined value. “K ₂ = 0” may be used.

The control for increasing the skip determination voltage _VTSKP as the duty DTY (DTY ₁ , DTY ₂ or DTY ₃ ) increases may be the control performed after the completion of the soft start operation, and during the execution of the soft start operation, the control may be performed. The skip determination voltage V _TSKP may be determined regardless of the duty DTY. For example, when using the circuit configuration of FIG. 22 (see also FIGS. 19 and 20), in the low level section of the signal SSEND, the voltage between both terminals of the resistor 117 _{is set to the skip determination voltage VTSKP,} and the high level of the signal SSEND is set. In the section, the skip determination voltage V _TSKP may be determined _{based on the equation “V TSKP} = k ₁ · DTY + k _{2”. In any case, when the second improved technology and the modified first improved technology are combined, the potential of the skip determination voltage VTSKP} is set to the initial potential when the switching power supply device AA is started (that is, when the power supply IC1 is started). After that (for example, after the signal SSEND is switched to the high level), _{the voltage corresponding to the duty DTY (DTY 1} , DTY ₂ or DTY ₃ ) may be set to the skip determination voltage _VTSKP.

<< Fourth Embodiment >>
A fourth embodiment of the present invention will be described. In the fourth embodiment, the applied technique, the modification technique, and the like applicable to any of the above-mentioned first to third embodiments will be described.

In the third embodiment, a configuration example of the skip determination voltage generation unit 23 capable of implementing both the first and second improved techniques has been described with reference to FIG. However, in the skip determination voltage generation unit 23, only the first improved technique may be carried out, or only the second improved technique may be carried out. However, it is preferable to implement both the first and second improved techniques.

The switching power supply device AA may be mounted on any electric device having a load LD. The switching power supply AA functions particularly beneficially in applications where there is a strong demand for reduction of ripple of output voltage V _{OUT and reduction of power consumption under light load, but the application of switching power supply AA is arbitrary.} An example of an electric device equipped with a switching power supply device AA is a PLC (Programmable Logic Controller). In this case, a microcomputer or ASIC (Application Specific Integrated Circuit) provided in the PLC can be the load LD.

Other examples of electrical equipment equipped with a switching power supply AA include home appliances such as refrigerators and washing machines. The lighting unit for illuminating the inside of the refrigerator can be a load LD. In the refrigerator, the lighting unit is turned off when the door is closed, while the lighting unit is turned on when the door is opened. Therefore, when the lighting unit becomes the load LD of the switching power supply device AA, the load current _ILD fluctuates greatly, and in the process of this fluctuation, smooth switching of control as described in each of the above-described embodiments effectively functions. do.

As described above, each circuit element of the power supply IC1 is formed in the form of a semiconductor integrated circuit, and the semiconductor device is configured by enclosing the semiconductor integrated circuit in a housing (package) made of resin. However, a circuit equivalent to the circuit in the power supply IC 1 may be configured by using a plurality of discrete components. Some of the circuit elements (for example, transistors M1 and M2) described above as included in the power supply IC1 may be provided outside the power supply IC1 and externally connected to the power supply IC1. On the contrary, some circuit elements described above as those provided outside the power supply IC1 may be provided inside the power supply IC1.

The switching power supply device AA includes a circuit for a switching power supply. It can be considered that the power supply IC 1 corresponds to the switching power supply circuit. It may be considered that the circuit obtained by removing a part of the components of the power supply IC1 from the above-mentioned power supply IC1 corresponds to the circuit for the switching power supply, or the above-mentioned power supply IC1 and any element other than the power supply IC1 are used for the switching power supply. You may think that the circuit is configured.

For any signal or voltage, the high-level and low-level relationships may be reversed in a manner that does not compromise the above-mentioned gist.

Each of the above-mentioned transistors may be any kind of transistor. For example, the transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor. Any transistor has a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In the IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is the base.

Although the configuration in which the present invention is applied to a step-down switching power supply of a synchronous rectification type is given as an example, the application target of the present invention is not limited to this, and the present invention is applied to a switching power supply of an asynchronous rectification type. The present invention may be applied to a step-up type or buck-boost type switching power supply device.

<< Consideration of the present invention >>
The present invention embodied in each of the above embodiments (particularly the third embodiment) will be considered.

The switching power supply circuit according to one aspect of the present invention (see FIGS. 1, 22, and 23) is a switching power supply circuit that generates an output voltage (V _{OUT ) from an input voltage (V IN) by a switching operation of an output transistor.} The error amplifier (11) that generates an _{error voltage (V CMP} ) according to the difference between the _{feedback voltage (V FB} ) corresponding to the output voltage and the reference voltage (V _{REF), and the output transistor It has a slope voltage generator (15) that generates a slope voltage (V SLP} ) according to the flowing current, and executes PWM control that performs the switching operation in synchronization with the clock signal based on the error voltage and the slope voltage. A skip comparator (21), comprising a possible control unit (10), which generates a skip signal (SKP) based on the result of comparison between the _{error voltage (V CMP} ) and the skip determination voltage ( _VTSKP). Further, the skip determination voltage generation unit (23) for generating the skip determination voltage is further provided, and the switching operation is performed according to the PWM control or the change in the height relationship between the error voltage and the skip determination voltage. The load control can be switched and executed based on the skip signal, and the skip determination voltage generation unit has a configuration (configuration _WA1 ) in which the skip determination voltage is variable according to the input voltage or the duty of the output transistor. Have.

According to the above configuration _WA1 , when the load is heavy to some extent, PWM control which performs switching operation in synchronization with the clock signal is executed, and when the load is light, the error voltage and the skip determination voltage are changed according to the change in the height relationship. It is possible to execute light load control that performs switching operation. Here, appropriate values are set for the skip determination voltage that enables stable operation of both PWM control and light load control, and the skip determination voltage for improving the efficiency (power conversion efficiency) during execution of light load control. It exists and its proper value depends on the input voltage or the duty of the output transistor. In consideration of this, the skip determination voltage is made variable according to the input voltage or the duty of the output transistor. As a result, the skip determination voltage is optimized according to the input voltage or the duty of the output transistor, and the stability of control and the efficiency at the time of light load control are improved.

Relates to a switching power supply circuit according to the above configuration W _A1, for example, in the above PWM control, the error voltage as the load current increases to receive a supply of the output voltage is changed toward the first direction (e.g., upward direction) As the current of the load becomes smaller, the error voltage changes in the second direction (for example, the downward direction) opposite to the first direction.
The skip comparator sets the skip signal to the first level (for example, SKP is low level when _{"V CMP} > V _{TSKP") when the error voltage is on the first direction side of the skip determination voltage, and the error.} When the voltage is on the second direction side of the skip determination voltage, the skip signal is set to the second level (for example, _{SKP is set to the high level when "V CMP} <V _TSKP "), and the control unit receives the skip signal. The PWM control is executed when the level is maintained at the first level (for example, low level), and the PWM control is stopped when the skip signal changes from the first level to the second level (for example, high level). _{The configuration (configuration WA2} ) that shifts to the light load control may be used.

As a result, when the load is heavy to some extent, PWM control is executed in which the switching operation is performed in synchronization with the clock signal, and when the load is light, the switching operation is performed according to the change in the height relationship between the error voltage and the skip determination voltage. The light load control to be performed will be executed. In such a configuration, by making the skip determination voltage variable according to the input voltage or the duty of the output transistor, the skip determination voltage is optimized according to the input voltage or the duty of the output transistor, and the control stability and lightness are reduced. Efficiency during load control can be improved.

In the switching power supply circuit according to the configuration _WA2 , for example, the slope voltage changes in the first direction (for example, an ascending direction) as the current flowing through the output transistor increases, and the error amplifier causes the error amplifier. The error voltage is configured to change in the first direction as the output voltage decreases, and in the PWM control, after the output transistor is turned on in synchronization with the clock signal, the error voltage and the error voltage are described. The output transistor is turned off based on the comparison result with the slope voltage, and in the light load control (see FIG. 12), the error voltage changes in the first direction (for example, the ascending direction) as the output voltage decreases. As a result, when the skip signal transitions from the second level (for example, high level) to the first level (for example, low level), the output transistor is turned on in response to the transition, and then the error voltage and the slope are used. The output transistor may be turned off based on the result of comparison with the voltage (configuration _WA3 ).

According to the configuration _WA3 , in PWM control, the on-time of the output transistor changes depending on the input voltage or the duty of the output transistor. In this case, if the skip determination voltage is fixed without depending on the input voltage or the duty of the output transistor, the on-time of the output transistor in PWM control is light depending on the input voltage or the duty of the output transistor. There is a large deviation from the on-time of the output transistor in load control. This can adversely affect your stability, including seamless switching of control schemes. Further, if the on-time of the output transistor in the light load control becomes too short, the efficiency in the light load control decreases. By appropriately adjusting the skip determination voltage according to the input voltage or the duty of the output transistor, the stability of control and the efficiency at the time of light load control can be improved.

The switching power supply circuit according to one aspect of the present invention (see FIGS. 1, 19, 20, 22, and 23) converts the input voltage (V _IN ) to the output voltage (V _OUT ) by the switching operation of the output transistor. An error amplifier (11), which is a switching power supply circuit _{to generate, and generates an error voltage (V CMP} ) according to the difference between the _{feedback voltage (V FB} ) corresponding to the output voltage and the reference voltage (V _{REF). It also has a slope voltage generator (15) that generates a slope voltage (VSLP} ) according to the current flowing through the output transistor, and has the switching operation in synchronization with the clock signal based on the error voltage and the slope voltage. A control unit (10) capable of executing PWM control is provided, and the control unit generates a skip signal (SKP) based on a comparison result between the _{error voltage (V CMP} ) and the skip determination voltage ( _VTSKP). It further has a skip comparator (21) and a skip determination voltage generation unit (23) that generates the skip determination voltage, and responds to the PWM control or the change in the height relationship between the error voltage and the skip determination voltage. the light load control for the switching operation, the a switchable executed based on the skip signal, the control unit may further include soft-start voltage generator for generating a soft-start voltage (V _SS) to (51), wherein When the switching power supply circuit is started, the soft start voltage generator gradually changes (for example, raises) the soft start voltage in the first direction across the reference voltage, and the error amplifier uses the soft start voltage. when the start voltage is in the first direction side than the reference voltage (when, for example, _{"V SS> V REF")} , and generates the error voltage according to a difference between the feedback voltage and the reference voltage, the soft start voltage than the reference voltage when in the second direction (when, for example, _{"V SS <V REF")} , and generates the error voltage according to a difference between the feedback voltage and the soft-start voltage, The first direction and the second direction are opposite to each other, and the skip determination voltage generation unit gradually changes the skip determination voltage toward the first direction when the switching power supply circuit is started. (Structure _WB1 ).

With the above configuration _WB1 , when the load is heavy to some extent, PWM control which performs switching operation in synchronization with the clock signal is executed, and when the load is light, the error voltage and the skip determination voltage are changed according to the change in the height relationship. It is possible to execute light load control that performs switching operation. Soft start the voltage gradually becomes possible to realize a soft-start operation to direct the desired voltage the output voltage by the function of the error amplifier utilizing, eventually skipping determination voltage if the skip determination voltage at all times a predetermined voltage (Configuration W _B1 Is the voltage to be fixed, and in FIG. 23, _{it corresponds to VTSKP} after _{timing t D2} ), the skip judgment voltage that is always fixed may hinder the ideal soft start operation. I am concerned. The configuration _WB1 eliminates such concerns.

Regarding the switching power supply circuit according to the configuration _WB1 , for example, in the PWM control, the error voltage changes in the first direction (for example, ascending direction) as the current of the load receiving the output voltage increases. As the current of the load becomes smaller, the error voltage changes toward the second direction (for example, the lowering direction), and the skip comparator has the error voltage higher than the skip determination voltage. When the skip signal is on the one-way side, the skip signal is set to the first level (for example, _{SKP is set to the low level when "V CMP} > V _TSKP "), and when the error voltage is on the second-direction side of the skip determination voltage, the skip signal is set. The skip signal is set to the second level (for example, _{SKP is set to a high level when "V CMP} <V _TSKP "), and the control unit performs the PWM when the skip signal is maintained at the first level (for example, low level). The control may be executed, and when the skip signal changes from the first level to the second level (for example, high level), the PWM control may be stopped and the control may be shifted to the light load control (configuration _WB2 ).

As a result, when the load is heavy to some extent, PWM control is executed in which the switching operation is performed in synchronization with the clock signal, and when the load is light, the switching operation is performed according to the change in the height relationship between the error voltage and the skip determination voltage. The light load control to be performed will be executed. If, (a final voltage should skip decision voltage is fixed in the structure W _B2, corresponding to the V _TSKP after timing t _D2 in FIG. 23) skip decision voltage is constantly predetermined voltage when being fixed at Immediately after the switching power supply circuit is started, the skip signal becomes the second level and the PWM control is stopped, which may hinder the ideal soft start operation. The configuration _WB2 eliminates such concerns.

In the switching power supply circuit according to the configuration _WB2 , for example, the slope voltage changes in the first direction (for example, an ascending direction) as the current flowing through the output transistor increases, and the error amplifier causes the error amplifier. The error voltage is configured to change in the first direction as the output voltage decreases, and in the PWM control, after the output transistor is turned on in synchronization with the clock signal, the error voltage and the error voltage are described. The output transistor is turned off based on the comparison result with the slope voltage, and in the light load control (see FIG. 12), the error voltage changes in the first direction (for example, the ascending direction) as the output voltage decreases. As a result, when the skip signal transitions from the second level (for example, high level) to the first level (for example, low level), the output transistor is turned on in response to the transition, and then the error voltage and the slope are used. The output transistor may be turned off based on the result of comparison with the voltage (configuration _WB3 ).

If, (a final voltage should skip decision voltage is fixed in the structure W _B2, corresponding to the V _TSKP after timing t _D2 in FIG. 23) skip decision voltage is constantly predetermined voltage when being fixed at Immediately after the switching power supply circuit is started, the skip signal becomes the second level and the PWM control is stopped, which may hinder the ideal soft start operation. The configuration _WB3 eliminates such concerns.

In the switching power supply AA of FIG. 1, the first level and the second level in the skip signal are low level and high level, respectively, but the first and second levels are high level and low level, respectively. The switching power supply device AA may be modified. That is, in a switching power supply circuit according to the present invention including a switching power supply circuit according to the configuration W _A1 to _W-A3 and W _B1 to _W-B3, of the first level and a second level, one can have a higher potential It doesn't matter. Strictly speaking, the fact that the skip signal is the first level and the second level means that the level of the skip signal is the first level and the second level (the same applies to other signals). It can also be considered that the first level skip signal is a skip signal having a first logical value, and the second level skip signal is a skip signal having a second logical value different from the first logical value (). The same applies to other signals). Further, in the switching power supply device AA of FIG. 1, the above-mentioned first direction and the second direction are the ascending direction and the descending direction, respectively, but the first direction and the second direction are the descending direction and the ascending direction, respectively. The switching power supply device AA may be modified so as to be. That is, in a switching power supply circuit according to the present invention including a switching power supply circuit according to the configuration W _A1 to _W-A3 and W _B1 to _W-B3, the first direction is the increasing direction and the second direction may be a reduction direction However, the first direction may be the downward direction and the second direction may be the upward direction.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and the constituent requirements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

AA switching power supply 1 Power supply IC
10 Control unit 11 Error amplifier 15 Slope voltage generator 16 Main comparator 17 Set signal generator 18 Control signal generator 21 Skip comparator 22 One-shot pulse generator 23 Skip judgment voltage generator 51 Soft start voltage generator M1 Output transistor M2 synchronization Rectifying transistor V _IN input voltage V _OUT output voltage V _FB feedback voltage

Claims (12)

In a switching power supply circuit that generates an output voltage from an input voltage by the switching operation of an output transistor.
It has an error amplifier that generates an error voltage according to the difference between the feedback voltage corresponding to the output voltage and the reference voltage, and a slope voltage generator that generates a slope voltage corresponding to the current flowing through the output transistor. A control unit capable of executing PWM control for performing the switching operation in synchronization with a clock signal based on the error voltage and the slope voltage is provided.
The control unit further includes a skip comparator that generates a skip signal based on a comparison result between the error voltage and the skip determination voltage, and a skip determination voltage generation unit that generates the skip determination voltage. The light load control that performs the switching operation according to the change in the height relationship between the error voltage and the skip determination voltage can be switched and executed based on the skip signal.
The skip determination voltage generation unit is a switching power supply circuit characterized in that the skip determination voltage is variable according to the input voltage or the duty of the output transistor. In the PWM control, the error voltage changes in the first direction as the current of the load receiving the output voltage becomes larger, and the error voltage becomes smaller in the first direction as the current of the load becomes smaller. It changes in the opposite direction to the second direction,
The skip comparator sets the skip signal as the first level when the error voltage is on the first direction side of the skip determination voltage, and when the error voltage is on the second direction side of the skip determination voltage. The skip signal is set as the second level.
The control unit executes the PWM control when the skip signal is maintained at the first level, and stops the PWM control when the skip signal changes from the first level to the second level. The switching power supply circuit according to claim 1, wherein the circuit shifts to light load control. The slope voltage changes in the first direction as the current flowing through the output transistor increases.
The error amplifier is configured such that the error voltage changes in the first direction as the output voltage decreases.
In the PWM control, after turning on the output transistor in synchronization with the clock signal, the output transistor is turned off based on the result of comparison between the error voltage and the slope voltage.
In the light load control, when the skip signal transitions from the second level to the first level by changing the error voltage in the first direction as the output voltage decreases, the skip signal responds to the transition. The switching power supply circuit according to claim 2, wherein the output transistor is turned on, and then the output transistor is turned off based on a comparison result between the error voltage and the slope voltage. The switching according to claim 2 or 3, wherein the skip determination voltage generation unit changes the skip determination voltage in the first direction as the input voltage decreases or the duty of the output transistor increases. Power supply circuit. The control unit further includes a soft start voltage generation unit that generates a soft start voltage.
At the time of starting the switching power supply circuit, the soft start voltage generation unit gradually changes the soft start voltage in the first direction across the reference voltage.
When the soft start voltage is on the first direction side of the reference voltage, the error amplifier generates the error voltage according to the difference between the feedback voltage and the reference voltage, and the soft start voltage is the soft start voltage. When it is on the second direction side of the reference voltage, the error voltage is generated according to the difference between the feedback voltage and the soft start voltage.
The skip determination voltage generation unit gradually changes the skip determination voltage toward the first direction when the switching power supply circuit is started, and then the voltage corresponding to the input voltage or the duty of the output transistor. The switching power supply circuit according to any one of claims 2 to 4, wherein a voltage corresponding to the above is set to the skip determination voltage. The switching power supply circuit according to claim 5, wherein the skip determination voltage generation unit uses the soft start voltage to gradually change the skip determination voltage toward the first direction. The invention according to any one of claims 1 to 6, wherein when an inductor is connected in series to the output transistor and the output transistor is in the ON state, a current based on the input voltage flows through the output transistor and the inductor. Circuit for switching power supply. In a switching power supply circuit that generates an output voltage from an input voltage by the switching operation of an output transistor.
It has an error amplifier that generates an error voltage according to the difference between the feedback voltage corresponding to the output voltage and the reference voltage, and a slope voltage generator that generates a slope voltage corresponding to the current flowing through the output transistor. A control unit capable of executing PWM control for performing the switching operation in synchronization with a clock signal based on the error voltage and the slope voltage is provided.
The control unit further includes a skip comparator that generates a skip signal based on a comparison result between the error voltage and the skip determination voltage, and a skip determination voltage generation unit that generates the skip determination voltage. The light load control that performs the switching operation according to the change in the height relationship between the error voltage and the skip determination voltage can be switched and executed based on the skip signal.
The control unit further includes a soft start voltage generation unit that generates a soft start voltage.
When the switching power supply circuit is started, the soft start voltage generator gradually changes the soft start voltage in the first direction across the reference voltage.
When the soft start voltage is on the first direction side of the reference voltage, the error amplifier generates the error voltage according to the difference between the feedback voltage and the reference voltage, and the soft start voltage is the soft start voltage. When it is on the second direction side of the reference voltage, the error voltage is generated according to the difference between the feedback voltage and the soft start voltage.
The first direction and the second direction are opposite to each other.
The skip determination voltage generation unit is a switching power supply circuit characterized in that the skip determination voltage is gradually changed toward the first direction when the switching power supply circuit is started. In the PWM control, the error voltage changes in the first direction as the current of the load receiving the output voltage becomes larger, and the error voltage becomes the second as the current of the load becomes smaller. Changing in the direction,
The skip comparator sets the skip signal as the first level when the error voltage is on the first direction side of the skip determination voltage, and when the error voltage is on the second direction side of the skip determination voltage. The skip signal is set as the second level.
The control unit executes the PWM control when the skip signal is maintained at the first level, and stops the PWM control when the skip signal changes from the first level to the second level. The switching power supply circuit according to claim 8, further comprising shifting to light load control. The slope voltage changes in the first direction as the current flowing through the output transistor increases.
The error amplifier is configured such that the error voltage changes in the first direction as the output voltage decreases.
In the PWM control, after turning on the output transistor in synchronization with the clock signal, the output transistor is turned off based on the result of comparison between the error voltage and the slope voltage.
In the light load control, when the skip signal transitions from the second level to the first level by changing the error voltage in the first direction as the output voltage decreases, the skip signal responds to the transition. The switching power supply circuit according to claim 9, wherein the output transistor is turned on, and then the output transistor is turned off based on a comparison result between the error voltage and the slope voltage. The switching power supply according to any one of claims 8 to 10, wherein the skip determination voltage generation unit gradually changes the skip determination voltage toward the first direction by using the soft start voltage. circuit. 8. Circuit for switching power supply.

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