[go: up one dir, main page]

JP2021044468A - Submount - Google Patents

Submount Download PDF

Info

Publication number
JP2021044468A
JP2021044468A JP2019166870A JP2019166870A JP2021044468A JP 2021044468 A JP2021044468 A JP 2021044468A JP 2019166870 A JP2019166870 A JP 2019166870A JP 2019166870 A JP2019166870 A JP 2019166870A JP 2021044468 A JP2021044468 A JP 2021044468A
Authority
JP
Japan
Prior art keywords
film
metal film
submount
solder
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019166870A
Other languages
Japanese (ja)
Other versions
JP7324665B2 (en
Inventor
光教 宮本
Mitsunori Miyamoto
光教 宮本
俊秀 関根
Toshihide Sekine
俊秀 関根
隆俊 木内
Takatoshi Kiuchi
隆俊 木内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Citizen Fine Device Co Ltd
Original Assignee
Citizen Watch Co Ltd
Citizen Fine Device Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd, Citizen Fine Device Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2019166870A priority Critical patent/JP7324665B2/en
Publication of JP2021044468A publication Critical patent/JP2021044468A/en
Application granted granted Critical
Publication of JP7324665B2 publication Critical patent/JP7324665B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Other Surface Treatments For Metallic Materials (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Lasers (AREA)

Abstract

To provide a submount that can stabilize a composition of a solder film and stably generate a eutectic structure of the solder film.SOLUTION: A submount 10 for placing electronic components on a support substrate includes a substrate 11, a first metal film 12b formed on at least one side of the substrate 11, and a solder film 14b formed on the first metal film 12b. On the side surface of the first metal film 12b, there is a second metal film 15a with a surface that has better wettability for the solder film 14b than that of the first metal film 12b.SELECTED DRAWING: Figure 1

Description

本発明は、レーザー素子等の電子部品を実装し、電子部品をステムや筐体等の支持基板に配置するためのサブマウントに関する。 The present invention relates to a submount for mounting an electronic component such as a laser element and arranging the electronic component on a support substrate such as a stem or a housing.

レーザー素子は、電流を光に変換する半導体素子であるが、光の変換効率が完全ではないので、必ず電流ロスがあり、そのロス分は熱に変換される。レーザー素子を実装するサブマウントには、電極配線の役割と素子から発生した熱を筐体に素早く伝達する役割がある。 A laser element is a semiconductor element that converts a current into light, but since the conversion efficiency of light is not perfect, there is always a current loss, and the loss is converted into heat. The submount on which the laser element is mounted has the role of electrode wiring and the role of quickly transferring the heat generated from the element to the housing.

レーザー用サブマウントは、熱伝導率の高いAlN等からなる基板上にレーザーを実装するためのはんだ膜と、サブマウントを支持基板に配置するためのはんだ膜とを備えている。これらのはんだ膜としてはAuSnはんだ膜が広く利用されており、このAuSnはんだ膜は基板に形成した薄膜のメタライズ(例えば、基板側よりTi/Pt/Auの積層膜)上に成膜されることが一般的である。 The laser submount includes a solder film for mounting the laser on a substrate made of AlN or the like having high thermal conductivity, and a solder film for arranging the submount on the support substrate. AuSn solder films are widely used as these solder films, and the AuSn solder films are formed on a metallized thin film formed on a substrate (for example, a Ti / Pt / Au laminated film from the substrate side). Is common.

また、レーザー用サブマウントの熱伝導率を更に高めるために、基板の表裏に熱伝導性のよい銅めっき等からなる厚い金属膜を配置したサブマウントが開発されている(例えば、特許文献1参照。)。図4は従来のサブマウントの模式図である。サブマウント100は、AlNからなる基板101の表裏面に銅めっき102a、102bを備えている。サブマウント100における一方の面に形成された銅めっき102aの上面には、レーザー素子を実装するためのAuSnはんだ膜103を備え、他方の面の銅めっき102bの上面全面には銅サブマウント100を図示しない支持基板へ取り付けるためのAuSnはんだ膜104を備えている。はんだ膜103と銅めっき102aの間、及びはんだ膜104と銅めっき102bの間には、銅めっき102a、102bの表面側よりTi/Pt/Auのメタライズ(不図示)が形成されている。銅めっき102a、102bの厚さは、一般的には20μm以上であり、100μmを超える場合もある。サブマウント100全体の体積のうち、銅めっき102a、102bの比率が高いほどサブマウント100の熱伝導率が高くなり、銅めっき102a,102bを備えていないサブマウントに比べて、レーザーの高出力化および省電力化が期待できる。 Further, in order to further increase the thermal conductivity of the laser submount, a submount in which a thick metal film made of copper plating or the like having good thermal conductivity is arranged on the front and back of the substrate has been developed (see, for example, Patent Document 1). .). FIG. 4 is a schematic view of a conventional submount. The submount 100 includes copper plating 102a and 102b on the front and back surfaces of the substrate 101 made of AlN. An AuSn solder film 103 for mounting a laser element is provided on the upper surface of the copper plating 102a formed on one surface of the submount 100, and the copper submount 100 is provided on the entire upper surface of the copper plating 102b on the other surface. An AuSn solder film 104 for attaching to a support substrate (not shown) is provided. Ti / Pt / Au metallization (not shown) is formed between the solder film 103 and the copper plating 102a and between the solder film 104 and the copper plating 102b from the surface side of the copper plating 102a and 102b. The thickness of the copper platings 102a and 102b is generally 20 μm or more, and may exceed 100 μm. The higher the ratio of the copper plating 102a and 102b to the total volume of the submount 100, the higher the thermal conductivity of the submount 100, and the higher the laser output than the submount without the copper plating 102a and 102b. And power saving can be expected.

特開平5−13820号公報Japanese Unexamined Patent Publication No. 5--13820

従来のサブマウントは、厚膜で形成した金属膜(従来例における銅めっき102a、102b)の側面が露出している。この金属膜を銅めっき、はんだ膜をAuSnはんだで形成した場合、はんだ膜を溶融して接合相手部材(例えば、レーザー素子やステム等の支持基板)と接合したとき、はんだ膜を構成するSn成分が金属膜へ拡散する。また、はんだ膜の拡散により金属膜側面とはんだ膜界面の物理的状況の変化によりはんだ膜の濡れ性が低下し、はんだ膜の金属膜側への濡れ広がりが不足し、代わって接合相手部材側に無駄に濡れ広がってしまうことがある。このような場合、はんだ膜の組成が不安定となり、本来のはんだ膜の共晶組織が得られなくなる。 In the conventional submount, the side surfaces of the metal film (copper plating 102a, 102b in the conventional example) formed of the thick film are exposed. When this metal film is copper-plated and the solder film is formed of AuSn solder, when the solder film is melted and bonded to a bonding partner member (for example, a supporting substrate such as a laser element or a stem), the Sn component constituting the solder film is formed. Diffuses into the metal film. In addition, due to the diffusion of the solder film, the wettability of the solder film is reduced due to the change in the physical condition between the side surface of the metal film and the interface between the solder film, and the wettability of the solder film to the metal film side is insufficient. It may get wet and spread unnecessarily. In such a case, the composition of the solder film becomes unstable, and the original eutectic structure of the solder film cannot be obtained.

はんだ膜の共晶組織が得られず、亜共晶あるいは過共晶となれば、接合強度が弱くなり、特にヒートサイクル試験などの熱膨張と熱収縮により接合部にクラックが生じやすくなり、著しく接合強度が低下する。 If the eutectic structure of the solder film cannot be obtained and it becomes subeutectic or hypereutectic, the joint strength becomes weak, and cracks are likely to occur at the joint due to thermal expansion and contraction, especially in a heat cycle test, which is remarkable. Bond strength decreases.

本発明は、上記課題を解決するために成されたものであり、はんだ膜の組成を安定化させ、はんだ膜の共晶組織を安定的に生成できるサブマウントを提供するものである。 The present invention has been made to solve the above problems, and provides a submount capable of stabilizing the composition of a solder film and stably forming a eutectic structure of the solder film.

電子部品を支持基板に配置するためのサブマウントであって、基板と、当該基板の少なくとも一方の面に形成された第1金属膜と、前記第1金属膜上に形成されたはんだ膜と、を備え、前記第1金属膜の側面上に、前記第1金属膜より前記はんだ膜のぬれ性がよい表面を備えた第2金属膜を有するサブマントとする。
さらに、前記第1金属膜の上面上であり、前記第1金属膜と前記はんだ膜との間に前記第2金属膜をさらに有するサブマウントとしてもよい。
また、前記第2金属膜は、前記第1金属膜より前記はんだ膜のぬれ性がよい表面金属層、該表面金属層の下層に位置し前記はんだ膜に対するバリア層及び該バリア層の下層であり前記第1金属膜と密着する密着層を備えたサブマウントとしてもよい。
また、前記第1金属膜の側面上に形成された第2金属膜と、前記第1金属膜の上面上に形成された前記第2金属膜とは、異なる材料により構成したサブマウントとしてもよい。
さらに、前記第2金属膜は、蒸着またはスパッタにより形成され、前記第2金属層の下層には、めっき法により形成され、前記第1金属膜より前記第1金属膜より前記はんだ膜のぬれ性がよい表面を備えた第3金属膜を有するサブマウントとしてもよい。
さらにまた、前記第1金属膜の側面は、前記第1金属膜の表面から前記基板に向かい広がる傾斜面としたサブマウントとしてもよい。
A submount for arranging electronic components on a support substrate, the substrate, a first metal film formed on at least one surface of the substrate, and a solder film formed on the first metal film. A submanto having a second metal film having a surface on the side surface of the first metal film, which has a better wettability of the solder film than the first metal film.
Further, it may be a submount which is on the upper surface of the first metal film and further has the second metal film between the first metal film and the solder film.
Further, the second metal film is a surface metal layer having better wettability of the solder film than the first metal film, a barrier layer for the solder film located below the surface metal layer, and a lower layer of the barrier layer. It may be a submount provided with an adhesion layer that adheres to the first metal film.
Further, the second metal film formed on the side surface of the first metal film and the second metal film formed on the upper surface of the first metal film may be a submount made of different materials. ..
Further, the second metal film is formed by vapor deposition or sputtering, and is formed by a plating method under the second metal layer, and the wettability of the solder film from the first metal film to the first metal film. It may be a submount having a third metal film having a good surface.
Furthermore, the side surface of the first metal film may be a submount having an inclined surface extending from the surface of the first metal film toward the substrate.

本発明のサブマウントによれば、サブマウントと、サブマウントと接合される接合部材とを接合するはんだ膜の組成を安定化させ、はんだ膜の共晶組織を安定的に生成することができる。 According to the submount of the present invention, the composition of the solder film that joins the submount and the joining member to be joined to the submount can be stabilized, and the eutectic structure of the solder film can be stably generated.

本発明に係るサブマウントの断面図である。It is sectional drawing of the submount which concerns on this invention. 本発明に係るサブマウントの断面図であり、サブマウントにレーザー素子およびステムが接合された後を示す図である。It is sectional drawing of the submount which concerns on this invention, and is the figure which shows after the laser element and the stem are bonded to the submount. 本発明に係るサブマウントの断面図である。It is sectional drawing of the submount which concerns on this invention. 従来のサブマウントの斜視図である。It is a perspective view of the conventional submount.

以下図面を参照して、本発明に係るサブマウントについて説明する。但し、本発明の技術的範囲はそれらの実施の形態に限定されず、特許請求の範囲に記載された発明とその均等物に及ぶ。 The submount according to the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to those embodiments, but extends to the inventions described in the claims and their equivalents.

図1は、本発明に係るサブマウントの第1実施形態の断面図である。 FIG. 1 is a cross-sectional view of the first embodiment of the submount according to the present invention.

サブマウント10は、AlN基板11と、AlN基板11の一方の面上に形成された銅めっき12aと、他方の面上に形成された銅めっき12bと、銅めっき12aの表面上に形成され、銅めっき12aの表面側から順にTi/Pt/Auの膜が積層された積層膜13aと、銅めっき12bの表面上に形成され、銅めっき12bの表面側から順にTi/Pt/Auの膜が積層された積層膜13bとを備える。銅めっき12a、12bは、AlN基板11の外形より小さく形成されており、積層膜13aは、銅めっき12aが形成されていないAlN基板11の一方の面上にも形成されており、積層膜13bは、銅めっき12b及び後述するNiめっき膜15aが形成されていないAlN基板11の他方の面上にも形成されている。さらに、サブマウント10は、積層膜13aの表面上に形成され、電子部品を実装するためのAuSnはんだ膜14aと、積層膜13bの表面上に形成され、ステム等の支持基板にサブマウント10を実装するためのAuSnはんだ膜14bとを備える。さらにまた、サブマウント10は、銅めっき12bの表面からAlN基板11の表面にわたり銅めっき12bの側面に形成されたNiめっき膜15aを備える。 The submount 10 is formed on the surface of the AlN substrate 11, the copper plating 12a formed on one surface of the AlN substrate 11, the copper plating 12b formed on the other surface, and the copper plating 12a. A laminated film 13a in which Ti / Pt / Au films are laminated in order from the surface side of the copper plating 12a, and a Ti / Pt / Au film formed on the surface of the copper plating 12b in order from the surface side of the copper plating 12b. It includes a laminated laminated film 13b. The copper platings 12a and 12b are formed smaller than the outer shape of the AlN substrate 11, and the laminated film 13a is also formed on one surface of the AlN substrate 11 on which the copper plating 12a is not formed. Is also formed on the other surface of the AlN substrate 11 on which the copper plating 12b and the Ni plating film 15a described later are not formed. Further, the submount 10 is formed on the surface of the laminated film 13a and is formed on the surface of the AuSn solder film 14a for mounting electronic components and the laminated film 13b, and the submount 10 is mounted on a support substrate such as a stem. It is provided with an AuSn solder film 14b for mounting. Furthermore, the submount 10 includes a Ni plating film 15a formed on the side surface of the copper plating 12b from the surface of the copper plating 12b to the surface of the AlN substrate 11.

AlN基板11は、例えばYをバインダーとして添加されたAlN焼結体を用いることできる。サブマウント10は高い熱伝導率を有することが望ましく、その観点から、SiC基板やその他のセラミックスも用いることができる。AlN基板11は、表面が研磨されていることが望ましいが、研削面や焼結後そのままの面でも構わない。 AlN substrate 11, for example, a Y 2 O 3 can be used the added AlN sintered body as a binder. It is desirable that the submount 10 has a high thermal conductivity, and from this viewpoint, a SiC substrate or other ceramics can also be used. The surface of the AlN substrate 11 is preferably polished, but a ground surface or a surface as it is after sintering may be used.

銅めっき12a、12bは、サブマウント10の熱伝導率を向上させるための金属膜であり、電気めっきで形成することができる。銅めっき12a、12bは、サブマント10を構成する部材の中で最も熱伝導率が高く、サブマウント10の熱伝導性の向上に寄与する。また、銅めっき12a、12bを電気めっきで形成する場合は、めっき成長のシードメタル膜として、あらかじめAlN基板11の表面に、表面側からTi/CuあるいはTiW/Cuの積層膜が薄膜で成膜されている(不図示。)。シードメタル膜におけるTiまたはTiWの膜は、AlN基板11とシードメタル膜のCuとを密着させる密着膜であるが、サブマウント10の基材に応じて、CrやNiなどを用いることもできる。電気めっきのほか、銅箔をAlN基板11にボンディング(DBC:Direct bonding copper)することでも同様の構造が得られる。銅箔をAlN基板11にボンディングする場合は、両者の密着性を向上させるため、AlN基板11または銅箔の表面を酸化処理したり、表面に金属膜を形成したりして行ってもよい。なお、銅めっき12a、12bは、熱伝導性のよい材料であれば銅めっきに限らず他の材料による金属膜としてもよく、その厚みが大きい程、熱伝導性の向上を図ることができる。 The copper platings 12a and 12b are metal films for improving the thermal conductivity of the submount 10, and can be formed by electroplating. The copper platings 12a and 12b have the highest thermal conductivity among the members constituting the submanto 10, and contribute to the improvement of the thermal conductivity of the submount 10. When the copper platings 12a and 12b are formed by electroplating, a Ti / Cu or TiW / Cu laminated film is formed as a thin film on the surface of the AlN substrate 11 in advance as a seed metal film for plating growth. (Not shown). The Ti or TiW film in the seed metal film is an adhesive film that adheres the AlN substrate 11 and the Cu of the seed metal film, but Cr, Ni, or the like can also be used depending on the base material of the submount 10. In addition to electroplating, a similar structure can be obtained by bonding a copper foil to the AlN substrate 11 (DBC: Direct bonding copper). When the copper foil is bonded to the AlN substrate 11, the surface of the AlN substrate 11 or the copper foil may be oxidized or a metal film may be formed on the surface in order to improve the adhesion between the two. The copper platings 12a and 12b are not limited to copper plating as long as they are materials having good thermal conductivity, and may be a metal film made of another material. The larger the thickness, the better the thermal conductivity.

銅めっき12a、12bは、AlN基板11より外形が小さく、エッチングによって、任意のパターン形状を作製することができる(サブトラクティブ法)。任意のパターン形状とする方法としては、レジスト開口したところに銅めっきして、直接所望の銅パターン形状を形成する方法でもよい(アディティブ法)。また、銅めっき12a、12bの側面は、AlN基板11に向かって広がる傾斜面となっている。 The copper platings 12a and 12b have a smaller outer shape than the AlN substrate 11, and any pattern shape can be produced by etching (subtractive method). As a method of forming an arbitrary pattern shape, a method of directly forming a desired copper pattern shape by copper plating on the resist opening (additive method) may be used. Further, the side surfaces of the copper platings 12a and 12b are inclined surfaces that spread toward the AlN substrate 11.

Ti/Pt/Au積層膜13a、13bは、典型的には厚さが、Ti=0.06μm、Pt=0.2μm、Au=0.5μm程度となるように成膜され、真空蒸着やスパッタリングを用いることができる。Tiは密着層、PtはAuSnはんだ膜14a、14b融解時の拡散を防止するバリア層、AuはAuSnはんだ膜14a、14bの融解時にAuSnはんだ膜14a、14b内に拡散し、AuSn全体の組成変動量を調節するための層である。バリア層は、Ptの他、Ni、Pd、Coなども用いることができる。但し、厚さは上述の限りではない。 The Ti / Pt / Au laminated films 13a and 13b are typically formed so that the thickness is about Ti = 0.06 μm, Pt = 0.2 μm, Au = 0.5 μm, and vacuum deposition or sputtering is performed. Can be used. Ti is an adhesion layer, Pt is a barrier layer that prevents diffusion when the AuSn solder films 14a and 14b are melted, Au is diffused into the AuSn solder films 14a and 14b when the AuSn solder films 14a and 14b are melted, and the composition of the entire AuSn varies. It is a layer for adjusting the amount. As the barrier layer, Ni, Pd, Co and the like can be used in addition to Pt. However, the thickness is not limited to the above.

AuSnはんだ膜14a、14bは、AuとSnの組成比が共晶点になるように調整された層であり、真空蒸着やスパッタリングを用いることができる。好ましくは、AuとSnを別々の蒸発源から蒸発させて所望の組成を得る2元同時蒸着法は膜質や組成が均一化するので良い。他にも、AuとSnを積層させて構成しても良い。 The AuSn solder films 14a and 14b are layers in which the composition ratio of Au and Sn is adjusted to be a eutectic point, and vacuum deposition or sputtering can be used. Preferably, the two-way simultaneous vapor deposition method in which Au and Sn are evaporated from different evaporation sources to obtain a desired composition is good because the film quality and composition are uniform. Alternatively, Au and Sn may be laminated to form a structure.

AuSnはんだ膜14、14bは、AuとSnの組成比をおよそ71:29(atomic%)が信頼性や接合強度の観点から良く用いられるが、6.3:93.7の組成比でも用いることができる。この組成比は、接合後にこの組成比となることが良く、Ti/Pt/Au積層膜13a、13bに含まれるAuや接合相手(電子部品や支持基板)に含まれるAuと混ざり合うため、予め、AuSnはんだ膜14a、14bはそれを見越して過共晶に設定しておくと良い。 For AuSn solder films 14 and 14b, a composition ratio of Au and Sn of about 71:29 (atomic%) is often used from the viewpoint of reliability and bonding strength, but a composition ratio of 6.3: 93.7 is also used. Can be done. This composition ratio is often set to this composition ratio after bonding, and is mixed with Au contained in the Ti / Pt / Au laminated films 13a and 13b and Au contained in the bonding partner (electronic component or supporting substrate) in advance. , AuSn solder films 14a and 14b should be set to hypereutectic in anticipation of this.

AuSnはんだ膜14aは、厚さが約1〜3μm程度であり、レーザー素子等の電子部品と接合する層であり、フォトリソなどによって、パターン化されている。一方、AuSnはんだ膜14bは、厚さが約3〜7μm程度であり、筐体あるいはステム等の支持基板と接合する層である。 The AuSn solder film 14a has a thickness of about 1 to 3 μm, is a layer for joining with an electronic component such as a laser element, and is patterned by a photolithography or the like. On the other hand, the AuSn solder film 14b has a thickness of about 3 to 7 μm, and is a layer for joining to a support substrate such as a housing or a stem.

Niめっき膜15aは、銅めっき12bの側面に形成される層であり、AuSnはんだ膜14bや、AuSnはんだ膜14bとTi/Pt/Au積層膜13bに含まれるAuや接合相手(支持基板)に形成されたサブマウント10搭載のためのAuとが混ざり合ったはんだ膜に対して、銅めっき12bより濡れ性のよい材料により構成される。Niめっき膜15aは、AuSnはんだ膜14bの溶融時にAuSnはんだ膜14bや、AuSnはんだ膜14bとTi/Pt/Au積層膜13bに含まれるAuや接合相手(支持基板)に形成されたサブマウント10搭載のためのAuとが混ざり合ったはんだ膜が銅めっき12bの側面を濡れ広がりよくするための層であり、更にはAuSnはんだ膜14bのSnが銅めっき12b中へ拡散することを抑制するためのバリア層としても機能する。Niめっき膜15aは、このはんだ膜に対し濡れ性のよい材料で構成すればNiに限らずPd、Coなどでも形成できるが、特にNiが望ましい。Niがよい理由は、AuSnはんだに対し濡れ性がよく、Ptに次いでAuSnはんだへの融解速度が遅い(バリア性が高い)ためである。なお、Niめっき膜15aとAlN基板11との間には、銅めっき12a、12bとAlN基板11との間に配設されたシードメタル膜が延設されていてもよい。この場合、Niめっき膜15aとAlN基板11との間において、このシードメタル膜は、Niめっき膜15aとAlN基板11とを密着させる密着膜として機能する。さらに、このシードメタル膜は、Ti/Pt/Au積層膜13a、13bとAlN基板11との間にまで延設してもよい。しかし、シードメタル膜におけるAlN基板11との密着層をTiWとした場合は、Ti/Pt/Au積層膜13a、13bにおけるAlN基板11との密着層であるTiと比較してAlN基板11との密着力が小さいことより、AuSnはんだ膜14bを溶融凝固した時の応力等によってAlN基板11との界面で剥離を引き起こす恐れがあり、この場合は、Ti/Pt/Au積層膜13a、13bとAlN基板11との間までシードメタル膜を延設しない方が好ましい。つまり、シードメタル膜とAlN基板11との密着力が、Ti/Pt/Au積層膜13a、13bとAlN基板11との密着力より小さい場合は、Ti/Pt/Au積層膜13a、13bとAlN基板11との間にシードメタル膜を配設しない方が好ましく、シードメタル膜とAlN基板11との密着力が、Ti/Pt/Au積層膜13a、13bとAlN基板11との密着力より大きい場合は、Ti/Pt/Au積層膜13a、13bとAlN基板11との間までシードメタル膜を配設してもよい。 The Ni plating film 15a is a layer formed on the side surface of the copper plating 12b, and is used on the AuSn solder film 14b, Au contained in the AuSn solder film 14b and the Ti / Pt / Au laminated film 13b, and the bonding partner (support substrate). It is made of a material having better wettability than copper plating 12b with respect to the formed solder film mixed with Au for mounting the submount 10. The Ni plating film 15a is a submount 10 formed on the AuSn solder film 14b when the AuSn solder film 14b is melted, Au contained in the AuSn solder film 14b and the Ti / Pt / Au laminated film 13b, and a bonding partner (support substrate). The solder film mixed with Au for mounting is a layer for making the side surface of the copper plating 12b wet and spread well, and further, for suppressing the Sn of the AuSn solder film 14b from diffusing into the copper plating 12b. It also functions as a barrier layer for soldering. The Ni plating film 15a can be formed not only with Ni but also with Pd, Co, etc. if it is made of a material having good wettability with respect to the solder film, but Ni is particularly preferable. The reason why Ni is good is that it has good wettability with respect to AuSn solder, and the melting rate to AuSn solder is slow (high barrier property) next to Pt. A seed metal film disposed between the copper platings 12a and 12b and the AlN substrate 11 may extend between the Ni plating film 15a and the AlN substrate 11. In this case, between the Ni plating film 15a and the AlN substrate 11, the seed metal film functions as an adhesion film that adheres the Ni plating film 15a and the AlN substrate 11. Further, the seed metal film may extend between the Ti / Pt / Au laminated films 13a and 13b and the AlN substrate 11. However, when the adhesion layer of the seed metal film with the AlN substrate 11 is TiW, it is compared with the Ti which is the adhesion layer with the AlN substrate 11 of the Ti / Pt / Au laminated films 13a and 13b with the AlN substrate 11. Since the adhesion is small, there is a risk of peeling at the interface with the AlN substrate 11 due to stress when the AuSn solder film 14b is melt-solidified. In this case, the Ti / Pt / Au laminated films 13a, 13b and AlN may occur. It is preferable not to extend the seed metal film between the substrate 11 and the substrate 11. That is, when the adhesion between the seed metal film and the AlN substrate 11 is smaller than the adhesion between the Ti / Pt / Au laminated films 13a and 13b and the AlN substrate 11, the Ti / Pt / Au laminated films 13a and 13b and AlN It is preferable not to dispose the seed metal film between the substrate 11 and the adhesion between the seed metal film and the AlN substrate 11 is larger than the adhesion between the Ti / Pt / Au laminated films 13a and 13b and the AlN substrate 11. In this case, the seed metal film may be arranged between the Ti / Pt / Au laminated films 13a and 13b and the AlN substrate 11.

Niめっき膜15aは、電気めっきや無電解めっきで形成することができ、厚さは上述の機能が発現すれば良いが、1μm以上が好ましい。真空蒸着やスパッタリングを用いることも可能であるが、この方法では銅めっき12bの側面に成膜されにくく、銅めっき12b側面の表面が露出する場合があるため、電気めっきなどで形成するのが好ましい。なお、Niめっき膜15aの側面を本実施例のように傾斜面とすることで、Niめっき膜15aの形成方法に関わらず、銅めっき12bの側面にNiめっき膜15aをより確実に形成することができる。また、図1に示す本実施例では、Niめっき膜15aを銅めっき12bの側面にのみ形成しているが、銅めっき12bの側面に加え、銅めっき12bとTi/Pt/Au積層膜13bとの間にNiめっき膜15aを備えた構成であっても、何ら問題無い。 The Ni plating film 15a can be formed by electroplating or electroless plating, and the thickness may be 1 μm or more as long as the above-mentioned functions are exhibited. Although it is possible to use vacuum deposition or sputtering, it is difficult to form a film on the side surface of the copper plating 12b by this method, and the surface of the side surface of the copper plating 12b may be exposed. Therefore, it is preferable to form the film by electroplating or the like. .. By making the side surface of the Ni plating film 15a an inclined surface as in this embodiment, the Ni plating film 15a can be more reliably formed on the side surface of the copper plating 12b regardless of the method of forming the Ni plating film 15a. Can be done. Further, in the present embodiment shown in FIG. 1, the Ni plating film 15a is formed only on the side surface of the copper plating 12b, but in addition to the side surface of the copper plating 12b, the copper plating 12b and the Ti / Pt / Au laminated film 13b are formed. There is no problem even if the configuration is provided with the Ni plating film 15a between the two.

次に、本発明に係るサブマウントにレーザー素子を搭載し、ステムに接合した状態を説明する。図2は、本発明に係るサブマウントの断面図であり、サブマウントにレーザー素子およびステムが接合された後の図である。 Next, a state in which the laser element is mounted on the submount according to the present invention and joined to the stem will be described. FIG. 2 is a cross-sectional view of the submount according to the present invention, which is a view after the laser element and the stem are joined to the submount.

サブマウント10は、AuSnはんだ膜14aを接合膜としてレーザー素子21を搭載し、AuSnはんだ膜14bを接合膜としてステム22に搭載される。図示していないが、レーザー素子21及びステム22の表面には、それぞれサブマウント10との接合のためのメタライズ膜が予め形成されており、AuSnはんだ膜14a、14bの溶融時にAuSnはんだ膜14a、14bとの接合膜として機能する。具体的には、AuSnはんだ膜14aとレーザー素子21表面のメタライズが接合し、AuSnはんだ膜14bとステム22表面のメタライズ膜とが接合する。レーザー素子21とステム22のメタライズ膜は、例えば、レーザー素子21、ステム22の表面側よりTi/Pt/Auを積層した積層膜、またはNi/Auを積層した積層膜などが用いられる。 The submount 10 mounts the laser element 21 with the AuSn solder film 14a as the bonding film, and mounts the AuSn solder film 14b on the stem 22 as the bonding film. Although not shown, metallized films for joining with the submount 10 are formed in advance on the surfaces of the laser element 21 and the stem 22, respectively, and the AuSn solder films 14a and 14b are formed when the AuSn solder films 14a and 14b are melted. It functions as a bonding film with 14b. Specifically, the AuSn solder film 14a and the metallized film on the surface of the laser element 21 are bonded, and the AuSn solder film 14b and the metallized film on the surface of the stem 22 are bonded. As the metallized film of the laser element 21 and the stem 22, for example, a laminated film in which Ti / Pt / Au is laminated from the surface side of the laser element 21 and the stem 22, or a laminated film in which Ni / Au is laminated is used.

サブマウント10とレーザー素子21およびステム22における接合は、AuSnはんだ膜14a、14bの共晶温度(Au:Sn=7:3at%では278℃)以上の温度で、真空中あるいはN雰囲気中で接合されるのが一般的である。 Junction in the sub-mount 10 and the laser element 21 and the stem 22, AuSn solder film 14a, 14b of the eutectic temperature (Au:: Sn = 7 In 3at% 278 ° C.) or higher temperatures, in a vacuum or in N 2 atmosphere It is generally joined.

接合後では、サブマウント10のTi/Pt/Au積層膜13a、13bのAuがそれぞれAuSnはんだ膜14a、14b中に拡散し、Ti/Pt膜23a、23bとなり、AuSnはんだ膜13a、13bはそれぞれAuSn共晶24a、24bとなる。図示していないが、Ti/Pt膜23a、23bとAuSn共晶24a、24bとの間にはAu、Sn及びPtで構成される金属間化合物(IMC:Intermetallic compound)が形成される。この金属間化合物は、接合条件によって、その厚さや組成比は異なる。 After joining, Au of the Ti / Pt / Au laminated films 13a and 13b of the submount 10 diffuses into the AuSn solder films 14a and 14b, respectively, and becomes Ti / Pt films 23a and 23b, and the AuSn solder films 13a and 13b are respectively. AuSn eutectic 24a and 24b. Although not shown, an intermetallic compound (IMC) composed of Au, Sn and Pt is formed between the Ti / Pt films 23a and 23b and the AuSn eutectic 24a and 24b. The thickness and composition ratio of this intermetallic compound differ depending on the bonding conditions.

また、サブマウント10とステム22との接合時には、サブマウント10は上面(サブマウント10にステム22が搭載される側とAlN基板11を挟み反対側)から荷重をかけるため、溶融したAuSnはんだ膜14b(以下、AuSnはんだと呼ぶ。)はサブマウント10上のAuSnはんだ膜14b形成領域から押し出され、AuSnはんだの一部はAuSnはんだ膜14b形成領域の周囲にはみ出す。はみ出したAuSnはんだは、銅めっき12b側面に形成されたNiめっき膜15aにより、銅めっき12b側面に適切に濡れ広がることによって、サブマウント10周囲にAuSn共晶24bが適切に形成される。もし、Niめっき膜15aが無い場合は、銅めっき12b側面にAuSnはんだが十分に濡れ広がることができず、ステム22の表面に濡れ広がってしまう。このような場合には、サブマウント10とステム22との間、及び銅めっき12b側面に濡れ広がるAuSnはんだ、つまり接合に寄与するAuSnはんだの量が不足し、AuSnはんだが亜共晶になりやすくAuSn共晶24bが生成されない恐れがある。 Further, when the submount 10 and the stem 22 are joined, the submount 10 applies a load from the upper surface (the side on which the stem 22 is mounted on the submount 10 and the opposite side sandwiching the AlN substrate 11), so that the molten AuSn solder film is formed. The 14b (hereinafter referred to as AuSn solder) is extruded from the AuSn solder film 14b forming region on the submount 10, and a part of the AuSn solder protrudes around the AuSn solder film 14b forming region. The protruding AuSn solder is appropriately wetted and spread on the side surface of the copper plating 12b by the Ni plating film 15a formed on the side surface of the copper plating 12b, so that the AuSn eutectic 24b is appropriately formed around the submount 10. If the Ni plating film 15a is not provided, the AuSn solder cannot sufficiently wet and spread on the side surface of the copper plating 12b, and will wet and spread on the surface of the stem 22. In such a case, the amount of AuSn solder that wets and spreads between the submount 10 and the stem 22 and on the side surface of the copper plating 12b, that is, the amount of AuSn solder that contributes to bonding is insufficient, and the AuSn solder tends to become subeutectic. AuSn eutectic 24b may not be produced.

さらに、Niめっき膜15aは、AuSnはんだ中のSn成分が銅めっき12b内に多量拡散することを防止し、AuSnはんだがAuリッチ組成に偏ることもなくなり、安定的なAuSn共晶組織の生成に寄与する。そのため、サブマウント10とステム22とを、安定して強固に接合することが可能となる。 Further, the Ni plating film 15a prevents a large amount of Sn component in the AuSn solder from diffusing into the copper plating 12b, and the AuSn solder is not biased toward the Au-rich composition, resulting in the formation of a stable AuSn eutectic structure. Contribute. Therefore, the submount 10 and the stem 22 can be stably and firmly joined to each other.

次に、本発明に係るサブマウントの第2の実施形態を説明する。図3は、本発明のサブマウントの第2の実施形態を示す断面図である。なお、本実施形態では、第1の実施形態のサブマウントと共通する構成については同一の符号を用い、当該共通の構成について特に言及のない点については第1の実施形態と同様の構成、機能である。 Next, a second embodiment of the submount according to the present invention will be described. FIG. 3 is a cross-sectional view showing a second embodiment of the submount of the present invention. In the present embodiment, the same reference numerals are used for the configurations common to the submounts of the first embodiment, and the same configurations and functions as those of the first embodiment are used unless the common configurations are particularly mentioned. Is.

サブマウント30は、AlN基板11と、AlN基板11の一方の面上に形成された銅めっき12aと、他方の面上に形成された銅めっき12bと、銅めっき12aの表面上に形成され、銅めっき12aの表面側から順にTi/Pt/Auの膜が積層された積層膜13aと、銅めっき12bの表面及び側面上に形成されたNiめっき膜15bと、Niめっき膜の表面、側面上に形成され、Niめっき膜15bの面上から順にTi/Pt/Auの膜が積層された積層膜13cとを備える。銅めっき12a、12bは、AlN基板11の外形より小さく形成されており、積層膜13aは、銅めっき12aが形成されていないAlN基板11の一方の面上にも形成されており、積層膜13cは、銅めっき12b及びNiめっき膜15bが形成されていないAlN基板11の他方の面上にも形成されている。さらに、サブマウント30は、銅めっき12a上の積層膜13aの表面上に形成され、電子部品を実装するためのAuSnはんだ膜14aと、積層膜13cの表面上に形成され、ステム等の支持基板にサブマウント30を実装するためのAuSnはんだ膜14bとを備える。 The submount 30 is formed on the surface of the AlN substrate 11, the copper plating 12a formed on one surface of the AlN substrate 11, the copper plating 12b formed on the other surface, and the copper plating 12a. A laminated film 13a in which Ti / Pt / Au films are laminated in order from the surface side of the copper plating 12a, a Ni plating film 15b formed on the surface and side surfaces of the copper plating 12b, and the surface and side surfaces of the Ni plating film. A laminated film 13c in which Ti / Pt / Au films are laminated in order from the surface of the Ni plating film 15b is provided. The copper platings 12a and 12b are formed smaller than the outer shape of the AlN substrate 11, and the laminated film 13a is also formed on one surface of the AlN substrate 11 on which the copper plating 12a is not formed. Is also formed on the other surface of the AlN substrate 11 on which the copper plating 12b and the Ni plating film 15b are not formed. Further, the submount 30 is formed on the surface of the laminated film 13a on the copper plating 12a, and is formed on the surface of the AuSn solder film 14a for mounting electronic components and the laminated film 13c, and is a support substrate such as a stem. Is provided with an AuSn solder film 14b for mounting the submount 30.

第1の実施形態のサブマウント10と本実施形態のサブマウント30との相違点は、銅めっき12bの側面だけでなくその表面上にもNiめっき膜15bを備えることと、そのNiめっき膜15bの側面上に積層膜13cを備えることである。本実施形態では、Niめっき膜15bの側面に積層膜13cを備えることで、サブマウントのAuSnはんだ膜14bの溶融時における銅めっき12b側面側の適切な濡れ広がりを確保するとともに、AuSnはんだ膜14bのSn成分が銅めっき12b中へ拡散することを抑制するバリア層としての機能を向上させている。 The difference between the sub-mount 10 of the first embodiment and the sub-mount 30 of the present embodiment is that the Ni plating film 15b is provided not only on the side surface of the copper plating 12b but also on the surface thereof, and the Ni plating film 15b is provided. The laminated film 13c is provided on the side surface of the above. In the present embodiment, by providing the laminated film 13c on the side surface of the Ni plating film 15b, an appropriate wet spread on the side surface side of the copper plating 12b at the time of melting the AuSn solder film 14b of the submount is ensured, and the AuSn solder film 14b is provided. The Sn component of the above is improved in function as a barrier layer for suppressing diffusion into the copper plating 12b.

サブマウント30は、Niめっき膜15b上に積層膜13cを備えるが、積層膜13cの最表層であるAu層は、AuSnはんだ膜14bに対する濡れ性がよいため、銅めっき12b側面側の適切な濡れ広がりを確保することができる。また、Niめっき膜15b上に積層膜13cを備える構成であり、Niめっき膜15bと積層膜13cにおけるAu層とにより、AuSnはんだ膜14bの濡れ性のよい層を複数積層した構成であるため、成膜が難しい銅めっき12bの側面等においてサブマウント30の表面側の成膜が不十分な場合(下地の層が露出してしまった場合)であっても、濡れ性が損なわれる恐れを小さくすることができる。なお、成膜をより確実に行うため、Niめっき膜15bの側面を傾斜面としておくとよいことは言うまでもない。 The submount 30 includes a laminated film 13c on the Ni plating film 15b, but since the Au layer, which is the outermost layer of the laminated film 13c, has good wettability with respect to the AuSn solder film 14b, appropriate wetting on the side surface side of the copper plating 12b The spread can be secured. Further, since the structure is such that the laminated film 13c is provided on the Ni plating film 15b, and a plurality of layers having good wettability of the AuSn solder film 14b are laminated by the Ni plating film 15b and the Au layer in the laminated film 13c. Even if the film formation on the surface side of the submount 30 is insufficient on the side surface of the copper plating 12b where film formation is difficult (when the underlying layer is exposed), the risk of impairing wettability is small. can do. Needless to say, it is preferable to set the side surface of the Ni plating film 15b as an inclined surface in order to perform the film formation more reliably.

また、Niめっき膜15bと積層膜13cにおけるバリア層を構成するPtとでは、Ptの方がAuSnはんだ膜14b内のSn成分の拡散抑制効果が大きい。したがって、AuSnはんだ膜14bに対するバリア層としての高い効果が期待でき、さらに、Niめっき膜15b上に積層膜13bを備える構成であるため、バリア層としての特性も有するNiめっき膜15bと、積層膜13cにおけるバリア層(具体的にはPt層)とによりバリア層を複数積層した構成であり、濡れ性と同様に、バリア機能が損なわれる恐れを小さくすることができる。なお、本実施例では、Niめっき膜15bを銅めっき12bの側面上、及び銅めっき12bと積層膜13cとの間に形成しているが、銅めっき12bと積層膜13cとの間に形成せずに、銅めっき12bの側面上のみに形成してあっても、何ら問題無い。 Further, of the Ni plating film 15b and the Pt forming the barrier layer in the laminated film 13c, the Pt has a greater effect of suppressing the diffusion of the Sn component in the AuSn solder film 14b. Therefore, a high effect as a barrier layer on the AuSn solder film 14b can be expected, and further, since the structure is such that the laminated film 13b is provided on the Ni plating film 15b, the Ni plating film 15b and the laminated film also have characteristics as a barrier layer. A plurality of barrier layers are laminated together with the barrier layer (specifically, the Pt layer) in 13c, and the risk of impairing the barrier function can be reduced as in the case of wettability. In this embodiment, the Ni plating film 15b is formed on the side surface of the copper plating 12b and between the copper plating 12b and the laminated film 13c, but it is formed between the copper plating 12b and the laminated film 13c. There is no problem even if it is formed only on the side surface of the copper plating 12b without it.

10、30 サブマウント
11 AlN基板
12a、12b 銅めっき
13a、13b、13c 積層膜
14a、14b AuSnはんだ膜
15a、15b Niめっき膜
21 レーザー素子
22 ステム
23a、23b Ti/Pt膜
24a、24b AuSn共晶
100 サブマウント
101 基板
102a、102b 銅めっき
103 はんだ膜
104 はんだ膜
10, 30 Submount 11 AlN Substrate 12a, 12b Copper Plating 13a, 13b, 13c Laminated Film 14a, 14b AuSn Solder Film 15a, 15b Ni Plating Film 21 Laser Element 22 Stem 23a, 23b Ti / Pt Film 24a, 24b AuSn Co-crystal 100 Submount 101 Substrate 102a, 102b Copper plating 103 Solder film 104 Solder film

Claims (6)

電子部品を支持基板に配置するためのサブマウントであって、
基板と、
当該基板の少なくとも一方の面に形成された第1金属膜と、
前記第1金属膜上に形成されたはんだ膜と、を備え、
前記第1金属膜の側面上に、前記第1金属膜より前記はんだ膜のぬれ性がよい表面を備えた第2金属膜を有することを特徴とするサブマント。
A sub-mount for arranging electronic components on a support board.
With the board
A first metal film formed on at least one surface of the substrate and
A solder film formed on the first metal film is provided.
A submanto having a second metal film having a surface on the side surface of the first metal film, which has a better wettability of the solder film than the first metal film.
前記第1金属膜の上面上であり、前記第1金属膜と前記はんだ膜との間に前記第2金属膜をさらに有することを特徴とする請求項1に記載のサブマウント。 The submount according to claim 1, wherein the submount is on the upper surface of the first metal film and further has the second metal film between the first metal film and the solder film. 前記第2金属膜は、前記第1金属膜より前記はんだ膜のぬれ性がよい表面金属層、該表面金属層の下層に位置し前記はんだ膜に対するバリア層及び該バリア層の下層であり前記第1金属膜と密着する密着層を備えたことを特徴とする請求項1または2に記載のサブマウント。 The second metal film is a surface metal layer having better wettability of the solder film than the first metal film, a barrier layer for the solder film located below the surface metal layer, and a lower layer of the barrier layer. 1 The submount according to claim 1 or 2, further comprising an adhesion layer that adheres to a metal film. 前記第1金属膜の側面上に形成された第2金属膜と、前記第1金属膜の上面上に形成された前記第2金属膜とは、異なる材料により構成されることを特徴とする請求項2に記載のサブマウント。 A claim characterized in that the second metal film formed on the side surface of the first metal film and the second metal film formed on the upper surface of the first metal film are made of different materials. Item 2. The submount described in Item 2. 前記第2金属膜は、蒸着またはスパッタにより形成され、前記第2金属層の下層には、めっき法により形成され、前記第1金属膜より前記第1金属膜より前記はんだ膜のぬれ性がよい表面を備えた第3金属膜を有することを特徴とする請求項1〜4のいずれか一項に記載のサブマウント。 The second metal film is formed by vapor deposition or sputtering, and is formed by a plating method in the lower layer of the second metal layer, and the solder film has better wettability than the first metal film than the first metal film. The submount according to any one of claims 1 to 4, wherein the submount has a third metal film provided with a surface. 前記第1金属膜の側面は、前記第1金属膜の表面から前記基板に向かい広がる傾斜面であることを特徴とする請求項1〜5のいずれか一項に記載のサブマウント。 The submount according to any one of claims 1 to 5, wherein the side surface of the first metal film is an inclined surface extending from the surface of the first metal film toward the substrate.
JP2019166870A 2019-09-13 2019-09-13 submount Active JP7324665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019166870A JP7324665B2 (en) 2019-09-13 2019-09-13 submount

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019166870A JP7324665B2 (en) 2019-09-13 2019-09-13 submount

Publications (2)

Publication Number Publication Date
JP2021044468A true JP2021044468A (en) 2021-03-18
JP7324665B2 JP7324665B2 (en) 2023-08-10

Family

ID=74864298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019166870A Active JP7324665B2 (en) 2019-09-13 2019-09-13 submount

Country Status (1)

Country Link
JP (1) JP7324665B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022180123A (en) * 2021-05-24 2022-12-06 日亜化学工業株式会社 Light-emitting device and method for manufacturing light-emitting device
WO2023017632A1 (en) * 2021-08-10 2023-02-16 ヌヴォトンテクノロジージャパン株式会社 Semiconductor laser device, soldered sub-mount, soldered sub-mount assembly, and testing method for semiconductor laser device
DE102023110655A1 (en) 2022-04-28 2023-11-02 Nichia Corporation Light emitting device and mounting component

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0276864U (en) * 1988-12-01 1990-06-13
JPH04250308A (en) * 1991-01-28 1992-09-07 Matsushita Electric Works Ltd Pattern width measuring method for printed wiring board
JPH04312937A (en) * 1991-03-26 1992-11-04 Mitsubishi Electric Corp Method of manufacturing semiconductor device
JPH0513820A (en) * 1991-07-02 1993-01-22 Omron Corp Semiconductor device
JP2000269583A (en) * 1999-03-19 2000-09-29 Fuji Photo Film Co Ltd Semiconductor light emitting device and manufacture thereof
JP2003046181A (en) * 2001-07-27 2003-02-14 Ricoh Co Ltd Sub-mount, semiconductor device, and method of manufacturing sub-mount
JP2003092431A (en) * 2001-07-11 2003-03-28 Nichia Chem Ind Ltd How to fix to the support face down
JP2003347650A (en) * 2002-05-29 2003-12-05 Rohm Co Ltd Semiconductor light emitting device
JP2004259770A (en) * 2003-02-24 2004-09-16 Kyocera Corp Ceramic substrate for thermoelectric exchange module
JP2006185931A (en) * 2004-12-24 2006-07-13 Tokuyama Corp Semiconductor laser device and manufacturing method thereof
JP2006351847A (en) * 2005-06-16 2006-12-28 Fujifilm Holdings Corp Semiconductor light-emitting device
JP2007013044A (en) * 2005-07-04 2007-01-18 Sony Corp Light emitting device
JP2007095715A (en) * 2005-09-26 2007-04-12 Dowa Holdings Co Ltd Submount and manufacturing method thereof
JP2008166579A (en) * 2006-12-28 2008-07-17 Allied Material Corp Heat dissipation member and semiconductor device
JP2008200728A (en) * 2007-02-21 2008-09-04 Mitsubishi Materials Corp Solder joining material, its manufacturing method, and power module substrate utilizing the solder joining material
JP2008205326A (en) * 2007-02-22 2008-09-04 Sanyo Electric Co Ltd Submount and semiconductor device using it
JP2009059904A (en) * 2007-08-31 2009-03-19 Sanyo Electric Co Ltd Sub-mount and semiconductor device equipped with it
JP2011222675A (en) * 2010-04-07 2011-11-04 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2013004571A (en) * 2011-06-13 2013-01-07 Hamamatsu Photonics Kk Semiconductor laser device
JP2015173218A (en) * 2014-03-12 2015-10-01 三菱電機株式会社 semiconductor laser light source
JP2016186997A (en) * 2015-03-27 2016-10-27 ウシオ電機株式会社 Semiconductor laser device and manufacturing method thereof
JP2017152551A (en) * 2016-02-25 2017-08-31 株式会社フジクラ Semiconductor laser module and manufacturing method for the same
US20180190520A1 (en) * 2016-12-30 2018-07-05 Luxnet Corporation Composite heat-dissipating substrate

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0276864U (en) * 1988-12-01 1990-06-13
JPH04250308A (en) * 1991-01-28 1992-09-07 Matsushita Electric Works Ltd Pattern width measuring method for printed wiring board
JPH04312937A (en) * 1991-03-26 1992-11-04 Mitsubishi Electric Corp Method of manufacturing semiconductor device
JPH0513820A (en) * 1991-07-02 1993-01-22 Omron Corp Semiconductor device
JP2000269583A (en) * 1999-03-19 2000-09-29 Fuji Photo Film Co Ltd Semiconductor light emitting device and manufacture thereof
JP2003092431A (en) * 2001-07-11 2003-03-28 Nichia Chem Ind Ltd How to fix to the support face down
JP2003046181A (en) * 2001-07-27 2003-02-14 Ricoh Co Ltd Sub-mount, semiconductor device, and method of manufacturing sub-mount
JP2003347650A (en) * 2002-05-29 2003-12-05 Rohm Co Ltd Semiconductor light emitting device
JP2004259770A (en) * 2003-02-24 2004-09-16 Kyocera Corp Ceramic substrate for thermoelectric exchange module
JP2006185931A (en) * 2004-12-24 2006-07-13 Tokuyama Corp Semiconductor laser device and manufacturing method thereof
JP2006351847A (en) * 2005-06-16 2006-12-28 Fujifilm Holdings Corp Semiconductor light-emitting device
JP2007013044A (en) * 2005-07-04 2007-01-18 Sony Corp Light emitting device
JP2007095715A (en) * 2005-09-26 2007-04-12 Dowa Holdings Co Ltd Submount and manufacturing method thereof
JP2008166579A (en) * 2006-12-28 2008-07-17 Allied Material Corp Heat dissipation member and semiconductor device
JP2008200728A (en) * 2007-02-21 2008-09-04 Mitsubishi Materials Corp Solder joining material, its manufacturing method, and power module substrate utilizing the solder joining material
JP2008205326A (en) * 2007-02-22 2008-09-04 Sanyo Electric Co Ltd Submount and semiconductor device using it
JP2009059904A (en) * 2007-08-31 2009-03-19 Sanyo Electric Co Ltd Sub-mount and semiconductor device equipped with it
JP2011222675A (en) * 2010-04-07 2011-11-04 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2013004571A (en) * 2011-06-13 2013-01-07 Hamamatsu Photonics Kk Semiconductor laser device
JP2015173218A (en) * 2014-03-12 2015-10-01 三菱電機株式会社 semiconductor laser light source
JP2016186997A (en) * 2015-03-27 2016-10-27 ウシオ電機株式会社 Semiconductor laser device and manufacturing method thereof
JP2017152551A (en) * 2016-02-25 2017-08-31 株式会社フジクラ Semiconductor laser module and manufacturing method for the same
US20180190520A1 (en) * 2016-12-30 2018-07-05 Luxnet Corporation Composite heat-dissipating substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022180123A (en) * 2021-05-24 2022-12-06 日亜化学工業株式会社 Light-emitting device and method for manufacturing light-emitting device
JP2024055970A (en) * 2021-05-24 2024-04-19 日亜化学工業株式会社 Light emitting device and method for manufacturing the same
WO2023017632A1 (en) * 2021-08-10 2023-02-16 ヌヴォトンテクノロジージャパン株式会社 Semiconductor laser device, soldered sub-mount, soldered sub-mount assembly, and testing method for semiconductor laser device
DE102023110655A1 (en) 2022-04-28 2023-11-02 Nichia Corporation Light emitting device and mounting component

Also Published As

Publication number Publication date
JP7324665B2 (en) 2023-08-10

Similar Documents

Publication Publication Date Title
JP5688412B2 (en) Method for thermally contacting opposing electrical connections of a semiconductor component array
US7390735B2 (en) High temperature, stable SiC device interconnects and packages having low thermal resistance
KR100940164B1 (en) Submount and Semiconductor Devices
JP7324665B2 (en) submount
WO2004015756A1 (en) Submount and semiconductor device
JP2007521639A (en) Thermal interface material and solder preform
JP2013016838A (en) Ceramics wiring substrate and semiconductor device using the same
JP5619167B2 (en) Electronic module manufacturing method and electronic module
TW548805B (en) Element bonding substrate and its forming method
JP5028217B2 (en) Optical device mounting method
JP2002368293A (en) Thermoelectric module, method of manufacturing thermoelectric module, thermoelectric device, fiber floodlight device
JP2008047604A (en) Metallized substrate, semiconductor device
JP2005032834A (en) Joining method of semiconductor chip and substrate
JP2002359425A (en) Submount and semiconductor device
JP2000138320A (en) Semiconductor element mounting substrate or heat sink and its manufacture and jointed body of the substrate or the heat sink with semiconductor element
US20050089700A1 (en) Solder film manufacturing method, heat sink furnished with solder film, and semiconductor-device-and-heat-sink junction
JP4951932B2 (en) Power module substrate manufacturing method
JP2021150464A (en) Electrode structure and junction structure including the same
JP6819385B2 (en) Manufacturing method of semiconductor devices
KR20140086373A (en) Wafer for led and manufacturing method thereof
JPH0786444A (en) Method for manufacturing composite heat dissipation substrate for semiconductor
JP4825403B2 (en) Submount and manufacturing method thereof
JP2006216766A (en) Ceramics wiring board and semiconductor device using it
JP2006303017A (en) Thermoelectric converter
TWI500190B (en) LED wafer and manufacturing method thereof

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20190913

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220215

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20221026

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221114

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230410

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230517

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230718

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230731

R150 Certificate of patent or registration of utility model

Ref document number: 7324665

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150