JP2021040041A - Superjunction semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device capable of reducing an ion implantation step for forming a p-type base region. A superjunction semiconductor device includes a first conductive type silicon carbide semiconductor substrate 1, a first conductive type first semiconductor layer 2, a first trench 30 provided in the first semiconductor layer 2, and a first. 1 It has a second trench 31 which is provided on the surface of the semiconductor layer 2 and whose bottom is continuous with the first trench 30 and which is wider than the first trench 30. The second conductive type third semiconductor region 6 is provided inside the first trench 30, and the second conductive type second semiconductor region 3 is provided inside the second trench 31. [Selection diagram] Fig. 1

Description

The present invention relates to a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device.

In a normal n-type channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the n-type conductive layer (drift layer) is the highest among a plurality of semiconductor layers formed in a semiconductor substrate. It is a semiconductor layer of resistance. The electrical resistance of this n-type drift layer has a great influence on the on-resistance of the entire vertical MOSFET. In order to reduce the on-resistance of the entire vertical MOSFET, it can be realized by reducing the thickness of the n-type drift layer and shortening the current path.

However, the vertical MOSFET also has a function of maintaining a withstand voltage by expanding the depletion layer to the n-type drift layer having high resistance in the off state. Therefore, when the n-type drift layer is thinned to reduce the on-resistance, the depletion layer spreads short in the off state, so that the fracture electric field strength is easily reached at a low applied voltage, and the withstand voltage is lowered. On the other hand, in order to increase the withstand voltage of the vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer, and the on-resistance increases. Such a relationship between on-resistance and withstand voltage is called a trade-off relationship, and it is generally difficult to improve both of them in a trade-off relationship. It is known that this trade-off relationship between the on-resistance and the withstand voltage is also established in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, and diodes.

As a structure of a semiconductor device that solves the above-mentioned problems, a super junction (SJ) structure is known. For example, a MOSFET having a superjunction structure (hereinafter referred to as SJ-MOSFET) is known. FIG. 32 is a cross-sectional view showing the structure of a conventional SJ-MOSFET. The structure of the SJ-MOSFET is shown as an example of the conventional superjunction semiconductor device 160.

As shown in FIG. 32, the SJ-MOSFET is made of a wafer in which an n-type drift layer 102 is grown on ^{an n ++ type semiconductor substrate 101 having a high impurity concentration.} A p-type pillar region 103 that penetrates the n-type drift layer 102 from the wafer surface ^{and does not reach the n ++} type semiconductor substrate 101 is provided. In Figure 32, the p-type pillar region 103 does not reach the n ⁺⁺ type semiconductor substrate 101, may be reached n ⁺⁺ type semiconductor substrate 101.

Further, in the n-type drift layer 102, a p-type region (p-type pillar region 103) and an n-type region (p-type) extending in a direction perpendicular to the main surface of the substrate and having a narrow width in a plane parallel to the main surface of the substrate. A parallel structure in which the portion of the n-type drift layer 102 sandwiched between the pillar regions 103, hereinafter referred to as the n-type pillar region 104) is alternately and repeatedly arranged on a plane parallel to the main surface of the substrate (hereinafter referred to as a parallel pn region 119). )have. The p-type pillar region 103 and the n-type pillar region 104 constituting the parallel pn region 119 are regions in which the impurity concentration is increased corresponding to the n-type drift layer 102. In the parallel pn region 119, by making the impurity concentrations contained in the p-type pillar region 103 and the n-type pillar region 104 substantially equal, it is possible to create a pseudo non-doped layer in the off state to increase the pressure resistance.

A p-type base region 106 is provided on the parallel pn region 119 of the SJ-MOSFET. ^{An n +} type source region 107 is provided inside the p-type base region 106. ^{A p +} type contact area may be provided inside the p type base area 106. Further, a gate insulating film 109 is provided over the surfaces of the p-type base region 106 and the n-type pillar region 104. A gate electrode 110 is provided on the surface of the gate insulating film 109, and an interlayer insulating film 111 is provided so as to cover the gate electrode 110. Further, a source electrode 112 is provided on the n ⁺ type source region 107, and a back surface electrode (drain electrode) 113 is provided on the back surface of ^{the n ++ type semiconductor substrate 101.}

For example, in SJ-MOSFET, n ^- -type layer previously formed recesses in, p so as to fill the trench ^- in forming a mold layer, by embedding also the recess, p ^- in a recess of the mold layer There is a technique of using the formed portion as a p-type layer formed on the SJ structure (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2014-132638

However, in the conventional superjunction semiconductor device 160, the p-type pillar region 103 and the p-type base region 106 are formed separately. The p-type pillar region 103 was formed by epitaxially growing the n-type drift layer 102, forming a trench, and filling the inside of the trench with p-type impurities. On the other hand, the p-type base region 106 was formed by ion-implanting p-type impurities into the n-type drift layer 102.

Thus, ion implantation of the p-type base region 106 was required as a separate process. In particular, since ion implantation into silicon carbide (SiC) requires high-temperature implantation at the time of implantation, it takes time to raise and lower the temperature. Also, when activating the injected ions, higher temperature annealing is required as compared with silicon (Si), so it takes time to raise and lower the temperature. As described above, in the conventional superjunction semiconductor device 160, the p-type pillar region 103 and the p-type base region 106 are formed separately, which causes high cost.

An object of the present invention is to provide a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device capable of reducing the ion implantation step for forming a p-type base region in order to solve the above-mentioned problems caused by the prior art. To do.

In order to solve the above-mentioned problems and achieve the object of the present invention, the superjunction semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate. A first trench is provided in the first semiconductor layer. On the surface of the first semiconductor layer, a second trench having a bottom portion continuous with the first trench and having a width wider than that of the first trench is provided. A second conductive type second semiconductor region is provided inside the first trench. A second conductive type third semiconductor region is provided inside the second trench. Inside the third semiconductor region, a first conductive type fourth semiconductor region having a higher impurity concentration than the first semiconductor layer is provided. A gate electrode is provided via a gate insulating film on at least a part of the surface of the third semiconductor region sandwiched between the fourth semiconductor region and the first semiconductor layer. The first electrode is provided on the surfaces of the fourth semiconductor region and the third semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate.

Further, in the above-described invention, the superjunction semiconductor device according to the present invention has a third trench provided in the second semiconductor region and the third semiconductor region, and a bottom portion provided on the surface of the third semiconductor region. A fourth trench wider than the third trench, which is continuous with the third trench, and a second conductive type second, which is provided inside the third trench and has a higher impurity concentration than the second semiconductor region. It is characterized by further comprising 5 semiconductor regions and a second conductive type sixth semiconductor region provided inside the fourth trench and having a higher impurity concentration than the third semiconductor region.

Further, in the superjunction semiconductor device according to the present invention, in the above-described invention, the second semiconductor region and the third semiconductor region have a rectangular shape, and the longitudinal direction of the second semiconductor region and the third semiconductor The longitudinal directions of the regions are orthogonal.

Further, in the above-described invention, the superjunction semiconductor device according to the present invention has a rectangular shape in the second semiconductor region, the third semiconductor region, the fifth semiconductor region, and the sixth semiconductor region. The longitudinal direction of the second semiconductor region and the longitudinal direction of the third semiconductor region are orthogonal to each other, and the longitudinal direction of the fifth semiconductor region and the longitudinal direction of the sixth semiconductor region are orthogonal to each other.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a superjunction semiconductor device according to the present invention has the following features. First, a first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is performed on the front surface of the first conductive type semiconductor substrate. Next, a second step of forming a first trench in the first semiconductor layer and a second trench wider than the first trench having a bottom continuous with the first trench on the surface of the first semiconductor layer is performed. Do. Next, a third step of forming a second conductive type second semiconductor region and a second conductive type third semiconductor region by epitaxial growth inside the first trench and inside the second trench is performed. Next, a fourth step of forming a first conductive type fourth semiconductor region having a higher impurity concentration than the first semiconductor layer is performed inside the third semiconductor region. Next, a fifth step of forming a gate electrode via a gate insulating film on at least a part of the surface of the third semiconductor region sandwiched between the fourth semiconductor region and the first semiconductor layer is performed. Next, a sixth step of forming the first electrode on the surfaces of the fourth semiconductor region and the third semiconductor region is performed. Next, a seventh step of forming the second electrode on the back surface of the semiconductor substrate is performed.

Further, in the above-described invention, the method for manufacturing a superjunction semiconductor device according to the present invention is a third trench in the second semiconductor region and the third semiconductor region after the third step and before the fourth step. A step of forming a fourth trench wider than the third trench on the surface of the third semiconductor region, the bottom of which is continuous with the first trench, and the inside of the third trench and the fourth trench. By epitaxial growth inside, a second conductive type fifth semiconductor region having a higher impurity concentration than the second semiconductor region and a second conductive type sixth semiconductor region having a higher impurity concentration than the third semiconductor region are formed. It is characterized by including a process.

In order to solve the above-mentioned problems and achieve the object of the present invention, the superjunction semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate. A first trench is provided in the first semiconductor layer. A second trench having a bottom surface continuous with the opening of the first trench and having a width wider than that of the first trench is provided on the front surface of the first semiconductor layer. A second conductive type second semiconductor region is provided inside the first trench. A second conductive type third semiconductor region is provided inside the second trench. Inside the third semiconductor region, a second conductive type fourth semiconductor region having a higher impurity concentration than the third semiconductor region is provided. A first conductive type fifth semiconductor region having a higher impurity concentration than the first semiconductor layer is provided on the surface of the third semiconductor region so as to be in contact with the fourth semiconductor region. A gate electrode is provided via a gate insulating film on at least a part of the surface of the third semiconductor region sandwiched between the fifth semiconductor region and the first semiconductor layer. The first electrode is provided on the surfaces of the fifth semiconductor region and the third semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate.

Further, in the superjunction semiconductor device according to the present invention, in the above-described invention, the interface between the fourth semiconductor region and the third semiconductor region is located at a position shallower than the interface between the second semiconductor region and the third semiconductor region. It is characterized by being.

Further, in the superjunction semiconductor device according to the present invention, in the above-described invention, the second semiconductor region and the third semiconductor region have a striped shape, and the longitudinal direction of the second semiconductor region and the third semiconductor region The third semiconductor region is provided inside the second trench.

Further, in the superjunction semiconductor device according to the present invention, in the above-described invention, the second semiconductor region and the third semiconductor region have a striped shape, and the longitudinal direction of the second semiconductor region and the third semiconductor region Is characterized in that the longitudinal directions of the above are orthogonal to each other.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a superjunction semiconductor device according to the present invention has the following features. First, a first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is performed on the front surface of the first conductive type semiconductor substrate. Next, a second step is performed in which the first trench is in contact with the first semiconductor layer and the bottom surface is in contact with the first trench on the surface of the first semiconductor layer to form a second trench wider than the first trench. .. Next, a third step of forming a second conductive type second semiconductor region and a second conductive type third semiconductor region by epitaxial growth inside the first trench and inside the second trench is performed. Next, a fourth step of forming a second conductive type fourth semiconductor region having a higher impurity concentration than the third semiconductor region is performed inside the third semiconductor region. Next, a fifth step of forming a first conductive type fifth semiconductor region having a higher impurity concentration than the first semiconductor layer is performed so that the surface of the third semiconductor region is in contact with the fourth semiconductor region. Next, a sixth step is performed in which a gate electrode is formed on at least a part of the surface of the third semiconductor region sandwiched between the fifth semiconductor region and the first semiconductor layer via a gate insulating film. Next, a seventh step of forming the first electrode on the surfaces of the fifth semiconductor region and the third semiconductor region is performed. Next, the eighth step of forming the second electrode on the back surface of the semiconductor substrate is performed.

According to the above-described invention, the p-type pillar region (second conductive type second semiconductor region) is formed by forming the first trench and the second trench and embedding p-type impurities in the first trench and the second trench. ) And the p-type base region (second conductive type third semiconductor region) are formed at the same time. This makes it possible to omit the step of forming the p-type base region by ion implantation. Therefore, the cost for manufacturing the superjunction semiconductor device can be reduced.

According to the superjunction semiconductor device and the method for manufacturing a superjunction semiconductor device according to the present invention, there is an effect that the ion implantation step for forming the p-type base region can be reduced.

It is sectional drawing which shows the structure of the superjunction semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the structure of the superjunction semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the superjunction semiconductor device which concerns on Embodiment 1 (the 1). It is sectional drawing which shows the state in the manufacturing process of the superjunction semiconductor device which concerns on Embodiment 1 (the 2). FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the superjunction semiconductor device according to the first embodiment (No. 3). FIG. 8 is a cross-sectional view taken along the line AB showing the other structure of the superjunction semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view taken along the line CD of FIG. 8 showing another structure of the superjunction semiconductor device according to the first embodiment. It is a top view which shows the other structure of the superjunction semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the structure of the superjunction semiconductor device which concerns on Embodiment 2. FIG. It is a top view which shows the structure of the superjunction semiconductor device which concerns on Embodiment 2. FIG. FIG. 13 is a sectional view taken along the line AB showing FIG. 13 showing another structure of the superjunction semiconductor device according to the second embodiment. FIG. 3 is a cross-sectional view taken along the line CD of FIG. 13 showing another structure of the superjunction semiconductor device according to the second embodiment. It is a top view which shows the other structure of the superjunction semiconductor device which concerns on Embodiment 2. FIG. FIG. 8 is a cross-sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 8 is a cross-sectional view taken along the line CD of FIG. 18 showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 8 is a sectional view taken along line EF of FIG. 18 showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 8 is a cross-sectional view taken along the line GH of FIG. 18 showing the structure of the superjunction semiconductor device according to the third embodiment. It is a top view which shows the structure of the superjunction semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing AB of FIG. 23 which shows the structure of the superjunction semiconductor device which concerns on Embodiment 4. FIG. FIG. 2 is a cross-sectional view taken along the line CD of FIG. 23 showing the structure of the superjunction semiconductor device according to the fourth embodiment. FIG. 3 is a sectional view taken along line EF of FIG. 23 showing the structure of the superjunction semiconductor device according to the fourth embodiment. FIG. 2 is a cross-sectional view taken along the line GH of FIG. 23 showing the structure of the superjunction semiconductor device according to the fourth embodiment. It is a top view which shows the structure of the superjunction semiconductor device which concerns on Embodiment 4. FIG. FIG. 26 is a sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the fifth embodiment. FIG. 6 is a cross-sectional view taken along the line CD of FIG. 26 showing the structure of the superjunction semiconductor device according to the fifth embodiment. It is a top view which shows the structure of the superjunction semiconductor device which concerns on Embodiment 5. FIG. 31 is a sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the sixth embodiment. FIG. 3 is a cross-sectional view taken along the line CD of FIG. 31 showing the structure of the superjunction semiconductor device according to the sixth embodiment. FIG. 3 is a sectional view taken along line EF of FIG. 31 showing the structure of the superjunction semiconductor device according to the sixth embodiment. FIG. 3 is a cross-sectional view taken along the line GH of FIG. 31 showing the structure of the superjunction semiconductor device according to the sixth embodiment. It is a top view which shows the structure of the superjunction semiconductor device which concerns on Embodiment 6. It is sectional drawing which shows the structure of the conventional superjunction semiconductor device.

Hereinafter, preferred embodiments of the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. When the notation of n and p including + and-is the same, it means that the concentrations are close to each other, and the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
The superjunction semiconductor device 60 according to the present invention is configured by using a wide bandgap semiconductor. In the first embodiment, a silicon carbide semiconductor device manufactured (manufactured) using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described by taking a superjunction MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of the superjunction semiconductor device according to the first embodiment. Further, FIG. 2 is a plan view showing the structure of the superjunction semiconductor device according to the first embodiment. FIG. 1 shows only two unit cells (functional units of elements), and other unit cells adjacent to them are not shown. The superjunction semiconductor device shown in FIG. 1 is provided with a MOS (Metal Oxide Semiconductor) gate on the front surface (surface on the p-type base region 6 side) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide. It is a super-junction MOSFET. In the following figure, n1, n2, n3, n4, n5 and the like mean that the layer or region is n-type, and the impurity concentration is n1 ≦ n2 ≦ n3 ≦ n4 ≦ n5. Similarly, p1, p2, p3, p4, p5 and the like also mean that the layer or region is p-type, and the impurity concentration is p1 ≦ p2 ≦ p3 ≦ p4 ≦ p5.

The silicon carbide substrate includes a low-concentration n-type drift layer 21 and a medium-concentration n-type drift layer 22 on the first main surface (front surface) ^{of the n ++ type semiconductor substrate (first conductive type semiconductor substrate) 1.} Each silicon carbide layer to be the high-concentration n-type drift layer 23 is epitaxially grown in order. The MOS gate has a p-type base region (second conductive type third semiconductor region) 6, an n ⁺ type source region (first conductive type fourth semiconductor region) 7, a p ⁺ type contact region 8, and a gate insulating film. It is composed of 9 and a gate electrode 10. Here, the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, and the high-concentration n-type drift layer 23 are combined to form the n-type drift layer (first conductive type first semiconductor layer) 2. To. The low-concentration n-type drift layer 21 is provided at a lower impurity concentration than the medium-concentration n-type drift layer 22, and the medium-concentration n-type drift layer 22 is provided at a lower impurity concentration than the high-concentration n-type drift layer 23.

The n-type drift layer 2 is provided with a parallel pn region 19. In the parallel pn region 19, the p-type pillar region (second conductive type second semiconductor region) 3 and the n-type region (n-type pillar region 4) sandwiched between the p-type pillar regions 3 are alternately and repeatedly joined. It is made. The p-type pillar region 3 penetrates the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 from the bottom surface of the p-type base region 6 (the surface on the n ^{++ type semiconductor substrate 1 side) and has a low concentration.} It is provided so as to reach the surface of the n-type drift layer 21 and not reach the n ^{++ type semiconductor substrate 1.} Further, the p-type pillar region 3 reaches the surface of the low-concentration n-type drift layer 21, but does not reach deep inside the low-concentration n-type drift layer 21. Therefore, when considering the charge balance between the p-type region and the n-type region, it is not necessary to consider the impurity concentration of the low-concentration n-type drift layer 21. The planar shapes of the p-type pillar region 3 and the n-type pillar region 4 are, for example, rectangular, hexagonal grid, or square.

Here, the low-concentration n-type drift layer 21 is a layer that shares the withstand voltage of the device, and the impurity concentration of the low-concentration n-type drift layer 21 is lowered to increase the film thickness of the low-concentration n-type drift layer 21. Thereby, high withstand voltage of the element can be realized. Further, the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 are layers that share the charge balance of the elements. Since there is a low-concentration n-type drift layer 21 that shares the high withstand voltage of the device, the film thicknesses of the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 can be reduced even when the device has a high withstand voltage. it can. Therefore, the depth of the p-type pillar region 3 provided in the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 (the depth of the parallel pn region 19) can be made shallow. As described above, even when the withstand voltage of the element is increased, the depth of the p-type pillar region 3 is shallow, so that the p-type pillar region 3 can be epitaxially grown at a uniform impurity concentration. Therefore, even when the withstand voltage is increased, the charge balance between the p-type region and the n-type region can be maintained, and the superjunction semiconductor device 60 having low on-resistance and high withstand voltage characteristics can be realized.

A p-type base region 6 is provided on the surface layer of the n-type drift layer 2 on the source side (source electrode 12 side), and the p-type pillar region 3 and the p-type base region 6 are formed at the same time, and thus are integrated. Has been done. Specifically, a second trench 31 having a depth of db and a first trench 30 having a depth da that is shallower than the second trench 31 are provided in the n-type drift layer 2. The second trench 31 is provided in the n-type drift layer 2, and the first trench 30 is provided in the surface layer of the n-type drift layer 2. The second trench 31 is continuous with the bottom of the first trench 30, and the width Wa of the first trench 30 is wider than the width Wp1 of the second trench 31.

The p-type pillar region 3 is formed by filling the second trench 31 with p-type impurities, and the p-type base region 6 is formed by filling the first trench 30 with p-type impurities. In this way, by forming a two-stage trench composed of the first trench 30 and the second trench 31, a structure corresponding to the p-type pillar region 3 and the p-type base region 6 is formed, and the p-type is formed therein. Impurities are embedded and the layer is used as the p-type pillar region 3 and the p-type base region 6.

Further, the impurity concentration increases in the order of the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, the high-concentration n-type drift layer 23, and the n ⁺ type source region 7 described later, and the p-type pillar is used as a charge balance. The product of the impurity concentration p1 of the region 3 and the width Wp1 of the p-type pillar region 3 is substantially equal to the product of the impurity concentration n1 of the n-type pillar region 4 and the width Wn1 of the n-type pillar region 4, that is,
n1 × Wn1 ≒ p1 × Wp1
Is established. At this time, it is preferable to slightly increase the impurity concentration p1 in the p-type pillar region 3 to slightly increase the p-type impurities.

Inside the p-type base region 6, and n ⁺ -type source region 7 and the p ⁺ -type contact region 8 are provided, respectively selectively in contact with each other. The depth of the p ^{+ type contact region 8 may be the same as, for example, the same depth as the n +} type source region 7, or may be deeper. p ⁺ -type contact region 8, as shown in FIG. 1, it may be provided side by side and the p ⁺ -type contact region 8 and the n ⁺ -type source region 7 in the width direction of the second trenches 31 (x direction) ..

A gate electrode 10 is provided on the surface of the p-type base region 6 ^{sandwiched between the n +} -type source region 7 and the n-type pillar region 4 via a gate insulating film 9. The gate electrode 10 may be provided on the surface of the n-type pillar region 4 via the gate insulating film 9.

The interlayer insulating film 11 is provided on the front surface side of the semiconductor substrate so as to cover the gate electrode 10. ^{The source electrode 12 is in contact with the n +} type source region 7 and the p-type base region 6 through a contact hole opened in the interlayer insulating film 11, ^{and is electrically connected to the n +} type source region 7 and the p-type base region 6. Be connected.

The source electrode (first electrode) 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A protective film (not shown) such as a passivation film made of polyimide is selectively provided on the source electrode 12.

A back electrode (second electrode) 13 is provided on the second main surface (back surface, that is, the back surface of the semiconductor substrate) of the ^{n ++ type semiconductor substrate 1.} The back surface electrode 13 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back surface electrode 13.

In the plan view of FIG. 2, the interlayer insulating film 11 and the source electrode 12 are omitted in order to make the internal structure easier to see. Similarly, in the other plan views thereafter, the interlayer insulating film 11 and the source electrode 12 are omitted.

(Manufacturing method of superjunction semiconductor device according to the first embodiment)
Next, a method of manufacturing the superjunction semiconductor device 60 according to the first embodiment will be described. 3 to 5 are cross-sectional views showing a state in the middle of manufacturing the superjunction semiconductor device 60 according to the first embodiment. First, an n ⁺⁺ type semiconductor substrate 1 made of silicon carbide is prepared. Then, the front surface of the n ⁺⁺ type semiconductor substrate 1, a low impurity concentration than n ⁺⁺ type semiconductor substrate 1 low-concentration n-type drift layer 21 is epitaxially grown. At this time, for example, the n-type impurities may be doped and epitaxially grown so that the impurity concentration of the low-concentration n-type drift layer 21 is 2.5 × 10 ¹⁵ / cm ^{3 and the film thickness is 40 μm.}

Next, a medium-concentration n-type drift layer 22 having a higher impurity concentration than the low-concentration n-type drift layer 21 is epitaxially grown on the surface of the low-concentration n-type drift layer 21. At this time, for example, the n-type impurities may be doped and epitaxially grown so that the impurity concentration of the medium-concentration n-type drift layer 22 is 1.5 × 10 ¹⁶ / cm ^{3 and the film thickness is 20 μm.}

Next, a high-concentration n-type drift layer 23 having a higher impurity concentration than the medium-concentration n-type drift layer 22 is epitaxially grown on the surface of the medium-concentration n-type drift layer 22. At this time, for example, the n-type impurities may be doped and epitaxially grown so that the impurity concentration of the high-concentration n-type drift layer 23 is 1.7 × 10 ¹⁶ / cm ^{3 and the film thickness is 2.5 μm.} The low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, and the high-concentration n-type drift layer 23 are combined to form the n-type drift layer 2.

Next, by photolithography and etching, it penetrates the medium-concentration n-type drift layer 22 and the high-concentration n-type drift layer 23, reaches the low-concentration n-type drift layer 21, ^{and does not reach the n ++} type semiconductor substrate 1. One trench 30 and a second trench 31 are formed. The first trench 30 is formed so that the bottom portion is continuous with the second trench 31 and is wider than the second trench 31. At this time, for example, the depth db of the second trench 30 may be formed to 20.1 μm, the width Wp1 may be formed to 7.1 μm, the depth da of the first trench 30 may be formed to 2 μm, and the width Wa may be formed to 8 μm. Further, for example, the distance Wn1 between the second trenches 31 may be 2.5 μm, and the distance Lj between the first trenches 30 may be 1.6 μm.

Here, in order to prevent the narrow portion from being blocked by the neck first and forming a cavity when the deep trench (second trench 31) is backfilled by epitaxial growth, the upper and lower corners of the second trench having a width of Wp1 are formed. The rounding radii rWp1 and cWp1 are preferably 0.05 μm or more. The rounding radii of the other top and bottom corners are less important. The state up to this point is shown in FIG.

Next, by embedding p-type impurities in the first trench 30 and the second trench 31, the p-type pillar region 3 and the p-type base region 6 are epitaxially grown, and after the growth, the surface of the high-concentration n-type drift layer 23 is formed. Polish the surface of the p-type base region 6 until it is at the same height as. The impurity concentration of the p-type pillar region 3 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentration in the p-type pillar region 3 is set to 6.7 × 10 ¹⁵ / cm ³ . The p-type base region 6 may have the same impurity concentration as the p-type pillar region 3. The state up to this point is shown in FIG.

As described above, in the first embodiment, the p-type pillar region 3 and the p-type base region 6 are formed at the same time by embedding the p-type impurities in the first trench 30 and the second trench 31. Therefore, the step of forming the p-type base region 6 by ion implantation can be omitted.

Next, a mask having a desired opening is formed on the surface of the p-type base region 6 by a photolithography technique, for example, with a resist. Then, using this resist mask as a mask, n-type impurities are ion-implanted by the ion implantation method. ^{As a result, the n +} type source region 7 is formed in a part of the surface region of the p-type base region 6. Further, for example, the distance Lch between the high-concentration n-type drift layer 23 and the n ^{+ -type source region 7, which is the channel length, is 1.5 μm.} The width Ln3 of the n ⁺ type source region 7 is, for example, 2 μm. Next, the mask used during ion implantation to form the ^{n + type source region 7 is removed.}

Next, an ion implantation mask (not shown) having a desired opening is formed on the surface of ^{the n + type source region 7 by a photolithography technique, for example, with an oxide film.} Using this ion implantation mask as a mask, ion implantation of p-type impurities is performed ^{to form a p +} -type contact region 8 having a higher impurity concentration than the p-type base region 6 on the surface layer of the ^{n + -type source region 7.} The width Lp3 of the p ⁺ type contact region 8 is, for example, 1 μm. Next, the ion implantation mask is removed.

Next, a heat treatment (annealing) is performed to activate ^{the n +} type source region 7 and the p ^{+ type contact region 8.} Further, the order in which the n ⁺ type source region 7 and the p ⁺ type contact region 8 are formed can be changed in various ways.

Next, the front surface side of the semiconductor substrate is thermally oxidized to form the gate insulating film 9. As a result, each region formed on the surface of the n-type drift layer 2 is covered with the gate insulating film 9.

Next, for example, a phosphorus-doped polycrystalline silicon layer is formed on the gate insulating film 9 as the gate electrode 10. Next, the polycrystalline silicon layer is patterned and selectively removed ^{, leaving the polycrystalline silicon layer on the portion of the p-type base region 6 sandwiched between the n +} type source region 7 and the n-type pillar region 4. At this time, the polycrystalline silicon layer may be left on the n-type pillar region 4.

Next, for example, phosphorus glass (PSG: Phospho Silicate Glass) is formed as the interlayer insulating film 11 so as to cover the gate electrode 10. Next, the interlayer insulating film 11 and the gate insulating film 9 are patterned and selectively removed. For example, by removing the interlayer insulating film 11 and the gate insulating film 9 on the n ⁺ -type source region 7 to form a contact hole to expose the n ⁺ -type source region 7. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11. The state up to this point is shown in FIG.

Next, the source electrode 12 is formed by sputtering, and the source electrode 12 is patterned by photolithography and etching. At this time, the source electrode 12 is embedded in the contact hole, and the n ⁺ type source region 7 and the source electrode 12 are electrically connected. A tungsten plug or the like may be embedded in the contact hole via a barrier metal.

Next, ^{for example, a nickel film is formed on the front surface of the n ++} type semiconductor substrate 1 (the back surface of the semiconductor substrate) as the back surface electrode 13. Then, heat treatment is performed to ^{form an ohmic contact between the n ++} type semiconductor substrate 1 and the back surface electrode 13.

In the above-mentioned epitaxial growth and ion implantation, examples of n-type impurities (n-type dopants) include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), which are n-type with respect to silicon carbide. Should be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), tallium (Tl), etc., which are p-type with respect to silicon carbide, may be used. .. As a result, the superjunction semiconductor device 60 shown in FIG. 1 is completed.

Next, another structure of the superjunction semiconductor device 60 according to the first embodiment will be described. FIG. 6 is a cross-sectional view taken along the line AB showing another structure of the superjunction semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view taken along the line CD of FIG. 8 showing another structure of the superjunction semiconductor device according to the first embodiment. FIG. 8 is a plan view showing another structure of the superjunction semiconductor device according to the first embodiment.

As shown in FIGS. 6 to 8, in another structure, the p ^{+ type contact region 8 has an n +} type source region 7 in the depth direction (z direction orthogonal to the x direction and the y direction) of the first trench 30. It is a structure provided side by side. Further, for example, ^{the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8 are 5 μm, respectively.

In the structure of FIG. 1, ^{there is a limit in shortening the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8, but in the structures of FIGS. 6 and 7, the n ⁺ type source region 7 Since there is a margin for shortening the width Ln3 of the width Ln3 and the width Lp3 of the p ^{+ type contact region 8, it can be freely designed as compared with the structure of FIG.}

As described above, according to the first embodiment, the p-type pillar region and p are formed by forming the first trench and the second trench and embedding p-type impurities in the first trench and the second trench. The mold base region is formed at the same time. This makes it possible to omit the step of forming the p-type base region by ion implantation. Therefore, the cost for manufacturing the superjunction semiconductor device can be reduced. Further, the on-current can be increased by the high-concentration n-type drift layer and the medium-concentration n-type drift layer, and the channel length, trench width, and mesa width can be freely designed by adjusting the concentration of the n-type drift layer.

(Embodiment 2)
Next, the superjunction semiconductor device 61 according to the second embodiment will be described. FIG. 9 is a cross-sectional view showing the structure of the superjunction semiconductor device according to the second embodiment. As shown in FIG. 9, the superjunction semiconductor device 61 according to the second embodiment has a structure in which the high-concentration p-type pillar region 5 is provided with respect to the superjunction semiconductor device 60 according to the first embodiment.

In the second embodiment, the third trench 40 and the fourth trench 41 are provided inside the first trench 30 and the second trench 31, and p-type impurities are embedded in the third trench 40 and the fourth trench 41. An upper high-concentration p-type pillar region (second conductive type sixth semiconductor region) 52 and a lower high-concentration p-type pillar region (second conductive type fifth semiconductor region) 51 are provided. The lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are combined to form the high-concentration p-type pillar region 5. The lower high-concentration p-type pillar region 51 has a higher impurity concentration than the p-type pillar region 3, and the upper high-concentration p-type pillar region 52 has a higher impurity concentration than the p-type base region 6. Further, since the lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are formed at the same time, the impurity concentrations are about the same. For example, the impurity concentration p1 of the p-type pillar region 3 is 5 × 10 ¹⁵ / cm ³ , and the impurity concentration p2 of the high-concentration p-type pillar region 5 is 8.9 × 10 ¹⁵ / cm ³ .

Further, the third trench 40 is provided in the central portion of the first trench 30 with a width of Lp2, and is separated from the high-concentration n-type drift layer 23 by a distance of tp1. The width Lp2 is, for example, 4.0 μm, and the distance tp1 is, for example, 2 μm. Further, the fourth trench 41 is provided in the central portion of the second trench 31 with a width Wp2, and is separated from the high-concentration n-type drift layer 23 by a distance of tp1 and from the bottom surface of the second trench 31 by a distance of tp1b. The width Wp2 is, for example, 3.1 μm, and the distance tp1b is, for example, 2 μm.

Further, as a charge balance, the product of the impurity concentration p1 of the p-type pillar region 3 and the width Wp1-Wp2 of the portion where the high-concentration p-type pillar region 5 of the p-type pillar region 3 is not provided and the high-concentration p-type pillar region The sum of the product of the impurity concentration p2 of 5 and the width Wp2 of the high-concentration p-type pillar region 5 is substantially equal to the product of the impurity concentration n1 of the n-type pillar region 4 and the width Wn1 of the n-type pillar region 4, that is, ,
n1 × Wn1 ≒ p1 × (Wp1-Wp2) + p2 × Wp2
Is established. At this time, it is preferable to slightly increase the impurity concentration p1 of the p-type pillar region 3 or the impurity concentration p2 of the high-concentration p-type pillar region 5 to slightly increase the p-type impurities.

Since the high-concentration p-type pillar region 5 is provided in the second embodiment, the impurity concentration of the n-type pillar region 4 can be made higher than that of the first embodiment. As a result, the resistance of the drift layer is reduced, so that the on-resistance of the superjunction semiconductor device 61 can be reduced.

(Manufacturing method of superjunction semiconductor device according to the second embodiment)
Next, a method of manufacturing the superjunction semiconductor device 61 according to the second embodiment will be described. First, as in the first embodiment, the p-type pillar region 3 and the p-type base region 6 are epitaxially grown by embedding p-type impurities in the first trench 30 and the second trench 31, and after the growth, the concentration is high. The step of polishing the surface of the p-type base region 6 is performed until the height becomes the same as the surface of the n-type drift layer 23 ”2 (see FIG. 4).

Next, by photolithography and etching, a third trench 40 and a fourth trench 41 that penetrate the p-type base region 6 and reach the p-type pillar region 3 and do not reach the low-concentration n-type drift layer 21 are formed. The third trench 40 is formed shallower than the first trench 30. That is, the bottom surface of the third trench 40 is formed closer to the source electrode 12 than the bottom surface of the first trench 30. Similarly, the fourth trench 41 is formed shallower than the second trench 31. The third trench 40 is formed so that the bottom portion is continuous with the fourth trench 41 and is wider than the fourth trench 41.

Next, by embedding p-type impurities in the third trench 40 and the fourth trench 41, the lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are epitaxially grown.

Next, the surface of the upper high-concentration p-type pillar region 52 is polished until the height becomes the same as the surface of the high-concentration n-type drift layer 23. The lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are combined to form the high-concentration p-type pillar region 5. The impurity concentration of the high-concentration p-type pillar region 5 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentrations of the p-type pillar region 3 and the high-concentration p-type pillar region 5 are set to 5 × 10 ¹⁵ / cm ³ and 8.9 × 10 ¹⁵ / cm ³ , respectively.

After that, as in the first embodiment, the steps after the step of forming the ^{n +} type source region 7 on a part of the surface region of the p-type base region 6 and the high-concentration p-type pillar region 5 are performed. The superjunction semiconductor device 61 shown in FIG. 9 is completed.

Next, another structure of the superjunction semiconductor device 61 according to the second embodiment will be described. FIG. 11 is a sectional view taken along line AB of FIG. 13 showing another structure of the superjunction semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view taken along the line CD of FIG. 13 showing another structure of the superjunction semiconductor device according to the second embodiment. FIG. 13 is a plan view showing another structure of the superjunction semiconductor device according to the second embodiment.

As shown in FIGS. 11 to 13, in another structure, the p ^{+ type contact region 8 has an n +} type source region 7 in the depth direction (z direction orthogonal to the x direction and the y direction) of the first trench 30. It is a structure provided side by side. The width Ln3 of the n ⁺ type source region 7 and ^{the width Lp3 of the p +} type contact region 8 are 5 μm, respectively.

In the structure of FIG. 9, ^{there is a limit in shortening the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8, but in the structures of FIGS. 11 and 12, the n ⁺ type source region 7 is used. Since there is a margin for shortening the width Ln3 of the width Ln3 and the width Lp3 of the p ^{+ type contact region 8, it can be freely designed as compared with the structure of FIG.} For example, the width La of the first trench 30 can be 6 μm, which is narrower than the 8 μm of the structure of FIG.

As described above, according to the second embodiment, since the p-type pillar region and the p-type base region are formed at the same time, the same effect as that of the first embodiment is obtained. Further, in the second embodiment, since the high concentration p-type pillar region is provided, the impurity concentration in the n-type pillar region can be made higher than that in the first embodiment. As a result, the resistance of the drift layer is reduced, so that the on-resistance of the superjunction semiconductor device can be reduced.

(Embodiment 3)
Next, the superjunction semiconductor device 62 according to the third embodiment will be described. 14 to 17 are cross-sectional views showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 14 is a cross-sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 15 is a cross-sectional view taken along the line CD of FIG. 18 showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 16 is a sectional view taken along line EF of FIG. 18 showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 17 is a cross-sectional view taken along the line GH of FIG. 18 showing the structure of the superjunction semiconductor device according to the third embodiment. FIG. 18 is a plan view showing the structure of the superjunction semiconductor device according to the third embodiment.

As shown in FIGS. 14 to 18, the p-type pillar region 3 has a rectangular shape extending in the x-axis direction, and the p-type base region 6 has a rectangular shape extending in the z-axis direction. The longitudinal direction (x-axis direction) of the p-type pillar region 3 and the longitudinal direction (z-axis direction) of the p-type base region 6 are orthogonal to each other. p ⁺ -type contact region 8, as shown in FIG. 18, may be provided side by side and the p ⁺ -type contact region 8 and the n ⁺ -type source region 7 in the width direction of the second trenches 31 (x direction) ..

Further, as in the first embodiment, the impurity concentration increases in the order of the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, the high-concentration n-type drift layer 23, and the n ⁺ type source region 7, and the charge is charged. As a balance, the product of the impurity concentration p1 of the p-type pillar region 3 and the width Wp1 of the p-type pillar region 3 is substantially equal to the product of the impurity concentration n1 of the n-type pillar region 4 and the width Wn1 of the n-type pillar region 4. In other words
n1 × Wn1 ≒ p1 × Wp1
Is established. At this time, it is preferable to slightly increase the impurity concentration p1 in the p-type pillar region 3 to slightly increase the p-type impurities.

As described above, in the third embodiment, since the longitudinal direction of the p-type pillar region 3 and the longitudinal direction of the p-type base region 6 are orthogonal to each other, the channel length Lch, the trench width Wp1, and the mesa width Wn1 can be freely designed. can do. For example, the channel length Lch may be 1.5 μm, the width Wp1 of the second trench 31 may be 2.5 μm, the mesa width Wn1 may be 2.5 μm, and the interval Lj between the p-type base regions 6 may be 1.6 μm.

(Manufacturing method of superjunction semiconductor device according to the third embodiment)
In the method for manufacturing the superjunction semiconductor device 62 according to the third embodiment, in the manufacturing method for the superjunction semiconductor device 61 according to the first embodiment, the second trench 31 on which the p-type pillar region 3 is formed is based on the p-type. It is formed by making the region 6 orthogonal to the first trench 30 in which the region 6 is formed.

For example, first, the n-type drift layer 2 is epitaxially grown in the same manner as in the first embodiment. Next, the first trench 30 that does not reach the medium-concentration n-type drift layer 22 is formed by photolithography and etching. For example, the depth da of the first trench 30 may be formed to 2 μm, and the width La may be formed to 9 μm. Further, the distance Lj between the first trenches 30 may be 1.6 μm.

Next, by photolithography and etching, it penetrates the medium-concentration n-type drift layer 22 and the high-concentration n-type drift layer 23, reaches the low-concentration n-type drift layer 21, ^{and does not reach the n ++} type semiconductor substrate 1. 2 Trench 31 is formed. The second trench 31 is formed in a direction orthogonal to the first trench 30, and the bottom of the first trench 30 is formed so as to be continuous with the second trench 31 and narrower than the first trench 30. For example, the depth db of the second trench 31 may be formed to 20.1 μm, and the width Wp1 may be formed to 2.5 μm. Further, for example, the distance Wn1 between the second trenches 31 may be 2.5 μm, and the distance Lj between the first trenches 30 may be 1.6 μm.

Here, in order to prevent the narrow portion from being blocked by the neck first and forming a cavity when the deep trench (second trench 31) is backfilled by epitaxial growth, the upper and lower corners of the second trench having a width of Wp1 are formed. The rounding radii rWp1 and cWp1 are preferably 0.05 μm or more.

Next, by embedding p-type impurities in the first trench 30 and the second trench 31, the p-type pillar region 3 and the p-type base region 6 are epitaxially grown, and after the growth, the surface of the high-concentration n-type drift layer 23 is formed. Polish the surface of the p-type base region 6 until it is at the same height as. The impurity concentration of the p-type pillar region 3 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentration in the p-type pillar region 3 is set to 1.9 × 10 ¹⁶ / cm ³ . The p-type base region 6 may have the same impurity concentration as the p-type pillar region 3.

^{After that, as in the first embodiment, the steps after the step of forming the n +} type source region 7 in a part of the surface region of the p-type base region 6 are performed, and are shown in FIGS. 14 to 18. The superjunction semiconductor device 62 is completed.

Next, another structure of the superjunction semiconductor device 62 according to the third embodiment will be described. Another structure is a structure in which the p ⁺ type contact region 8 is provided side by side with the ^{n +} type source region 7 in the depth direction (z direction orthogonal to the x direction and the y direction) of the first trench 30. Further, for example, ^{the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8 are 3 μm, respectively.

In the structures of FIGS. 14 to 18, ^{there is a limit to shortening the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8, but in other structures, the width Lp3 of the n ⁺ type source region 7 Since there is a margin for shortening the width Ln3 and the width Lp3 of the p ⁺ type contact region 8, it can be freely designed as compared with the structures of FIGS. 14 to 18.

As described above, according to the third embodiment, since the p-type pillar region and the p-type base region are formed at the same time, the same effect as that of the first embodiment is obtained. Further, in the third embodiment, since the longitudinal direction of the p-type pillar region and the longitudinal direction of the p-type base region are orthogonal to each other, the channel length, trench width, and mesa width can be freely designed.

(Embodiment 4)
Next, the superjunction semiconductor device 63 according to the fourth embodiment will be described. FIG. 19 is a cross-sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the fourth embodiment. FIG. 20 is a cross-sectional view taken along the line CD of FIG. 23 showing the structure of the superjunction semiconductor device according to the fourth embodiment. FIG. 21 is a sectional view taken along line EF of FIG. 23 showing the structure of the superjunction semiconductor device according to the fourth embodiment. FIG. 22 is a cross-sectional view taken along the line GH of FIG. 23 showing the structure of the superjunction semiconductor device according to the fourth embodiment. FIG. 23 is a plan view showing the structure of the superjunction semiconductor device according to the fourth embodiment.

As shown in FIGS. 19 to 22, the p-type pillar region 3 has a rectangular shape extending in the x-axis direction, and the p-type base region 6 has a rectangular shape extending in the z-axis direction. Further, the upper high-concentration p-type pillar region 52 has a rectangular shape extending in the z-axis direction, and the lower high-concentration p-type pillar region 51 has a rectangular shape extending in the x-axis direction. The longitudinal direction of the p-type pillar region 3 (x-axis direction) and the longitudinal direction of the p-type base region 6 (z-axis direction) are orthogonal to each other, and the longitudinal direction (z-axis direction) of the upper high-concentration p-type pillar region 52 is The longitudinal direction (x-axis direction) of the lower high-concentration p-type pillar region 51 is orthogonal to each other. Further, as shown in FIGS. 19 to 22, the p ⁺ type contact region 8 is provided at the same depth as, for example, the n ^{+ type source region 7, and is n +} type in the width direction (x direction) of the first trench 30. It is provided alongside the source area 7.

Further, as in the first embodiment, the impurity concentration increases in the order of the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, the high-concentration n-type drift layer 23, and the n ^{+ type source region 7.} The lower high-concentration p-type pillar region 51 has a higher impurity concentration than the p-type pillar region 3, and the upper high-concentration p-type pillar region 52 has a higher impurity concentration than the p-type base region 6. Further, since the lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are formed at the same time, the impurity concentrations are about the same. For example, the impurity concentration p1 of the p-type pillar region 3 is 5 × 10 ¹⁵ / cm ³ , and the impurity concentration p2 of the high-concentration p-type pillar region 5 is 2.75 × 10 ¹⁶ / cm ³ .

Further, the third trench 40 is provided in the central portion of the first trench 30 with a width of Lp2, and is separated from the high-concentration n-type drift layer 23 by a distance of tp1. The width Lp2 is, for example, 5.0 μm, and the distance tp1 is, for example, 2 μm. Further, the fourth trench 41 is provided in the central portion of the second trench 31 with a width Wp2, and is separated from the high-concentration n-type drift layer 23 by a distance of tp1 and from the bottom surface of the second trench 31 by a distance of tp1b. The width Wp2 is, for example, 1 μm, and the distance tp1b is, for example, 2 μm.

Further, as a charge balance, the product of the impurity concentration p1 of the p-type pillar region 3 and the width Wp1-Wp2 of the portion where the high-concentration p-type pillar region 5 of the p-type pillar region 3 is not provided and the high-concentration p-type pillar region The sum of the product of the impurity concentration p2 of 5 and the width Wp2 of the high-concentration p-type pillar region 5 is substantially equal to the product of the impurity concentration n1 of the n-type pillar region 4 and the width Wn1 of the n-type pillar region 4, that is, ,
n1 × Wn1 ≒ p1 × (Wp1-Wp2) + p2 × Wp2
Is established. At this time, it is preferable to slightly increase the impurity concentration p1 of the p-type pillar region 3 or the impurity concentration p2 of the high-concentration p-type pillar region 5.

As described above, in the fourth embodiment, the longitudinal direction of the p-type pillar region 3 and the longitudinal direction of the p-type base region 6 are orthogonal to each other, and the longitudinal direction of the lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar are orthogonal to each other. It is orthogonal to the longitudinal direction of the region 52. Therefore, the channel length Lch, the trench width Wp1, and the mesa width Wn1 can be freely designed. Further, the trench width Wp1 can be shortened as compared with the third embodiment, and the mesa width Wn1 can be shortened to narrow the cell pitch. For example, the channel length Lch may be 1.5 μm, the trench width Wp1 may be 5 μm, the mesa width Wn1 may be 2.5 μm, and the interval Lj between the p-type base regions 6 may be 1.6 μm.

(Manufacturing method of superjunction semiconductor device according to the fourth embodiment)
In the method for manufacturing the superjunction semiconductor device 63 according to the fourth embodiment, in the method for manufacturing the superjunction semiconductor device 61 according to the second embodiment, the first trench 30 in which the p-type base region 6 is formed is formed in the p-type pillar. The third trench 40 in which the upper high-concentration p-type pillar region 52 is formed is orthogonal to the second trench 31 in which the region 3 is formed, and is orthogonal to the fourth trench 41 in which the lower high-concentration p-type pillar region 51 is formed. It is formed by letting it.

For example, first, the n-type drift layer 2 is epitaxially grown in the same manner as in the second embodiment. Next, the first trench 30 that does not reach the medium-concentration n-type drift layer 22 is formed by photolithography and etching. For example, the depth da of the first trench 30 may be formed to 2 μm, and the width La may be formed to 9 μm. Further, the distance Lj between the first trenches 30 may be 1.6 μm.

Next, by photolithography and etching, it penetrates the medium-concentration n-type drift layer 22 and the high-concentration n-type drift layer 23, reaches the low-concentration n-type drift layer 21, ^{and does not reach the n ++} type semiconductor substrate 1. 2 Trench 31 is formed. The second trench 31 is formed in a direction orthogonal to the first trench 30, and the bottom of the first trench 30 is formed so as to be continuous with the second trench 31 and narrower than the first trench 30. For example, the depth db of the second trench 31 may be formed to 20.1 μm, and the width Wp1 may be formed to 5 μm. Further, for example, the distance Wn1 between the second trench 31 may be 2.5 μm.

Here, in order to prevent the narrow portion from being closed first by the neck and forming a cavity when the deep trench (second trench 31) is backfilled by epitaxial growth, the upper and bottom corners of the second trench 31 having a width of Wp1 are prevented. The rounding radii rWp1 and cWp1 are preferably 0.05 μm or more.

Next, the p-type pillar region 3 and the p-type base region 6 are epitaxially grown by embedding p-type impurities in the first trench 30 and the second trench 31. The impurity concentration of the p-type pillar region 3 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentration in the p-type pillar region 3 is set to 5 × 10 ¹⁵ / cm ³ . The p-type base region 6 may have the same impurity concentration as the p-type pillar region 3.

Next, by photolithography and etching, a third trench 40 and a fourth trench 41 that penetrate the p-type base region 6 and reach the p-type pillar region 3 and do not reach the low-concentration n-type drift layer 21 are formed. The third trench 40 is formed shallower than the first trench 30. That is, the bottom surface of the third trench 40 is formed closer to the source electrode 12 than the bottom surface of the first trench 30. Similarly, the fourth trench 41 is formed shallower than the second trench 31. The third trench 40 is formed so that the bottom portion is continuous with the fourth trench 41 and is wider than the fourth trench 41.

Next, by embedding p-type impurities in the third trench 40 and the fourth trench 41, the lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are epitaxially grown.

Next, the surface of the upper high-concentration p-type pillar region 52 is polished until the height becomes the same as the surface of the high-concentration n-type drift layer 23. The lower high-concentration p-type pillar region 51 and the upper high-concentration p-type pillar region 52 are combined to form the high-concentration p-type pillar region 5. The impurity concentration of the high-concentration p-type pillar region 5 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentrations of the p-type pillar region 3 and the high-concentration p-type pillar region 5 are set to 5 × 10 ¹⁵ / cm ³ and 2.75 × 10 ¹⁵ / cm ³ , respectively.

After that, as in the second embodiment, the steps after the step of forming the ^{n +} type source region 7 on a part of the surface region of the p-type base region 6 and the high-concentration p-type pillar region 5 are performed. The superjunction semiconductor device 63 shown in FIGS. 19 to 23 is completed.

Next, another structure of the superjunction semiconductor device 63 according to the fourth embodiment will be described. Another structure is a structure in which the p ⁺ type contact region 8 is provided side by side with the ^{n +} type source region 7 in the depth direction (z direction orthogonal to the x direction and the y direction) of the first trench 30. Further, for example, ^{the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8 are 5 μm, respectively.

In the structures of FIGS. 19 to 23, ^{there is a limit in shortening the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8, but in other structures, the width Lp3 of the n ⁺ type source region 7 Since there is a margin for shortening the width Ln3 and the width Lp3 of the p ⁺ type contact region 8, it can be freely designed as compared with the structures of FIGS. 19 to 23. For example, the width La of the first trench 30 can be made 6 μm, which is narrower than 9 μm of the structures of FIGS. 19 to 23.

As described above, according to the fourth embodiment, since the p-type pillar region and the p-type base region are formed at the same time, the same effect as that of the first embodiment is obtained. Further, since the high-concentration p-type pillar region is provided, it has the same effect as that of the second embodiment. Further, since the longitudinal direction of the p-type pillar region and the longitudinal direction of the p-type base region are orthogonal to each other, the same effect as that of the third embodiment is obtained.

(Embodiment 5)
Next, the superjunction semiconductor device 64 according to the fifth embodiment will be described. FIG. 24 is a cross-sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the fifth embodiment. Further, FIG. 25 is a cross-sectional view taken along the line CD showing the structure of the superjunction semiconductor device according to the fifth embodiment. Further, FIG. 26 is a plan view showing the structure of the superjunction semiconductor device according to the fifth embodiment. FIG. 24 shows only two unit cells (functional units of the element), and other unit cells adjacent to them are not shown. In the superjunction semiconductor device 64 shown in FIG. 24, a MOS (Metal Oxide Semiconductor) gate is provided on the front surface (surface on the p-type base region 6 side) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide. It is a super-junction MOSFET equipped.

The silicon carbide substrate includes a low-concentration n-type drift layer 21 and a medium-concentration n-type drift layer 22 on the first main surface (front surface) ^{of the n ++ type semiconductor substrate (first conductive type semiconductor substrate) 1.} Each silicon carbide layer to be the high-concentration n-type drift layer 23 is epitaxially grown in order. The MOS gate includes a p-type base region (second conductive type third semiconductor region) 6, an n ⁺ type source region (first conductive type fifth semiconductor region) 7, a p ⁺ type contact region 8, and a gate insulating film. It is composed of 9 and a gate electrode 10. Here, the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, and the high-concentration n-type drift layer 23 are combined to form the n-type drift layer (first conductive type first semiconductor layer) 2. To. The low-concentration n-type drift layer 21 is provided at a lower impurity concentration than the medium-concentration n-type drift layer 22, and the medium-concentration n-type drift layer 22 is provided at a lower impurity concentration than the high-concentration n-type drift layer 23.

The n-type drift layer 2 is provided with a parallel pn region 19. In the parallel pn region 19, the p-type pillar region (second conductive type second semiconductor region) 3 and the n-type region (n-type pillar region 4) sandwiched between the p-type pillar regions 3 are alternately and repeatedly joined. It is made. The p-type pillar region 3 penetrates the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 from the bottom surface of the p-type base region 6 (the surface on the n ^{++ type semiconductor substrate 1 side) and has a low concentration.} It is provided so as to reach the surface of the n-type drift layer 21 and not reach the n ^{++ type semiconductor substrate 1.} Further, the p-type pillar region 3 reaches the surface of the low-concentration n-type drift layer 21, but does not reach deep inside the low-concentration n-type drift layer 21. Therefore, when considering the charge balance between the p-type region and the n-type region, it is not necessary to consider the impurity concentration of the low-concentration n-type drift layer 21. The planar shapes of the p-type pillar region 3 and the n-type pillar region 4 are, for example, rectangular, hexagonal grid, or square.

Here, the low-concentration n-type drift layer 21 is a layer that shares the withstand voltage of the device, and the impurity concentration of the low-concentration n-type drift layer 21 is lowered to increase the film thickness of the low-concentration n-type drift layer 21. Thereby, high withstand voltage of the element can be realized. Further, the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 are layers that share the charge balance of the elements. Further, the high-concentration n-type drift layer 23 is a so-called current diffusion layer (Current Spreading Layer: CSL) that reduces the spreading resistance of carriers. The high-concentration n-type drift layer 23 can increase the on-current.

Since there is a low-concentration n-type drift layer 21 that shares the high withstand voltage of the device, the film thicknesses of the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 can be reduced even when the device has a high withstand voltage. it can. Therefore, the depth of the p-type pillar region 3 provided in the high-concentration n-type drift layer 23 and the medium-concentration n-type drift layer 22 (the depth of the parallel pn region 19) can be made shallow. As described above, even when the withstand voltage of the element is increased, the depth of the p-type pillar region 3 is shallow, so that the p-type pillar region 3 can be epitaxially grown at a uniform impurity concentration. Therefore, even when the withstand voltage is increased, the charge balance between the p-type region and the n-type region can be maintained, and the superjunction semiconductor device 64 having low on-resistance and high withstand voltage characteristics can be realized.

A p-type base region 6 is provided on the surface layer of the n-type drift layer 2 on the source side (source electrode 12 side), and the p-type pillar region 3 and the p-type base region 6 are formed at the same time, and thus are integrated. Has been done. Specifically, a second trench 31 having a depth of db and a first trench 30 having a depth of da are provided in the n-type drift layer 2 at a position shallower than the second trench 31. The second trench 31 is provided in the n-type drift layer 2, and the bottom surface of the first trench 30 is continuous with the opening of the second trench 31 and opens on the front surface of the n-type drift layer 2. The width Wa of the 1 trench 30 is wider than the width Wp1 of the second trench 31.

The p-type pillar region 3 is formed by filling the second trench 31 with p-type impurities, and the p-type base region 6 is formed by filling the first trench 30 with p-type impurities. In this way, by forming a two-stage trench composed of the first trench 30 and the second trench 31, a structure corresponding to the p-type pillar region 3 and the p-type base region 6 is formed, and the p-type is formed therein. Impurities are embedded and the layer is used as the p-type pillar region 3 and the p-type base region 6.

A high-concentration p-type pillar region 5 having a higher impurity concentration than the p-type pillar region 3 is selectively provided inside the p-type base region 6. The withstand voltage of the semiconductor device can be improved by the high concentration p-type pillar region 5. Further, the high-concentration p-type pillar region 5 is not provided inside the p-type pillar region 3. Therefore, the first interface between the high-concentration p-type pillar region 5 and the p-type base region 6 is shallower than the second interface between the p-type pillar region 3 and the p-type base region 6. That is, the first interface is on the surface side of the p-type base region 6 from the second interface. This eliminates the need to take into account the impurity concentration of the high-concentration p-type pillar region 5 in the charge balance of the SJ-MOSFET. For example, the distance tp1b between the first interface and the second interface is 3.6 μm. Further, the high-concentration p-type pillar region 5 is provided in the central portion of the p-type base region 6 with a width Lp2, and is separated from the high-concentration n-type drift layer 23 by tp1. The width Lp2 is, for example, 0.8 μm, and the distance tp1 is, for example, 3.6 μm. Further, for example, the impurity concentration p1 of the p-type pillar region 3 is 6.7 × 10 ¹⁵ / cm ³ , and the impurity concentration p2 of the high-concentration p-type pillar region 5 is 4 × 10 ¹⁸ / cm ³ .

Further, the impurity concentration increases in the order of the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, the high-concentration n-type drift layer 23, and the n ⁺ type source region 7 described later, and the p-type pillar is used as a charge balance. The product of the impurity concentration p1 of the region 3 and the width Wp1 of the p-type pillar region 3 is substantially equal to the product of the impurity concentration n1 of the n-type pillar region 4 and the width Wn1 of the n-type pillar region 4, that is,
n1 × Wn1 ≒ p1 × Wp1
Is established. At this time, it is preferable to slightly increase the impurity concentration p1 in the p-type pillar region 3 to slightly increase the p-type impurities.

Inside the p-type base region 6, and n ⁺ -type source region 7 and the p ⁺ -type contact region 8 are provided, respectively selectively in contact with each other. The depth of the p ^{+ type contact region 8 may be the same as, for example, the same depth as the n +} type source region 7, or may be deeper. As ^{shown in FIG. 3, the p + type contact region 8 is provided with the p +} type contact region 8 and the n ⁺ type source region 7 arranged side by side in the depth direction (y-axis direction) of the second trench 31.

A gate electrode 10 is provided on the surface of the p-type base region 6 ^{sandwiched between the n +} -type source region 7 and the n-type pillar region 4 via a gate insulating film 9. The gate electrode 10 may be provided on the surface of the n-type pillar region 4 via the gate insulating film 9.

The interlayer insulating film 11 is provided on the front surface side of the semiconductor substrate so as to cover the gate electrode 10. ^{The source electrode 12 is in contact with the n +} type source region 7 and the p-type base region 6 through a contact hole opened in the interlayer insulating film 11, ^{and is electrically connected to the n +} type source region 7 and the p-type base region 6. Be connected.

The source electrode (first electrode) 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A protective film (not shown) such as a passivation film made of polyimide is selectively provided on the source electrode 12.

A back electrode (second electrode) 13 is provided on the second main surface (back surface, that is, the back surface of the semiconductor substrate) of the ^{n ++ type semiconductor substrate 1.} The back surface electrode 13 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back surface electrode 13.

In the plan view of FIG. 26, the interlayer insulating film 11 and the source electrode 12 are omitted in order to make the internal structure easier to see. Similarly, in the other plan views thereafter, the interlayer insulating film 11 and the source electrode 12 are omitted.

(Manufacturing method of superjunction semiconductor device according to the fifth embodiment)
Next, a method of manufacturing the superjunction semiconductor device 64 according to the fifth embodiment will be described. First, an n ⁺⁺ type semiconductor substrate 1 made of silicon carbide is prepared. Then, the front surface of the n ⁺⁺ type semiconductor substrate 1, a low impurity concentration than n ⁺⁺ type semiconductor substrate 1 low-concentration n-type drift layer 21 is epitaxially grown. At this time, for example, the n-type impurities may be doped and epitaxially grown so that the impurity concentration of the low-concentration n-type drift layer 21 is 2.5 × 10 ¹⁵ / cm ^{3 and the film thickness tn 4 is 40 μm.}

Next, a medium-concentration n-type drift layer 22 having a higher impurity concentration than the low-concentration n-type drift layer 21 is epitaxially grown on the surface of the low-concentration n-type drift layer 21. At this time, for example, the n-type impurities may be doped and epitaxially grown so that the impurity concentration of the medium-concentration n-type drift layer 22 is 1.5 × 10 ¹⁶ / cm ^{3 and the film thickness tn1 is 20 μm.}

Next, a high-concentration n-type drift layer 23 having a higher impurity concentration than the medium-concentration n-type drift layer 22 is epitaxially grown on the surface of the medium-concentration n-type drift layer 22. At this time, for example, the n-type impurities may be doped so as to have ^{an impurity concentration of 1.7 × 10 16} / cm ³ and a film thickness of 4.7 μm in the high-concentration n-type drift layer 23 for epitaxial growth. The low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, and the high-concentration n-type drift layer 23 are combined to form the n-type drift layer 2.

Next, by photolithography and etching, it penetrates the medium-concentration n-type drift layer 22 and the high-concentration n-type drift layer 23, reaches the low-concentration n-type drift layer 21, ^{and does not reach the n ++} type semiconductor substrate 1. One trench 30 and a second trench 31 are formed. The first trench 30 is formed so that the bottom portion is continuous with the second trench 31 and is wider than the second trench 31. At this time, for example, even if the depth db of the second trench 31 is formed to 20.1 μm and the width Wp1 is formed to 7.1 μm, the depth da of the first trench 30 is formed to 4.2 μm and the width Wa is formed to 8 μm. Good. Further, for example, the distance Wn1 between the second trenches 31 may be 2.5 μm, and the distance Lj between the first trenches 30 may be 1.6 μm.

Here, in order to prevent the narrow portion from being blocked by the neck first and forming a cavity when the deep trench (second trench 31) is backfilled by epitaxial growth, the upper and lower corners of the second trench having a width of Wp1 are formed. The rounding radii rWp1 and cWp1 are preferably 0.05 μm or more. The rounding radii of the other top and bottom corners are less important.

Next, the p-type pillar region 3 and the p-type base region 6 are epitaxially grown by embedding p-type impurities in the first trench 30 and the second trench 31. The impurity concentration of the p-type pillar region 3 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentration in the p-type pillar region 3 is set to 6.7 × 10 ¹⁵ / cm ³ . The p-type base region 6 may have the same impurity concentration as the p-type pillar region 3. Here, since the second trench 31 is formed at the bottom of the first trench 30, when a p-type impurity is embedded in the first trench 30, a groove is formed in the center of the p-type impurity embedded in the first trench 30. Is formed.

As described above, in the fifth embodiment, the p-type pillar region 3 and the p-type base region 6 are formed at the same time by embedding the p-type impurities in the first trench 30 and the second trench 31. Therefore, the step of forming the p-type base region 6 by ion implantation can be omitted.

Next, the high-concentration p-type pillar region 5 is epitaxially grown by embedding p-type impurities in the groove. The impurity concentration of the high-concentration p-type pillar region 5 is higher than that of the p-type base region 6. For example, the impurity concentration of the high-concentration p-type pillar region 5 is set to 4 × 10 ¹⁸ / cm ³ .

Next, the surfaces of the high-concentration p-type pillar region 5 and the p-type base region 6 are polished until they are flush with the surface of the high-concentration n-type drift layer 23.

Next, a mask having a desired opening is formed on the surfaces of the high-concentration p-type pillar region 5 and the p-type base region 6 by a photolithography technique, for example, with a resist. Then, using this resist mask as a mask, n-type impurities are ion-implanted by the ion implantation method. ^{As a result, the n +} type source region 7 is formed in a part of the surface region of the high-concentration p-type pillar region 5 and the p-type base region 6. Further, for example, the distance Lch between the high-concentration n-type drift layer 23 and the n ^{+ -type source region 7, which is the channel length, is 1.5 μm.} The width Ln3 of the n ⁺ type source region 7 is, for example, 5 μm. Next, the mask used during ion implantation to form the ^{n + type source region 7 is removed.}

Next, an ion implantation mask (not shown) having a desired opening is formed on the surfaces of the high-concentration p-type pillar region 5 and the p-type base region 6 by a photolithography technique, for example, with an oxide film. Using this ion implantation mask as a mask, ion implantation of p-type impurities is performed, and the p-type base region 6 and the high-concentration p-type pillar are partially implanted in the surface regions of the high-concentration p-type pillar region 5 and the p-type base region 6. ^{A p +} type contact region 8 having a higher impurity concentration than the region 5 is formed. The width Lp3 of the p ⁺ type contact region 8 is about the same as the width Ln3 of the n ⁺ type source region 7, for example, 5 μm. Next, the ion implantation mask for forming the ^{p + type contact region 8 is removed.}

Next, a heat treatment (annealing) is performed to activate ^{the n +} type source region 7 and the p ^{+ type contact region 8.} Further, the order in which the n ⁺ type source region 7 and the p ⁺ type contact region 8 are formed can be changed in various ways.

Next, the front surface side of the semiconductor substrate is thermally oxidized to form the gate insulating film 9. As a result, each region formed on the surface of the n-type drift layer 2 is covered with the gate insulating film 9.

Next, for example, a phosphorus-doped polycrystalline silicon layer is formed on the gate insulating film 9 as the gate electrode 10. Next, the polycrystalline silicon layer is patterned and selectively removed ^{, leaving the polycrystalline silicon layer on the portion of the p-type base region 6 sandwiched between the n +} type source region 7 and the n-type pillar region 4. At this time, the polycrystalline silicon layer may be left on the n-type pillar region 4.

Next, for example, phosphorus glass (PSG: Phospho Silicate Glass) is formed as the interlayer insulating film 11 so as to cover the gate electrode 10. Next, the interlayer insulating film 11 and the gate insulating film 9 are patterned and selectively removed. For example, by removing the interlayer insulating film 11 and the gate insulating film 9 on the n ⁺ -type source region 7 to form a contact hole to expose the n ⁺ -type source region 7. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11.

Next, the source electrode 12 is formed by sputtering, and the source electrode 12 is patterned by photolithography and etching. At this time, the source electrode 12 is embedded in the contact hole, and the n ⁺ type source region 7 and the source electrode 12 are electrically connected. A tungsten plug or the like may be embedded in the contact hole via a barrier metal.

Next, ^{for example, a nickel film is formed on the front surface of the n ++} type semiconductor substrate 1 (the back surface of the semiconductor substrate) as the back surface electrode 13. Then, heat treatment is performed to ^{form an ohmic contact between the n ++} type semiconductor substrate 1 and the back surface electrode 13.

In the above-mentioned epitaxial growth and ion implantation, examples of n-type impurities (n-type dopants) include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), which are n-type with respect to silicon carbide. Should be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), tallium (Tl), etc., which are p-type with respect to silicon carbide, may be used. .. As a result, the superjunction semiconductor device 64 shown in FIGS. 24 to 26 is completed.

As described above, according to the fifth embodiment, the p-type pillar region and p are formed by forming the first trench and the second trench and embedding p-type impurities in the first trench and the second trench. The mold base region is formed at the same time. This makes it possible to omit the step of forming the p-type base region by ion implantation. Therefore, the cost for manufacturing the superjunction semiconductor device can be reduced. Further, the on-current can be increased by the high-concentration n-type drift layer and the medium-concentration n-type drift layer, and the channel length, trench width, and mesa width can be freely designed by adjusting the concentration of the n-type drift layer.

(Embodiment 6)
Next, the superjunction semiconductor device 65 according to the sixth embodiment will be described. FIG. 27 is a cross-sectional view taken along the line AB showing the structure of the superjunction semiconductor device according to the sixth embodiment. Further, FIG. 28 is a cross-sectional view taken along the line CD of FIG. 31 showing the structure of the superjunction semiconductor device according to the sixth embodiment. Further, FIG. 29 is a sectional view taken along line EF of FIG. 31 showing the structure of the superjunction semiconductor device according to the sixth embodiment. Further, FIG. 30 is a cross-sectional view taken along the line GH of FIG. 31 showing the structure of the superjunction semiconductor device according to the sixth embodiment. Further, FIG. 31 is a plan view showing the structure of the superjunction semiconductor device according to the sixth embodiment.

As shown in FIGS. 27 to 31, the p-type pillar region 3 has a rectangular shape extending in the x-axis direction, and the p-type base region 6 has a rectangular shape extending in the z-axis direction. The longitudinal direction (x-axis direction) of the p-type pillar region 3 and the longitudinal direction (z-axis direction) of the p-type base region 6 are orthogonal to each other. As ^{shown in FIG. 27, the p + type contact region 8 is provided with the p +} type contact region 8 and the n ⁺ type source region 7 arranged side by side in the depth direction (z-axis direction) of the first trench 30.

Further, as in the fifth embodiment, the impurity concentration increases in the order of the low-concentration n-type drift layer 21, the medium-concentration n-type drift layer 22, the high-concentration n-type drift layer 23, and the n ⁺ type source region 7, and the charge is charged. As a balance, the product of the impurity concentration p1 of the p-type pillar region 3 and the width Wp1 of the p-type pillar region 3 is substantially equal to the product of the impurity concentration n1 of the n-type pillar region 4 and the width Wn1 of the n-type pillar region 4. That is,
n1 × Wn1 ≒ p1 × Wp1
Is established. At this time, it is preferable to slightly increase the impurity concentration p1 in the p-type pillar region 3 to slightly increase the p-type impurities.

As described above, in the sixth embodiment, since the longitudinal direction of the p-type pillar region 3 and the longitudinal direction of the p-type base region 6 are orthogonal to each other, the channel length Lch, the trench width Wp1, and the mesa width Wn1 can be freely designed. can do. In the fifth embodiment, ^{there is a limit to shortening the width Ln3 of the n +} type source region 7 and ^{the width Lp3 of the p +} type contact region 8, but in the sixth embodiment, the width Ln3 of the n ⁺ type source region 7 Since ^{there is a margin for shortening the width Lp3 of the p +} type contact region 8, the cell pitch can be narrowed as compared with the fifth embodiment. Therefore, the impurity concentration in the p-type pillar region 3 and the impurity concentration in the p-type base region 6 can be designed independently. For example, the channel length Lch is 1.5 μm, the width La of the first trench 30 is 6 μm, the width Wp1 of the second trench 31 is 2.5 μm, the mesa width Wn1 is 2.5 μm, and the spacing between the p-type base regions 6 (the first). The mesa width of 1 trench 30) Lj may be 1.6 μm.

(Manufacturing method of superjunction semiconductor device according to the sixth embodiment)
In the method for manufacturing the superjunction semiconductor device 65 according to the sixth embodiment, in the manufacturing method for the superjunction semiconductor device 65 according to the sixth embodiment, the second trench 31 on which the p-type pillar region 3 is formed is based on the p-type. It is formed by making the region 6 orthogonal to the first trench 30 in which the region 6 is formed.

For example, first, the n-type drift layer 2 is epitaxially grown in the same manner as in the fifth embodiment. The n-type drift layer 2 is composed of a low-concentration n-type drift layer 21, a medium-concentration n-type drift layer 22, and a high-concentration n-type drift layer 23. The film thickness and the impurity concentration of the high-concentration n-type drift layer 23 are the same as those in the fifth embodiment.

Next, the first trench 30 that does not reach the medium-concentration n-type drift layer 22 is formed by photolithography and etching. For example, the depth da of the first trench 30 may be formed to be 2 μm, and the width La may be formed to be 6 μm. Further, the distance Lj between the first trenches 30 may be 1.6 μm.

Next, by photolithography and etching, it penetrates the medium-concentration n-type drift layer 22 and the high-concentration n-type drift layer 23, reaches the low-concentration n-type drift layer 21, ^{and does not reach the n ++} type semiconductor substrate 1. 2 Trench 31 is formed. The second trench 31 is formed in a direction orthogonal to the first trench 30, and the bottom of the first trench 30 is formed so as to be continuous with the second trench 31 and narrower than the first trench 30. For example, the depth db of the second trench 31 from the bottom of the first trench 30 may be 20.1 μm, and the width Wp1 may be 2.5 μm. Further, for example, the distance Wn1 between the second trench 31 may be 2.5 μm.

Here, in order to prevent the narrow portion from being blocked by the neck first and forming a cavity when the deep trench (second trench 31) is backfilled by epitaxial growth, the upper and lower corners of the second trench having a width of Wp1 are formed. The rounding radii rWp1 and cWp1 are preferably 0.05 μm or more.

Next, the p-type pillar region 3 and the p-type base region 6 are epitaxially grown by embedding p-type impurities in the first trench 30 and the second trench 31. The impurity concentration of the p-type pillar region 3 is determined so as to maintain the charge balance between the p-type region and the n-type region. For example, the impurity concentration in the p-type pillar region 3 is set to 1.9 × 10 ¹⁶ / cm ³ . The p-type base region 6 may have the same impurity concentration as the p-type pillar region 3. Here, since the second trench 31 is formed at the bottom of the first trench 30, when a p-type impurity is embedded in the first trench 30, a groove is formed in the center of the p-type impurity embedded in the first trench 30. Is formed.

Next, the high-concentration p-type pillar region 5 is epitaxially grown by embedding p-type impurities in the groove. The impurity concentration of the high-concentration p-type pillar region 5 is higher than that of the p-type base region 6. For example, the impurity concentration of the high-concentration p-type pillar region 5 is set to 4 × 10 ¹⁸ / cm ³ .

Next, the surfaces of the high-concentration p-type pillar region 5 and the p-type base region 6 are polished until they are flush with the surface of the high-concentration n-type drift layer 23. ^{After that, as in the fifth embodiment, the steps after the step of forming the n +} type source region 7 on a part of the surface region of the p-type base region 6 are performed, and are shown in FIGS. 27 to 31. The superjunction semiconductor device 65 is completed.

As described above, according to the sixth embodiment, since the p-type pillar region and the p-type base region are formed at the same time, the same effect as that of the fifth embodiment is obtained. Further, in the sixth embodiment, since the longitudinal direction of the p-type pillar region and the longitudinal direction of the p-type base region are orthogonal to each other, the channel length, trench width, and mesa width can be freely designed. Further, in the sixth embodiment, ^{since there is a margin for shortening the width of the n +} type source region and the width of the p ⁺ type contact region, the cell pitch can be narrowed as compared with the fifth embodiment. Therefore, the impurity concentration in the p-type pillar region and the impurity concentration in the p-type base region can be designed independently.

In the present invention, the case where the MOS gate structure is configured on the first main surface of the silicon carbide substrate made of silicon carbide has been described as an example, but the present invention is not limited to this, and the surface orientation of the main surface of the substrate is variously changed. It is possible. Further, in the present invention, the first conductive type is n-type and the second conductive type is p-type in each embodiment, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. The same holds true. Further, in the above description, although MOSFET has been described as an example, it can also be applied to an IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor). In this case, the n ⁺⁺ type semiconductor substrate may be a p-type collector layer.

As described above, the superjunction semiconductor device and the method for manufacturing a superjunction semiconductor device according to the present invention are useful for high withstand voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines.

1,101 n ⁺⁺ type semiconductor substrate 2,102 n-type drift layer 21 Low-concentration n-type drift layer 22 Medium-concentration n-type drift layer 23 High-concentration n-type drift layer 3,103 p-type pillar region 4,104 n-type pillar Region 5 High-concentration p-type pillar region 51 Lower high-concentration p-type pillar region 52 Upper high-concentration p-type pillar region 6,106 p-type base region 7,107 n ⁺ type source region 8 p ⁺ type contact region 9,109 Gate insulation Film 10, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back surface electrode 19, 119 Parallel pn region 30 First trench 31 Second trench 32 Groove 40 Third trench 41 Fourth trench 60, 61, 62, 63, 64, 65, 160 super-junction semiconductor devices

Claims (11)

The first conductive type semiconductor substrate and
A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate, which is provided on the front surface of the semiconductor substrate,
The first trench provided in the first semiconductor layer and
A second trench, which is provided on the surface of the first semiconductor layer and whose bottom is continuous with the first trench and is wider than the first trench,
A second conductive type second semiconductor region provided inside the first trench, and
A second conductive type third semiconductor region provided inside the second trench, and
A first conductive type fourth semiconductor region having a higher impurity concentration than the first semiconductor layer, which is provided inside the third semiconductor region,
A gate electrode provided on the surface of the third semiconductor region sandwiched between the fourth semiconductor region and the first semiconductor layer via a gate insulating film, and a gate electrode.
A first electrode provided on the surface of the fourth semiconductor region and the third semiconductor region,
A second electrode provided on the back surface of the semiconductor substrate and
A superjunction semiconductor device characterized by being equipped with. The second semiconductor region, the third trench provided in the third semiconductor region, and
A fourth trench, which is provided on the surface of the third semiconductor region and whose bottom is continuous with the third trench and is wider than the third trench.
A second conductive type fifth semiconductor region having a higher impurity concentration than the second semiconductor region, which is provided inside the third trench,
A second conductive type sixth semiconductor region having a higher impurity concentration than the third semiconductor region, which is provided inside the fourth trench,
The superjunction semiconductor device according to claim 1, further comprising. The second semiconductor region and the third semiconductor region have a rectangular shape and have a rectangular shape.
The superjunction semiconductor device according to claim 1, wherein the longitudinal direction of the second semiconductor region and the longitudinal direction of the third semiconductor region are orthogonal to each other. The second semiconductor region, the third semiconductor region, the fifth semiconductor region, and the sixth semiconductor region have a rectangular shape.
The second aspect of claim 2 is characterized in that the longitudinal direction of the second semiconductor region and the longitudinal direction of the third semiconductor region are orthogonal to each other, and the longitudinal direction of the fifth semiconductor region and the longitudinal direction of the sixth semiconductor region are orthogonal to each other. The superjunction semiconductor device described. A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the front surface of the first conductive type semiconductor substrate.
A second step of forming a first trench in the first semiconductor layer and a second trench having a bottom continuous with the first trench on the surface of the first semiconductor layer and having a width wider than that of the first trench.
A third step of forming a second conductive type second semiconductor region and a second conductive type third semiconductor region by epitaxial growth inside the first trench and inside the second trench.
A fourth step of forming a first conductive type fourth semiconductor region having a higher impurity concentration than the first semiconductor layer inside the third semiconductor region.
A fifth step of forming a gate electrode via a gate insulating film on at least a part of the surface of the third semiconductor region sandwiched between the fourth semiconductor region and the first semiconductor layer.
The sixth step of forming the first electrode on the surfaces of the fourth semiconductor region and the third semiconductor region, and
The seventh step of forming the second electrode on the back surface of the semiconductor substrate, and
A method for manufacturing a superjunction semiconductor device, which comprises. After the third step and before the fourth step,
A third trench is formed in the second semiconductor region and the third semiconductor region, and a fourth trench having a bottom continuous with the third trench and having a width wider than the third trench is formed on the surface of the third semiconductor region. Process and
Due to epitaxial growth inside the third trench and inside the fourth trench, a second conductive type fifth semiconductor region having a higher impurity concentration than the second semiconductor region and a higher impurity concentration than the third semiconductor region The process of forming the second conductive type sixth semiconductor region and
The method for manufacturing a superjunction semiconductor device according to claim 5, wherein the superjunction semiconductor device comprises. The first conductive type semiconductor substrate and
A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate, which is provided on the front surface of the semiconductor substrate,
The first trench provided in the first semiconductor layer and
A second trench having a bottom surface continuous with the opening of the first trench, opening at the front surface of the first semiconductor layer, and wider than the first trench.
A second conductive type second semiconductor region provided inside the first trench, and
A second conductive type third semiconductor region provided inside the second trench, and
A second conductive type fourth semiconductor region having a higher impurity concentration than the third semiconductor region, which is provided inside the third semiconductor region,
A first conductive type fifth semiconductor region having a higher impurity concentration than the first semiconductor layer, which is provided on the surface of the third semiconductor region so as to be in contact with the fourth semiconductor region,
A gate electrode provided on the surface of the third semiconductor region sandwiched between the fifth semiconductor region and the first semiconductor layer via a gate insulating film, and a gate electrode.
A first electrode provided on the surface of the fifth semiconductor region and the third semiconductor region,
A second electrode provided on the back surface of the semiconductor substrate and
A superjunction semiconductor device characterized by being equipped with. The superjunction semiconductor device according to claim 7, wherein the interface between the fourth semiconductor region and the third semiconductor region is located at a position shallower than the interface between the second semiconductor region and the third semiconductor region. The second semiconductor region and the third semiconductor region have a striped shape and have a striped shape.
The longitudinal direction of the second semiconductor region and the longitudinal direction of the third semiconductor region are parallel to each other.
The superjunction semiconductor device according to claim 7 or 8, wherein the third semiconductor region is provided inside the second trench. The second semiconductor region and the third semiconductor region have a striped shape and have a striped shape.
The superjunction semiconductor device according to claim 7 or 8, wherein the longitudinal direction of the second semiconductor region and the longitudinal direction of the third semiconductor region are orthogonal to each other. A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the front surface of the first conductive type semiconductor substrate.
A second trench having a first trench in the first semiconductor layer, a bottom surface continuous with the opening of the first trench, an opening in the front surface of the first semiconductor layer, and a width wider than the first trench. The second step of forming and
A third step of forming a second conductive type second semiconductor region and a second conductive type third semiconductor region by epitaxial growth inside the first trench and inside the second trench.
A fourth step of forming a second conductive type fourth semiconductor region having a higher impurity concentration than the third semiconductor region inside the third semiconductor region.
A fifth step of forming a first conductive type fifth semiconductor region having a higher impurity concentration than the first semiconductor layer so as to be in contact with the fourth semiconductor region on the surface of the third semiconductor region.
A sixth step of forming a gate electrode via a gate insulating film on at least a part of the surface of the third semiconductor region sandwiched between the fifth semiconductor region and the first semiconductor layer.
A seventh step of forming a first electrode on the surfaces of the fifth semiconductor region and the third semiconductor region,
The eighth step of forming the second electrode on the back surface of the semiconductor substrate, and
A method for manufacturing a superjunction semiconductor device, which comprises.

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