JP2020188082A - Semiconductor package - Google Patents

Abstract

To provide a semiconductor package capable of achieving space saving and sufficient radiation characteristics.SOLUTION: A semiconductor package 100a includes: at least one or more semiconductor chips 102, 104; a sealing material for sealing the semiconductor chip; and ground wiring 106. At least a part of the ground wiring, a radiation member 108 is provided. At a part or the whole of the ground wiring used to apply a GND potential, a radiation member such as a radiation plate or a radiation fin is provided.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor package.

In recent years, semiconductor devices with high heat generation density such as discrete semiconductors, LSIs, optical semiconductors, microwave devices, power semiconductors, and various sensors have been mounted in electronic and electrical equipment.

Semiconductor devices are generally sealed with a resin, ceramic, or the like to protect the semiconductor chips used, and are treated as semiconductor packages. Further, the operation of the semiconductor chip is an exothermic reaction, and this heat may cause a malfunction of the semiconductor device. Therefore, in order to release the generated heat to the outside of the semiconductor device and ensure high reliability in driving the device, the semiconductor package is required to have high heat dissipation (see, for example, Patent Document 1).

A semiconductor package is generally a type in which a semiconductor chip is sealed with a resin or ceramic. The resin or ceramic may also seal the heat radiating member that dissipates the heat generated by the semiconductor chip.

As the heat radiating member, a metal having high thermal conductivity (copper, aluminum, aluminum alloy, magnesium alloy, etc.) is used, and heat radiating fins molded by the extrusion molding method or the die casting molding method are arranged near the heat generating source. , A method of efficiently dissipating heat to the outside air is adopted.

Japanese Unexamined Patent Publication No. 2001-298131

However, the above-mentioned heat dissipation measures have a problem that it is necessary to increase the outer dimensions of the heat dissipation fins in order to secure the heat dissipation area in order to realize high heat dissipation performance. In addition, with the recent miniaturization and speeding up of semiconductor devices, the number of chips housed in the package has increased and the amount of heat generated has increased, so that there is a problem that sufficient heat dissipation characteristics cannot be realized. .. In particular, in a three-dimensional package in which a plurality of chips are stacked in the vertical direction in order to minimize the mounting area of the package, the semiconductor chip in the center does not have a portion in contact with the upper and lower heat radiating plates, so that self-heating is large. It had a big problem of becoming.

The present invention has been proposed in view of the above points, and an object of the present invention is to provide a semiconductor package having space saving and sufficient heat dissipation characteristics on one aspect.

The semiconductor package according to one aspect of the present invention includes at least one or more semiconductor chips, a sealing material for sealing the semiconductor chips, and a grounded wiring, and dissipates heat to at least a part of the grounded wiring. Semiconductor package with members

According to the embodiment of the present invention, on one aspect, it is possible to provide a semiconductor package having space saving properties and sufficient heat dissipation characteristics.

It is the schematic sectional drawing for demonstrating an example of the structure of the semiconductor package which concerns on this embodiment. It is the schematic sectional drawing for demonstrating another example of the structure of the semiconductor package which concerns on this Embodiment. It is the schematic sectional drawing for demonstrating another example of the structure of the semiconductor package which concerns on this Embodiment. It is the schematic sectional drawing for demonstrating another example of the structure of the semiconductor package which concerns on this Embodiment. It is the schematic sectional drawing for demonstrating another example of the structure of the semiconductor package which concerns on this Embodiment. It is the schematic sectional drawing for demonstrating another example of the structure of the semiconductor package which concerns on this Embodiment. It is the schematic sectional drawing for demonstrating another example of the structure of the semiconductor package which concerns on this Embodiment.

Hereinafter, the semiconductor package according to this embodiment will be described in detail.

The present inventors provide heat-dissipating members such as a heat-dissipating plate and heat-dissipating fins on a part or all of the grounding wiring used for applying the GND potential to the semiconductor chip in the semiconductor package, so that the heat-dissipating body is close to the heat-generating body. We have found that a sufficient heat dissipation effect can be obtained without forming a large heat dissipation member (space saving) (heat dissipation), and completed the present invention here. That is, the semiconductor package according to the present embodiment can be applied to all semiconductor devices packaged with at least one or more semiconductor chips and ground wiring.

Specific semiconductor devices include individual semiconductor elements such as diodes, transistors (including power transistors), rectifying elements, and thyristors; light emitting devices such as LEDs (light emitting diodes) and light emitting diodes, and light receiving light from photodiodes and phototransistors. Optical semiconductor devices such as devices and optical communication devices; microwave devices; various sensors; memories such as volatile memory and non-volatile memory, integrated circuits such as logic ICs and analog ICs; and the like.

In the present embodiment, the semiconductor substrate forming the semiconductor chip may include, for example, a semiconductor element such as silicon (Si) and germanium (Ge), or a compound semiconductor such as SiC, GaAs, InAs and InP. Further, the semiconductor substrate may have an SOI (silicon on insulator) structure. Further, the semiconductor substrate may include a BOX layer (burried oxide layer). Furthermore, the semiconductor substrate may also include a conductive region, for example, a well doped with impurities.

In the present embodiment, the semiconductor chip may be a semiconductor element including one or a plurality of individual elements. As individual elements, various microelectronic elements, for example, MOSFETs (metric-axis-semiconductor transistors) such as CMOS transistors (complementary metal-instrutor-semiconductor transistors), system LSIs, system LSIs (shelters) An image sensor such as an imaging transistor), a MOSFET (micro-electronic system), an active element, a passive element, and the like may be included. Further, the semiconductor chip may be a processor unit (processor unit), and specifically, for example, an MPU (micro processor unit) or a GPU (graphics processing unit). Further, the semiconductor chip may be a logic semiconductor chip or a memory semiconductor chip. Specific examples of the memory semiconductor chip include a volatile memory semiconductor chip such as a DRAM (dynamic random access memory) or SRAM (static random access memory), a PRAM (phase-change memory access memory), and a PRAM (phase-change memory access memory). It may be a non-volatile memory semiconductor chip such as magnetorestive random access memory), FeRAM (ferroductive random access memory) or RRAM (registered trademark) (resistive random access memory).

Further, the semiconductor package according to the present embodiment is not limited to the type of package, and is limited to a DIP system (Dual Inline Package), a SIP system (Single Inline Package), a ZIP system (Zigzag Inline Package), and a QFP system (Quad Flat Package). , SOJ (Small Outline J-read package) and other J-lead systems, PGA (Pin Grid Array), BGA (Ball Grid Array) and other grid array systems, SOP (Small Outline Package) and other SO systems, SOT systems It can be applied to packages such as TO system such as OutlineTransistor) and TransistorOutline.

Further, the semiconductor package according to the present embodiment can be applied to a semiconductor package in which only a single chip is packaged, and a plurality of integrated circuit chips can be housed in the same package by using MCP (Multi Chip Package) technology. It may be installed. When using the MCP technology, a flat MCP that integrates a plurality of chips in a plane using an interposer substrate, a laminated MCP that laminates a plurality of integrated circuit chips on an interposer substrate by die bonding, and a base integrated circuit chip. It can also be applied to CoC (Chip on Chip) or the like in which another integrated circuit chip is laminated face-to-face with a metal bump.

The semiconductor chip may be mounted on the package base substrate. Examples of the package-based substrate include a printed circuit board, a ceramics substrate, an interposer substrate, and the like.

As the heat radiating member used in the semiconductor package according to the present embodiment, all conventionally known forms such as a heat radiating plate and heat radiating fins can be used.

Further, in the present embodiment, the heat radiating member also serves as a part or all of the ground wiring used for applying the GND potential to the semiconductor chip. Therefore, for example, when a part of the lead pin (when there is a lead) of the semiconductor package is used as a ground (ground) terminal and a heat dissipation member is provided in the path from the semiconductor chip to the ground terminal, the ground wiring of other wiring such as a signal line Etch the heat dissipation member so that it does not get in the way. As a result, it is possible to secure the same degree of freedom in wiring as in the case where the heat radiating member is not provided.

Considering a MOS transistor and a CMOS circuit as an example, heat generation becomes particularly large when a current flows through a channel portion of a transistor having a high resistance. Therefore, it can be said that the heat dissipation effect of the present invention in which the heat dissipation member can be arranged on a part or all of the ground wire connected to the source electrode of the N channel MOS is particularly effective.

As the material of the heat radiating member, it is preferable to use a material having high thermal conductivity, and carbon-based materials other than metal are suitable. For example, graphene (about 5000 Wm ^-1 K ^-1 ) and carbon nanotubes (about 3000 Wm) are suitable. ^-1 K ^-1 ), graphite (approximately 2000 Wm ^-1 K ^-1 ), etc. are excellent in electrical conductivity and are suitable as the heat dissipation member of the present invention, and graphene having the highest thermal conductivity is used. It is preferable to do so.

(Example)
Next, the present invention will be described in more detail with reference to specific examples, but the present invention is not limited to these specific examples.

1 to 7 are schematic views for explaining an example of the configuration of the semiconductor package according to the present embodiment. In the figure, for the sake of explanation, some components are omitted and shown schematically.

In this embodiment, a CMOS transistor is taken as an example of the semiconductor chip, but the present invention is not limited in this respect.

The semiconductor package 100a shown in FIG. 1 is an embodiment in which a CMOS transistor chip 102 and a CMOS transistor chip 104 are laminated on a Face To Face. In the example shown in FIG. 1, a heat radiating plate 108 is installed on a part of the ground wiring 106, for example, a side surface of the semiconductor package 100a to dissipate heat on four sides.

The semiconductor package 100b shown in FIG. 2 is an embodiment in which a CMOS transistor chip 104 and a CMOS transistor chip 102 are laminated on a Face To Back. In the example shown in FIG. 2, a heat radiating plate 108 is installed on a part of the ground wiring 106, for example, a side surface of the semiconductor package 100b to dissipate heat on four sides.

The semiconductor package 100c shown in FIG. 3 is an embodiment in which a CMOS transistor chip 104 and a CMOS transistor chip 102 are laminated on a Back To Back. In the example shown in FIG. 3, a heat radiating plate 108 is installed on a part of the ground wiring 106, for example, the side surface of the semiconductor package 100c to dissipate heat on four sides.

The semiconductor package 100d shown in FIG. 4 is an embodiment in which a CMOS transistor chip 104 and a CMOS transistor chip 102 are bonded to a Back To Back. In the example shown in FIG. 4, a heat radiating plate 108 is installed on a part of the ground wiring 106, for example, the side surface of the semiconductor package 100d to dissipate heat on four sides.

The semiconductor package 100e shown in FIG. 5 is an embodiment in which three chips of a CMOS transistor chip 102, a CMOS transistor chip 104, and a CMOS transistor chip 110 are mounted in three layers. In the example shown in FIG. 5, a heat radiating plate 108 is installed on a part of the ground wiring 106, for example, the bottom surface and the surface of the semiconductor package 100e to dissipate heat on two surfaces.

The semiconductor package 100f shown in FIG. 6 is an embodiment in which a CMOS transistor chip 102 and a CMOS transistor chip 104 are laminated on a Face To Face. In the example shown in FIG. 6, heat radiating plates 108 are installed on a part of the ground wiring 106, for example, the side surface and the back surface of the semiconductor package 100f to dissipate heat on five surfaces.

The semiconductor package 100g shown in FIG. 7 is an embodiment in which three chips of a CMOS transistor chip 102, a CMOS transistor chip 104, and a CMOS transistor chip 110 are mounted in three layers. In the example shown in FIG. 7, heat radiating plates 108 are installed on a part of the ground wiring 106, for example, the side surface, the front surface, and the back surface of the semiconductor package 100 g to dissipate heat on six surfaces.

As shown in the specific examples in FIGS. 1 to 7, the semiconductor package according to the present embodiment is provided with a heat radiating member at least a part of the ground wiring. Therefore, even in the MCP technology in which heat generation per unit volume increases as the number of chips housed in the package increases, it is possible to arrange heat radiating members that obtain sufficient heat radiating characteristics while ensuring space saving.

100 Semiconductor Package 102 CMOS Transistor Chip 104 CMOS Transistor Chip 106 Ground Wiring 108 Heat Dissipating Plate

Claims (2)

With at least one or more semiconductor chips
A sealing material for sealing the semiconductor chip and
Grounding wiring and
Have,
A heat radiating member is provided at least a part of the ground wiring.
Semiconductor package. The material of the heat radiating member is carbon.
The semiconductor package according to claim 1.

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