JP2020162060A - Compensation circuit, gate control circuit, and switching circuit - Google Patents

Abstract

To achieve a compensation circuit for use in a gate control circuit for suppressing imbalance of a burden voltage between semiconductor elements with a simple configuration.SOLUTION: A compensation circuit (10) conducts a second switch (Sw2) capable of bypassing a second transient current for discharging gate capacitance when a second semiconductor element (QB) is turned off when a first current detector (CdA) detects a first transient current for discharging gate capacitance of a first semiconductor element (QA).SELECTED DRAWING: Figure 1

Description

The present invention relates to a compensation circuit, a gate control circuit using the compensation circuit, and a switching circuit.

Switching circuits using semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) are known. The output voltage of the switching circuit is basically limited by the withstand voltage of the semiconductor elements constituting the main circuit.

A switching circuit is also known in which a plurality of semiconductor elements are connected in series and on / off control of these semiconductor elements is performed at the same time in order to cope with a higher output voltage. In such a switching circuit, a gate control circuit including a gate driver provided for each semiconductor element is used, and the gate signal to each semiconductor element is configured to be on / off controlled at the same time.

However, if the turn-off timing differs between the semiconductor elements, the power supply voltage cannot be evenly distributed between the semiconductor elements after the turn-off, and the specific semiconductor element bears an excessive voltage. Then, there is a fear that voltage destruction may occur in a specific semiconductor element. Therefore, it has been studied to provide a compensation circuit in the gate control circuit so as not to cause such an imbalance of the burden voltage.

Japanese Unexamined Patent Publication No. 2012-253488

Such a compensation circuit monitors the burden voltage (collector-emitter voltage in the case of an IGBT) for each semiconductor element, and detects the generation of an excessive burden voltage or the imbalance of the burden voltage between semiconductor elements. Therefore, the gate signal to each semiconductor element is adjusted.

However, in such a conventional compensation circuit, the circuit configuration is complicated because it is necessary to monitor the burden voltage for each semiconductor element and compensate or control the gate signal accordingly.

One aspect of the present invention is to realize a compensation circuit used for a gate control circuit capable of suppressing imbalance of a burden voltage between semiconductor elements and effectively suppressing destruction of semiconductor elements with a simple configuration. ..

In order to solve the above problems, the compensation circuit according to one aspect of the present invention is a compensation circuit for compensating for a gate signal that controls a first semiconductor element and a second semiconductor element connected in series. The gate signal that controls the first semiconductor element has a first transient current that discharges the gate capacitance when the first semiconductor element turns off, and the gate is attached to the first semiconductor element. The second current detector connected to a first current detector provided on a first line for applying a signal and a second line for applying the gate signal to the second semiconductor element. The first current detector comprises a second switch capable of bypassing a second transient current that discharges the gate capacitance when the semiconductor device turns off, when the first current detector detects the first transient current. , The second switch is made conductive.

According to the compensation circuit of one aspect of the present invention, it is possible to realize a compensation circuit used for a gate control circuit capable of suppressing imbalance of the burden voltage between semiconductor elements and effectively suppressing destruction of the semiconductor element with a simple configuration. ..

It is a figure which shows the compensation circuit which concerns on Embodiment 1 of this invention, the gate control circuit and the switching circuit using it. It is a figure which shows the operation of the compensation circuit which concerns on Embodiment 1 and 2 of this invention, the gate control circuit and the switching circuit using it. It is a figure which shows the compensation circuit which concerns on Embodiment 2 of this invention, the gate control circuit and the switching circuit using it.

[Embodiment 1]
An embodiment of the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a diagram showing a compensation circuit 10 according to the first embodiment, a switching circuit 101 using the compensation circuit 10, and a gate control circuit 100.

(Configuration of switching circuit)
The switching circuit 101 according to the first embodiment includes a semiconductor element QA (first semiconductor element), a semiconductor element QB (second semiconductor element), and a gate control circuit 100.

The semiconductor element QA and the semiconductor element QB are voltage-controlled semiconductor switching elements (transistors), and specifically, can be IGBTs.

The semiconductor element QA and the semiconductor element QB are connected in series. When these are IGBTs, the emitter of the semiconductor element QA and the collector of the semiconductor element QB are connected.

A gate control signal GCS for instructing on / off control of the output of the switching circuit 101 is input to the gate control circuit 100.

From the gate control circuit 100, the compensated gate signal is input to the semiconductor elements QA and QB, respectively, and the on / off of the respective semiconductor elements QA and QB is controlled.

The switching circuit 101 is a circuit that controls the output with respect to the load by using a power supply and a load (not shown) connected in series to the semiconductor element QA and the semiconductor element QB.

(Structure of gate control circuit)
The gate control circuit 100 according to the first embodiment includes a compensation circuit 10, a gate driver 20 (first gate driver), a gate driver 30 (second gate driver), a gate resistor RgA (first gate resistor), and a gate resistor. It has RgB (second gate resistor).

A common gate control signal GCS is input to the gate driver 20 and the gate driver 30.

The gate driver 20 outputs a gate signal to the gate signal line 21 (first line). A gate resistor RgA is provided on the gate signal line 21, and the gate signal is input to the gate of the semiconductor element QA through the compensation circuit 10.

The gate driver 30 outputs a gate signal to the gate signal line 31 (second line). A gate resistor RgB is provided on the gate signal line 31, and the gate signal is input to the gate of the semiconductor element QB through the compensation circuit 10.

The gate driver 20 and the gate driver 30 are known gate drivers also disclosed in Patent Document 1.

The gate driver 20 executes the following operations.

When the gate control signal GCS is an on signal, the transistor TrA1 is turned on, the transistor TrA2 is turned off, and a voltage substantially equal to the high potential voltage V1 for turning on the semiconductor element QA is output to the gate signal line 21. When the gate control signal GCS is an off signal, the transistor TrA1 is turned off, the transistor TrA2 is turned on, and a voltage substantially equal to the low potential voltage V2 for turning off the semiconductor element QA is output to the gate signal line 21. The gate signal to the semiconductor device QA may include a signal of such a voltage.

Further, the gate driver 20 passes a transient current that charges the gate capacitance (flows toward the gate of the semiconductor element QA) when the semiconductor element QA turns on. Further, the gate driver 20 passes a transient current that discharges the gate capacitance (flows in the direction opposite to the charging current) when the semiconductor element QA turns off. The gate signal to the semiconductor device QA may include a signal of such a current.

The gate driver 30 executes the following operations.

When the gate control signal GCS is an on signal, the transistor TrB1 is turned on, the transistor TrB2 is turned off, and a voltage substantially equal to the high potential voltage V3 for turning on the semiconductor element QB is output to the gate signal line 31. When the gate control signal GCS is an off signal, the transistor TrB1 is turned off, the transistor TrB2 is turned on, and a voltage substantially equal to the low potential voltage V4 for turning off the semiconductor element QB is output to the gate signal line 31. The gate signal to the semiconductor device QB may include a signal of such a voltage.

Further, the gate driver 30 passes a transient current that charges the gate capacitance (flows toward the gate of the semiconductor element QB) when the semiconductor element QB turns on. Further, the gate driver 30 passes a transient current that discharges the gate capacitance (flows in the direction opposite to the charging current) when the semiconductor element QB turns off. The gate signal to the semiconductor device QB may include a signal of such a current.

Normally, when the high potential voltages V1 and V3 are equal to the voltage Vc, the low potential voltages V2 and V4 are configured to be equal to the voltage −Vc, but the present invention is not limited to this.

(Compensation circuit configuration)
The compensation circuit 10 according to the first embodiment includes a current detector CdA (first current detector), a current detector CdB (second current detector), a switch SwA (first switch), and a switch SwB (second switch). Switch), a bypass resistor RbA (first bypass resistor), and a bypass resistor RbB (second bypass resistor).

The current detector CdA is provided on the gate signal line 21, and the current detector Cdb is provided on the gate signal line 31.

A bypass resistor RbA is connected so as to branch off from the gate signal line 21 between the current detector CdA and the semiconductor element QA, and a switch SwA is connected in series with the bypass resistor RbA. Further ahead of the switch SwA is connected to a part of the gate driver 20 so that a low potential voltage V2 is applied. The line from the branch with the gate signal line 21 to the gate driver 20 via the bypass resistor RbA and the switch SwA is referred to as a bypass line 22.

A bypass resistor RbB is connected so as to branch from the gate signal line 31 between the current detector CdB and the semiconductor element QB, and a switch SwB is connected in series with the bypass resistor RbB. Further ahead of the switch SwB is connected to a part of the gate driver 30 so that a low potential voltage V4 is applied. The line from the branch with the gate signal line 31 to the gate driver 30 via the bypass resistor RbB and the switch SwB is referred to as a bypass line 32.

The current detector CdA turns on the switch SwB when a current of a predetermined magnitude or more (a negative gate current IgA of a predetermined magnitude or more) flows through the gate signal line 21 in the direction of the current for discharging the gate capacitance. , An element that controls the switch SwB to be turned off at other times.

The current detector CdB turns on the switch SwA when a current of a predetermined magnitude or more (a negative gate current IgB of a predetermined magnitude or more) flows through the gate signal line 31 in the direction of the current for discharging the gate capacitance. , An element that controls the switch SwA to be turned off at other times.

(motion)
With reference to FIG. 2, the operations of the compensation circuit 10, the gate control circuit 100, and the switching circuit 101 will be described below. FIG. 2 is a time chart showing the signal status of each point in the circuit or the operation of each element with the passage of time.

FIG. 2 shows the operation when the gate control signal GCS transitions from on to off and the output of the switching circuit 101 turns off.

When the gate control signal GCS transitions from on to off, the transistor TrA2 of the gate driver 20 and the transistor TrB2 of the gate driver 30 turn on. However, here, the case where the characteristics of the gate driver 20 and the gate driver 30 do not match and the turn-on timings of the transistor TrA2 and the transistor TrB2 are different is shown in FIG.

When the transistor TrA2 is turned on first, a transient current (first transient current) flows through the gate signal line 21 as the gate current IgA due to the discharge of the gate capacitance of the semiconductor element QA. As shown in FIG. 1, since the gate current IgA takes a positive direction toward the gate of the semiconductor element QA, the transient current is a negative current.

Then, when the current detector CdA detects a predetermined current, the switch SwB is turned on.

As a result, the gate of the semiconductor element QB is connected to the low potential voltage V4 through the bypass resistor RbB via the bypass wire 32. Then, although the transistor TrB2 has not been turned on yet, the discharge of the gate capacitance of the semiconductor element QB is executed as the compensation current IcB via the bypass line 32.

As a result, the discharge of the gate capacitance of the semiconductor element QA and the discharge of the gate capacitance of the semiconductor element QB have very close start timings. Therefore, as shown in the figure, the timing of changes in the gate voltage VgA of the semiconductor element QA and the gate voltage VgB of the semiconductor element QB are also very close.

In this way, the semiconductor element QA and the semiconductor element QB turn off almost at the same time, and the imbalance of the burden voltage (collector-emitter voltage in the IGBT) caused by the turn-off timing shift is suppressed.

When the magnitude of the transient current due to the discharge of the gate capacitance of the semiconductor element QA passing through the current detector CdA falls below a predetermined value, the current detector CdA turns off the switch SwB.

(effect)
As described above, according to the first embodiment, even if the characteristics of the gate driver 20 and the gate driver 30 do not match and the turn-on timings of the transistor TrA2 and the transistor TrB2 are different, the semiconductor element QA and the semiconductor element QB You can turn off at almost the same time. This is due to the action that the discharge of the gate capacitance of the semiconductor element QB starts immediately through the bypass line 32 on the side of the delayed gate driver 30.

Therefore, the semiconductor element QA and the semiconductor element QB can be turned off almost at the same time regardless of the degree of turn-on timing deviation between the transistor TrA2 and the transistor TrB2.

As a result, if the conventional compensation circuit is not provided, the power supply voltage cannot be evenly distributed between the semiconductor elements after the turn-off, and the specific semiconductor element bears an excessive voltage, resulting in element destruction. The problems that occur are effectively suppressed.

The current detector CdA turns on the switch SwB only when a current of a predetermined magnitude or more in the direction of the current for discharging the gate capacitance flows through the gate signal line 21. Such a current flows only when the semiconductor element QA turns off, and the switch SwB does not turn on in other cases. Therefore, the provision of the bypass wire 32 does not affect the operation of the semiconductor element QB except when the semiconductor element QA is turned off.

Further, in the compensation circuit 10, it is not necessary to detect the burden voltage of the semiconductor element (collector-emitter voltage in the IGBT) for its operation. Therefore, the problem of imbalance can be suppressed with a simple circuit configuration as shown in FIG.

Moreover, since the low potential voltage V4 used by the gate driver 30 is used to discharge the gate capacitance from the bypass line 32 by the compensation current IcB, a separate power supply is not required.

In the compensation circuit 10, a bypass resistor RbB is provided on the bypass line 32. By adjusting the magnitude of the bypass resistor RbB, the magnitude or duration of the transient current that discharges the gate capacitance through the bypass wire 32 can be adjusted. For example, by adjusting the ratio of the value to the gate resistance RgA, it becomes possible to adjust the relative value with respect to the transient current that discharges the gate capacitance of the semiconductor element QA, and the adjustment that suppresses the imbalance more appropriately can be performed. It will be possible.

[Embodiment 2]
Other embodiments of the present invention are described below. For convenience of explanation, the same reference numerals will be added to the members having the same functions as the members described in the above embodiment, and the description will not be repeated. The same applies to the following embodiments.

FIG. 3 is a diagram showing a compensation circuit 11 according to the second embodiment, a switching circuit 111 using the compensation circuit 11, and a gate control circuit 110.

The switching circuit 111 and the gate control circuit 110 according to the second embodiment have the same configuration as the first embodiment except that the configuration of the compensation circuit is different.

The compensation circuit 11 according to the second embodiment will be described below with reference to FIG. In the compensation circuit 11, the current detector CdA, the current detector CdB, the switch SwA, and the switch SwB of the compensation circuit 10 according to the first embodiment are more specifically exemplified.

The compensation circuit 11 includes a photocoupler PcA (first photocoupler), a photocoupler PcB (second photocoupler), a diversion resistor RdA (first diversion resistor), a diversion resistor RdB (second diversion resistor), and a bypass. It has a resistor RbA (first bypass resistor) and a bypass resistor RbB (second bypass resistor).

The light emitting diode DA of the photocoupler PcA and the flow dividing resistor RdA are connected in series, and these are connected in parallel to the gate resistor RgA. The light emitting diode DA is arranged so that a part of the transient current when discharging the gate capacitance of the semiconductor element QA can be energized. That is, the light emitting diode DA does not allow a current (positive gate current IgA) in a direction different from the transient current when discharging the gate capacitance to pass through.

The first embodiment includes a light emitting diode DA and a current dividing resistor RdA connected in parallel with the gate resistor RgA, which are configured to be able to split the gate current IgA when the gate current IgA of the gate signal line 21 is negative. Corresponds to the current detector CdA (first current detector) of.

The light emitting diode DB of the photocoupler PcB and the diversion resistor RdB are connected in series, and these are connected in parallel to the gate resistor RgB. The light emitting diode DB is arranged so that a part of the transient current when discharging the gate capacitance of the semiconductor element QB can be energized. That is, the light emitting diode DB does not allow a current (positive gate current IgB) in a direction different from the transient current when discharging the gate capacitance to pass through.

It is configured so that the gate current IgB can be diverted when the gate current IgB of the gate signal line 31 is negative. The light emitting diode DB and the current dividing resistor RdB connected in parallel with the gate resistor RgB correspond to the current detector CdB (second current detector) of the first embodiment.

Further, in the second embodiment, the switch SwA and the switch SwB are specifically phototransistors of the photocoupler PcA and the photocoupler PcB, respectively.

The light emitting diode DA emits light when a current of a predetermined magnitude or more (negative gate current IgA of a predetermined magnitude or more) flows through the gate signal line 21 in the direction of the current for discharging the gate capacitance, and turns on the switch SwB. And. At other times, the light emitting diode DA cannot emit light, and the switch SwB is off.

The light emitting diode DB emits light when a current of a predetermined magnitude or more (negative gate current IgB of a predetermined magnitude or more) in the direction of the current for discharging the gate capacitance flows through the gate signal line 31, and turns on the switch SwA. And. At other times, the light emitting diode DB cannot emit light, and the switch SwA is off.

With the above configuration, in the second embodiment, the current detector CdA, the current detector CdB, the switch SwA, and the switch SwB of the first embodiment are made more specific, but the operation is the same. The operations of the compensation circuit 11, the gate control circuit 110, and the switching circuit 111 according to the second embodiment are also as shown in FIG.

Also in the second embodiment, the same effect as that of the first embodiment is achieved.

In the compensation circuit 11, a flow dividing resistor RdA and a light emitting diode DA connected in parallel to the gate resistor RgA are arranged. Therefore, the threshold value of the magnitude of the gate current IgA that turns on the switch SwB can be easily adjusted by the resistance value of the diversion resistor RdA.

Further, in the compensation circuit 11, the light emitting diode DA blocks the passage of a current (positive gate current IgA) in the direction opposite to the direction of the current that discharges the gate capacitance, and a positive gate current IgA is generated. Does not affect operation. Therefore, the function of the current detector CdA (first current detector) that turns on the switch SwB only when a current of a predetermined magnitude or more in the direction of the current that discharges the gate capacitance flows through the gate signal line 21. , It is concretely realized with an extremely simple configuration.

Moreover, in the second embodiment, in order to exert the function of the current detector CdA (first current detector) and the function of the switch SwB, a separate power supply for that purpose is not required. That is, the compensation circuit 11 is a passive circuit that does not require a separate power supply in order to exert the effect of suppressing the imbalance of the burden voltage when the semiconductor element QA and the semiconductor element QB are off. Therefore, the problem of imbalance can be suppressed with an extremely simple circuit configuration as shown in FIG.

In the above, the case where the semiconductor element is an IGBT has been described in each embodiment. However, the application of the present invention is not limited to IGBTs, and similarly, it is applied to voltage-controlled transistors such as MOS-FETs (Metal Oxide Semiconductor field-effect transistors) and other FETs (field-effect transistors). It is applicable.

[Summary]
The compensation circuit according to the first aspect of the present invention is a compensation circuit for compensating for a gate signal that controls a first semiconductor element and a second semiconductor element connected in series, and the first semiconductor element is used. The gate signal to be controlled has a first transient current that discharges the gate capacitance when the first semiconductor element is turned off, and is a first for applying the gate signal to the first semiconductor element. The said, which is connected to a first current detector provided on a line (gate signal line 21) and a second line (gate signal line 31) for applying the gate signal to the second semiconductor element. The first current detector detects the first transient current, comprising a second switch capable of bypassing a second transient current that discharges the gate capacitance when the second semiconductor device turns off. When this is done, the second switch is made conductive.

According to the above configuration, it is possible to realize a compensation circuit used for a gate control circuit, which can suppress the imbalance of the burden voltage between the semiconductor elements and effectively suppress the destruction of the semiconductor elements with a simple configuration.

In the first aspect, the compensation circuit according to the second aspect of the present invention is connected to the second current detector provided on the second line and the first line, and bypasses the first transient current. The second current detector may further include a possible first switch, and may have a configuration in which the first switch is made conductive when the second transient current is detected.

According to the above configuration, even if the turn-off of either the first semiconductor element or the gate signal for controlling the second semiconductor element is delayed, the imbalance of the burden voltage between the semiconductor elements is suppressed. , It is possible to realize a compensation circuit used for a gate control circuit that can effectively suppress the destruction of semiconductor elements.

The compensation circuit according to the third aspect of the present invention has, in the second aspect, the first bypass resistor provided in series with the first switch and the second bypass resistor provided in series with the second switch. And may be provided.

According to the above configuration, by adjusting the magnitude of these bypass resistors, the magnitude or duration of the transient current that discharges the gate capacitance through the bypass wire can be adjusted, and more appropriately between the semiconductor elements. It becomes possible to suppress the imbalance of the burden voltage of.

In the compensation circuit according to the fourth aspect of the present invention, in the second or third aspect, the first current detector is connected in parallel with the first gate resistor provided in the first line, and the first current detector is connected in parallel. The second light emitting diode has a first light emitting diode capable of energizing a part of a transient current, the first light emitting diode and the second switch form a first photocoupler, and the second current detector is The second light emitting diode and the second light emitting diode, which are connected in parallel with the second gate resistor provided on the second line and have a second light emitting diode capable of energizing a part of the second transient current. The first switch may have features that make up the second photocoupler.

According to the above configuration, it is possible to suppress the imbalance of the burden voltage between the semiconductor elements and effectively suppress the destruction of the semiconductor elements with an extremely simple configuration that does not require a separate power supply for compensating the gate signal. , A compensation circuit used for a gate control circuit can be realized.

In the compensation circuit according to the fifth aspect of the present invention, in the fourth aspect, the first current detector has a first current diversion resistor connected in series with the first light emitting diode, and the second current detector. The current detector may have a configuration having a second diversion resistor connected in series with the second light emitting diode.

According to the above configuration, by adjusting the magnitude of these diversion resistors, the conditions for conducting each switch can be appropriately set.

The gate control circuit according to the sixth aspect of the present invention is connected to the compensation circuit according to any one of the first to fifth aspects, the first gate driver connected to the first line, and the second line. It is equipped with a second gate driver.

According to the above configuration, it is possible to realize a gate control circuit capable of suppressing the imbalance of the burden voltage between the semiconductor elements and effectively suppressing the destruction of the semiconductor elements with a simple configuration.

The switching circuit according to the seventh aspect of the invention includes the gate control circuit according to the sixth aspect, the first semiconductor element, and the second semiconductor element.

According to the above configuration, it is possible to realize a switching circuit capable of suppressing the imbalance of the burden voltage between the semiconductor elements and effectively suppressing the destruction of the semiconductor elements with a simple configuration. Such a switching circuit can be suitably applied to a semiconductor power conversion device.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the claims, and the technique of the present invention also relates to an embodiment obtained by appropriately combining the disclosed technical means. Included in the target range.

10, 11 Compensation circuit 20, 30 Gate driver 21, 31 Gate signal line 22, 32 Bypass line RbA, RbB Bypass resistor CdA, CdB Current detector SwA, SwB switch PcA, PcB Optocoupler RdA, RdB diversion resistor RgA, RgB gate Resistance QA, QB Semiconductor element 100, 110 Gate control circuit 101, 111 Switching circuit

Claims (7)

It is a compensation circuit for compensating the gate signal that controls the first semiconductor element and the second semiconductor element connected in series.
The gate signal that controls the first semiconductor element has a first transient current that discharges the gate capacitance when the first semiconductor element turns off.
A first current detector provided on the first line for applying the gate signal to the first semiconductor element, and
A second transient current connected to a second line for applying the gate signal to the second semiconductor element, which discharges the gate capacitance when the second semiconductor element turns off, can be bypassed. With 2 switches,
The first current detector is a compensation circuit, characterized in that, when the first transient current is detected, the second switch is made conductive. A second current detector provided on the second line and
A first switch connected to the first line and capable of bypassing the first transient current is further provided.
The compensation circuit according to claim 1, wherein the second current detector conducts the first switch when the second transient current is detected. A first bypass resistor provided in series with the first switch,
The compensation circuit according to claim 2, further comprising a second bypass resistor provided in series with the second switch. The first current detector has a first light emitting diode that is connected in parallel with a first gate resistor provided on the first line and is capable of energizing a portion of the first transient current.
The first light emitting diode and the second switch form a first photocoupler.
The second current detector has a second light emitting diode that is connected in parallel with a second gate resistor provided on the second line and is capable of energizing a portion of the second transient current.
The compensation circuit according to claim 2 or 3, wherein the second light emitting diode and the first switch form a second photocoupler. The first current detector has a first diversion resistor connected in series with the first light emitting diode.
The compensation circuit according to claim 4, wherein the second current detector has a second current diversion resistor connected in series with the second light emitting diode. The compensation circuit according to any one of claims 1 to 5.
With the first gate driver connected to the first line,
A gate control circuit including a second gate driver connected to the second line. The gate control circuit according to claim 6 and
With the first semiconductor element
A switching circuit including the second semiconductor element.

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