JP2020150483A - D / A conversion device, audio equipment, electronic musical instruments and D / A conversion method - Google Patents

Abstract

An object of the present invention is to effectively utilize an output signal obtained by delta-sigma conversion and reduce noise without reducing the noise shaping effect. SOLUTION: A ΔΣ modulator 15A that performs ΔΣ calculation on sequentially input data, an output section 15C that generates a PWM (pulse width modulation) signal according to the calculation result of the ΔΣ modulator 15A, and a ΔΣ modulator 15A. The shift register unit 15B detects that the operation result is a series of specific values, and if the operation result of the ΔΣ operation circuit in the shift register unit 15B is a series of specific values, the output unit 15C A control circuit (92F to 92H, 93 to 96) for generating a PWM signal with a period of an integral multiple corresponding to the continuous period. [Selection diagram] Fig. 1

Description

The present invention relates to a D / A conversion device, an audio device, an electronic musical instrument, and a D / A conversion method.

For example, in the D / A conversion unit provided in the output stage of an electronic musical instrument, the pulse width of the signal output obtained by ΔΣ conversion of the oversampled digital value audio data is requantized by the analog integrator in the subsequent stage. It is removed and converted into a voltage signal for D / A conversion with a low-pass filter. The accuracy of this voltage signal in the time axis direction is directly linked to the conversion accuracy, so that high accuracy is required.

The D / A conversion unit generally has a configuration clock generation unit using a PLL (phase-locked loop) circuit and a crystal oscillator, and the jitter component of these PLL circuits and the crystal oscillator causes noise for the reason described above. It becomes a factor that deteriorates the sound quality.

It is known that jitter has many components that fluctuate at a constant rate with respect to the period of oscillation frequency. The time of the maximum value of the jitter component does not change due to the nature of the digital circuit even if the transmission frequency is divided. Therefore, if the frequency division ratio is increased and the speed is lowered, the jitter ratio of the clock becomes smaller and the noise of the signal is reduced. This means that by making the pulse a long period, the proportion of the constant jitter component becomes small, and the noise component is relatively reduced.

However, on the other hand, when converting digital value audio data into ΔΣ, it is necessary to increase the operating frequency in order to further enhance the noise shaping effect.

From such contradictory requirements, it is a difficult factor to determine how many times the operating frequency when performing delta-sigma conversion is set to the sampling frequency Fs of digital audio data.

In a DA conversion device using this type of oversampling and noise shaping, a technique for obtaining a highly accurate analog output that is less affected by noise and jitter has been proposed. (For example, Patent Document 1)

Japanese Unexamined Patent Publication No. 05-037382

Including the techniques described in the patent documents, there has been a search for a technique capable of reliably reducing noise in an analog signal obtained during D / A conversion.

The present invention has been made in view of the above circumstances, and an object of the present invention is to effectively utilize the output signal obtained by ΔΣ conversion and reduce noise without reducing the effect of noise shaping. It is an object of the present invention to provide a possible D / A conversion device, audio equipment, electronic musical instrument, and D / A conversion method.

One aspect of the present invention includes a ΔΣ calculation circuit that executes a ΔΣ calculation on sequentially input data, a detection circuit that detects whether or not a specific value is continuous based on the calculation result of the ΔΣ calculation circuit, and the above. When the detection circuit detects that the specific values are not continuous, a PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and the detection circuit detects that the specific values are continuous. A PWM signal generation circuit that generates a PWM signal at a cycle longer than that of the first PWM cycle.

According to the present invention, it is possible to effectively utilize the output signal obtained by the ΔΣ conversion and reduce noise without reducing the effect of noise shaping.

The block diagram which shows the structure of the whole electronic musical instrument using the D / A conversion apparatus which concerns on one Embodiment of this invention. A timing chart showing a waveform example of a clock and a PWM signal according to the same embodiment. A timing chart showing a waveform of a PWM signal output by the output unit 15C according to the same embodiment. The block diagram which shows the functional structure of the arithmetic circuit which the ΔΣ modulator which concerns on this embodiment has. The figure which shows the noise shaping frequency characteristic which graphed e (noise) which concerns on the same embodiment. The block diagram which shows the structure realized by the concrete hardware circuit of the ΔΣ modulator which concerns on the same embodiment. The figure which shows the content of the arithmetic processing by the ΔΣ modulator which concerns on this embodiment in association with the count value of an m counter. The block diagram which shows the specific circuit structure of the shift register part which concerns on the same embodiment. The block diagram which shows the concrete structure of the hardware circuit of the output part and the D flip-flop which concerns on this embodiment.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an entire electronic musical instrument using the D / A conversion device (DAC) according to the present embodiment. In the figure, for example, an operation signal in the operation unit 11 composed of a keyboard or the like is input to the CPU 12 of the LSI chip CH1. The CPU 12 includes a ROM 13 that stores an operation program for an electronic musical instrument, standard data, and the like in the LSI chip CH1 via a bus B1, a sound source unit 14 that generates digital audio data corresponding to the operated contents, and a DAC 15. Be connected.

Further, a crystal oscillator (Xtal) 16 and a PLL 17 are provided in the LSI chip CH1. The crystal oscillator 16 applies a constant voltage to the crystal oscillator CU1 externally attached to the LSI chip CH1 to oscillate the clock clk-xtal, which is the reference first clock, and each circuit in the LSI chip CH1. And supply to PLL17.

The PLL 17 receives the clock clk-xtal, oscillates the clock clk-pll, which is a second clock with a higher frequency, and supplies the clock clk-pll to each circuit in the LSI chip CH1.

The CPU 12 transmits parameters such as pitch and volume to the sound source unit 14 according to the operation signal received from the operation unit 11. Upon receiving this, the sound source unit 14 outputs the corresponding digital audio data to the DAC 15.

The DAC 15 has a ΔΣ modulator 15A, a shift register unit 15B, an output unit 15C, and a D flip-flop (DF / F) 15D.

The ΔΣ modulator 15A receives the digital audio data input from the sound source unit 14, performs ΔΣ modulation based on the clock clk-pll from the PLL 17, and outputs the quantization data as the calculation result to the shift register unit 15B.

The shift register unit 15B delays the quantization data from the ΔΣ modulator 15A by 8 clocks of the clock clk-pll by the internal shift register and outputs the same data to the output unit 15C, for example, duty. It is determined whether or not the data having a ratio of 50 [%] is continuous, and the determination result is combined and sent to the output unit 15C.

The output unit 15C generates a balanced PWM signal according to the input quantization data and the determination result, and outputs the balanced PWM signal to the D flip-flop 15D.

The D flip-flop 15D outputs the balanced PWM signal output by the output unit 15C to the low-pass filter 18 outside the LSI chip CH1 after waveform shaping based on the clock clk-pll from the PLL 17.

The low-pass filter 18 uses, for example, a series RC circuit as shown in the figure, converts a given PWM signal into an analog audio signal, and outputs the signal to the amplifier (amp) 19. As the amplifier 19, it is desirable to use a differential amplifier as described later. When a differential amplifier is used as the amplifier 19, actually two series RC circuits are provided corresponding to the balanced signal.

The speaker 20 is loudened and emitted by the analog audio signal appropriately amplified by the amplifier 19 at the amplification factor.

FIG. 2 is a diagram illustrating the relationship between the clock clk-pll oscillated by the PLL 17 (FIG. 2 (A)) and the PWM signal (FIGS. 2 (B) to 2 (D)) created by the output unit 15C. is there.

It is assumed that the output unit 15C operates so as to output a PWM signal, with eight clocks of the clock clk-pll as one cycle of calculation.

The PWM signals generated by the output unit 15C are illustrated in FIGS. 2 (B) to 2 (D).

FIG. 2B shows a case where the “H” section of the PWM signal has a time width that is one full of eight cycles of the clock clk-pll.

Similarly, FIGS. 2C and 2D show a case where the “H” section of the PWM signal has a time width of 6 cycles and 4 cycles of the clock clk-pll.

As shown in these, the minimum change width of the PWM signal is symmetrical in time with one cycle of the clock clk-pll as a unit for both the rising timing and the falling timing. A signal level of 5 levels can be expressed by 8 clocks in one cycle.

When the duty ratio of the PWM signal is 50 [%], the content expressed as an audio signal is "0", that is, it indicates silence.

For example, if the ΔΣ modulator 15A is operating at an oversampling frequency 32 times the sampling frequency Fs of the sound source, the output unit 15C that PWMs the output of the ΔΣ modulator 15A is “1/32” of the sampling frequency Fs. The period of the output PWM signal can be extended in a range larger than that.

FIG. 3 is a timing chart showing the waveforms of the clock clk-pll and the PWM signal output by the output unit 15C.

As shown in FIG. 3 (A), it is assumed that the ΔΣ modulator 15A operates as one basic calculation cycle as shown in FIG. 3 (B) for eight cycles of the clock clk-pll output by the PLL 17.

Further, when the digital audio data input from the sound source unit 14 to the DAC 15 has a content "0" indicating silence continuously in time, it is based on a match determination signal from the shift register unit 15B that detects it. The output unit 15C has 16 cycles of the clock clk-pll, which is twice the basic cycle as shown in FIG. 3 (C), and the clock clk-, which is four times the basic cycle as shown in FIG. 3 (D). The PWM signal for 32 cycles of pll and 64 cycles of clock clk-pll, which is 8 times the basic cycle as shown in FIG. 3 (E), is output.

A block diagram showing a functional configuration of an arithmetic circuit included in the ΔΣ modulator 15A will be described with reference to FIG.
In the figure, the ΔΣ modulator 15A includes a subtractor (-) 41, an adder (+) 42, 44, 46, 47, 51, a delay device (Z ^-1 ) 43, 48, 52, 54, and a multiplier 45, 49. , 50, and quantizer 53.

The digital voice data input from the sound source unit 14 is subtracted by the subtractor 41 by the output of the delayer 54 that delays the output of the quantizer 53, and the difference is output to the adder 42. The adder 42 adds the output z0 of the delayer 43 that delays its own output, and outputs the sum to the delayer 43, the adder 44, and the multiplier 45.

The multiplier 45 multiplies the output of the adder 42 by a multiplier k0 and outputs the product to the adder 46. The adder 46 adds the output of the multiplier 45 and the output of the multiplier 49, and outputs the sum to the adder 47.

The adder 47 adds the output of the adder 46 and the output z1 of the delayer 48 that delays its own output, and outputs the sum to the adder 48, the adder 44, and the multiplier 50. The multiplier 50 multiplies the output of the adder 47 by a multiplier k1 and outputs the product to the adder 51.

The adder 51 adds the output of the multiplier 50 and the output z2 of the delayer 52 that delays its own output, and outputs the sum to the delayer 52, the adder 44, and the multiplier 49. The multiplier 49 multiplies the output of the adder 51 by a multiplier a0 and outputs the product to the adder 46.

The adder 44 adds the outputs of the adders 42, 47, and 51, outputs the sum to the quantizer 53, and quantizes the sum. Then, the output of the quantizer 53 is output to the shift register unit 15B of the next stage as the output of the ΔΣ modulator 15A, and is also output to the delay device 54. The delayer 54 delays the output of the quantizer 53 and gives the output z3 to the subtractor 41 as a subtraction to give negative feedback to the input.

When e is the quantization noise, the characteristics of the quantization e at the output y of the quantizer 53 are shown in the following equation.

FIG. 5 is a diagram showing a noise shaping frequency characteristic in which e (noise) of the above equation is graphed. In the figure, the horizontal axis is the angular velocity and the vertical axis is the noise signal level (Quantization Noise) [dB]. In the figure, when the required noise shaping amount is -100 [dB], the audible band is in the range of about 0.06 (= 1/16) angular velocity.

That is, the sampling rate Fsp of the noise shaper is required to be about 16 times the sampling frequency Fsd of the digital voice data.

FIG. 6 is a block diagram illustrating a case where the functional configuration of the arithmetic circuit shown in FIG. 4 is executed by a specific hardware circuit.
The clock clk-pll is input to the control unit 61. The control unit 61 internally includes an m counter (mcnt) 61A for counting the clock clk-pll, and controls each of the following circuits, specifically, register latch enable, selector selection, and parameter selection. To do.

In addition to the control unit 61, the ΔΣ modulator 15A includes registers 62, 63, selectors 64 to 66, a multiplier (MUL) 67, an adder (ADD) 68, a parameter constant generator 69, a quantizer 70, and a delay. Has registers 71A to 71D for use.

The digital audio data from the sound source unit 14 in the previous stage is input to the selector 66. The outputs of the selector 65 and the multiplier 67 are also input to the selector 66, and one value selected according to the control unit 61 is output to the adder 68.

The holding value of the register (AC) 62 is also input to the adder 68, and the sum added according to the control unit 61 is added to the registers (z0 to z3) 71A to used in the delayers 43, 48, 52, 54 of FIG. Output to 71D and selector 64.

The holding values of the registers 71A to 71D are input to the selector 65. The selector 65 selects one of the holding values of the registers 71A to 71D according to the control from the control unit 61, and outputs the selected value to the selector 66 and the multiplier 67.

The multiplier 67 multiplies the output of the selector 65 with any of the parameter constants k0, k1, and a0 given by the parameter constant generator 69, and outputs the product to the selector 66.

The selector 64 selects one of the output of the adder 68 and the output of the quantizer 70 (53) according to the control unit 61 and holds it in the register (AC) 62. The holding value of the register 62 is read out to the quantizer 70 and the adder 68.

Then, the calculation result of the ΔΣ calculation unit 15B output by the quantizer 70 is sent to the selector 64, while being held in the register (DR) 63, the holding value is read out, and the shift register unit in the next stage is read. It is output to 15B.

FIG. 7 is a diagram showing the contents of arithmetic processing by the ΔΣ modulator 15A executed by the hardware circuit of FIG. 6 in association with the count value of the m counter 61A of the control unit 61. The m counter 61A is a basic counter that controls the operation of the ΔΣ modulator 15A, and can take 8 count values of “0” to “7”.

The m counter 61A is reset every PWM cycle to become "0", then counts up by "+1" by the clock clk-pll, and after reaching the maximum value "7", until it is reset, until it is reset. Holds the count value "7".
While the count value of the m counter 61A is "7", the reset operation is in a standby state.

The operation contents by the control unit 61 in the ΔΣ modulator 15A corresponding to the count values “0” to “7” of the m counter 61A will be briefly described.

0: When the m counter 61A is reset to "0", the delay value z3 held by the register 71D is selected by the selector 65, and the selection result of the selector 65 and the input data from the sound source unit 14 are sequentially selected by the selector 66. Let me. Each selection result is added by the adder 68, and the sum output thereof is selected by the selector 64 and held in the register 62.

In addition, the holding value of the register 62 is read out and output to the quantizer 70 for quantization processing, and the output is output to the shift register unit 15B of the next stage via the register 63.

1: The delay value z0 held by the register 71A is selected by the selector 65, and the selection result of the selector 65 is selected by the selector 66. The adder 68 adds the selection result of the selector 66 and the holding value of the register 62, and the sum output thereof is held in the register 71A.

In addition, the output of the quantizer 70 is held in the register 71D via the selector 64, the register 62, and the adder 68.
2: The delay value z2 held by the register 71C is selected by the selector 65, the parameter constant a0 is output to the parameter constant generator 69, and these two values are multiplied by the multiplier 67. The obtained product is held in the register 62 via the selector 66, the adder 68, and the selector 64.

3: The delay value z0 held by the register 71A is selected by the selector 65, the parameter constant k0 is output to the parameter constant generator 69, and these two values are multiplied by the multiplier 67. The product to be obtained is selected by the selector 66, and the holding value of the register 62 is read out and output to the adder 68. The adder 68 adds these two values, and the sum of them is held in the register 62 again via the selector 64.

4: The delay value z1 held by the register 71B is selected by the selectors 65 and 66 and output to the adder 68, and the holding value of the register 62 is read and output to the adder 68. The adder 68 adds these two values, and the sum of them is held in the register 71B again.

5: The delay value z1 held by the register 71B is selected by the selector 65, the parameter constant k1 is output to the parameter constant generator 69, and these two values are multiplied by the multiplier 67. The obtained product is held in the register 62 via the selector 66, the adder 68, and the selector 64.

6: The delay value z2 held by the register 71C is selected by the selectors 65 and 66 and output to the adder 68, and the holding value of the register 62 is read and output to the adder 68. The adder 68 adds these two values, and the sum of them is held in the register 71C again.

7: The delay values z0 to z2 held by the registers 71A to 71C are sequentially selected by the selectors 65 and 66, and are serially output to the adder 68. The adder 68 adds these three values, and the sum is held in the register 62 via the selector 64.

In this way, the ΔΣ calculation process is executed as described above according to the count value mctnt of the m counter 61A, which is reset every PWM cycle and counts by the clock clk-pll.

FIG. 8 is a block diagram showing a specific circuit configuration of the shift register unit 15B that delays the output of the ΔΣ modulator 15A.

The shift register unit 15B has a shift register composed of eight stages of 3-bit D flip-flops 81A to 81H, and 0 comparators 82 to 84. The output of the ΔΣ modulator 15A is output to the output unit 15C of the subsequent stage via the D flip-flops 81A to 81H. A ΔΣ cycle clock is supplied from the ΔΣ modulator 15A to the D flip-flops 81A to 81H as an operating clock.

The outputs of the eight-stage D flip-flops 81A to 81H constituting the shift register are output to the 0 comparator 82. Further, each output of the rear four-stage D flip-flops 81E to 81H is output to the 0 comparator 83. In addition, the outputs of the last two-stage D flip-flops 81G and 81H are output to the 0 comparator 84.

The 0 comparator 82 outputs an 8-value matching signal to the output unit 15C when the outputs of the D flip-flops 81A to 81H are all “0”. Similarly, the 0 comparator 83 outputs a four-value matching signal to the output unit 15C when the outputs of the D flip-flops 81E to 81H are all “0”. The 0 comparator 84 outputs a binary match signal to the output unit 15C when the outputs of the D flip-flops 81G and 81H are both “0”.

In addition, since the shift register unit 15B has the shift register composed of the above-mentioned eight-stage D flip-flops 81A to 81H, a delay of eight PWM cycles occurs in the process of signal transmission.

However, in this embodiment, it is premised that oversampled audio data of about 32 times is handled. For example, in the case of audio data oversampled 32 times at a basic sampling frequency of 44.1 [KHz]. , Approximately 5.67 [μsec] (= 1 / (44.1 × 10 ³ × (32/8))) delay will occur, which does not affect human perception, and is a very minute time. Therefore, no problem occurs in practical use.

FIG. 9 is a block diagram showing a specific hardware circuit configuration of the output unit 15C and the D flip-flop 15D.

The output unit 15C includes n-counters 91 that count by the clock clk-xtal, decoders 92A to 92H that decode the count values of the n-counters 91, and first selector 93, second selector 94, third selector 95, and fourth selector. It has a selector 96.

The decoders 92A to 92E have pulse widths of 0 [%], 25 [%], 50 [%], 75 [%], and 100 [%], respectively, in a normal PWM cycle based on the count value of the n counter 91. The pulse signal is output to the first selector 93.

The decoder 92F outputs a pulse signal having a pulse width of 50 [%] to the second selector 94 in a cycle twice the normal PWM cycle based on the count value of the n counter 91.

The decoder 92G outputs a pulse signal having a pulse width of 50 [%] to the third selector 95 at a cycle four times the normal PWM cycle based on the count value of the n counter 91.

The decoder 92H outputs a pulse signal having a pulse width of 50 [%] to the fourth selector 96 at a cycle eight times the normal PWM cycle based on the count value of the n counter 91.

The first selector 93 selects one of the pulse signals output by the decoders 92A to 92E according to the FIFO signal given at the latch timing, and outputs the pulse signal to the second selector 94.

The second selector 94 selects a pulse signal having a double-period pulse width of 50 [%] output by the decoder 92F when there is a binary match signal from the shift register unit 15B in the previous stage, and the binary selector 94. When there is no matching signal, the pulse signal of the normal cycle output by the first selector 93 is selected and output to the third selector 95.

The third selector 95 selects a pulse signal having a pulse width of 50 [%] with a quadruple cycle output by the decoder 92G when there is a quadrature matching signal from the shift register unit 15B in the previous stage, and also quadrature. When there is no matching signal, the pulse signal which is the selection output in the second selector 94 is selected and output to the fourth selector 96.

The fourth selector 96 selects a pulse signal having an 8-fold cycle pulse width of 50 [%] output by the decoder 92H when there is an 8-value matching signal from the shift register unit 15B in the previous stage, and also has 8-values. When there is no matching signal, the pulse signal, which is the selection output of the third selector 95, is selected, and the forward rotation signal is output to the D flip-flop 97 and the reverse rotation signal is output to the D flip-flop 98.

The D flip-flops 97 and 98 are two-staged to obtain a balanced output to form the D flip-flop 15D, and both latch the output of the fourth selector 96 with the clock clk_pll to obtain the positive electrode output and the negative electrode output. And.

In the configuration of the shift register unit 15B and the output unit 15C described above, first, in the shift register unit 15B that delays the output of the ΔΣ modulator 15A by 8 cycles of the normal PWM cycle, a specific signal is used by the 0 comparators 82 to 84. Here, a match is detected whether or not "0" indicating silence is continuous eight times, four times, or two times, and if a match is detected, a match signal is output to the DAC15.

In the output unit 15C, when silence is not continuous as a result of the ΔΣ calculation, any signal of the decoders 92A to 92E is selected by the first selector 93 according to a normal PWM cycle, and the second selector 94 and the third selector are selected. It operates to output to the D flip-flop 15D via 95 and the fourth selector 96.

On the other hand, when the silence is continuous as a result of the ΔΣ calculation, the shift register unit 15B has a binary matching signal by the 0 comparator 84 and a quadrature matching signal by the 0 comparator 83, depending on the degree of continuity. , 0 Comparator 82 outputs an 8-value match signal.

In the output unit 15C, selectors 93 to 96 are configured so as to preferentially select a case where the period of continuous silence is longer, and when silence is continuous according to the ΔΣ calculation result, the length is increased. The PWM signal with a duty ratio of 50 [%] for 2 cycles, 4 cycles, or 8 cycles of the normal PWM cycle shown in FIGS. 3 (C) to 3 (E) becomes "0" indicating silence. It is selected as the corresponding signal and output to the D flip-flop 15D.

In the D flip-flop 15D, the waveforms are shaped in the process of latching the selective output of the sound source unit 14 by the clock clk-pll, and output as a balanced positive electrode output and a negative electrode output, respectively.

The outputs of these D flip-flops 15D are each output to the amplifier 19 as analog audio signals via the low-pass filter 18. The amplifier 19 is composed of a differential amplifier as described above, and amplifies the analog audio signal at a given amplification factor according to the difference between the forward rotation signal and the reverse rotation signal, and emits sound from the speaker 20.

Many of the noise components superimposed on the signal in a series of digital processing and wiring transmission lines are similarly superimposed on the forward and reverse signals, and by configuring the amplifier 19 with a differential amplifier, only the signal difference is amplified. By doing so, the noise components of the same phase can be canceled out and removed.

As described in detail above, according to the present embodiment, the output signal obtained by delta-sigma conversion is effectively utilized, and when a predetermined delta-sigma conversion result is continuous, noise is reduced without reducing the effect of noise shaping. Is possible.

Further, in the present embodiment, when a predetermined ΔΣ conversion result is continuous, an appropriate one is generated from a plurality of cycles, for example, 2 cycles, 4 cycles, and 8 cycles, depending on the degree of continuity. Therefore, it is possible to efficiently reduce noise by adapting to the content of the signal.

More specifically, with respect to the standard PWM cycle, about -3 [dB] when the PWM signal is 2 cycles, about -6 [dB] when the PWM signal is 4 cycles, and 8 cycles. It should be added that a noise reduction effect of about -9 [dB] was obtained by the experiment when it was used as a PWM signal.

The invention of the present application is not limited to the above-described embodiment, and can be variously modified at the implementation stage without departing from the gist thereof. In addition, each embodiment may be carried out in combination as appropriate as possible, in which case the combined effect can be obtained. Further, the embodiments include inventions at various stages, and various inventions can be extracted by an appropriate combination in a plurality of disclosed constitutional requirements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problems described in the problem column to be solved by the invention can be solved, and the effects described in the effect column of the invention can be solved. If is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

Hereinafter, the inventions described in the claims of the original application of the present application will be added.
[Claim 1]
A delta-sigma operation circuit that executes delta-sigma operations on sequentially input data,
A detection circuit that detects whether or not a specific value is continuous based on the calculation result of the ΔΣ calculation circuit, and
When the detection circuit detects that the specific values are not continuous, a PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and the detection circuit detects that the specific values are continuous. In addition, a PWM signal generation circuit that generates a PWM signal in a cycle longer than the first PWM cycle,
A D / A conversion device including.
[Claim 2]
When the PWM signal generation circuit detects that the specific value is continuous twice, it generates a PWM signal in a second PWM cycle that is twice as long as the first PWM cycle.
The D / A conversion device according to claim 1.
[Claim 3]
When the PWM signal generation circuit detects that the specific value is continuous four times, it generates a PWM signal in a third PWM cycle that is four times as long as the first PWM cycle.
The D / A conversion device according to claim 1 or 2.
[Claim 4]
When the PWM signal generation circuit detects that the specific value is continuous eight times, it generates a PWM signal in a fourth PWM cycle that is eight times longer than the first PWM cycle.
The D / A conversion device according to any one of claims 1 to 3.
[Claim 5]
The specific value is a value indicating 0.
The D / A conversion device according to any one of claims 1 to 4.
[Claim 6]
The D / A conversion device according to any one of claims 1 to 5.
A speaker that sounds based on the PWM signal generated by the D / A conversion device, and
Audio equipment equipped with.
[Claim 7]
The D / A conversion device according to any one of claims 1 to 5.
An operator for specifying the pitch and
A speaker that produces a sound based on the PWM signal generated by the D / A conversion device in response to a user operation on the operator.
Electronic musical instrument equipped with.
[Claim 8]
On the computer of electronic musical instruments
Delta-sigma operation is executed on the sequentially input data,
Whether or not a specific value is continuous is detected based on the result of the ΔΣ operation.
When it is detected that the specific values are not continuous, a PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and when it is detected by the detection that the specific values are continuous, the first Generates a PWM signal with a cycle longer than the PWM cycle of
D / A conversion method.

11 ... Operation unit,
12 ... CPU,
13 ... ROM,
14 ... Sound source section,
15 ... DAC,
15A ... ΔΣ modulator,
15B ... Shift register,
15C ... Output unit (PWM),
15D ... D flip-flop (DF / F),
16 ... Crystal oscillator (Xtal),
17 ... PLL,
18 ... Low-pass filter,
19 ... Amp.
20 ... Speaker,
41 ... Subtractor (-),
42,44,46,47,51 ... Adder (+),
43, 48, 52, 54 ... Delayer (Z ^-1 ),
45, 49, 50 ... Multiplier,
53 ... Quantumizer,
61 ... Control unit,
61A ... m counter (mcnt),
62 ... Register (AC),
63 ... Register (DR),
64-66 ... Selector,
67 ... Multiplier (MUL),
68 ... Adder (ADD),
69 ... Parameter constant generator,
70 ... Quantumizer,
71A-71D ... Register,
81A-81H ... D flip-flop (DF / F),
82-84 ... 0 comparator,
91 ... n counter,
92A-92H ... Decoder,
93 ... 1st selector,
94 ... 2nd selector,
95 ... 3rd selector,
96 ... 4th selector,
97, 98 ... D flip-flop,
B1 ... Bus,
CH1 ... LSI chip,
CU1 ... Crystal oscillator.

Claims (8)

A delta-sigma operation circuit that executes delta-sigma operations on sequentially input data,
A detection circuit that detects whether or not a specific value is continuous based on the calculation result of the ΔΣ calculation circuit, and
When the detection circuit detects that the specific values are not continuous, a PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and the detection circuit detects that the specific values are continuous. In addition, a PWM signal generation circuit that generates a PWM signal in a cycle longer than the first PWM cycle,
A D / A conversion device including. When the PWM signal generation circuit detects that the specific value is continuous twice, it generates a PWM signal in a second PWM cycle that is twice as long as the first PWM cycle.
The D / A conversion device according to claim 1. When the PWM signal generation circuit detects that the specific value is continuous four times, it generates a PWM signal in a third PWM cycle that is four times as long as the first PWM cycle.
The D / A conversion device according to claim 1 or 2. When the PWM signal generation circuit detects that the specific value is continuous eight times, it generates a PWM signal in a fourth PWM cycle that is eight times longer than the first PWM cycle.
The D / A conversion device according to any one of claims 1 to 3. The specific value is a value indicating 0.
The D / A conversion device according to any one of claims 1 to 4. The D / A conversion device according to any one of claims 1 to 5.
A speaker that sounds based on the PWM signal generated by the D / A conversion device, and
Audio equipment equipped with. The D / A conversion device according to any one of claims 1 to 5.
An operator for specifying the pitch and
A speaker that produces a sound based on the PWM signal generated by the D / A conversion device in response to a user operation on the operator.
Electronic musical instrument equipped with. On the computer of electronic musical instruments
Delta-sigma operation is executed on the sequentially input data,
Whether or not a specific value is continuous is detected based on the result of the ΔΣ operation.
When it is detected that the specific values are not continuous, a PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and when it is detected by the detection that the specific values are continuous, the first Generates a PWM signal with a cycle longer than the PWM cycle of
D / A conversion method.