JP2020129866A - Overcurrent detection circuit and current output circuit - Google Patents

Abstract

To achieve an overcurrent detection circuit capable of effectively preventing FET breakdown due to an overcurrent with a simple configuration.SOLUTION: An overcurrent detection circuit (10) includes: a first resistor (Rs) into which an output current (Im) of a current sense (Qm) of a FET (20) is introduced; and a current transformer (CT) into which a gate current (Ig) of the FET is introduced. An overcurrent signal is output according to a voltage (Vm + Vt) obtained by subtracting an applied voltage of a second resistance (Rt) connected between both terminals on a secondary side of the current transformer from an applied voltage of the first resistance.SELECTED DRAWING: Figure 1

Description

The present invention relates to an overcurrent detection circuit and a current output circuit using the same.

As a power semiconductor device, a transistor such as a MOS-FET (Metal-Oxide Semiconductor Field Effect Transistor) having a function of outputting a sense current proportional to a load current flowing in a main circuit is used. ing.

In such a current-sensing function built-in MOS-FET, for example, the drain electrode of the sense FET element is arranged on the semiconductor wafer together with the drain electrode which is the current output electrode of the main FET element as the main circuit, and is connected in parallel. And a part of the current flowing through the main FET element is shunted.

FIG. 5 shows an equivalent circuit of the MOS-FET 50 having a built-in current sensing function. The MOS-FET 50 includes a drain terminal Fd, a gate terminal Fg, and a source terminal Fs, which are connected to the drain, source, and gate of the main FET element Q, respectively, as external connection terminals.

As shown, the MOS-FET 50 includes a main FET element Q and a sense FET element Qm. Each drain and gate are connected in parallel.

Further, the MOS-FET 50 is provided with a sense terminal pair (sense terminal Fm, sense terminal Fr) for extracting the sense current Im flowing through the sense FET element Qm to the outside. The sense terminal Fr is common with the source terminal Fs. When the shunt resistor Rs is connected between the pair of sense terminals, the sense current Im flows through the shunt resistor Rs, and the drain current Id corresponding to the load current can be detected by the voltage Vm across the sense current Im.

In the MOS-FET 50, the electrode area for the sense FET element Qm is extremely smaller than that of the main FET element. As a result, the sense current Im, which is the drain current of the sense FET element Qm, becomes smaller than the drain current Id flowing through the main FET element. As a specific example, the magnitude of the sense current Im is about 1/50,000 of the drain current Id flowing through the main FET element.

The sense current Im is used as a monitor current that is input to the overcurrent detection circuit for preventing the MOS-FET 50 from being irreversibly destroyed due to an excessive load current (drain current Id). When the sense current Im exceeds a predetermined value, the overcurrent detection circuit determines that the load current is excessive and outputs a signal indicating that the overcurrent has been detected to the gate drive circuit that performs on/off control of the MOS-FET. It outputs and turns off the MOS-FET. A protection technique for such a power semiconductor device is disclosed in, for example, Patent Document 1.

JP-A-5-276761

The sense current Im of the transistor having the current sensing function as described above is usually proportional to the load current of the main circuit (drain current Id of the main FET element). However, it is known that when the main FET element Q is turned on, the sense current Im transiently jumps up like a surge.

This phenomenon is confirmed even when no voltage is applied between the drain terminal Fd and the source terminal Fs, and no drain current flows in both the main FET element Q and the sense FET element Qm. FIG. 6 is a diagram showing this phenomenon, and shows the waveforms of the gate-source voltage Vgs of the MOS-FET 50 and the voltage Vm applied to the shunt resistor Rs. The voltage Vm applied to the shunt resistor Rs is proportional to the sense current Im. As shown in the figure, there is a phenomenon in which a large sense current Im transiently flows in the sub-microsecond order when the MOS-FET 50 is turned on.

As shown in FIG. 6, even when the MOS-FET 50 is turned off, a surge-like large transient current appears in the sense current Im in the opposite direction to that at the time of turn-on.

The phenomenon of the sense current Im jumping up at the time of turn-on may cause erroneous detection of overcurrent. If the detection threshold for overcurrent is set high in order to prevent erroneous detection, the protection of the MOS-FET 50 becomes insufficient.

Therefore, in the conventional technique of Patent Document 1, the sense current Im is bypassed for a certain period in synchronization with the turn-on of the transistor, and the sense current Im is not input to the overcurrent detection circuit.

However, such a conventional technique has a problem that an overcurrent cannot be detected during the bypass period. Further, it is necessary to perform the bypass in synchronization with the drive circuit of the transistor, which causes a problem that the circuit configuration is complicated and the cost is high.

One aspect of the present invention is to realize an overcurrent detection circuit which can suppress erroneous detection of overcurrent due to a jump of the sense current Im at turn-on with a simple configuration and can effectively prevent destruction of FET due to overcurrent. With the goal.

In order to solve the above problems, an overcurrent detection circuit according to one embodiment of the present invention is an overcurrent detection circuit that monitors an output current of a current sense incorporated in an FET and detects an overcurrent of the FET. A first resistor, a second resistor, a current transformer, and a comparator, the output current is introduced to the first resistor, and the gate of the FET is provided on the primary side of the current transformer. A current is introduced, the second resistor is connected between both terminals on the secondary side of the current transformer, and from the applied voltage of the first resistor due to the output current, due to the gate current, When the applied voltage of the second resistor exceeds a predetermined value, the comparator outputs a signal indicating that the overcurrent of the FET has been detected by the comparator.

In order to solve the above problems, a current output circuit according to one aspect of the present invention includes an overcurrent detection circuit according to one aspect of the present invention, an FET incorporating current sense, and a gate drive circuit for the FET. It is characterized by including.

According to the overcurrent detection circuit of one embodiment of the present invention, it is possible to suppress erroneous detection of overcurrent due to a jump of the sense current Im at turn-on with a simple configuration, and to effectively prevent destruction of the FET due to overcurrent. A current detection circuit can be realized.

Further, according to the current output circuit of one embodiment of the present invention, a current output circuit having the same effect can be realized.

It is a figure which shows the overcurrent detection circuit which concerns on Embodiment 1 of this invention, and the current output circuit using the same. FIG. 6 is a diagram for explaining the operation of the overcurrent detection circuit according to the first embodiment of the present invention. It is a figure which shows the overcurrent detection circuit of a comparative example, and the current output circuit using the same. It is a figure for demonstrating operation|movement of the overcurrent detection circuit of a comparative example. It is an equivalent circuit diagram which shows MOS-FET provided with the current sense function. It is a figure for showing the sense current waveform of MOS-FET.

[Embodiment 1]
Below, one Embodiment of this invention is described in detail using FIGS.

FIG. 1 is a diagram showing an overcurrent detection circuit 10 according to the first embodiment and a current output circuit 1 using the overcurrent detection circuit 10. The current output circuit 1 includes a MOS-FET 20, a gate drive circuit 30 that controls the MOS-FET 20, and an overcurrent detection circuit 10.

(Structure of MOS-FET)
The MOS-FET 20 includes a drain terminal Fd, a gate terminal Fg, and a source terminal Fs, which are connected to the drain, source, and gate of the main FET element Q, respectively, as external connection terminals. Normally, the drain terminal Fd is connected to the positive side of the power source through the load, and the source terminal Fs is connected to the negative side of the power source for use.

As shown in FIG. 1, the MOS-FET 20 includes a main FET element Q and a sense FET element Qm (current sense). Each drain and gate are connected in parallel.

Further, the MOS-FET 20 includes a sense terminal pair (sense terminal Fm and sense terminal Fr) for extracting the sense current Im (current sense output current) flowing through the sense FET element Qm to the outside. The sense terminal Fr is common with the source terminal Fs. Therefore, the sense terminal Fr does not necessarily have to be provided independently of the source terminal Fs.

In the MOS-FET 20, the electrode area for the sense FET element Qm is configured to be much smaller than that of the main FET element. As a result, the sense current Im, which is the drain current of the sense FET element Qm, becomes smaller than the drain current Id flowing through the main FET element. As a specific example, the magnitude of the sense current Im is about 1/50,000 of the drain current Id flowing through the main FET element.

As described above, the MOS-FET 20 has the same configuration as the MOS-FET 50 described with reference to FIG.

(Structure of gate drive circuit)
The gate drive circuit 30 is a circuit for controlling ON/OFF of the MOS-FET 20 by biasing between the gate and the source of the MOS-FET 20.

The gate drive circuit 30 has a gate control signal output terminal Do. The gate drive circuit 30 controls the voltage of the output terminal Do to be high (high: for example, the gate-source voltage Vgs is +15V) or low (low: for example, the gate-source voltage Vgs is −15V), so that the MOS- The on/off control of the FET 20 is performed.

The gate drive circuit 30 also includes an overcurrent signal input terminal Ds. When a signal (for example, a high signal) indicating that an overcurrent has been detected is input to the overcurrent signal input terminal Ds, the output of the output terminal Do is set to low and the MOS-FET 20 is turned off.

(Structure of overcurrent detection circuit)
The overcurrent detection circuit 10 is a circuit whose basic function is to monitor the sense current Im of the MOS-FET 20 and prevent irreversible destruction of the MOS-FET 20 due to an excessive load current.

The overcurrent detection circuit 10 includes a monitor terminal pair (monitor terminal Pm and monitor terminal Pr) for introducing the sense current Im from the MOS-FET 20. In the current output circuit 1, the sense terminal Fm and the sense terminal Fr of the MOS-FET 20 are connected to the monitor terminal Pm and the monitor terminal Pr of the overcurrent detection circuit 10, respectively.

Further, the overcurrent detection circuit 10 includes an overcurrent signal output terminal Ps for outputting a signal indicating that an overcurrent has been detected. In the current output circuit 1, the overcurrent signal output terminal Ps of the overcurrent detection circuit 10 is connected to the overcurrent signal input terminal Ds of the gate drive circuit 30.

Further, the overcurrent detection circuit 10 includes a gate signal input terminal Pi and a gate signal output terminal Po. In the current output circuit 1, the output terminal Do of the gate drive circuit 30 is connected to the gate signal input terminal Pi of the overcurrent detection circuit 10. The gate signal output terminal Po of the overcurrent detection circuit 10 is connected to the gate terminal Fg of the MOS-FET 20.

Details of the internal configuration of the overcurrent detection circuit 10 are as follows.

The primary side of the current transformer CT is arranged in the line connecting the gate signal input terminal Pi and the gate signal output terminal Po. That is, one terminal on the primary side of the current transformer CT is connected to the gate signal input terminal Pi, and the other terminal is connected to the gate signal output terminal Po. A resistor Rt is connected between the secondary side terminals of the current transformer CT.

The line connecting the gate signal input terminal Pi and the gate signal output terminal Po is configured so as not to have a great influence on the gate control signal output from the gate drive circuit 30 to the MOS-FET 20.

A shunt resistor Rs (first resistor) is connected between the monitor terminal pair (monitor terminal Pm and monitor terminal Pr). Here, the potential of the monitor terminal Pm based on the monitor terminal Pr is defined as the applied voltage Vm (voltage between the monitor terminal pair) of the shunt resistor Rs.

The sense terminal Fm on the high potential side of the shunt resistor Rs is connected to one terminal of the resistor Rt. The other terminal of the resistor Rt is connected to one input of the comparator 11. Here, the potential of the other terminal of the resistor Rt based on one terminal of the resistor Rt (sense terminal Fm) is defined as the applied voltage Vt of the resistor Rt. When the gate current Ig flows from the gate signal input terminal Pi to the gate signal output terminal Po, the voltage Vt applied to the resistor Rt is negative.

A predetermined threshold voltage Vth is applied to the other input of the comparator 11. The output terminal of the comparator 11 is connected to the overcurrent signal output terminal Ps.

With such a configuration, when the combined voltage Vm+Vt of the applied voltage Vm of the shunt resistor Rs (voltage between the monitor terminal pair) and the applied voltage Vt of the resistor Rt is larger than the predetermined threshold voltage Vth, the comparator 11 causes the overcurrent signal. A signal (for example, a high signal) indicating that an overcurrent has been detected by the gate drive circuit 30 is output to the output terminal Ps. On the contrary, when the combined voltage Vm+Vt is smaller than the predetermined threshold voltage Vth, the comparator 11 outputs a signal (for example, a low signal) indicating that the overcurrent is not detected.

(Operation of overcurrent detection circuit)
Next, a specific operation of the overcurrent detection circuit 10 will be described.

FIG. 2 is a diagram showing a waveform of a signal in each part of the current output circuit 1. In the figure, gate-source voltage Vgs of MOS-FET 20, gate current Ig, drain current Id, sense current Im, applied voltage Vm of shunt resistor Rs (voltage between monitor terminal pair), applied voltage Vt of resistor Rt, composite The voltage Vm+Vt is displayed. Since the applied voltage Vm of the shunt resistor Rs is proportional to the sense current Im, it is shown as the same waveform in the figure.

At time Ts, the gate drive circuit 30 changes the gate-source voltage Vgs from low to high, turning on the MOS-FET 20.

When the MOS-FET 20 is turned on, a current for charging the gate capacitance of the MOS-FET 20 (gate capacitance charging current) flows. Therefore, the gate current Ig has a waveform in which a large current transiently flows at the time of turn-on. When the MOS-FET 20 is turned off, a current that draws out the charge charged in the gate capacitance flows, so that the gate current Ig has a waveform in which a large transient current flows in the negative direction.

The drain current Id, which is the load current, starts flowing when the MOS-FET 20 is turned on. Here, consider a case where the load current starts to increase at time To after time Ts due to some abnormality on the load side and continues to increase as time goes by. The waveform of the drain current Id is a waveform that takes this case into consideration.

The sense current Im is a current that is in principle proportional to such a drain current Id, but as described with reference to FIG. 6, a transiently large current flows at the time of turn-on and turn-off. Therefore, the waveform shown in FIG. 2 is obtained by adding the surge-like waveform at the time of turn-on and at the time of turn-off to the waveform of the drain current Id. The waveform of the applied voltage Vm of the shunt resistor Rs is also the same.

The applied voltage Vt to the resistor Rt is a voltage caused by a current flowing back through the secondary side of the current transformer CT and the resistor Rt. Therefore, this has a waveform proportional to the gate current Ig flowing through the primary side of the current transformer CT, but since the direction of the voltage is defined as described above, it becomes a negative value when the gate current Ig is a positive value. Therefore, the waveform of the applied voltage Vt of the resistor Rt is a waveform in which the gate current Ig is reversed.

Then, in the combined voltage Vm+Vt, the surge-like transient large voltage of the applied voltage Vm at the time of turn-on has a waveform that is offset by the surge-like transient large negative voltage of the applied voltage Vt of the resistor Rt. .. Further, the waveforms are likewise canceled at the time of turn-off. Here, the term “cancellation” does not mean that the influences are completely canceled, but at least the influences are added so that the mutual influences are opposite to each other. In other words, it is a concept that includes both cases of partial offset and cases of excessive offset.

Therefore, the combined voltage Vm+Vt is close to the waveform shape of the drain current Id.

That is, at the time of turn-on, the voltage input to the comparator 31 is configured such that the effect of the sense current Im jumping up is offset by the gate capacitance charging current in the gate current Ig. The same applies at the time of turn-off.

When the drain current Id further increases after a while from the time Td, the combined voltage Vm+Vt reaches the threshold voltage Vth at the time Td. Then, the output (the overcurrent signal output terminal Ps) of the comparator 11 is a signal (for example, a low signal) indicating that the overcurrent is not detected, and the signal (for example, a high signal) indicating that the overcurrent is detected. The MOS-FET 20 is turned off under the control of the gate drive circuit 30.

In this way, destruction of the MOS-FET 20 due to an excessive load current (drain current Id) is prevented in advance.

(Comparison with comparative examples and effects)
As described above, the overcurrent detection circuit 10 has a configuration that suppresses the influence of the surge of the waveform of the sense current Im at the time of turn-on. For comparison, the operation of the overcurrent detection circuit of the comparative example which does not have such a configuration will be described.

FIG. 3 is a diagram showing a current output circuit 3 using the overcurrent detection circuit 40 of the comparative example. The MOS-FET 20 and the gate drive circuit 30 are the same as those in the current output circuit 1 of the first embodiment. Since the overcurrent detection circuit 40 of the comparative example does not have a function of monitoring the gate current Ig, the output terminal Do of the gate drive circuit 30 is directly connected to the gate terminal Fg of the MOS-FET 20. Unlike the overcurrent detection circuit 10 according to the first embodiment, the overcurrent detection circuit 40 of the comparative example does not include the gate signal input terminal Pi and the gate signal output terminal Po.

A shunt resistor Rs is connected between the monitor terminal pair (monitor terminal Pm and monitor terminal Pr) of the overcurrent detection circuit 40 of the comparative example. In the overcurrent detection circuit 40, the potential corresponding to the voltage Vm generated by the flow of the sense current Im through the shunt resistor Rs is compared with the threshold voltage Vth by the comparator 41 to detect the overcurrent.

FIG. 4 is a diagram showing a signal waveform in each part of the current output circuit 3 using the overcurrent detection circuit 40 of the comparative example. In the figure, the gate-source voltage Vgs of the MOS-FET 20, the drain current Id, the sense current Im, and the voltage Vm between the monitor terminal pair are displayed. Since the voltage Vm between the monitor terminal pair has a waveform proportional to the sense current Im, it is shown as having the same waveform shape in FIG.

At time Ts, the gate drive circuit 30 changes the gate-source voltage Vgs from low to high, turning on the MOS-FET 20.

The drain current Id, which is the load current, starts flowing when the MOS-FET 20 is turned on. Here, as in the case of FIG. 2, consider a case where the load current starts to increase at time To after time Ts due to some abnormality on the load side, and further increases with time. The waveform of the drain current Id is a waveform that takes this case into consideration.

Then, the waveform of the sense current Im becomes as shown in FIG.

In order to prevent erroneous detection of overcurrent due to the jump of the sense current Im at turn-on, the threshold voltage Vth must be set higher than the transient value of Vm corresponding to the jump of the sense current Im. Then, as shown in FIG. 4, the level of the drain current Id for detecting the overcurrent must be increased. If the threshold voltage Vth is set smaller than that in the state of FIG. 4, the voltage Vm between the monitor terminal pairs exceeds the threshold voltage Vth at turn-on, and the MOS-FET 20 is turned off due to an erroneous detection. End up.

As is clear from comparison between FIG. 2 and FIG. 4, this means that the period from the time To at which the abnormal current starts to the time Td at which the MOS-FET 20 is forcibly turned off due to overcurrent detection becomes longer. It also causes the situation. Then, the thermal energy due to the overcurrent causes the MOS-FET 20 to be easily destroyed. That is, in order to prevent the destruction of the MOS-FET 20, it is important to maintain the instantaneous value of the load current at a predetermined value or less and to end the period of the overcurrent state in a short period.

In the overcurrent detection circuit 10 according to the first embodiment, with respect to the signal input to the comparator 11, the influence of the jump of the sense current Im at turn-on is suppressed. Therefore, erroneous detection due to a jump of the sense current Im at turn-on is suppressed, and it is not necessary to unnecessarily increase the level of overcurrent detection. Therefore, the level of the detection of the overcurrent by the threshold voltage Vth can be set appropriately, and the occurrence of the overcurrent can be detected promptly, so that the destruction of the MOS-FET 20 due to the overcurrent can be effectively prevented.

In the overcurrent detection circuit 10, the line through which the gate control signal passes (the line from the gate signal input terminal Pi to the gate signal output terminal Po) detects the overcurrent (the signal is input to the comparator 11). Side line) is insulated by a current transformer CT. Therefore, the influence of the overcurrent detection circuit 10 on the gate control signal can be reduced.

Further, in the prior art overcurrent detection circuit of Patent Document 1, in order to suppress the influence of the sense current Im jumping up, synchronization with the gate drive circuit and a logic circuit therefor are necessary. However, the overcurrent detection circuit 10 according to the first embodiment does not require such a logic circuit and has a simple circuit configuration. Therefore, it is possible to suppress the influence of the jump of the sense current Im with a lower cost circuit configuration.

Note that the degree of canceling the influence of the jump of the sense current Im can be adjusted by selecting the winding ratio of the current transformer CT and the resistance value of the resistor Rt. Since it is desirable that the waveform of the combined voltage Vm+Vt input to the comparator 11 be similar to the waveform shape of the drain current Id, it is preferable to appropriately adjust the above parameters so as to be such.

Thus, unlike the prior art of Patent Document 1, the overcurrent detection circuit 10 detects the overcurrent even when the sense current Im jumps at turn-on by appropriately setting these parameters. It becomes possible.

In the detailed description of the invention, the MOS-FET having the function of outputting the sense current proportional to the load current flowing in the main circuit has been described above. However, the application of the present invention is not limited to MOS-FETs, and the same applies to other FETs, IGBTs (Insulated Gate Bipolar Transistors), and overcurrent detection circuits for other transistors. Which is applicable to
[Summary]
The overcurrent detection circuit according to the first aspect of the present invention monitors the output current (sense current Im) of the current sense (sense FET element Qm) incorporated in the FET (MOS-FET 20) and detects the overcurrent of the FET. Which includes a first resistor (shunt resistor Rs), a second resistor (resistor Rt), a current transformer, and a comparator, and the first resistor receives the output current. The gate current of the FET is introduced to the primary side of the current transformer, the second resistor is connected between both terminals of the secondary side of the current transformer, and the second current caused by the output current is introduced. When the applied voltage of the second resistor resulting from the gate current is subtracted from the applied voltage of the first resistor by a voltage exceeding a predetermined value, the comparator detects an overcurrent of the FET. Is output.

According to the above configuration, it is possible to realize an overcurrent detection circuit that can prevent erroneous detection of an overcurrent due to a jump of the sense current Im at turn-on with a simple configuration, and can effectively prevent the FET from being destroyed due to the overcurrent.

The overcurrent detection circuit according to Aspect 2 of the present invention is the overcurrent detection circuit according to Aspect 1, wherein the second resistor is applied at the reduced voltage when the FET is turned on, due to a surge current generated in the output current. The voltage is reduced by the applied voltage of the second resistor caused by the gate capacitance charging current generated in the gate current.

According to the above configuration, the signal waveform due to the surge-like current generated in the output current at the time of turn-on is canceled by the signal waveform due to the gate capacitance charging current, so that the overcurrent is erroneously detected due to the jump of the sense current Im at the time of turn-on. Can be effectively suppressed.

A current output circuit according to a third aspect of the present invention includes the overcurrent detection circuit according to the first or second aspect, an FET (MOS-FET 20) incorporating current sense, and a gate drive circuit for the FET.

According to the above configuration, an erroneous detection of an overcurrent due to a jump of the sense current Im at turn-on can be suppressed with a simple configuration, and a current output circuit that can effectively prevent the destruction of the FET due to the overcurrent can be realized.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and an embodiment obtained by appropriately combining the disclosed technical means is also a technique of the present invention. It is included in the target range.

1 Current output circuit 10 Overcurrent detection circuit 11 Comparator Rs Shunt resistance (first resistance)
Rt resistance (second resistance)
CT current transformer Pi gate signal input terminal Po gate signal output terminal Pm, Pr monitor terminal Ps overcurrent signal output terminal 20 MOS-FET (FET)
Q Main FET element Qm Sense FET element (current sense)
Fd drain terminal Fg gate terminal Fs source terminal Fm, Fr sense terminal 30 gate drive circuit Ds overcurrent signal input terminal Do output terminal Id drain current Ig gate current Im sense current (output current of current sense)
Vgs Gate-source voltage Vm Shunt resistor Rs applied voltage (first resistor applied voltage)
Vt resistance Rx applied voltage (second resistance applied voltage)
Vth threshold voltage

Claims (3)

An overcurrent detection circuit for monitoring an output current of a current sense incorporated in an FET and detecting an overcurrent of the FET,
A first resistor, a second resistor, a current transformer, and a comparator,
The output current is introduced into the first resistor,
The gate current of the FET is introduced to the primary side of the current transformer,
The second resistor is connected between both terminals of the secondary side of the current transformer,
When the applied voltage of the second resistor caused by the gate current is subtracted from the applied voltage of the first resistor caused by the output current and the subtracted voltage exceeds a predetermined value, the comparator causes the FET An overcurrent detection circuit, which outputs a signal indicating that an overcurrent has been detected. At the reduced voltage at turn-on of the FET,
The applied voltage of the second resistor due to the surge current generated in the output current is
The overcurrent detection circuit according to claim 1, wherein the overcurrent detection circuit is reduced by an applied voltage of the second resistor caused by a gate capacitance charging current generated in the gate current. A current output circuit comprising the overcurrent detection circuit according to claim 1 or 2, a FET incorporating current sense, and a gate drive circuit of the FET.

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