JP2020086872A - Debug system, bios, information processor, and debug method - Google Patents

Abstract

To provide a method for debugging a BIOS.SOLUTION: A debug system includes: an exception detection unit configured to detect exceptions that occur in a BIOS (Basic Input/Output System); an SMI issuing unit configured to issue an SMI (System Management Interrupt) when the exception detection unit detects an exception; and a debug function unit configured to execute a debug function in an SMM (System Management Mode).SELECTED DRAWING: Figure 11

Description

The present invention relates to a debug system, a BIOS, an information processing device and a debug method.

In a server equipped with a Xeon (registered trademark) processor or the like, initialization is performed by repeatedly changing the system management mode (SMM: System Management Mode) and the non-SMM mode. A system management interrupt (SMI) is a hardware interrupt with the highest priority. The SMM is a mode in which the SMI is used as a trigger for the transfer, and the processor changes the operation mode to the SMM when the SMI is issued. The SMM is an independent environment that cannot be accessed by users including the operating system (OS). A memory space (SMM protected memory) that can be accessed only while operating in SMM is set, and when the processor references a code other than SMM protected memory while operating in SMM, security is provided to cause an exception interrupt. (Patent Document 1).

The general software debugging method is based on the non-SMM and cannot access the SMM protected memory. When debugging a general OS or application, since the debugging is intended for a program that does not use the SMM protected memory, there is no particular inconvenience even if the SMM protected memory cannot be accessed. However, when the BIOS (Basic Input/Output System) is debugged, the SMM protected memory may be the debug target. For example, in the case of BIOS, a program that operates in non-SMM (non-SMM program) and a program that operates in SMM (SMM program) may cooperate to perform processing. In this case, even if the non-SMM program performs an unexpected operation, the cause may be the SMM program. Therefore, when an unexpected operation occurs in the BIOS, it is necessary to debug both the SMM program and the non-SMM program in order to clarify the cause.

Generally, in the development of BIOS firmware, an external device (debugger) of JTAG (Joint Test Action Group) standard is connected to the JTAG port for debugging. The JTAG port is used for the purpose of development evaluation, and is often deleted from the base at the time of shipment due to security considerations. In other words, even if a problem occurs after shipping, it cannot be debugged by the JTAG standard debugger.

In Patent Document 1, system data to be protected that is readable in both SMM and non-SMM and can be rewritten only in SMM is stored in a read-only area, and is stored during execution of non-SMM code. A method is disclosed that allows access to a read-only area.

Japanese Patent Publication No. 2013-536505

When an OS or application running on the server calls and uses a service provided by the BIOS, a failure due to the BIOS program may occur. There is a demand for a method capable of debugging a program that operates by using the SMM protected memory even when the JTAG standard debugger cannot be used.

Therefore, an object of the present invention is to provide a debug system, a BIOS, an information processing device, and a debug method that solve the above-mentioned problems.

According to one aspect of the present invention, a debug system issues an exception detection unit that detects an exception that occurs in a BIOS (Basic Input/Output System) and an SMI (System Management Interrupt) when the exception detection unit detects an exception. And a debug function unit that executes a debug function in SMM (System Management Mode).

Further, according to one aspect of the present invention, the BIOS has an exception detection unit that detects an exception that occurs in the BIOS, an SMI issuing unit that issues an SMI when the exception detection unit detects an exception, and a debug function by the SMM. A debug function unit to be executed is provided in the non-SMM layer.

According to another aspect of the present invention, an information processing device includes a processor capable of operating in SMM and the BIOS described above.

Further, according to another aspect of the present invention, a debugging method includes a step of detecting an exception that occurs in a BIOS, a step of issuing an SMI when the exception is detected, and a debug function using an SMM transitioned by the SMI issue. And a step of performing.

According to the present invention, a program that operates by accessing the SMM protected memory can be debugged.

It is a 1st figure which shows an example of the debugging system by one Embodiment of this invention. It is a figure explaining the handling of the BIOS exception interruption by 1st embodiment of this invention. 6 is a flowchart showing an example of initialization processing at OS startup according to the first embodiment of the present invention. It is a flow chart which shows an example of calling processing of a debugger of BIOS by a first embodiment of the present invention. It is a figure explaining the handling of the BIOS exception assertion by 2nd embodiment of this invention. It is a figure which shows an example of the parameter used for the assertion by 2nd embodiment of this invention. It is a 1st flowchart which shows an example of the calling process of the debugger of BIOS by 2nd embodiment of this invention. It is a 2nd flowchart which shows an example of the calling process of the debugger of BIOS by 2nd embodiment of this invention. It is a 2nd figure which shows an example of the debugging system by one Embodiment of this invention. It is a 3rd figure which shows an example of the debugging system by one Embodiment of this invention. It is a figure which shows the minimum structure of the debug system by each embodiment of this invention. It is a figure which shows an example of the hardware constitutions of the information processing apparatus which mounts the debug system in each embodiment of this invention.

Hereinafter, a debug system according to each embodiment of the present invention will be described with reference to the drawings.
(System configuration)
FIG. 1 is a diagram showing an example of a debug system according to each embodiment of the present invention.
The debug system 1 includes an OS 10 and a BIOS 20. The OS 10 and the BIOS 20 are software. The debug system 1 is mounted on a computer such as a server and is executed by a processor such as a CPU (Central Processing Unit) included in the computer.

The OS 10 includes an IDT (Interrupt Descriptor Table) 110, an OS exception interrupt handling function 120, and an OS initial completion notification function 130.
The IDT 110 is a table that sets an exception interrupt vector and an exception interrupt handler. In the IDT 110, memory addresses of exception interrupt handlers that are called when respective exceptions occur are registered for various exceptions such as division by 0 interrupt, breakpoint interrupt, and page fault.
The OS exception interrupt handling function 120 is a handler that is executed when an exception defined in the IDT 110 occurs. When an exception occurs, the OS 10 refers to the IDT 110 and calls the OS exception interrupt handling function 120 corresponding to the exception. The IDT 110 and the OS exception interrupt handling function 120 are general OS functions.

The OS initial completion notification function 130 notifies the BIOS 20 that the initialization of the IDT 110 is completed. A general OS does not have this function. In the boot flow of a server or the like, the initialization of ACPI (Advanced Configuration and Power Interface) is started after the initialization of the IDT 110 is completed. The OS initial completion notification function 130 can be implemented, for example, so as to be triggered by the execution of “\_SB._INI”, which is the trigger for starting the initialization of ACPI. Alternatively, the OS initial completion notification function 130 may be implemented as a daemon service application that detects the completion of initialization of the IDT 110 and notifies the BIOS 20 of that fact, and may be automatically executed.

The BIOS 20 includes a non-SMM layer 30 and an SMM layer 40. The non-SMM layer 30 is executed when operating in non-SMM, and the SMM layer 40 is executed when operating in SMM.
The non-SMM layer 30 includes an SMI issuing function 310, a Debug/Release switching function 320, a BIOS exception interrupt handling function 330, an IDT rewriting function 340, and an assertion handling function 350.

The SMI issuing function 310 issues an SMI. As mentioned above, the SMI is an interrupt for populating the SMM. In this embodiment, the issuance of the SMI is used to call the debug function 410 of the SMM layer 40, which will be described later.
The Debug/Release switching function 320 is a function for switching the current operation mode to either the detailed analysis mode (debug) or the shipping mode (release). For this function, for example, a setting file in which any operation mode is set may be stored in the OS, and the operation mode may be switched according to the setting. Alternatively, any operation mode may be set as a UEFI variable that is an environment variable related to UEFI (Unified Extensible Firmware Interface), stored in a nonvolatile medium, and the operation mode may be switched by reading the setting. In addition, the Debug/Release switching function 320 can determine the current operation mode based on the setting file and the like.

The BIOS exception interrupt handling function 330 determines whether a BIOS exception interrupt or an OS exception interrupt occurs when an exception interrupt occurs, and calls the OS exception interrupt handling function 120 or the SMI issuing function 310. Next, as will be described with reference to FIGS. 2 and 3, the BIOS exception interrupt handling function 330 behaves like an exception interrupt handler.
The IDT rewriting function 340 rewrites the IDT 110 and enables the BIOS exception interrupt handling function 330. In one implementation, the IDT rewrite function 340, for a predetermined exception registered in the IDT 110 after the initialization (for example, PageFut exception), the interrupt number (interrupt vector) corresponding to the exception, and the BIOS exception interrupt. A memory address for calling the handling function 330 is associated and registered. In other words, the IDT rewriting function 340 rewrites the IDT 110 so that the BIOS exception interrupt handling function 330 is called when the rewritten exceptions occur.
The assertion handling function 350 is a function that calls the SMI issuing function 310 when an assertion occurs. This function will be described later with reference to FIG.

The SMM layer 40 has a debug function 410.
The debug function 410 is a function for debugging the BIOS. The debug function 410 is a function included in a general BIOS. The debug function 410 includes, for example, a register dump, a memory dump, and an interactive debug function.

<First embodiment>
(BIOS exception interrupt handling function)
Next, the calling process of the debug function in the first embodiment will be described. First, the BIOS exception interrupt handling function 330 will be described with reference to FIG.
FIG. 2 is a diagram illustrating handling of a BIOS exception interrupt according to the first embodiment of the present invention.
When an exception occurs and the call is received, the BIOS exception interrupt handling function 330 determines whether the generated interrupt is a PageFault interrupt based on the interrupt vector of the generated exception (step S200). In the case of the Page Fault interrupt (step S200; Yes), the BIOS exception interrupt handling function 330 calls the OS exception interrupt handling function 120 (step S210). Specifically, the BIOS exception interrupt handling function 330 calls an interrupt handler for PageFault interrupt. Here, the PageFault interrupt is an exception interrupt generated by hardware when a program accesses a page in a virtual address space that is not physical memory mapped. The Page Fault interrupt does not call the debug function of the BIOS because it is not a program error. Further, the BIOS exception interrupt handling function 330 internally holds a correspondence table of the exception interrupt vector registered in the IDT 110 before rewriting by the IDT rewriting function 340 and the calling address of the exception interrupt handler, and based on this correspondence table. Then, the OS exception interrupt handling function 120 is called according to the exception.

When it is not the Page Fault interrupt (step S200; No), the BIOS exception interrupt handling function 330 determines whether the memory address where the exception occurred is outside the BIOS area (step S220). In a general CPU such as x86 architecture, when an exception interrupt occurs, the instruction address and the exception interrupt factor at the time of the exception interrupt are stored in a register of the CPU. The BIOS exception interrupt handling function 330 can determine whether an exception interrupt has occurred in the BIOS area by checking whether the instruction address at the time of the exception interrupt occurrence is the BIOS area (code area). The BIOS code area can be determined by referring to the UEFI Memory Map generated by the BIOS.

If it is outside the BIOS area (step S220; Yes), the BIOS exception interrupt handling function 330 calls the OS exception interrupt handling function 120 corresponding to the exception (step S230).
If it is within the BIOS area (step S220; No), the BIOS exception interrupt handling function 330 calls the SMI issuing function 310 (step S240).
By making the BIOS exception interrupt handling function 330 callable in this way, when an exception occurs in the BIOS code area, it is possible to transfer to the SMM by issuing an SMI. Next, an example of processing for making the BIOS exception interrupt handling function 330 callable will be described with reference to FIG.

(Initialize the BIOS exception interrupt handling function)
FIG. 3 is a flowchart showing an example of initialization processing at OS startup according to the first embodiment of the present invention.
A process (initialization) for registering in the IDT 110 so that the BIOS exception interrupt handling function 330 can be called when the OS 10 is activated will be described with reference to FIG.
First, the OS 10 initializes the OS exception interrupt handling function 120 (step S310). For example, the OS 10 makes various handlers executable so that the interrupt handler can be called when various exceptions occur.
Next, the OS 10 initializes the IDT 110 (step S320). For example, the OS 10 registers exception interrupt handlers corresponding to various exception interrupt vectors in the IDT 110.
Next, the OS 10 executes the OS initialization completion notification function 130. The OS initialization completion notifying function 130 notifies the BIOS 20 of the completion of initialization of the IDT 110 (step S330).
Upon receiving the initialization completion notification of the IDT 110, the BIOS 20 confirms the current operation mode by the Debug/Release switching function 320 (step S340). If the current operation mode is Release (shipping mode), this initialization processing ends.
When the current operation mode is Debug (detailed analysis mode), the BIOS 20 calls the IDT rewriting function 340 (step S350). The IDT rewriting function 340 registers in the IDT 110 so that the BIOS exception interrupt handling function 330 can be called. For example, the IDT rewrite function 340 registers a predetermined interrupt vector and the address of the BIOS exception interrupt handling function 330 in association with each other in the initialized IDT 110. This enables the BIOS exception interrupt handling function 330 to be called when an exception indicated by a predetermined interrupt vector occurs. As described with reference to FIG. 2, the BIOS exception interrupt handling function 330 calls the OS exception interrupt handling function 120 corresponding to the exception if the exception generation area is not the BIOS code area based on the exception interrupt vector. If the exception generation area is the BIOS code area, the SMI issuing function 310 is called.

(Debugger call processing)
Next, a process of calling the BIOS debugger when the SMI issuing function 310 is called will be described with reference to FIG.
FIG. 4 is a flowchart showing an example of calling processing of the BIOS debugger according to the first embodiment of the present invention.
It is assumed that the BIOS exception interrupt handling function 330 is registered in the IDT 110 by the processing described in FIG. 3, an exception occurs, and the SMI issuing function 310 is called by the processing described in FIG.
First, the SMI issuing function 310 stores predetermined debug request information in the memory area secured by the BIOS (step S410). Next, the SMI issuing function 310 issues an SMI (step S420). For example, when a chip equipped with a PCH (Platform Controller Hub) is mounted, an SMI can be issued by writing a predetermined value in the IO address of the Advanced Power Management Control Port of the PCH.

When the SMI is issued, the operation of the processor transits to SMM. The SMM layer 40 saves the information (context) when the SMI interrupt occurs in the memory (SMM protected memory) (step S430). At this time, the debug request information stored in step S410 is also stored in the memory. Next, the SMM layer 40 refers to the memory and determines whether the debug request information is stored (step S440).
When the debug request information is stored (step S440; Yes), the SMM layer 40 executes the debug function 410 (step S450). The debug function 410 executes register dump and memory dump. As a result, when an OS or application in the system operating in the detailed analysis mode fails while using a service provided by the BIOS, it is possible to transfer to the SMM and activate the debugger. As a result, it is possible to collect the failure information generated in the BIOS code area (including the SMM program and the non-SMM program).

After executing step S450 or when it is determined in step S440 that there is no debug request, the processor refers to the information stored in step S430, restores the state at the SMI interrupt time (step S460), and issues the SMM end command. Issue (step S470).

According to this embodiment, it is possible to debug an exception that has occurred in the BIOS without requiring an external device. In particular, the SMM protected memory can be accessed to debug an operating SMM program.

<Second embodiment>
In the first embodiment, the method of calling the debug function of the BIOS by supplementing the BIOS exception interrupt and issuing the SMI in the detailed analysis mode has been described. In the second embodiment, an assertion is described in the non-SMM program, and the SMI issuance is performed based on the diagnosis result of the assertion. Assertions are methods and functions for expressing the processing of programs and the establishment of conditions. In the present embodiment, the following description is inserted in the part of the code of the non-SMM program that performs the diagnosis.
ASSERT (expression)
The assertion handling function 350 has a function of calling the SMI issuing function 310 according to the result of the diagnosis (the value of the evaluation expression). The assertion handling function 350 will be described with reference to FIG.
FIG. 5 is a diagram illustrating an assertion handling function according to the second embodiment of the present invention.
It is assumed that the non-SMM program in which the assertion is described is executed and ASSERT (expression) is executed. The assertion handling function 350 determines the value of the evaluation expression expression of the assertion (step S510). If the expression value is not TRUE, the assertion handling function 350 calls the SMI issuing function 310 (step S520). The process after calling the SMI issuing function 310 is the same as that described with reference to FIG. That is, by issuing the SMI, it is possible to import into the SMM and execute the debug function 410.

By providing the assertion handling function 350 in the non-SMM 30 layer 30, for example, by writing an assertion at a place where the SMM program is called from the non-SMM program, the failure information generated in the BIOS code area including the SMM protected memory can be displayed. Can be collected. The debugger calling method of the second embodiment can also be applied to the shipping mode.

Furthermore, by extending the assertion check, it is possible to improve the parseability and availability. The parameters used for the extended assertion will be described with reference to FIG.
FIG. 6 is a diagram showing an example of parameters used for an assertion according to the second embodiment of the present invention.
For example, the following expanded assertion is described in the part that diagnoses the non-SMM program.
ASSERT_EX(expression, debug_policy, debug_interactive, output_data, recovery)
An evaluation expression is set in expression among the above arguments. Further, the operation in the shipping mode is set in the debug_policy. For example, it is set whether to perform debugging in the shipping mode (release_mode_debug), only recovery (release_mode_recovery_only), or nothing (release_mode_none). In debug_interactive, whether to perform interactive debugging is set. Data required for analysis is set in output_data. For recovery, whether continuous operation is performed (recovery_mode_need), OS dump is performed (recovery_mode_dump), or nothing is performed (recovery_mode_none) is set. In addition, in the case of setting to perform continuous operation, the content of the recovery process (expression for solving the assertion factor) can be set (recovery_expression).

(Debugger call processing)
Next, the debugger calling process using the expanded assertion (ASSERT_EX) will be described more specifically with reference to FIGS. 7 and 8.
7 and 8 are a first flowchart and a second flowchart, respectively, showing an example of the calling process of the BIOS debugger according to the second embodiment of the present invention.
It is assumed that the non-SMM program in which the expanded assertion is described is being executed. The assertion handling function 350 executes the following processing for each place where the assertion is described.
First, the assertion handling function 350 determines whether the value of the evaluation expression expression of ASSERT_EX is TRUE (step S710). When the expression value is TRUE (step S710; Yes), the process of this flowchart ends. When the expression value is FALSE (step S710; No), the debug process is started. For example, when (val==1) is described in expression, if val is other than 1, the expression value becomes FALSE, so the assertion handling function 350 starts the following processing.

First, the assertion handling function 350 uses the Debug/Release switching function 320 to acquire the current operation mode (step S720). The assertion handling function 350 determines whether the current operation mode is Release and the debug_policy of ASSERT_EX is release_mode_none (step S730). If this condition is satisfied (step S730; Yes), the process of this flowchart is ended. If the condition is not satisfied (step S730; No), the assertion handling function 350 calls the SMI issuing function 310 (step S740). Then, as described using FIG. 4, the SMI issuing function 310 stores the debug request information in the memory and issues the SMI. When the SMI is issued, the operation of the processor transits to SMM.

The SMM layer 40 saves the information (context) when the SMI interrupt occurs in the memory (SMM protected memory) (step S750). At this time, the debug request information stored by the SMI issuing function 310 is also stored in the memory. Next, the SMM layer 40 refers to the memory and determines whether the debug request information is stored (step S760). When the debug request information is not stored (step S760; No), the processes after step S860 are performed (described later).

When the debug request information is stored (step S760; Yes), the SMM layer 40 executes the debug function 410. The debug function 410 acquires information on the current operation mode acquired by the Debug/Release switching function 320 in step S720 (step S770). The debug function 410 determines whether the current operation mode is Debug and the debug_interactive of ASSERT_EX is set to true (step S780). When this condition is satisfied (step S780; Yes), the debug function 410 executes the interactive debug function (step S790). This allows the user to interactively debug.

When the condition is not satisfied (step S780; No), the debug function 410 determines whether the current operation mode is Release and the release_mode_recovery_only of ASSERT_EX is set to false (step S800). When this condition is satisfied (step S800; Yes), the debug function 410 displays the information specified by output_data of ASSERT_EX (step S810). For example, when variables val_a, val_b, and val_c are set to output_data as (val_a; val_b; val_c) as values required for debugging, the values of val_a, val_b, and val_c at the time of program execution are displayed.
After execution of step S810 or when the determination in step S800 is No, the debug function 410 next determines whether recovery_mode_need is set in the recovery of ASSERT_EX (step S820). If this condition is satisfied, the debug function 410 executes the recovery process specified by recovery_expression (step S830). For example, when recovery_expression is set to (val_a=2;), val_a=2 is executed in step S830.

When the condition is not satisfied (step S820; No), the debug function 410 determines whether or not the recovery_mode_dump is set in the recovery of the ASSERT_EX (step S840). If this condition is satisfied, the debug function 410 executes an OS dump interrupt (step S850). Generally, an NMI (Non-Maskable Interrupt) is used for the OS dump interrupt. The NMI can be issued by using a general PCH function.

After executing any of step S790, step S830, and step S850, or when the determination of step S760 or step S840 is No, the SMM layer 40 refers to the information stored in step S750 and restores the state at the time of the SMI interrupt. Then, the SMM end command is issued (step S860) (step S870).

According to this embodiment, even in the shipping mode, it is possible to collect the failure information generated in the BIOS code area (including the SMM program and the non-SMM program). When the further expanded assertion (ASSERT_EX) is used, detailed operation designation and recovery processing can be set, so that it is possible to achieve both analyticity and availability. In particular, in the shipping mode, it is possible to collect data necessary for problem analysis while continuing normal operation of the system.

<Other Embodiments>
Although FIG. 1 shows a configuration example of the debug system 1 having the functions of both the first embodiment and the second embodiment, a configuration in which only the functions of the first embodiment are mounted may be used. is there. Specifically, in one embodiment, the debug system 1A can be configured as shown in FIG. In the debug system 1A, the OS 10 includes an IDT 110, an OS exception interrupt handling function 120, and an OS initial completion notification function 130. In the BIOS 20, the non-SMM layer 30 includes an SMI issuing function 310, a Debug/Release switching function 320, a BIOS exception interrupt handling function 330, and an IDT rewriting function 340, and the SMM layer 40 includes a debug function 410.

Further, it is possible to configure the debug system 1B shown in FIG. 10 in which only the functions of the second embodiment are mounted. In the debug system 1B in the BIOS 20, the non-SMM layer 30 includes an SMI issuing function 310, a Debug/Release switching function 320, and an assertion handling function 350, and the SMM layer 40 includes a debug function 410.

FIG. 11 is a diagram showing the minimum configuration of the debug system according to each embodiment of the present invention.
As shown in FIG. 11, the debug system 50 includes at least an exception detection unit 501, an SMI issuing unit 502, and a debug function unit 503.
The exception detection unit 501 detects an exception that occurs in the BIOS code area. The exception detection unit 501 corresponds to the BIOS exception interrupt handling function 330 and the assertion handling function 350 of the above embodiment.
The SMI issuing unit 502 issues an SMI when the exception detecting unit 501 detects an exception. The SMI issuing unit 502 corresponds to the SMI issuing function 310.
The debug function unit 503 executes the debug function using SMM. The debug function unit 503 corresponds to the debug function 410.
In one embodiment, the debug system 50 is implemented in the non-SMM layer 30 of the BIOS 20 of the above embodiments.

FIG. 12 is a diagram showing an example of a hardware configuration of an information processing apparatus equipped with a debug system according to each embodiment of the present invention.
The computer 900 includes a CPU 901, a main storage device 902, an auxiliary storage device 903, an input/output interface 904, and a communication interface 905.
The CPU 901 is a processor capable of operating in SMM. The CPU 901 is, for example, a CPU of Intel Intel 64 and IA-32 architecture. The OS 10 and the BIOS 20 described above are stored in the auxiliary storage device 903 in the form of programs. Then, the CPU 901 reads the program from the auxiliary storage device 903, expands it in the main storage device 902, and executes the above-described processing according to the program. Further, the CPU 901 secures a storage area in the main storage device 902 according to the program.

Note that in at least one embodiment, the auxiliary storage device 903 is, for example, a ROM on a motherboard, and the BIOS 20 is stored in this ROM. Further, in another embodiment, the auxiliary storage device 903 is an example of a non-transitory tangible medium. Other examples of non-transitory tangible media include magnetic disks, magneto-optical disks, CD-ROMs, DVD-ROMs, semiconductor memories, etc. connected via the input/output interface 904. Further, when this program is distributed to the computer 900 via a communication line, the computer 900 that has received the distribution may expand the program in the main storage device 902 and execute the above processing. Further, the program may be for realizing some of the functions described above. Further, the program may be a so-called difference file (difference program) that realizes the above-mentioned function in combination with another program already stored in the auxiliary storage device 903. Further, the auxiliary storage device 903 may be configured as a separate body from the arithmetic device including the CPU 901.

In addition, it is possible to appropriately replace the components in the above-described embodiments with known components without departing from the spirit of the present invention. Further, the technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
The UEFI Memory Map is an example of the range of the address area assigned to the BIOS.

1, 1A, 1B, 50... Debug system 10... OS
110... IDT
120...OS exception interrupt handling function 130...OS initialization completion notification function 20...BIOS
30... Non-SMM layer 310... SMI issuing function 320... Debug/Release switching function 330... BIOS exception interrupt handling function 340... IDT rewriting function 350... Assertion handling function 40... SMM layer 410... Debug function 501... Exception detection unit 502... SMI issuing unit 503... Debug function unit 900... Computer 901... CPU
902... Main storage device 903... Auxiliary storage device 904... Input/output interface 905... Communication interface

Claims (10)

An exception detection unit that detects exceptions that occur in BIOS (Basic Input/Output System),
An SMI issuing unit that issues an SMI (System Management Interrupt) when the exception detecting unit detects an exception;
A debug function unit that executes a debug function in SMM (System Management Mode),
Debug system with. The exception detection unit detects the occurrence of the exception based on a function of detecting an exception interrupt included in the operating system, and based on the detected address of the occurrence place of the exception and the range of the address area assigned to the BIOS. , Detect exception in BIOS,
The debug system according to claim 1. The exception detection unit,
An interrupt handler registered in the IDT in association with a predetermined exception interrupt vector,
The debug system according to claim 1 or 2. The exception detection unit detects the occurrence of an exception in the BIOS based on the value of the assertion evaluation expression described in the BIOS program.
The debug system according to any one of claims 1 to 3. In the assertion, in addition to the evaluation expression, settings relating to execution of a debugger when the value of the evaluation expression is not True can be set.
The debug system according to claim 4. In the setting related to the execution of the debugger, it is possible to set whether to start the debugger during normal operation of the system,
The debug system according to claim 5. The assertion can further set recovery processing for the program.
The debug system according to claim 5 or 6. An exception detection unit that detects an exception that occurs in the BIOS in the non-SMM layer,
An SMI issuing unit that issues an SMI when the exception detecting unit detects an exception;
A debug function unit that executes the debug function in SMM,
BIOS with. A processor capable of operating in SMM,
BIOS according to claim 8,
An information processing apparatus including. Detecting an exception that occurs in the BIOS,
Issuing an SMI when the exception is detected,
Executing a debug function in the SMM transitioned by issuing the SMI;
A debugging method having.

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