JP2020027509A - Relay system - Google Patents

Abstract

To activate each of a first CPU and a second CPU before another processing means is activated.SOLUTION: In a relay system, a controller 50 includes: a first CPU, which is activated by reading a first activation program and executing processing; a second CPU, which is activated by reading a second activation program and executing processing; an HDD module for storing the first and second activation programs; an IF switch for relaying sending of the data stored in the module to the first and second CPUs; first communication paths 57 and 58 for connecting the first CPU and the IF switch; and a second communication unit 59 for switching the second CPU and the IF switch. The IF switch receives a request to read data through one of the first and second communication paths, reads the requested data from storage means through a rapid communication path 60, and sends the data through a communication path for which the request to read has been accepted.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a relay system.

In Patent Document 1, a high-speed device is connected to a switch having a buffer via a high-speed interface enabling high-speed data transfer, and the switch is connected to a plurality of low-speed interfaces via a plurality of low-speed interfaces enabling low-speed data transfer. A configuration connected to a device is disclosed.
Patent Literature 2 discloses that a path for the first CPU to access the HDD is automatically switched according to whether the second CPU is operating or not operating.

Japanese Patent No. 5057833 JP 2005-135269 A

There is a technique for controlling the operation of a device using a first processing unit and a second processing unit, each of which executes a process. The first processing means and the second processing means are activated by respectively reading an activation program from the storage means.
Here, the second processing means may be provided so as to be able to acquire a start-up program of the storage means via the first processing means. In this case, the second processing means is activated until the first processing means is started. The means cannot read the start-up program, and the second processing means has to wait for the start until the first processing means starts.

  An object of the present invention is to activate each of the first processing unit and the second processing unit without waiting for the activation of the other processing unit.

According to the first aspect of the present invention, a first processing unit that starts by reading a first startup program and executes a process, and a second processing unit that starts by reading a second startup program and executes a process. Processing means, storage means for storing the first startup program and the second startup program, and storage of data stored in the storage means to the first processing means and the second processing means. A relay unit that relays the transfer, a first communication path that connects the first processing unit and the relay unit, and forms a path through which a data read request from the first processing unit passes; And a second communication path that connects the second processing means and the relay means, and forms a path through which a data read request from the second processing means passes. The first data The data is transmitted to the relay means via a communication path and a high-speed communication path having a higher speed when data passes than the second communication path, and the relay means includes the first communication path and the second communication path. When a data read request is received via any of the above, the requested data is read from the storage means via the high-speed communication path, and the data is transmitted via the communication path to which the read request passed. A relay system, characterized in that:
According to a second aspect of the present invention, the first processing means and the relay means are connected to each other, and a speed at which data passes through the first communication path and the second communication path is higher. A third communication path that can be used after activation of the first processing means, wherein the second processing means stores the third communication path in the storage means via the first processing means and the third communication path; 2. The relay system according to claim 1, wherein stored data is acquired.
According to a third aspect of the present invention, the storage means includes a first storage area for storing the first startup program, a second storage area for storing the second startup program, and the third communication. A third storage area for storing data specified by a data read request received by the relay means via a channel, and a third storage area for storing data designated by the relay means via the third communication path. 3. The relay system according to claim 2, wherein the storage destination of the data specified in the third storage area coincides with a storage destination in the third storage area.
According to a fourth aspect of the present invention, in the storage device, the first storage area for storing the first startup program, the second storage area for storing the second startup program, and the relay unit being activated. A third storage area for storing data specified by a read request received from the first processing unit and / or the second processing unit after activation; 2. The relay according to claim 1, wherein data can be read from each of the first storage area, the second storage area, and the third storage area via a high-speed communication path. System.
According to a fifth aspect of the present invention, the third processing means and the relay means are connected to each other, and the third processing means has a third data transfer speed higher than that of the first communication path and the second communication path. Further comprising a communication path, wherein the relay unit, upon receiving a data read request via the third communication path, transmits the data stored in the third storage area via the high-speed communication path. The method according to claim 4, wherein the data is read and the data is transmitted through the third communication path, and the third communication path and the high-speed communication path are configured by communication paths of the same standard. It is a relay system.
The invention according to claim 6, wherein the relay unit acquires the data related to the read request from a storage area of the storage unit corresponding to a communication path through which the data read request has passed. It is a relay system of description.
The invention according to claim 7, wherein the storage means has a first storage area for storing the first activation program and a second storage area for storing the second activation program, and the relay means Acquiring the data associated with the read request from the first storage area when the communication path through which the data read request has passed is the first communication path, and setting the communication path through which the data read request has passed through the 7. The relay system according to claim 6, wherein when the communication path is the second communication path, data related to the read request is acquired from the second storage area.
The invention according to claim 8, wherein the relay means includes a storage destination of data specified by a data read request received via one of the first communication path and the second communication path. A management unit is provided for managing storage location information associated with a storage location of data stored in the storage unit. When the relay unit receives the read request, the relay unit receives a request specified by the read request. 2. The relay system according to claim 1, wherein data corresponding to a storage destination of the storage unit associated with a storage destination in the storage destination information is read.

According to the first aspect of the invention, each of the first processing means and the second processing means can be activated without waiting for the activation of the other processing means.
According to the second aspect of the present invention, when a data path passes faster than the second communication path without connecting the communication path having a higher speed when data passes than the second communication path to the second processing means. The second processing means can acquire the data via the high-speed communication path.
According to the third aspect of the present invention, the relay unit reads the data from the storage unit without replacing the storage destination of the data specified by the read request received via the third communication path with another storage destination. Request can be made.
According to the fourth aspect of the present invention, one of the communication paths used for transmitting the data stored in the first storage area, the second storage area, and the third storage area of the storage means to the relay means. There is no need to provide a communication path other than the high-speed communication path.
According to the fifth aspect of the present invention, the relay unit reads the data from the storage unit without replacing the storage destination of the data specified by the read request received via the third communication path with another storage destination. Request can be made.
According to the invention of claim 6, it is possible to set the communication path through which the data read request passes and the data acquired from the storage means in association with the type of the processing means which has issued the read request.
According to the seventh aspect of the present invention, the relay unit can acquire a startup program for starting the processing unit that has issued the read request in accordance with the communication path through which the data read request has passed.
According to the invention of claim 8, even if the communication path connecting the processing means and the relay means and the communication path connecting the relay means and the storage means have different standards, the processing means makes a read request. Data can be read from the storage means.

FIG. 1 is a diagram illustrating an example of a configuration of an image forming system. It is a block diagram showing an example of the internal structure of a control part. FIG. 2 is a diagram illustrating an example of an internal configuration of an HDD module. 5 is a flowchart illustrating a flow of a startup process of the image forming apparatus. 5 is a flowchart illustrating a flow of a data read process performed by a first CPU after a communication protocol of a first high-speed bus is established. FIG. 9 is a diagram illustrating a modification of the internal configuration of the HDD module. FIG. 3 is a diagram illustrating a configuration of a control unit to which an option board is connected.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Configuration of Image Forming System>
FIG. 1 is a diagram illustrating an example of the configuration of the image forming system according to the present embodiment.
The image forming system according to the present embodiment includes an image forming apparatus 1, a terminal device 3, a facsimile device 4, and a server device 5. The image forming apparatus 1 and the terminal apparatus 3, the image forming apparatus 1 and the facsimile apparatus 4, and the image forming apparatus 1 and the server apparatus 5 are connected via the network 2.
The image forming apparatus 1 has a scan function, a print function, a copy function, and a facsimile function.

  The network 2 is an information communication network that performs communication between the image forming apparatus 1 and the terminal device 3, communication between the image forming apparatus 1 and the facsimile apparatus 4, and communication between the image forming apparatus 1 and the server apparatus 5. The type of the network 2 is not particularly limited as long as data can be transmitted and received, and may be, for example, the Internet, a LAN (Local Area Network), a WAN (Wide Area Network), or the like. A communication line used for data communication may be wired or wireless. The network 2 connecting the image forming apparatus 1 and the terminal device 3, the network 2 connecting the image forming apparatus 1 and the facsimile apparatus 4, and the network 2 connecting the image forming apparatus 1 and the server 5 are common. Network 2 or a different network. Although not particularly shown, the network 2 may be provided with a relay device such as a gateway or a hub for connecting a network or a communication line.

The terminal device 3 is a computer device operated by a user when printing a document. The terminal device 3 issues an instruction such as printing to the image forming apparatus 1 via the network 2. The terminal device 3 is realized by, for example, a computer, a tablet information terminal, or another information processing device.
The facsimile apparatus 4 transmits and receives a facsimile to and from the image forming apparatus 1 via the network 2.
The server device 5 is a server that transmits and receives data to and from the image forming apparatus 1 via the network 2. The server device 5 is realized by, for example, a computer. The server device 5 may be configured by a single computer, or may be realized by distributed processing by a plurality of computers.

  Further, the image forming apparatus 1 includes an image reading unit 10 that reads an image formed on a recording medium such as paper, an image forming unit 20 that forms an image on a recording medium, and an instruction from a user. A user interface (UI) 30 for displaying a message. The image forming apparatus 1 includes a transmitting / receiving unit 40 for transmitting / receiving data to / from the terminal device 3, the facsimile device 4, and the server device 5 via the network 2, and an operation of the image forming unit 20, the UI 30, and the transmitting / receiving unit 40. And a control unit 50 for controlling

  In the image forming apparatus 1, a scanning function is realized by the image reading unit 10, a printing function is realized by the image forming unit 20, and a copying function is realized by the image reading unit 10 and the image forming unit 20. The facsimile function is realized by the forming unit 20 and the transmitting / receiving unit 40.

<Internal structure of control unit 50>
FIG. 2 is a block diagram showing an example of the internal structure of the control unit 50.
The control unit 50 includes a first CPU 51A, a second CPU 51B, a first DRAM 53, a second DRAM 54, an HDD (Hard Disk Drive) module 55, and an interface (IF) switch 56. The control unit 50 includes a first low-speed bus 57 connecting the first CPU 51A and the IF switch 56, a first high-speed bus 58 connecting the first CPU 51A and the IF switch 56, and a second CPU 51B and the IF switch 56. , A second high-speed bus 60 connecting the IF switch 56 and the HDD module 55, and a third high-speed bus 52 connecting the first CPU 51A and the second CPU 51B. ing.

As the first low-speed bus 57 and the second low-speed bus 59 of the present embodiment, buses based on the SPI (Serial Peripheral Interface) communication standard are used.
In addition, as the first high-speed bus 58, the second high-speed bus 60, and the third high-speed bus 52 of the present embodiment, buses based on the SATA (Serial AT Attachment) communication standard are used.

The data transfer speed of the first high-speed bus 58 is higher than the transfer speed of the first low-speed bus 57 or the second low-speed bus 59.
The data transfer speed of the second high-speed bus 60 as an example of the high-speed communication path is higher than the transfer speed of the first low-speed bus 57 and the second low-speed bus 59.
The data transfer speed of the third high-speed bus 52 is higher than the transfer speed of the first low-speed bus 57 or the second low-speed bus 59.

The first CPU 51A as an example of a first processing unit controls the operation of the entire image forming apparatus 1. The first CPU 51A executes processing while exchanging data with the first DRAM 53.
The second CPU 51 </ b> B as an example of a second processing unit performs processing on image data input from the image reading unit 10 and image data output to the image forming unit 20. The second CPU 51B executes processing while exchanging data with the second DRAM 54. In the following, when the first CPU 51A and the second CPU 51B are not distinguished, they are simply referred to as the CPU 51.
Each of the first DRAM 53 and the second DRAM 54 is a volatile memory.

The HDD module 55 as an example of a storage unit stores a first boot program. The first CPU 51A is activated by reading the first boot program. Specifically, the first CPU 51 </ b> A is activated by expanding the first boot program read from the HDD module 55 on the first DRAM 53. Here, the first boot program is regarded as a first boot program.
Further, the HDD module 55 stores a second boot program. The second CPU 51B is activated by reading the second boot program. Specifically, the second CPU 51B is activated by expanding the second boot program read from the HDD module 55 on the second DRAM 54. Here, the second boot program is regarded as a second boot program.
The HDD module 55 is a nonvolatile memory.

  The IF switch 56 as an example of a relay unit relays the transfer of data stored in the HDD module 55 to the first CPU 51A and the second CPU 51B. Specifically, upon receiving a request to read data stored in the HDD module 55 from the first CPU 51A or the second CPU 51B, the IF switch 56 reads the requested data from the HDD module 55 and transmits the read data to the requesting CPU 51. I do.

  Further, the IF switch 56 is provided with an address conversion table 561 as an example of a management unit. The address conversion table 561 is a table in which address information on the second high-speed bus 60 is associated with address information on the first low-speed bus 57 and address information on the second low-speed bus 59.

  Specifically, in the address conversion table 561, the first boot program stored in the HDD module 55 is included in the address information included in the first boot program read request received by the IF switch 56 via the first low-speed bus 57. Address information corresponding to the program is associated with the program. The address information included in the read request of the second boot program received by the IF switch 56 via the second low-speed bus 59 is associated with the address information corresponding to the second boot program stored in the HDD module 55. Have been. The information shown in the address conversion table 561, that is, the address information specified by the data read request received via one of the first low-speed bus 57 and the second low-speed bus 59 and the HDD module Information associated with the address information corresponding to the data stored in 55 is regarded as storage destination information.

  When receiving the read request of the first boot program or the read request of the second boot program, the IF switch 56 refers to the address conversion table 561. Then, a read request is made to the HDD module 55, replacing the address information with the address information associated with the address conversion table 561.

Note that, in the present embodiment, as described above, the first high-speed bus 58 and the second high-speed bus 60 are configured by communication paths of the same standard.
Therefore, the address information included in the data read request received by the IF switch 56 via the first high-speed bus 58 matches the address information corresponding to the data stored in the HDD module 55. Therefore, when receiving a data read request via the first high-speed bus 58, the IF switch 56 issues a read request to the HDD module 55 without referring to the address conversion table 561. In other words, when receiving a data read request via the first high-speed bus 58, the IF switch 56 makes a read request to the HDD module 55 without performing address conversion.

  In the present embodiment, the first CPU 51A, the second CPU 51B, the first DRAM 53, the second DRAM 54, the HDD module 55, the IF switch 56, the first low speed bus 57, the first high speed bus 58, the second low speed bus 59, the second The high-speed bus 60 and the third high-speed bus 52 are regarded as a relay system that relays the transfer of data stored in the HDD module 55 to the CPU 51.

<Internal Configuration of HDD Module 55>
Next, the internal configuration of the HDD module 55 will be described.
FIG. 3 is a diagram showing an example of the internal configuration of the HDD module 55.
The HDD module 55 has an HDD 551 and an internal controller 552.

The HDD 551 includes a first boot program storage area A1, a second boot program storage area A2, a program storage area A3, and a work area A4.
The first boot program storage area A1 as an example of the first storage area is an area where the first boot program is stored.
The second boot program storage area A2 as an example of the second storage area is an area where the second boot program is stored.
The program storage area A3 is an area in which a program file to be executed by the first CPU 51A or the second CPU 51B after the start-up processing of the image forming apparatus 1 is completed is stored.
The work area A4, which is an example of the third storage area, is an area in which data and the like generated by processing by the first CPU 51A and the second CPU 51B and execution of a program are temporarily stored.

The internal controller 552 exchanges data with the IF switch 56, and controls reading and writing of data from and to the HDD 551.
Upon receiving the data read request from the IF switch 56, the internal controller 552 extracts the requested data from the storage area of the data corresponding to the address information included in the read request from the storage area of the HDD 551, and Send to

<Startup process of image forming apparatus 1>
Next, a start process of the image forming apparatus 1 will be described.
FIG. 4 is a flowchart illustrating a flow of the startup processing of the image forming apparatus 1. The activation process of the image forming apparatus 1 is executed, for example, when a reset instruction is input to the CPU 51 when the power of the image forming apparatus 1 is turned on via the UI 30 (see FIG. 1).

  When the CPU 51 receives the reset instruction, the reset is executed by the CPU 51 (S101). Specifically, the first CPU 51A clears the contents stored in the first DRAM 53. Further, the stored contents of the second DRAM 54 are cleared by the second CPU 51B.

In the present embodiment, when the storage content of the first DRAM 53 is cleared, data cannot be transmitted / received via the first high-speed bus 58 until the communication protocol of the first high-speed bus 58 is established. On the other hand, even if the storage contents of the first DRAM 53 and the storage contents of the second DRAM 54 are cleared, the communication protocol of the first low-speed bus 57 and the second low-speed bus 59 has been established, and the communication via the first low-speed bus 57 has been established. Data transmission / reception and data transmission / reception via the second low-speed bus 59 can be performed. That is, the first low-speed bus 57 is a bus used when the first CPU 51A is started. The second low-speed bus 59 is a bus used when the second CPU 51B is started.
In the present embodiment, the first low-speed bus 57 is regarded as a first communication path. Further, the second low-speed bus 59 is regarded as a second communication path. Further, the first high-speed bus 58 is regarded as a third communication path.

  Subsequently, the IF switch 56 receives a data read request from the CPU 51 (S102). More specifically, the IF switch 56 receives a boot program read request from the CPU 51.

  The IF switch 56 requests the HDD module 55 to read the boot program (S103). Specifically, the IF switch 56 replaces the address information included in the read request received from the CPU 51 with address information associated with the address information in the address conversion table 561, and , A read request is issued to the HDD module 55.

  Next, the IF switch 56 acquires the boot program stored in the HDD 551 from the internal controller 552 of the HDD module 55 (S104). Specifically, when receiving a read request from the IF switch 56, the internal controller 552 refers to the address information included in the read request, and corresponds to the referenced address information in the boot program stored in the HDD 551. Get the boot program. Then, the acquired boot program is transmitted to the IF switch 56 via the second high-speed bus 60.

  Subsequently, the IF switch 56 transmits a boot program to the CPU 51 (S105). Specifically, the IF switch 56 transmits the acquired boot program to the CPU 51 that has received the read request. If the IF switch 56 has received a boot program read request via the first low-speed bus 57, the IF switch 56 acquires the first boot program and sends the first boot program to the first CPU 51A via the first low-speed bus 57. Send. When a request to read a boot program has been received via the second low-speed bus 59, the second boot program is acquired, and the second boot program is transmitted to the second CPU 51B via the second low-speed bus 59.

Subsequently, the CPU 51 reads and starts the boot program (S106). When the first CPU 51A obtains the first boot program in step 105, the first CPU 51A starts by expanding the first boot program in the first DRAM 53. Further, when the second CPU 51B acquires the second boot program in step 105, the second CPU 51B starts by expanding the second boot program in the second DRAM 54.
Further, the first CPU 51A acquires a program necessary for establishing a communication protocol of the first high-speed bus 58 from the HDD 551, and develops this program in the first DRAM 53, thereby establishing a communication protocol of the first high-speed bus 58. .

  As described above, in the present embodiment, upon receiving a data read request via one of the first low-speed bus 57 and the second low-speed bus 59, the IF switch 56 transmits the requested data to the HDD module 55. From the HDD module 55 via the second low-speed bus 57 and the second low-speed bus 59 to which the read request has passed.

Here, the second CPU 51B may acquire and start the second boot program from the HDD module 55 via the first CPU 51A. In this case, the second CPU 51B cannot read the second boot program until the first CPU 51A is activated, and the activation of the second CPU 51B is waited until the first CPU 51A reads and activates the first boot program.
On the other hand, when each of the first CPU 51A and the second CPU 51B is configured to be able to read the boot program irrespective of the activation of the other CPU 51 as in the present embodiment, each of the first CPU 51A and the second CPU 51B is replaced with the other CPU 51A. Can be activated without waiting for activation.

  In particular, in the present embodiment, an IF switch 56 is provided between the first CPU 51A and the second CPU 51B and the HDD module 55, and the IF switch 56 transmits and receives data to and from the HDD module 55 via the second high-speed bus 60. .

  Further, in this embodiment, the address of the data specified by the data read request received by the IF switch 56 via one of the first low-speed bus 57 and the second low-speed bus 59 is provided to the IF switch 56. An address conversion table 561 for managing storage destination information in which information is associated with address information corresponding to data stored in the HDD module 55 is provided. Then, when receiving the read request, the IF switch 56 reads data corresponding to the address information of the HDD module 55 associated with the address information specified by the read request in the address conversion table 561.

  In this case, even if the communication path connecting the CPU 51 and the IF switch 56 is different from the communication path connecting the IF switch 56 and the HDD module 55, the data requested by the CPU 51 to read is stored in the HDD module 55. Is read from.

<Data reading process after activation of image forming apparatus 1>
Next, a data read process performed by the first CPU 51A after the communication protocol of the first high-speed bus 58 is established will be described.
FIG. 5 is a flowchart showing a flow of a data reading process by the first CPU 51A after the communication protocol of the first high-speed bus 58 is established.
First, the first CPU 51A issues a data read request to the IF switch 56 (S201). Specifically, the first CPU 51A issues a data read request to the IF switch 56 via the first high-speed bus 58.

  Next, the IF switch 56 issues a data read request to the HDD module 55 via the second high-speed bus 60 (S202). If the bus to which the data read request has passed is the first high-speed bus 58, the IF switch 56 sends the request to the HDD module 55 via the second high-speed bus 60 without referring to the address conversion table 561. A data read request is made.

  Subsequently, the IF switch 56 acquires data related to the read request from the HDD module 55, and transmits the acquired data to the first CPU 51A (S203). Specifically, the internal controller 552 of the HDD module 55 acquires data corresponding to the address information included in the read request from the data stored in the HDD 551, and transmits the acquired data to the second high-speed bus 60. And sends it to the IF switch 56 via the Then, the IF switch 56 transmits the acquired data to the first CPU 51A via the first high-speed bus 58.

  When the second CPU 51B issues a data read request via the first CPU 51A, first, the second CPU 51B issues a data read request to the first CPU 51A via the third high-speed bus 52. Subsequently, after the processing of steps 201 to 203 shown in FIG. 5 is performed, the first CPU 51A transmits the acquired data to the second CPU 51B via the third high-speed bus 52.

  As described above, in the present embodiment, after the first CPU 51A is activated, the first high-speed bus 58 is used for a data read request by the first CPU 51A. Further, after the first CPU 51A and the second CPU 51B are activated, the first high-speed bus 58 is used for a data read request by the second CPU 51B.

As described above, in the present embodiment, the IF switch 56 is connected to the HDD module corresponding to the bus of the first low-speed bus 57, the first high-speed bus 58, and the second low-speed bus 59 that has passed the data read request. Data related to the read request is obtained from the 55 storage areas.
Specifically, the IF switch 56 acquires the first boot program from the first boot program storage area A1 of the HDD 551 when the bus through which the data read request has passed is the first low-speed bus 57. If the bus from which the data read request has passed is the second low-speed bus 59, the second boot program is acquired from the second boot program storage area A2 of the HDD 551. Further, when the bus to which the data read request has passed is the first high-speed bus 58, the data related to the read request is acquired from the work area A4 of the HDD 551.

  In the present embodiment, the HDD module 55 is specified by a read request received from the first CPU 51A and / or the second CPU 51B after the boot by the first boot program storage area A1, the second boot program storage area A2, and the IF switch 56. A work area A4 for storing data to be stored. Then, the IF switch 56 reads data from each of the first boot program storage area A1, the second boot program storage area A2, and the work area A4 via the second high-speed bus 60.

  In this case, the second high-speed bus is used as a bus used to transmit data stored in the first boot program storage area A1, the second boot program storage area A2, and the work area A4 of the HDD module 55 to the IF switch 56. There is no need to provide a bus other than the bus 60.

<Modification>
Subsequently, a modified example of the internal configuration of the HDD module 55 will be described.
FIG. 6 is a diagram showing a modification of the internal configuration of the HDD module 55.
As shown in FIG. 6, the HDD 551 is provided with a first boot program storage area A1, a second boot program storage area A2, a program storage area A3, and a work area A4. The HDD 551 has an additional boot program storage area A5.

  The additional boot program storage area A5 is an area where the additional boot program is stored. Here, the additional boot program is a boot program that is read by the CPU provided on the option board to start when the option board to which the CPU is added is provided in the control unit 50.

FIG. 7 is a diagram illustrating a configuration of the control unit 50 to which the option board is connected.
As shown in FIG. 7, an option board 61 is connected to the control unit 50. Specifically, the option board 61 and the IF switch 56 are connected by a third low-speed bus 62. The second CPU 51B and the option board 61 are connected by a fourth high-speed bus 63.
The option board 61 is provided with an additional CPU 64 and an additional DRAM 65.

As the third low-speed bus 62, a bus based on the SPI communication standard is used. As the fourth high-speed bus 63, a bus based on the SATA communication standard is used.
In the address conversion table 561, the address information included in the additional boot program read request performed via the third low-speed bus 62 is associated with the address information corresponding to the additional boot program stored in the HDD 551. Have been.

  When activating the additional CPU 64 in the activation process of the image forming apparatus 1, the additional CPU 64 requests the IF switch 56 to read the additional boot program via the third low-speed bus 62.

The IF switch 56 refers to the address conversion table 561 when the bus to which the read request for the additional boot program has passed is the third low-speed bus 62. Then, the address information included in the read request is replaced with the address information associated with the address information in the address conversion table 561, and the boot information is additionally booted to the HDD module 55 via the second high-speed bus 60. Make a program read request.
Upon receiving the read request for the additional boot program, the internal controller 552 of the HDD module 55 reads the additional boot program stored in the additional boot program storage area of the HDD 551 as data corresponding to the address information included in the read request. Then, the additional boot program is transmitted to the IF switch 56 via the second high-speed bus 60.
The IF switch 56 transmits the acquired additional boot program to the additional CPU 64 via the third low-speed bus 62.
The additional CPU 64 is activated by expanding the acquired additional boot program in the additional DRAM 65.

Further, the additional CPU 64 reads out a program for establishing the communication protocol of the fourth high-speed bus 63 from the HDD 551 and expands the program on the additional DRAM 65, whereby the communication protocol of the fourth high-speed bus 63 is established.
After the establishment of the third communication protocol, the additional CPU 64 acquires data stored in the work area A4 of the HDD 551 via the fourth high-speed bus 63, the second CPU 51B, and the first CPU 51A.

As described above, the additional boot program may be stored in the HDD 551 in advance.
In this case, the additional CPU 64 can be activated without waiting for the activation of the first CPU 51A or the second CPU 51B. Further, it is not necessary to store an additional boot program in the option board 61.

In the present embodiment, the configuration is such that the second CPU 51B and the option board 61 are connected, but the present invention is not limited to this.
For example, the first CPU 51A and the option board 61 may be connected.

In the present embodiment, buses based on the SATA communication standard are used as the first high-speed bus 58, the second high-speed bus 60, the third high-speed bus 52, and the fourth high-speed bus 63. It is not limited to.
For example, buses based on the PCIe (PCI express) communication standard may be used as the first high-speed bus 58, the second high-speed bus 60, the third high-speed bus 52, and the fourth high-speed bus 63.

  Also, in the present embodiment, the configurations (first CPU 51A, second CPU 51B, first DRAM 53, second DRAM 54, HDD module 55, IF switch 56, first low-speed bus 57, first high-speed bus 58, the second low-speed bus 59, the second high-speed bus 60, and the third high-speed bus 52) are provided in the image forming apparatus 1, but the apparatus in which the relay system is provided is the image forming apparatus 1 It is not limited to.

  Further, the present disclosure is not limited to the above-described embodiments at all, and can be implemented in various forms without departing from the gist of the present disclosure.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 50 ... Control part, 51A ... 1st CPU, 51B ... 2nd CPU, 55 ... HDD module, 56 ... IF switch, 57 ... 1st low speed bus, 58 ... 1st high speed bus, 59 ... No. 2 low-speed buses, 60 ... second high-speed buses

Claims (8)

First processing means for starting by reading the first start program and executing processing;
A second processing unit that starts up by reading a second startup program and executes processing;
Storage means for storing the first activation program and the second activation program;
Relay means for relaying transfer of data stored in the storage means to the first processing means and the second processing means;
A first communication path connecting the first processing means and the relay means, and forming a path through which a data read request from the first processing means passes;
A second communication path connecting the second processing means and the relay means, and forming a path through which a data read request from the second processing means passes;
Has,
The storage means transmits the stored data to the relay means via a high-speed communication path having a higher speed when data passes than the first communication path and the second communication path,
The relay means, upon receiving a request to read data via one of the first communication path and the second communication path, transfers the requested data from the storage means via the high-speed communication path. A relay system for reading and transmitting the data via a communication path through which the read request has passed. The first processing means and the relay means are connected, and the speed at which data passes through is faster than that of the first communication path and the second communication path, and can be used after the first processing means is started. Further comprising a third communication path,
2. The relay system according to claim 1, wherein the second processing unit acquires the data stored in the storage unit via the first processing unit and the third communication path. The storage means receives a first storage area for storing the first startup program, a second storage area for storing the second startup program, and the relay means via the third communication path. A third storage area for storing data specified by the data read request;
3. The storage destination of data specified by a data read request received by the relay unit via the third communication path matches a storage destination in the third storage area. Relay system. The storage means includes a first storage area for storing the first activation program, a second storage area for storing the second activation program, and the first processing means after activation of the relay means. And / or a third storage area for storing data specified by a read request received from the second processing means after activation.
The relay unit is capable of reading data from each of the first storage area, the second storage area, and the third storage area via one high-speed communication path. The relay system according to claim 1, wherein Connecting the first processing unit and the relay unit, further comprising a third communication path having a higher transfer speed when data passes than the first communication path and the second communication path;
Upon receiving a request to read data via the third communication path, the relay means reads the data stored in the third storage area via the high-speed communication path, and reads the data from the third communication path. Send the data via
The relay system according to claim 4, wherein the third communication path and the high-speed communication path are configured by communication paths of the same standard.   2. The relay system according to claim 1, wherein the relay unit acquires data related to the read request from a storage area of the storage unit corresponding to a communication path through which the data read request has passed. The storage means has a first storage area for storing the first startup program and a second storage area for storing the second startup program,
When the communication path through which the data read request passes is the first communication path, the relay unit acquires the data related to the read request from the first storage area, and transmits the data through the data read request. 7. The relay system according to claim 6, wherein when a path is the second communication path, data related to the read request is acquired from the second storage area. The relay means includes a storage destination of data specified by a data read request received via one of the first communication path and the second communication path and data stored in the storage means. A management unit that manages storage location information associated with the storage location of
The relay unit, upon receiving the read request, reads out data corresponding to a storage destination of the storage unit in which the storage destination specified by the read request is associated with the storage destination information. 2. The relay system according to claim 1, wherein

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