JP2020010195A - Frequency estimation device and tracking receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency estimation device and a tracking receiver capable of correctly estimating the frequency of a residual carrier wave. A frequency estimation device (10) has a discrete Fourier transform unit (6) that generates a frequency spectrum that is a complex number for each frequency point by performing a discrete Fourier transform on an orthogonal detection and a digitized received signal, and an amplitude value of the frequency spectrum. From the signal level calculation unit 73 that calculates the signal level for each frequency point based on, and the signal levels of a plurality of frequency points in a predetermined range in the vicinity of the frequency point for each frequency point, the periphery of the frequency point. Peripheral signal level calculation unit 74 that calculates the signal level, protrusion degree calculation unit 75 that calculates the degree of protrusion indicating the degree of magnitude of the signal level with respect to the peripheral signal level at each frequency point, and the received signal based on the degree of protrusion. It is provided with a residual carrier frequency estimation unit 8 for estimating the frequency of the residual carrier. [Selection diagram] Fig. 1

Description

  The present invention relates to a frequency estimation device and a tracking receiver.

  The tracking receiver estimates the frequency of the carrier of the input signal, performs capture and tracking processing, and removes extra noise using a low-pass filter in order to reduce the amount of noise during azimuth calculation. It is necessary to improve the accuracy of frequency synchronization in order to prevent the residual carrier from remaining in the input signal, but the tracking receiver becomes large due to the addition of a processing circuit or the like. Further, there is a demand for an apparatus and method for estimating and removing a residual carrier with a simple structure even in a normal communication device.

  The tracking receiver can estimate the frequency of the modulated signal using the discrete Fourier transform when the modulated signal in which the residual carrier exists is input. For example, the device described in Patent Document 1 detects a power peak value of a spectral component and estimates the frequency of a residual carrier.

Japanese Patent Application Laid-Open No. 05-136631

  However, the device described in Patent Literature 1 detects a power peak value of a spectrum component and performs reception frequency estimation. Therefore, modulation is performed by a PCM (Pulse Code Modulation) / PM (Phase Modulation) method having a large modulation factor. When the modulated signal is received, the modulated signal component may be larger than the residual carrier component. As a result, the device described in Patent Document 1 may erroneously detect a modulated signal component as a residual carrier component.

  Therefore, an object of the present invention is to provide a frequency estimating apparatus and a tracking receiver capable of correctly estimating the frequency of a residual carrier.

  The frequency estimating apparatus of the present invention includes a discrete Fourier transform unit that performs discrete Fourier transform on a quadrature detection and digitized received signal to generate a frequency spectrum that is a complex number for each frequency point, and a frequency point based on an amplitude value of the frequency spectrum. Signal level calculator for calculating a signal level for each frequency point, and for each frequency point, a signal level of a plurality of frequency points in a predetermined range near the frequency point, and calculating a peripheral signal level of the frequency point A peripheral signal level calculator, a saliency calculator for calculating a saliency indicating a magnitude of the signal level with respect to the peripheral signal level at each frequency point, and a frequency of a carrier remaining in the received signal based on the saliency. And a residual carrier frequency estimator for estimating the residual carrier frequency.

  According to the present invention, the frequency of the residual carrier can be correctly estimated.

FIG. 2 is a block diagram illustrating a configuration of a tracking receiver 1 according to Embodiment 1. (A) is a figure showing the structure of the analog receiving part 2S. (B) is a diagram illustrating a configuration of the analog receiving unit 2E. (A) is a figure showing the structure of quadrature detection part 4S. (B) is a figure showing the composition of quadrature detection part 4E. (A) is a figure showing the structure of 11 S of complex phase rotation parts. (B) is a diagram illustrating a configuration of a complex phase rotation unit 11E. FIG. 3 is a diagram illustrating a configuration of an azimuth calculating unit 12. FIG. 3 is a diagram illustrating a configuration of a window function multiplier 5. (A) is a figure showing the example of a power spectrum. (B) is a diagram showing a peripheral signal level P _N for each frequency point. (C) is a diagram showing a plurality of frequency points used for calculating the peripheral signal level _PN at the frequency point A. FIG. 3 is a schematic diagram of a power spectrum of a PCM / PM signal. FIG. 3 is a schematic diagram of a power spectrum obtained by performing a discrete Fourier transform on a PCM / PM signal. It is a figure showing the simulation result of the power spectrum of a PCM / PM signal. FIG. 4 is a schematic diagram of a protrusion degree PR for each frequency point calculated according to the first embodiment. FIG. 11 is a diagram illustrating a result of calculating a protrusion degree PR from the simulation result of FIG. 10. FIG. 13 is an enlarged view of a part of FIG. 12 in a direction of a frequency f. FIG. 9 is a block diagram illustrating a configuration of a tracking receiver 101 according to Embodiment 2. FIG. 3 is a diagram illustrating a configuration of a frequency tracking unit 9. FIG. 13 is a block diagram showing a configuration of a tracking receiver 201 according to a first modification of the second embodiment. FIG. 9 is a diagram illustrating a configuration of a phase tracking unit 209. (A) is a figure showing the structure of complex phase rotation part 211S. (B) is a diagram illustrating a configuration of a complex phase rotation unit 211E. FIG. 13 is a block diagram illustrating a configuration of a tracking receiver 301 according to Embodiment 3. (A) is a figure showing the mapping point of a QPSK signal. (B) is a figure showing the mapping point of the QPSK signal raised to the fourth power. FIG. 14 is a diagram illustrating a simulation result of raising a QPSK signal to the fourth power. FIG. 3 is a diagram illustrating a power spectrum of a QPSK signal. It is a figure showing the power spectrum of the QPSK signal raised to the fourth power. It is a figure showing the protruding degree PR of the QPSK signal raised to the fourth power. FIG. 3 is a diagram illustrating an example of a hardware configuration of frequency estimation devices 10 and 310 according to Embodiments 1 to 3.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a tracking receiver 1 according to the first embodiment. The tracking receiver 1 is mounted on a mobile body such as an aircraft, for example, and obtains a pointing direction error of an antenna mounted on the mobile body to communicate with a communication partner such as a communication satellite. A sum signal (normal signal) and a difference signal (a signal corresponding to a directional error) generated by the antenna are input to the tracking receiver 1, and the tracking receiver 1 calculates the directional error and outputs the calculated directional error. I do. The pointing direction error is input to a driving device that changes the pointing direction of the antenna, and is controlled so that the antenna faces the direction of the communication partner.

  The tracking receiver 1 uses an IF signal (Intermediate Frequency signal) as a sum signal and a difference signal. The IF signal is a signal obtained by frequency-converting an RF signal (Radio Frequency, the frequency of a radio wave) to a lower frequency. A BB signal (Base Band, a signal of information to be communicated) is extracted from the IF signal. As shown in FIG. 1, the tracking receiver 1 includes a complex sum signal generation unit 25S, a complex difference signal generation unit 25E, a frequency estimation device 10, complex phase rotation units 11S and 11E, and an azimuth calculation unit 12. Prepare.

  The complex sum signal generation unit 25S includes an analog reception unit 2S, an ADC (Analog Digital Converter) 3S, and a quadrature detection unit 4S. The complex difference signal generator 25E includes an analog receiver 2E, an ADC 3E, and a quadrature detector 4E.

  The analog receiving unit 2S performs a receiving process of the sum signal SUM-IF in the intermediate frequency band generated by the antenna. FIG. 2A is a diagram illustrating a configuration of the analog receiving unit 2S. The analog receiving unit 2S includes a band-pass filter (BPF) 21S, an amplifier (AMP) 22S, and a low-pass filter (LPF) 23S.

  The BPF 21S removes noise and spurious from the sum signal SUM-IF in the intermediate frequency band generated by the antenna. The AMP 22S amplifies the level of the signal output from the BPF 21S to an appropriate level. The LPF 23S removes high-frequency components from the signal output from the AMP 22S so that aliasing noise does not occur in the ADC 3S at the subsequent stage. The received sum signal SUM1 of the intermediate frequency band is output from LPF 23S.

  The analog receiving unit 2E executes a receiving process of the difference signal ERR-IF of the intermediate frequency band generated by the antenna. FIG. 2B is a diagram illustrating a configuration of the analog receiving unit 2E. The analog receiving unit 2E includes a band-pass filter (BPF) 21E, an amplifier (AMP) 22E, and a low-pass filter (LPF) 23E.

  The BPF 21E removes noise and spurious from the difference signal ERR-IF in the intermediate frequency band generated by the antenna. The AMP 22E amplifies the level of the signal output from the BPF 21E to an appropriate level. The LPF 23E removes a high-frequency component from a signal output from the AMP 22E so that aliasing noise does not occur in the ADC 3E at the subsequent stage. The received intermediate frequency band difference signal ERR1 is output from the LPF 23E.

  The ADC 3S converts the analog intermediate frequency band sum signal SUM1 output from the analog receiving unit 2S into a digital intermediate frequency band sum signal SUM2. The ADC 3E converts the analog intermediate frequency band difference signal ERR1 output from the analog receiving unit 2E into a digital intermediate frequency band difference signal ERR2.

  The quadrature detector 4S performs quadrature detection on the digital intermediate frequency band sum signal SUM2 output from the ADC 3S and converts it into a baseband complex sum signal (SUM3I + jSUM3Q). FIG. 3A is a diagram illustrating a configuration of the quadrature detection unit 4S. The quadrature detector 4S has a numerically controlled oscillator (NCO) 41S, a cos / sin generator 42S, multipliers 43S and 44S, and LPFs 45S and 46S.

  The NCO 41S outputs a value obtained by integrating values specified for each sampling cycle. The cos / sin generator 42S generates a complex local signal (cosξ + jsinξ) having the phase (ξ) of the value output from the numerically controlled oscillator 41S. Multiplier 43S multiplies digital sum signal SUM2 of the intermediate frequency band by cosξ. Multiplier 44S multiplies sum signal SUM2 of the digital intermediate frequency band by sinξ. The LPFs 45S and 46S remove harmonics from the multiplication results of the multipliers 43S and 44S, respectively. LPFs 45S and 46S output baseband complex sum signals (SUM3I + jSUM3Q).

  The quadrature detection unit 4E performs quadrature detection on the digital intermediate frequency band difference signal ERR2 output from the ADC 3E, and converts it into a baseband complex difference signal (ERR3I + jERR3Q). FIG. 3B is a diagram illustrating a configuration of the quadrature detection unit 4E. The quadrature detector 4E has a numerically controlled oscillator (NCO) 41E, a cos / sin generator 42E, multipliers 43E and 44E, and LPFs 45E and 46E.

  The NCO 41E outputs a value obtained by integrating values specified for each sampling cycle. The cos / sin generator 42E generates a complex local signal (cosξ + jsinξ) having the phase (ξ) of the value output from the numerically controlled oscillator 41E. The multiplier 43E multiplies the digital intermediate frequency band difference signal ERR2 by cosco. The multiplier 44E multiplies the digital intermediate frequency band difference signal ERR2 by sin と. The LPFs 45E and 46E remove harmonics from the multiplication results of the multipliers 43E and 44E, respectively. The LPFs 45E and 46E output a complex difference signal (ERR3I + jERR3Q) in the bass band.

The difference between the frequency of the complex local signal output from the cos / sin generator 42S in the quadrature detector 4S and the frequency of the carrier of the input digital intermediate frequency band sum signal SUM2 is defined as ΔF ₀ . Complex sum signal obtained by the quadrature detection by the quadrature detector 4S (SUM3I + jSUM3Q) is expressed as {I (t) + jQ ( t)} × exp (j2π × ΔF 0 × t). I (t) + jQ (t) is a baseband signal to be demodulated. ΔF ₀ is the frequency deviation. This ΔF ₀ corresponds to the frequency of the carrier remaining in the complex sum signal (SUM3I + jSUM3Q) that is the received signal.

  The frequency estimating apparatus 10 estimates a frequency deviation, that is, a residual carrier frequency which is a frequency of a carrier remaining in a complex sum signal (SUM3I + jSUM3Q) which is a digitized and orthogonally detected reception signal. Let the estimated frequency be ΔF.

  The complex phase rotator 11S converts the sign of the baseband complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S and the frequency estimation value ΔF of the residual carrier output from the frequency estimation device 10 by inverting the sign of the frequency correction value (− Based on the phase correction value (−Δθ) obtained from ΔF), a complex sum signal (SUM6I + jSUM6Q) obtained by removing the residual carrier from the complex sum signal (SUM3I + jSUM3Q) is output. By removing the residual carrier, the center of the frequency spectrum of the complex sum signal (SUM6I + jSUM6Q) becomes “0”.

FIG. 4A is a diagram illustrating a configuration of the complex phase rotation unit 11S. The complex phase rotation unit 11S includes a phase correction value calculation unit 231S and a phase rotation unit 232S.
The phase correction value calculator 231S includes a numerically controlled oscillator (NCO) 111S. The phase rotation unit 232S includes a cos / sin generation unit 112S, a complex multiplier 350S, and low-pass filters (LPFs) 115AS and 115BS. Complex multiplier 350S includes multipliers 113AS, 113BS, 113CS, and 113DS, and adders 114AS and 114BS.

  The NCO 111S receives from the frequency estimating apparatus 10 a frequency correction value obtained by inverting the sign of the frequency estimation value ΔF of the residual carrier (−ΔF) as a frequency correction value, and integrates the frequency correction value (−ΔF) to obtain a phase correction value (−Δθ). ) Is output. The cos / sin generator 112S generates a complex local signal exp (-jΔθ) of the phase correction value (-Δθ) output from the NCO 111S. The multipliers 113AS, 113BS, 113CS, 113DS multiply the baseband complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S by the complex local signal exp (-jΔθ). The adder 114AS adds the multiplication result of the multiplier 113AS and a value obtained by inverting the sign of the multiplication result of the multiplier 113BS. Adder 114BS adds the multiplication result of multiplier 113CS and the multiplication result of multiplier 113DS. The LPFs 115AS and 115BS remove extra harmonics and noise from the outputs of the adders 114AS and 114BS. LPFs 115AS and 115BS output baseband complex sum signals (SUM6I + jSUM6Q).

  A method in which the NCO 111S integrates the frequency correction value (-ΔF) to obtain the phase correction value (-Δθ) will be described. The input of the NCO 111S is the ratio F / Fs of the frequency F to the sampling frequency Fs. Here, -0.5 ≦ F / Fs <0.5. According to the sampling theorem, a signal having only a frequency component up to a frequency F equal to or less than の of the sampling frequency Fs can restore the original signal even if it is sampled. The NCO 111S can output a phase advanced by φ = (2π) × (F / Fs) for each sampling cycle (1 / Fs). Since −0.5 ≦ F / Fs <0.5, φ is −0.5 ≦ φ / (2π) <0.5. Therefore, when the frequency correction value (−ΔF) is input to the NCO 111S, the NCO 111S outputs a phase correction value (−Δθ) obtained by integrating the frequency correction value (−ΔF).

  The complex phase rotation unit 11E inverts the sign of the baseband complex difference signal (ERR3I + jERR3Q) output from the quadrature detection unit 4E and the sign of the frequency estimation value ΔF of the residual carrier output from the frequency estimation device 10 (−ΔF). Based on the obtained phase correction value (−Δθ), a complex difference signal (ERR6I + jERR6Q) obtained by removing the residual carrier from the complex difference signal (ERR3I + jERR3Q) is output. By removing the residual carrier, the center of the frequency spectrum of the complex difference signal (ERR6I + jERR6Q) becomes “0”.

FIG. 4B is a diagram illustrating a configuration of the complex phase rotation unit 11E. The complex phase rotator 11E includes a phase correction value calculator 231E and a phase rotator 232E.
The phase correction value calculator 231E includes a numerically controlled oscillator (NCO) 111E. The phase rotation unit 232E includes a cos / sin generation unit 112E, a complex multiplier 350E, and low-pass filters (LPFs) 115AE and 115BE. Complex multiplier 350E includes multipliers 113AE, 113BE, 113CE, and 113DE, and adders 114AE and 114BE.

  The NCO 111E receives from the frequency estimating apparatus 10 the frequency correction value (−ΔF) obtained by inverting the sign of the frequency estimation value ΔF of the residual carrier as a frequency correction value, and integrates the frequency correction value (−ΔF) to obtain the phase correction value (−Δθ). ) Is output. The cos / sin generator 112E generates a complex local signal exp (-jΔθ) of the phase correction value (-Δθ) output from the NCO 111E. The multipliers 113AE, 113BE, 113CE, and 113DE multiply the complex difference signal (ERR3I + jERR3Q) of the baseband output from the quadrature detector 4E by the complex local signal exp (-jΔθ). The adder 114AE adds the multiplication result of the multiplier 113AE and a value obtained by inverting the sign of the multiplication result of the multiplier 113BE. Adder 114BE adds the multiplication result of multiplier 113CE and the multiplication result of multiplier 113DE. The LPFs 115AE and 115BE remove extra harmonics and noise from the outputs of the adders 114AE and 114BE. LPFs 115AE and 115BE output baseband complex difference signals (ERR6I + jERR6Q).

  The azimuth calculating unit 12 calculates the directional error (X + jY) based on the complex sum signal (SUM6I + jSUM6Q) output from the complex phase rotation unit 11S and the complex difference signal (ERR6I + jERR6Q) output from the complex phase rotation unit 11E. Perform azimuth calculation. The directional error (X + jY) is the difference between the arriving direction, which is the direction in which the radio wave arrives, and the directional direction, which is the direction in which the antenna is pointing. FIG. 5 is a diagram illustrating a configuration of the azimuth calculation unit 12. The azimuth calculation unit 12 includes a complex division circuit 121, low-pass filters (LPFs) 122 and 123, and multipliers 124 and 125.

  The complex divider 121 divides the complex difference signal (ERR6I + jERR6Q) output from the complex phase rotator 11E by the complex sum signal (SUM6I + jSUM6Q) output from the complex phase rotator 11S, and divides the result (PX + jPY). Is output. The LPF 122 performs a smoothing process on the real part PX of the division result (PX + jPY). The multiplier 124 multiplies the signal output from the LPF 122 by the reciprocal (= 1 / γθ) of the normalized error sensitivity γθ [V / V / deg], and outputs the real part X of the directivity error. The LPF 123 performs a smoothing process on the imaginary part PY of the division result (PX + jPY). The multiplier 125 multiplies the signal output from the LPF 123 by the reciprocal (= 1 / γθ) of the normalized error sensitivity γθ [V / V / deg], and outputs the imaginary part Y of the pointing direction error.

  The complex phase rotators 11S and 11E determine that the frequency spectra of the complex sum signal (SUM6I + jSUM6Q) and the complex difference signal (ERR6I + jERR6Q) are centered on "0", so that the LPFs 122 and 123 pass through a narrow band low-pass band. It can be a filter. Since noise can be removed by the LPFs 122 and 123, the directional error can be accurately obtained.

  Referring again to FIG. 1, the configuration of the frequency estimation device 10 will be described. The frequency estimating apparatus 10 includes a window function multiplier 5, a discrete Fourier transform unit 6, a power calculating unit 71, an LPF 72, a signal level calculating unit 73, a peripheral signal level calculating unit 74, a protrusion degree calculating unit 75, and a residual carrier frequency estimating unit. 8

  The window function multiplier 5 is connected to the subsequent stage of the quadrature detection unit 4S, and multiplies a window function such as a Hanning window. FIG. 6 is a diagram illustrating a configuration of the window function multiplier 5. The window function multiplier 5 has a window function signal generator 51 and multipliers 52 and 53. The window function signal generator 51 generates a signal for a window function such as a Hanning window or a Blackman window. The multipliers 52 and 53 multiply the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detection unit 4S and the window function signal output from the window function signal generation unit 51 to output a complex sum signal (SUM4I + jSUM4Q). I do.

  The reason for using the window function will be described. The discrete Fourier transform converts from the time domain to the frequency domain on the assumption that the waveform within the observation time is repeated. The frequency of the residual carrier component is unknown, and the frequency of the residual carrier is not always an integral multiple of 1 / T0 (Hz) when the observation time T0 used in the discrete Fourier transform is one cycle. If the frequency of the residual carrier is not an integral multiple of 1 / T0 (Hz), the frequency spectrum obtained by the discrete Fourier transform has many components other than the frequency of the residual carrier, and it becomes difficult to detect the frequency of the residual carrier. The window function is a function determined so that the value near the boundary of the observation time of the discrete Fourier transform becomes small. By multiplying the input signal by the window function, the spread of the frequency component of the frequency spectrum obtained by the discrete Fourier transform can be reduced.

  The discrete Fourier transform unit 6 subjects the complex sum signal (SUM4I + jSUM4Q), which is a digitized received signal, to discrete Fourier transform to generate a frequency spectrum composed of the complex sum signal (SUM5I + jSUM5Q) for each frequency point.

  More specifically, the discrete Fourier transform unit 6 converts the complex sum signal (SUM4I + jSUM4Q) on the time axis into a complex sum signal (SUM5I + jSUM5Q) on the frequency axis by a discrete Fourier transform process. The discrete Fourier transform unit 6 may be realized by using a fast Fourier transform processing algorithm called FFT (Fast Fourier Transform).

  The power calculation unit 71 obtains the power value of each frequency point from the discrete Fourier transform result (SUM5I + jSUM5Q) of each frequency point by the square sum of the I component and the Q component. Further, the power calculator 71 may calculate the amplitude value of each frequency point by performing a route calculation of the power value of each frequency point.

  The LPF unit 72 performs a time-series smoothing process on the power value or the amplitude value of each frequency point. The LPF unit 72 performs a smoothing process on the power value or the amplitude value of each frequency point in time series using an IIR (Infinite Impulse Response) filter or the like. This makes it possible to reduce the variance of random signal components including noise.

The signal level calculating unit 73 calculates the signal level P _S of each frequency point based on the power value obtained by squaring the amplitude value of the frequency spectrum, or the amplitude value. For example, the signal level calculating unit 73 may be a power or amplitude values of the frequency spectrum which has passed through the LPF 72 and the signal level P _S. 7 (a) is a diagram illustrating an example of a power spectrum representing the signal level P _S of each frequency point. In the example of FIG. 7 (a), and the power value of the power spectrum and the signal level P _S.

Near the signal level calculating unit 74, each of the frequency points, from the signal level P _S near frequency point set is a plurality of frequency points in the range with a predetermined vicinity of the frequency points, near the signal level of the frequency point Calculate _PN . 7 (b) is a diagram showing a peripheral signal level P _N for each frequency point.

  Here, the peripheral frequency point set is determined so as not to include a predetermined number of frequency points that are continuously arranged on a frequency axis including at least the frequency point for which the peripheral signal level is to be calculated.

FIG. 7C is a diagram illustrating a plurality of frequency points used for calculating the peripheral signal level _PN at the frequency point A. FIG. 7C is an enlarged view of the vicinity of the frequency point A in FIG. Near the signal level calculating unit 74, a frequency point L1~L8 from the second point without the immediate one point adjacent to the frequency point A on each side 8 points, the average value of the signal level P _S of the R1 to R8, frequency it can be a peripheral signal level P _N point a. The frequency points L1 to L8 for calculating the average value and R1 to R8 are surrounded by broken lines in FIG.

Protruding degree calculation unit 75, at each frequency point, it calculates the signal level _{P S} of the peripheral signal level _{P N} in dividing the degree of protrusion _{PR (= P S / P N} ).

When it contains residual carrier in the received signal, higher signal level P _S at the frequency of the residual carrier, and the signal level P _N of the frequency around the frequency of the residual carrier is characterized in that low. To use this feature, it uses protruding degree PR obtained by dividing the signal level P _S around the signal level P _N. When determining the ambient signal level P _N, the exclusion of any frequency point and immediately Sum 3 points adjacent for the following reason. The frequency width of the residual carrier is ideally 0 Hz. However, as described above, the frequency of the residual carrier is not always an integral multiple of 1 / T0 (Hz) when the observation time T0 used in the discrete Fourier transform is set to one cycle, and the window function , The frequency of the residual carrier has some width in the frequency spectrum. For this purpose, when calculating the peripheral signal level of each frequency point, the width of three consecutive points on the frequency axis including at least the frequency point is excluded. The number of frequency points to be excluded may be a predetermined number of five or more. A set of frequency points used when calculating the peripheral signal level is called a frequency peripheral point set.

Protruding degree PR is an index indicating the order of magnitude to the peripheral signal level P _N of the signal level P _S. The protrusion degree PR may be calculated by a method other than dividing the signal level P _S by the peripheral signal level P _N.

The residual carrier frequency estimating unit 8 estimates the frequency of the carrier remaining in the received signal based on the degree of protrusion PR. The residual carrier frequency estimating unit 8 includes a frequency point determining unit 181 and a frequency calculating unit 182. The frequency point determination unit 181 detects a frequency point PO at which the degree of protrusion PR calculated by the degree of protrusion calculation unit 75 is maximum. The frequency calculation unit 182 calculates the frequency estimation value ΔF of the residual carrier by multiplying the value of the frequency point PO at which the degree of protrusion PR is the maximum by the frequency interval between two adjacent frequency points of the discrete Fourier transform. . When the sample frequency of the complex sum signal (SUM4I + jSUM4Q) input to the discrete Fourier transform unit 6 is 2.19 MHz and the number of samples of the discrete Fourier transform is 4096, the residual carrier for the frequency point PO of X (0 ≦ X ≦ 4095) Is represented by the following equation.
ΔF = X * (2.19 / 4096) (0 ≦ X ≦ 2047)… (1)
ΔF = (X-4096) * {2.19 / 4096} (2048 ≦ X ≦ 4096)… (2)
Here, the relationship between X and frequency is as follows.
X = 0 is the middle frequency point on the frequency axis. X = 2047 is the rightmost frequency point on the frequency axis. X = 2048 is the leftmost frequency point on the frequency axis.
X = 4095 is the frequency point one point to the left of the center on the frequency axis. As described above, the frequency estimate ΔF of the residual carrier is calculated for each frequency point of the frequency spectrum calculated by the discrete Fourier transform, that is, the complex sum It can be obtained every 4096 samples of the signal (SUM4I + jSUM4Q).

  FIG. 1 is a diagram in which the frequency calculation unit 182 outputs the frequency estimation value ΔF. In FIG. 1, the frequency estimation value ΔF is not input. During adjustment of the tracking receiver 1 or the like, a signal having a frequency deviation of ΔF is input to the adjustment device, and the estimated frequency value ΔF can be confirmed on a screen or the like.

Next, the effect of the first embodiment when a signal modulated by the PCM / PM method having a large modulation factor (hereinafter, PCM / PM signal) is received will be described.
FIG. 8 is a schematic diagram of a power spectrum of a PCM / PM signal. FIG. 8 shows a power spectrum of a PCM signal using a bi-phase PCM code. The power spectrum of the PCM / PM signal includes a residual carrier component at the center and other data signal components. A received signal received in actual operation includes a noise component such as a white Gaussian noise component shown as a noise component.

FIG. 9 is a schematic diagram of a power spectrum obtained by performing a discrete Fourier transform on a PCM / PM signal. FIG. 10 is a diagram illustrating a simulation result of a power spectrum of a PCM / PM signal. FIG. 10 shows the result of applying a FFT of 4096 points to a PCM / PM signal to which a large modulation factor of 1.5 rad is applied to a signal waveform in a simulation in which noise is added. In general, in PCM / PM modulation, the power of a residual carrier component and the power of a data signal component are uniquely determined with respect to a carrier level using a modulation degree m (rad). Assuming that the power of all the carriers is Pc (dB), the power of the residual carrier component is Pr (dB), and the power of the data signal component is Ps (dB), the following equation holds.
Pr = Pc + 10 * log ₁₀ (cos ² (m))… (3)
Ps = Pc + 10 * log ₁₀ (sin ² (m))… (4)
For example, if m = 1.5 rad, Pr = Pc−23 dB and Ps = Pc−0.02 dB, which indicates that the residual carrier component is significantly smaller than the data component.

  In FIG. 10, the power value of the power spectrum of the residual carrier component 81 is a value of about “−25” dB, while the power value of the power spectrum of the data signal component 82 is a value of about “−23” dB. The power value of the power spectrum of the data signal component 82 is larger than the power value of the power spectrum of the residual carrier component 81. Therefore, based on the magnitude of the power value in the power spectrum. The frequency of the residual carrier component 81 cannot be detected.

  FIG. 11 is a schematic diagram of the protrusion degree PR for each frequency point calculated according to the first embodiment. As shown in FIG. 11, the degree of protrusion PR becomes maximum at a frequency point including the residual carrier component. FIG. 12 is a diagram illustrating a result of calculating the protrusion degree PR from the simulation result of FIG. FIG. 13 is a diagram in which a part of FIG. 12 is enlarged in the direction of the frequency f. As shown in FIGS. 12 and 13, the protrusion PR of the residual carrier component 101 is a little over 20 dB, but the protrusion PR of the data signal component 102 is less than 10 dB. By using the maximum value of the degree of protrusion PR instead of the maximum value of the power value, the residual carrier component can be accurately detected.

Modification 1 of Embodiment 1
The signal level calculating unit 73, the power or amplitude values of the frequency spectrum which has passed through the LPF 72 and the signal level P _S, near the signal level calculating unit 74 for each frequency point, determined with the vicinity of the frequency point a plurality of frequency points the signal level of the ranges have been calculated peripheral signal level P _N of the frequency points, not limited thereto.

Near the signal level calculating unit 74 for each frequency point, from the power or amplitude values of the frequency spectrum of a plurality of frequency points in a range with a predetermined vicinity of the frequency point, a peripheral signal level P _N of the frequency points It may be calculated. The signal level calculating unit 73, for each frequency point, a value obtained by subtracting the ambient signal level P _N from the power or amplitude values of the frequency spectrum may be a signal level P _S of the frequency points.

Modification 2 of Embodiment 1
In the above embodiments, the peripheral signal level calculator 74, the average value of the signal level P _S of a point on each side 8 points away two points from the frequency point, although the peripheral signal level P _N of the frequency points, It is not limited to this. Near the signal level calculating unit 74, a value obtained by dividing the frequency spacing between two adjacent frequency points of further discrete Fourier transform of the above average value, may be a peripheral signal level P _N. The residual carrier component is equivalent to CW (Continuous Wave), and the level is irrelevant to the bandwidth. _Therefore , it is easier to grasp the reception state by considering P _S / P _N0 .

Modification 3 of Embodiment 1
In the above embodiment, the frequency calculation unit 182 sets the frequency corresponding to the value of the frequency point at which the degree of protrusion PR is the maximum as the frequency estimation value ΔF of the residual carrier, but is not limited thereto. The frequency calculation unit 182 uses the frequency corresponding to the frequency point at which the protrusion degree PR is the maximum and the frequency corresponding to the frequency points before and after the frequency point at which the protrusion degree is the maximum, for example, to obtain a primary or secondary frequency. By the interpolation processing, the frequency estimation value ΔF of the residual carrier may be calculated with a resolution higher than the frequency interval between two adjacent frequency points of the discrete Fourier transform.

Modification 4 of Embodiment 1
In the above embodiment, the complex sum signal generation unit 25S converts the sum signal SUM-IF in the intermediate frequency band generated by the antenna into a digital signal and then performs quadrature detection, but the present invention is not limited to this. That is, the complex sum signal generation unit 25S may convert the sum signal SUM-IF of the intermediate frequency band generated by the antenna into a digital signal after performing quadrature detection. The same applies to the complex difference signal generator 25E. In other words, the complex sum signal generation unit 25S converts the sum signal SUM-IF of the intermediate frequency band generated by the antenna into a digital signal after quadrature detection, or performs quadrature detection after converting the sum signal SUM-IF into a digital signal. Generate a sum signal. The complex difference signal generation unit 25E converts the difference signal ERR-IF of the intermediate frequency band generated by the antenna into a digital signal after quadrature detection, or performs quadrature detection after converting it into a digital signal, and performs complex detection. Generate a signal.

Embodiment 2 FIG.
FIG. 14 is a block diagram illustrating a configuration of a tracking receiver 101 according to Embodiment 2. The tracking receiver 101 according to the second embodiment includes a frequency tracking unit 9 in addition to the components of the tracking receiver 1 according to the first embodiment.

The frequency tracking section 9 is a circuit that performs feedback control using a phase locked loop (PLL) and controls the phase difference between the phase of an input signal and a phase reference value to be zero. FIG. 15 is a diagram illustrating a configuration of the frequency tracking unit 9. The frequency tracking unit 9 includes a thinning processing unit 91, a phase comparator 92, and a loop filter 93. FIG. 15 is a diagram when a received signal is modulated by the QPSK modulation method. In addition to QPSK, the present invention can be similarly applied to a digital modulation method in which symbol points arranged on a complex plane have rotational symmetry N times (N is a natural number of 2 or more).
The frequency tracking unit 9 brings the residual carrier frequency closer to zero based on the residual carrier frequency (ΔFinit) estimated by the frequency estimation device 10 and the phase of the complex sum signal (SUM6I + jSUM6Q) output from the complex phase rotation unit 11S. Thus, the frequency correction value (−ΔFadj) is output. As a result, a phase correction value (-Δθ) is generated in the complex phase rotation units 11S and 11S.

  The thinning processing unit 91 reduces the sampling frequency of the baseband complex sum signal (SUM6I + jSUM6Q) output from the complex phase rotation unit 11S. The thinning-out processing unit 91 mainly uses a CIC (Cascaded Integrator Comb) filter or the like to remove high-frequency components so as not to generate aliasing noise, and when the thinning rate is K, the sampling frequency is set to (1 / K). Convert. If the noise amount of the input complex sum signal (SUM6I + jSUM6Q) is small and the one-sided equivalent noise bandwidth BL of the PLL can be widened, the thinning-out processing need not be performed.

The phase comparator 92 includes a calculation unit 381, a remainder calculator 382, and an adder 383. The operation unit 381 calculates a phase θa which is a declination (an angle between a complex number and a real axis) of the complex sum signal (SUM6I + jSUM6Q). Specifically, the calculation unit 381 calculates the phase θa using the real part and the imaginary part of the complex sum signal (SUM6I + jSUM6Q) according to the following equation.
θa = arctan (SUM6Q / SUM6I) (4)

  The remainder calculator 382 performs an operation of modulating the addition result of the phase θa and the phase correction value (−θadj) calculated by the operation unit 381 by 2π / N to obtain a remainder (mod operation at 2π / N). I do. For example, if the received signal is a signal modulated by the QPSK modulation method (hereinafter, QPSK signal), since N = 4, the mod operation is performed at π / 2 [rad]. An adder 383 further subtracts a reference value for mapping. The reference value of the mapping is an angle value so that the phase error of the complex sum signal with respect to the reference mapping point determined according to the modulation scheme is in a range centered on zero. In the case of QPSK, the reference value for mapping is π / 4 [rad], so π / 4 [rad] is subtracted. In FIG. 15, the mod operation of π / 2 [rad] with respect to the input signal is expressed as mod (π / 2).

  In general, in a digital modulation method having N rotational symmetries, the remainder calculator 382 may perform the operation of mod (2π / N), and the adder 383 may subtract (−π / N). For example, in the case of BPSK, the result is mod (π), and the adder 383 subtracts (−π / 2).

  The result obtained by subtracting the reference value of the mapping is output as a phase difference Δθdiff. The phase difference Δθdiff is a phase error of the complex sum signal (SUM6I + jSUM6Q). The phase comparator 92 is a phase error detector that detects a phase error of the complex sum signal (SUM6I + jSUM6Q).

  Based on the phase difference Δθdiff, the loop filter 93 detects that the frequency of the output signal has a frequency deviation ΔF, and integrates the result obtained by multiplying the phase difference Δθdiff by the loop gain to obtain the frequency deviation ΔF. Ask. The loop filter 93 includes a multiplier 83, a multiplier 84, an integrator 95, an adder 85, a multiplier 94, and a selection capturing unit 96. The integrator 95 includes an adder 97 and a delay circuit 86.

  The multiplier 83 multiplies the phase difference Δθdiff output from the phase comparator 92 by the loop gain G1 and outputs the result to the adder 85. The multiplier 84 multiplies the phase difference Δθdiff output from the phase comparator 92 by the loop gain G2 and outputs the result to the integrator 95. The output of the multiplier 84 is cumulatively added by the adder 97 and the delay circuit 86 in the integrator 95. The integrator 95 can sequentially accumulate information about the frequency deviation ΔF. The adder 85 obtains the frequency deviation ΔF by adding the output of the integrator 95 and the output of the multiplier 83. The multiplier 94 generates (−ΔF) by multiplying (−1) to invert the sign of the frequency deviation ΔF output from the adder 85. The multiplier 94 further multiplies (−ΔF) by K to output a frequency correction value (−ΔFadj) in order to match the sampling frequency of the complex phase rotation unit 11S.

  The frequency correction value (−ΔFadj) obtained by inverting the sign of the residual carrier frequency and multiplying by a coefficient is input to the phase correction value calculation unit 231S of the complex phase rotation unit 11S. As described in the first embodiment, the phase correction value calculation unit 231S outputs a phase correction value (-Δθadj) by integrating the frequency correction value (-ΔFadj). The phase rotation unit 232S rotates the phase of the complex sum signal (SUM3I + jSUM3Q) by the phase correction value (−Δθadj). That is, the phase rotation unit 232S multiplies the complex local signal exp (-jθadj) by the complex sum signal (SUM3I + jSUM3Q). As a result, the phase of the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S is sequentially rotated by the phase correction value (-Δθadj). In the first embodiment, the phase correction value is expressed as (−Δθ), but in the second embodiment, the phase correction value is expressed as (−Δθadj). As a result, a complex sum signal (SUM6I + jSUM6Q) from which the phase difference due to the frequency deviation ΔF generated in the quadrature detection unit 4S has been removed can be output. Further, the feedback processing is implemented such that the phase difference Δθdiff approaches 0.

  The phase correction value calculation unit 231E of the complex phase rotation unit 11E receives the frequency correction value (−ΔFadj) obtained by inverting the sign of the residual carrier frequency and multiplying by a coefficient. As described in the first embodiment, the phase correction value calculation unit 231E outputs a phase correction value (-Δθadj) by integrating the frequency correction value (-ΔFadj). The phase rotation unit 232E rotates the phase of the complex difference signal (ERR3I + jERR3Q) by the phase correction value (−Δθadj). That is, the phase rotation unit 232E multiplies the complex local signal exp (−jθadj) by the complex difference signal (ERR3I + jERR3Q). As a result, the phase of the complex difference signal (ERR3I + jERR3Q) output from the quadrature detector 4E is sequentially rotated by the phase correction value (-Δθadj). Thereby, it is possible to output a complex difference signal (ERR6I + jERR6Q) from which the phase difference due to the frequency deviation ΔF generated in the quadrature detection unit 4S has been removed.

  A phase comparator 92 in the frequency tracking unit 9, a loop filter 93 including an integrator 95 in the frequency tracking unit 9, an NCO 111S as an integrator in the complex phase rotation unit 11S, and a complex filter in the complex phase rotation unit 11S. The multiplier 350S forms a PLL whose transfer function is quadratic. The phase of the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S is corrected by the second-order PLL by the phase correction value (-Δθadj) obtained by integrating the frequency correction value (-ΔFadj) output from the loop filter 93. Thus, the phase difference Δθdiff in the phase comparator 92 can be made close to zero. Further, the frequency correction value (−ΔFadj) output from the loop filter 93 is made closer to the frequency deviation ΔF of the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detection unit 4S by the secondary PLL. (−ΔFadj) can be adjusted.

  It is possible to follow the frequency deviation ΔF accumulated in the integrator 95 with a further frequency deviation of about one-side equivalent noise bandwidth BL determined by the loop gains G1 and G2 in the loop filter 93.

  A feedback loop is formed by the complex phase rotation unit 11S and the frequency tracking unit 9. The loop gains G1 and G2 are set small so that the feedback loop does not become unstable. In order to quickly bring the frequency deviation closer to zero, the selection acquisition unit 96 receives, as an input to the integrator 95, an estimated value of the frequency (frequency deviation) of the residual carrier at the indicated time, which is output from the residual carrier frequency estimating unit 8. ΔF is taken as the initial frequency estimated value ΔFinit and output to the delay circuit 86.

  Specifically, by setting the output of the loop filter 93 to “0” until the frequency deviation ΔFinit output from the residual carrier frequency estimating unit 8 becomes stable, the input of the NCO 1111S in the complex phase rotation unit 11S becomes Fixed to "0". When it is determined that the frequency deviation ΔFinit output from the residual carrier frequency estimating section 8 is stable, it is instructed to capture the frequency deviation ΔFinit, and the selective capturing section 96 outputs the latest frequency from the residual carrier frequency estimating section 8 to the latest frequency. The deviation ΔFinit is obtained and output to the delay circuit 86. When it is not instructed to capture the frequency deviation ΔFinit, the selective capturing unit 96 captures the output of the adder 97 and outputs it to the delay circuit 86. Thereby, ΔFinit is set as an initial value of the frequency correction value (−ΔFadj), and based on the phase of the complex sum signal (SUM6I + jSUM6Q) after the phase is rotated by the complex phase rotation unit 11S, the frequency correction value (−Fadj) is set. ΔFadj) is adjusted.

  In this way, the frequency tracking unit 9 can track the fluctuation of the frequency deviation ΔF with ΔFinit as the initial value. That is, it becomes possible to calculate the frequency deviation ΔF more precisely and in sample processing units than ΔFinit estimated on the frequency axis by the discrete Fourier transform. However, when the PLL loses lock, the output of the loop filter 93 is set to “0” until ΔFinit is fetched again. When it is desired to maintain the state before the lock is released, the value of the integrator 95 immediately before the lock is released may be maintained instead of “0”.

For example, when the sampling frequency of the data input to the discrete Fourier transform unit 6 is 2.19 MHz, the thinning rate K is 256, and the data length (the number of samples) input to the discrete Fourier transform unit 6 is 4096 points, the discrete Fourier transform The frequency interval between adjacent frequency points of the frequency spectrum output from the converter 6 has a resolution of 534 Hz. Even if an interpolation process is performed to obtain an accuracy of 1/10, it is 53 Hz. The decimation processing section 91 in the frequency tracking section 9 resamples the data after passing through the CIC filter or the like at a decimation rate K at a sampling frequency of 2.19 MHz, thereby setting the sampling frequency to 8. Reduce to 545 kHz. When the input of the complex phase rotation unit 11S is 32 bits and the decimal point position is the 23rd bit (Q23 format), the decimal point position is equivalent to 8.545 kHz, so that 0.001 Hz (= 8.545 kHz / 2 ²³ ) It is possible to calculate the frequency deviation ΔF with an accurate frequency resolution.

  In Embodiments 1 and 2, the tracking receiver that estimates and removes the frequency of the residual carrier has been described. Even in a normal communication device, if a frequency offset or a frequency mismatch exists between a transmitter and a receiver, communication quality such as an increase in demodulation errors when demodulating a received signal deteriorates. The techniques of Embodiment 1 and Embodiment 2 for accurately estimating and removing the frequency of the residual carrier can also be applied to ordinary communication devices.

Modification 1 of Embodiment 2
FIG. 16 is a block diagram illustrating a configuration of a tracking receiver 201 according to the first modification of the second embodiment. The tracking receiver 201 according to the second embodiment includes a phase tracking unit 209 in addition to the components of the tracking receiver 1 according to the first embodiment. The tracking receiver 201 according to the second embodiment includes complex phase rotators 211S and 211E different from the complex phase rotators 11S and 11E according to the first embodiment.

FIG. 17 is a diagram illustrating a configuration of the phase tracking unit 209. The phase tracking unit 209 differs from the frequency tracking unit 9 of the second embodiment in that the phase tracking unit 209 includes an integrator 99, the input to the thinning processing unit 91, the configuration of the phase comparator 292, and the output of the phase tracking unit 209. Is a different point.
The phase tracking unit 209 brings the residual carrier frequency closer to zero based on the residual carrier frequency (ΔFinit) estimated by the frequency estimation device 10 and the phase of the complex sum signal (SUM6I + jSUM6Q) output from the complex phase rotation unit 11S. Thus, the phase correction value (−Δθadj) is output.

  The thinning processing unit 91 reduces the sampling frequency of the baseband complex sum signal (SUM3I + jSUM3Q) output from the quadrature detection unit 4S. The thinning-out processing section 91 mainly converts the sampling frequency to (1 / K) times using a CIC (Cascaded Integrator Comb) filter or the like while removing high-frequency components so as not to generate aliasing noise.

  The integrator 99 is a second integrator that integrates a value based on the output of the integrator 95. The integrator 99 includes an adder 87, a delay circuit 88, and a delay circuit 89. The adder 87 and the delay circuit 88 accumulatively add the frequency correction value (−ΔFadj) output from the multiplier 94. The output of the delay circuit 89 is sent to the complex phase rotation units 211S and 211E as a phase correction value (-Δθadj).

  The phase comparator 292 includes an adder 384 that adds a phase correction value (−Δθadj) to the phase θa output from the calculation unit 381. The output of the adder 384 is input to the remainder calculator 382. The phase comparator 292 is a phase error detector that detects a phase error of the complex sum signal (SUM6I + jSUM6Q) corrected by the phase correction value (-Δθadj).

  The selection acquisition unit 96 acquires the latest frequency deviation ΔFinit from the residual carrier frequency estimating unit 8 and outputs it to the delay circuit 86 when instructed to acquire the frequency deviation ΔFinit. When it is not instructed to capture the frequency deviation ΔFinit, the selective capturing unit 96 captures the output of the adder 97 and outputs it to the delay circuit 86. Thereby, ΔFinit is set as an initial value of the frequency correction value (−ΔFadj), and based on the phase of the complex sum signal (SUM3I + jSUM3Q) before the phase is rotated by the complex phase rotation unit 211S, the frequency correction value (−Fadj) is set. ΔFadj) is adjusted.

  FIG. 18A is a diagram illustrating a configuration of the complex phase rotation unit 211S. The difference between the complex phase rotation unit 211S and the complex phase rotation unit 11S of FIG. 4A is as follows. The complex phase rotation unit 211S does not include the phase correction value calculation unit 231S including the NCO 111S, but includes delay circuits 116AS and 116BS.

  The con / sin generator 112S generates a complex local signal exp (-jΔθadj) of the phase correction value (-Δadj) sent from the phase follower 209, not from the NCO 111S. The delay circuits 116AS and 116BS delay the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S, and output the delayed sum signal to the adders 113AS, 113BS, 113CS, and 113DS. The reason for the delay is to make the timing of the complex multiplication in the complex phase rotator 211S and the timing of the phase comparison of the phase comparator 292 of the phase follower 209 the same. When the timing is not adjusted, even if the phase difference Δθdiff and the frequency difference (the difference between ΔF and ΔFadj) can be removed inside the secondary PLL in the phase tracking unit 209, a phase difference occurs in the complex phase rotation unit 211S. However, there arises a problem that the phase of the constellation is shifted.

  FIG. 18B is a diagram illustrating a configuration of the complex phase rotation unit 211E. The difference of the complex phase rotation unit 211E from the complex phase rotation unit 11E of FIG. 4B is as follows. The complex phase rotation unit 211E does not include the phase correction value calculation unit 231E including the NCO 111E, but includes delay circuits 116AE and 116BE. The con / sin generation unit 112E generates a complex local signal exp (-jΔθadj) of the phase correction value (-Δθadj) sent from the phase tracking unit 209, not from the NCO 111E. The delay circuits 116AE and 116BE delay the complex difference signal (ERR3I + jERR3Q) output from the quadrature detector 4E and output the delayed signals to the adders 113AE, 113BE, 113CE, and 113DE.

  A second-order PLL is configured by the phase comparator 292 in the phase tracking unit 209, the loop filter 93 including the integrator 95 in the phase tracking unit 209, and the integrator 99 in the phase tracking unit 209. A complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S based on a phase correction value (-Δθadj) obtained by integrating a frequency correction value (-ΔFadj) output from the loop filter 93 by a PLL whose transfer function is quadratic. Is corrected, and the phase difference Δθdiff in the phase comparator 292 can be approximated to zero. Furthermore, the sum of the frequency deviation ΔF of the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detection unit 4S and the frequency correction value (−ΔFadj) output from the loop filter 93 is made closer to zero by the secondary PLL. In addition, the frequency correction value (-ΔFadj) can be adjusted.

Modification 2 of Embodiment 2
In the above embodiment, the output of the multiplier 94 receiving the output of the adder 85 is sent to the complex phase rotators 11S and 11E as the frequency correction value (−ΔFadj). However, the present invention is not limited to this. . The loop filter 93 does not include the multiplier 83 and the adder 85, and the output of the integrator 95 is inverted in sign by the multiplier 94 and sent to the complex phase rotators 11S and 11E as a frequency correction value (−ΔFadj). May be used.

Embodiment 3 FIG.
FIG. 19 is a block diagram illustrating a configuration of a tracking receiver 301 according to the third embodiment. The frequency estimating device 310 of the tracking receiver 301 according to the third embodiment includes an N-th power detector 13 and a frequency 1 / N multiplying unit 14 in addition to the components of the frequency estimating device 10 of the tracking receiver 1 according to the first embodiment. Is provided.

The N-th power detector 13 raises the complex sum signal (SUM3I + jSUM3Q) output from the quadrature detector 4S to the Nth power. Here, N is a positive integer. The purpose of N-th power detection is to multiply the phase of the input signal by N. The N-th power detector 13 may calculate the phase value θ of the complex sum signal (SIM3I + jSUMQ) instead of the N-th power operation, and multiply the phase value θ by four. This is because the phase becomes N times in the Nth power operation.
Complex signal (I + jQ) the N-th power signal (I + ^{jQ) N} can be modified as follows. Here, it is assumed that the complex signal (I + jQ) is represented by R × exp (jθ) in polar coordinates.
(I + jQ) ^N = (R × exp (jθ)) ^N = (R ^N × exp (jN × θ))
The mapping points of the NPSK signal are arranged at intervals of 2π / N (rad). For example, in the case of a QPSK signal, N = 4. In the case of a BPSK signal, N = 2.

  FIG. 20A is a diagram illustrating a mapping point of a QPSK signal. For example, the mapping points of the QPSK signal are located at θ1, θ2, θ3, and θ4. Here, θ1 = π / 4, θ2 = 3π / 4, θ3 = -3π / 4, and θ4 = -π / 4. When there is a phase difference Δθ due to the residual carrier, each mapping point is shifted by Δθ.

FIG. 20B is a diagram illustrating mapping points of the QPSK signal raised to the fourth power. The phases of the QPSK signal raised to the fourth power are 4 × θ1, 4 × θ2, 4 × θ3, and 4 × θ4. Here, a function for obtaining a remainder obtained by dividing X by Y is mod (X, Y). It looks like this:
mod (4 × θ1, 2π) = π,
mod (4 × θ2, 2π) = mod (3π, 2π) = π,
mod (4 × θ3, 2π) = mod (−3π, 2π) = π,
mod (4 × θ4, 2π) = mod (−π, 2π) = π
When there is a phase difference Δθ due to the residual carrier, each mapping point is shifted by 4 × Δθ. As shown above, when the QPSK signal is raised to the fourth power, the mapping points are gathered at one point of π. That is, data near the Nyquist point can be indicated by one point. The component appears as a line spectrum component on the frequency axis. When the frequency of the residual carrier is ΔF, the points gathered at this one location rotate at a speed of 4 × ΔF / Fs per sample. Fs is the sampling frequency of the complex sum signal (SUM3I + jSUM3Q) input to the N-th power detector 13.

  FIG. 21 is a diagram illustrating a simulation result obtained by raising the QPSK signal to the fourth power. FIG. 21 shows a constellation when the QPSK signal is raised to the fourth power under the condition of ΔF / Rs = 2/4096.

The frequency of the line spectrum component is a value obtained by multiplying the original residual carrier frequency ΔF ₀ by N. In order to obtain the original frequency ΔF ₀ of the residual carrier, a frequency 1 / N multiplying unit 14 is provided in the frequency estimating device 8 for the residual carrier. The frequency 1 / N multiplying unit 14 multiplies the frequency point at which the degree of protrusion PR determined by the frequency point determining unit 181 is maximum by 1 / N, and sends the result to the frequency calculating unit 182.

  FIG. 22 is a diagram illustrating a power spectrum of a QPSK signal. In FIG. 22, the horizontal axis is the normalized frequency obtained by dividing the frequency by the symbol rate Rs. In FIG. 22, the estimated frequency ΔF of the residual carrier is 0.25 × Rs. FIG. 23 is a diagram illustrating a power spectrum of a QPSK signal raised to the fourth power. In FIG. 23, the horizontal axis is the normalized frequency. A line spectrum 2001 is generated at a position where the normalized frequency is “1”. That is, the line spectrum 2001 occurs at a frequency of 1 × Rs. From FIG. 23, it can be detected that the frequency at which the power becomes maximum is 1 × Rs. The frequency at which the power becomes maximum (= 1 × Rs) is four times the frequency estimate ΔF (= 0.25 × Rs) of the residual carrier. The reason for quadrupling is that the QPSK signal is raised to the fourth power. The frequency of the residual carrier can be specified by multiplying the frequency at which the power becomes maximum by 1/4.

FIG. 24 is a diagram showing the degree of protrusion PR of the QPSK signal raised to the fourth power. In order to calculate the degree of protrusion PR, the peripheral signal level _PN was a power average value of 8 points (16 points on both sides) starting from a position 3 points away from each frequency point. As shown in FIG. 24, as in FIG. 23, a line spectrum 2101 is generated at a position where the normalized frequency is “1”. That is, at a frequency of 1 × Rs, a line spectrum 2101 is generated. From FIG. 24, it can be detected that the frequency at which the degree of protrusion PR is maximum is 1 × Rs. The frequency at which the degree of protrusion PR becomes maximum (= 1 × Rs) is four times the frequency estimate ΔF (= 0.25 × Rs) of the residual carrier. The reason for quadrupling is that the QPSK signal is raised to the fourth power. As in the case of the power example in FIG. 23, the frequency of the residual carrier can be specified by multiplying the frequency at which the degree of protrusion PR is maximum by 1/4. Therefore, when the QPSK signal is raised to the Nth power, the frequency of the residual carrier can be detected by the degree of protrusion PR in the same manner as the frequency of the residual carrier can be detected by the power value.

Modification 1 of Embodiment 3
If the symbol points arranged on the complex plane are digital modulation methods having N times rotational symmetry for natural numbers N of 2 or more, the N-th power detector 13 and the frequency 1 / N multiplier 14 can be applied. Therefore, in addition to the N-PSK (N-Phase Shift Keying) signal as well as the QAM (Quadrature Amplitude Modulation) signal or the N-APSK (N-Amplitude Phase Shift Keying) signal, the N-th power detector 13 and the frequency 1 / An N-fold unit 14 can be applied.

Modification 2 of Embodiment 3
In the above embodiment, the frequency 1 / N multiplying unit 14 multiplies the frequency point at which the degree of protrusion PR determined by the frequency point determining unit 181 is maximum by 1 / N, and sends the result to the frequency calculating unit 182. However, the present invention is not limited to this. The frequency 1 / N multiplying unit 14 may receive the frequency estimation value ΔF of the residual carrier calculated by the frequency calculating unit 182 and multiply the frequency estimation value ΔF by 1 / N.

Hardware configuration.
FIG. 25 is a diagram illustrating an example of a hardware configuration of frequency estimating apparatuses 10 and 310 according to the first to third embodiments. As shown in FIG. 25, the hardware of the frequency estimating apparatuses 10 and 310 includes a processor 1100 and a memory 1200 connected to the processor 1100 and a bus 1300.

  The functions of at least some of the components of the frequency estimating apparatuses 10 and 310 are realized by the processor 1110 such as a CPU executing a program stored in the memory 1200. Further, a plurality of processors and a plurality of memories may cooperate to execute the functions of the above-described components. Further, the functions of the above components may be realized by a processing circuit such as a system LSI. Further, a plurality of processing circuits may cooperate to execute the functions of the above components.

  The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present disclosure is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 101, 201, 301 tracking receiver, 2S, 2E analog receiving section, 3S, 3E ADC, 4S, 4E quadrature detecting section, 5 window function multiplier, 6 discrete Fourier transform section, 8 residual frequency estimating section, 9 frequency Tracking unit, 10,310 frequency estimation device, 11S, 11E, 211S, 211E complex phase rotation unit, 12 azimuth calculation unit, 13Nth power detection unit, 14 frequency 1 / N times unit, 21S, 21E bandpass filter, 22S 22E AMP, 23S, 23E, 45S, 45E, 46S, 46E, 72, 115AS, 115AE, 115BS, 115BE, 122, 123 Low-pass filter, 25S complex sum signal generator, 25E complex difference signal generator, 41S, 41E , 111S, 111E Numerically controlled oscillator, 42S, 42E, 112S, 112E cos / s in generator, 43S, 43E, 44S, 44E, 52, 53, 83, 84, 94, 113AS, 113AE, 113BS, 113BE, 113CS, 113CE, 113DS, 113DE, 124, 125 multiplier, 51 window function signal generator , 71 power calculation unit, 73 signal level calculation unit, 74 peripheral signal level calculation unit, 75 protrusion degree calculation unit, 85, 87, 97, 114AS, 114AE, 114BS, 114BE, 383, 384 adder, 88, 89, 116AS , 116AE, 116BS, 116BE delay circuit, 91 decimation processing section, 92,292 phase comparator (phase error detector), 93 loop filter, 95,99 integrator, 96 selection acquisition section, 121 complex division circuit, 181 frequency Point judgment unit, 182 Frequency calculation unit, 209th place Phase follower, 231S, 231E phase correction value calculator, 232S, 232E phase rotator, 350S, 350E complex multiplier, 381 arithmetic unit, 382 remainder calculator, 1100 processor, 1200 memory, 1300 bus.

Claims (13)

A discrete Fourier transform unit that performs a discrete Fourier transform on the quadrature detection and the digitized received signal to generate a frequency spectrum that is a complex number for each frequency point,
A signal level calculation unit that calculates a signal level for each frequency point based on the amplitude value of the frequency spectrum,
For each of the frequency points, a peripheral signal for calculating a peripheral signal level of the frequency point from the signal levels of a set of peripheral frequency points, which are a plurality of frequency points in a predetermined range near the frequency point. A level calculator,
At each of the frequency points, a saliency calculating unit that calculates a saliency indicating a degree of magnitude of the signal level with respect to the peripheral signal level,
A frequency estimating unit for estimating a frequency of a carrier remaining in the received signal based on the degree of protrusion.   The peripheral frequency point set is determined so as not to include a predetermined number of the frequency points continuously arranged on a frequency axis including at least the frequency point for which the peripheral signal level is to be calculated. 2. The frequency estimation device according to 1.   3. The peripheral signal level calculator according to claim 1, wherein the peripheral signal level calculator calculates an average value of the signal levels of the frequency points included in the peripheral frequency point set, and sets the average value as the peripheral signal level. 4. Frequency estimation device.   The frequency estimation according to any one of claims 1 to 3, wherein the signal level calculation unit sets an amplitude value of the frequency spectrum or a power value obtained by squaring the amplitude value as the signal level for each frequency point. apparatus.   The frequency estimation according to any one of claims 1 to 4, wherein the residual carrier frequency estimating unit estimates a frequency of a carrier remaining in the received signal based on the frequency point at which the degree of protrusion is maximum. apparatus. The received signal is modulated by a digital modulation method in which symbol points arranged on a complex plane have N times (N is a natural number of 2 or more) rotational symmetry,
The discrete Fourier transform unit performs a discrete Fourier transform on a signal obtained by digitizing the received signal and multiplying the phase of a complex digital signal obtained by quadrature detection by N times,
The frequency estimating apparatus according to claim 5, wherein the residual carrier frequency estimating unit estimates a frequency 1 / N times a frequency estimated based on the degree of protrusion as a frequency of a carrier remaining in the received signal. A complex sum signal generation unit that generates a complex sum signal by orthogonally detecting and digitizing an analog sum signal output by an antenna that receives a radio wave from a radio source,
By performing quadrature detection and digitization of the analog difference signal output by the antenna, a complex difference signal generation unit that generates a complex difference signal,
The frequency estimating device according to any one of claims 1 to 6, wherein the frequency estimating device estimates a residual carrier frequency that is a frequency of a carrier remaining in the complex sum signal.
A first complex phase rotation unit that rotates the phase of the complex sum signal according to a phase correction value based on the residual carrier frequency;
A second complex phase rotation unit that rotates the phase of the complex difference signal according to the phase correction value;
Based on the complex difference signal output by the second complex phase rotator and the complex sum signal output by the first complex phase rotator, the direction of arrival of the radio wave and the direction of the antenna A tracking direction error calculating unit that calculates a pointing direction error that is a difference from the pointing direction.   Based on the residual carrier frequency estimated by the frequency estimating device and the phase of the complex sum signal output by the first complex phase rotator, integrate the residual carrier frequency so as to approach zero. The tracking receiver according to claim 7, further comprising a frequency tracking unit that outputs a frequency correction value at which the phase correction value is generated.   The first complex phase rotator and the second complex phase rotator receive a frequency correction value obtained by inverting the sign of the residual carrier frequency and multiplying by a coefficient, and integrate the frequency correction value. The tracking receiver according to claim 8, further comprising: a phase correction value calculation unit that outputs a phase correction value by performing the phase correction, and a phase rotation unit that rotates a phase by the phase correction value. The frequency tracking unit is instructed as a phase error detector that detects a phase error of the complex sum signal, an integrator that integrates a value obtained by multiplying an output of the phase error detector by a coefficient, and an input of the integrator. Having a selection capturing unit that selects and captures the residual carrier frequency at the time of
The tracking receiver according to claim 8, wherein the frequency tracking unit calculates the frequency correction value based on an output of the integrator.   Based on the residual carrier frequency estimated by the frequency estimating device and the phase of the complex sum signal input to the first complex phase rotator, such that the residual carrier frequency approaches zero, The tracking receiver according to claim 7, further comprising a phase tracking unit that outputs a correction value.   The first complex phase rotator and the second complex phase rotator have a phase rotator for rotating the phase by the input phase correction value, and the first complex phase rotator is input. The tracking receiver according to claim 11, further comprising a delay circuit that delays the complex sum signal, wherein the second complex phase rotation unit includes a delay circuit that delays the input complex difference signal. A phase error detector that detects a phase error of the complex sum signal corrected by the phase correction value; an integrator that integrates a value obtained by multiplying the phase error by a coefficient; and And a second integrator that integrates a value based on an output of the integrator, the second integrator integrating a value based on an output of the integrator. The tracking receiver according to claim 11, wherein the tracking receiver is calculated based on an output of the integrator.