JP2020009960A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To provide a semiconductor device having favorable electric characteristics.SOLUTION: A transistor including an oxide semiconductor in a channel formation region, has a gate, a source, and a drain. A first insulator is formed below the oxide semiconductor. A second insulator is formed between the gate and the oxide semiconductor. One or both of the first insulator and the second insulator have a layer containing silicon and a layer containing gallium.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that a semiconductor device in this specification and the like refers to any device that can function by utilizing semiconductor characteristics. A semiconductor device such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like sometimes includes a semiconductor device. .

  Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor is attracting attention as another material. As an oxide semiconductor, for example, not only a single metal oxide such as indium oxide and zinc oxide but also a multimetal oxide is known. Among oxides of multi-component metals, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

  Through research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous in an oxide semiconductor have been found (see Non-Patent Documents 1 to 3). .). Non-Patent Documents 1 and 2 also disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Documents 4 and 5 show that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has minute crystals.

  Further, a transistor using IGZO as an active layer has an extremely low off-state current (see Non-Patent Document 6), and an LSI and a display utilizing the characteristics have been reported (see Non-Patent Documents 7 and 8). .).

S. Yamazaki et al. , "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p. 151-154 S. Yamazaki et al. , "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, "ECS Transactions", 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217 S. Amano et al. , "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p. 626-629

  An object of one embodiment of the present invention is to provide a semiconductor device having favorable electric characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

  An object of one embodiment of the present invention is to provide a semiconductor device which can hold data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. An object of one embodiment of the present invention is to provide a semiconductor device that can reduce power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

  Note that the description of these objects does not disturb the existence of other objects. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that issues other than these are obvious from the description of the specification, drawings, claims, etc., and that other issues can be extracted from the description of the description, drawings, claims, etc. It is.

  One embodiment of the present invention is a transistor including an oxide semiconductor in a channel formation region; the transistor has a gate, a source, and a drain, and a first insulator is formed below the oxide semiconductor. , A second insulator is formed between the gate and the oxide semiconductor, and one or both of the first insulator and the second insulator include a layer containing silicon and gallium. And a layer containing the same.

  One embodiment of the present invention is a transistor including an oxide semiconductor in a channel formation region, the transistor including a first gate, a second gate, a source, and a drain; A first insulator is formed between the semiconductor and the semiconductor, a second insulator is formed between the first gate and the oxide semiconductor, and the first insulator and the second insulator are formed. Either or both of the insulators include a layer containing silicon and a layer containing gallium.

  In the above invention, the oxide semiconductor contains indium, zinc, and gallium.

  In the above invention, the layer containing an oxide semiconductor and gallium has a crystal structure.

  In the above invention, a semiconductor device including a capacitor, wherein the capacitor includes a layer containing silicon and a layer containing gallium included in the transistor.

  In the above invention, the capacitor is formed above the transistor.

  In the above invention, the capacitor is formed below the transistor.

  A semiconductor device including the transistor described above, a third insulator, and a fourth insulator, wherein the third insulator includes aluminum and oxygen, and the fourth insulator Has silicon and nitrogen, and one or more of an upper surface, a lower surface, and side surfaces of the transistor are covered with a third insulator and a fourth insulator.

  In the above invention, it is located inside the fourth insulator.

  One embodiment of the present invention is a method for manufacturing a transistor including an oxide semiconductor in a channel formation region, wherein the transistor includes an oxide semiconductor, a first insulator, a gate, a source, and a drain; The insulator includes a layer containing gallium and a layer containing silicon, and the method for manufacturing the transistor includes, at least, a step of forming an oxide semiconductor and a step of forming a source and a drain over the oxide semiconductor. Forming a first insulator on the top surface of the oxide semiconductor and side surfaces of the source and the drain; and forming a gate on the first insulator. In the step of forming a layer, a layer containing gallium and a layer containing silicon are continuously formed under reduced pressure.

  According to one embodiment of the present invention, the transistor further includes a second insulator and a second gate; the method for manufacturing the transistor includes at least a step of forming a second gate; Forming a second insulator, forming an oxide semiconductor, forming a source and a drain over the oxide semiconductor, forming a top surface of the oxide semiconductor, and a side surface of the source and the drain. Forming a first insulator; and forming a gate on the first insulator, wherein the step of forming the first insulator includes a layer containing gallium and a layer containing silicon. Are continuously formed under reduced pressure.

  In the above invention, the oxide semiconductor contains indium, zinc, and gallium, and the oxide semiconductor is formed by a sputtering method.

  In the above invention, the layer containing an oxide semiconductor and gallium is formed to have crystallinity.

  In the above invention, the layer containing an oxide semiconductor and gallium is formed by heating at a temperature of 100 ° C or higher.

  In the above invention, the first insulator is formed by an ALD method.

  According to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  Alternatively, a semiconductor device capable of holding data for a long period can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with high design flexibility can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. It should be noted that effects other than these are obvious from the description of the specification, drawings, claims, and the like, and other effects can be extracted from the description of the specification, drawings, claims, and the like. It is.

4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a film formation method according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a metal oxide according to one embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a film formation method according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a film formation apparatus according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a film formation apparatus according to one embodiment of the present invention. 4A and 4B illustrate a film formation method according to one embodiment of the present invention. FIG. 4 illustrates a range of an atomic ratio of a metal oxide according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 3 is a schematic view of a semiconductor device according to one embodiment of the present invention. FIG. 13 is a schematic diagram of a storage device according to one embodiment of the present invention. FIG. 13 illustrates an electronic device according to one embodiment of the present invention. FIG. 4 is a diagram for explaining stress time dependency of ΔVsh in the example. FIG. 4 is a diagram for explaining rewriting endurance of the embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiment can be implemented in many different modes, and that the mode and details can be variously changed without departing from the spirit and scope. You. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

  In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show ideal examples, and are not limited to the shapes and values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally reduced due to processing such as etching, but may not be reflected in the drawings for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated in some cases. Further, when referring to the same function, the hatch pattern is the same, and there is a case where no particular reference numeral is given.

  In addition, in some cases, particularly in a top view (also referred to as a “plan view”) or a perspective view, description of some components is omitted in order to facilitate understanding of the invention. In addition, some hidden lines and the like may be omitted.

  In this specification and the like, ordinal numbers given as first, second, and the like are used for convenience, and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, ordinal numbers described in this specification and the like do not always coincide with ordinal numbers used for specifying one embodiment of the present invention.

  Further, in this specification and the like, words indicating an arrangement such as "over" and "under" are used for convenience in describing the positional relationship between components with reference to drawings. Further, the positional relationship between the components changes as appropriate according to the direction in which each component is described. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately paraphrased according to the situation.

  For example, in this specification and the like, when it is explicitly described that X and Y are connected, the case where X and Y are electrically connected, and the case where X and Y function It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, the connection relation is not limited to the predetermined connection relation, for example, the connection relation shown in the figure or the text, and it is assumed that anything other than the connection relation shown in the figure or the text is also described in the figure or the text.

  Here, X and Y are objects (for example, an apparatus, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, and the like).

  In addition, the functions of the source and the drain may be switched when transistors with different polarities are used or when the direction of current changes in circuit operation. For this reason, in this specification and the like, the terms of source and drain may be used interchangeably.

  Note that in this specification and the like, depending on a structure of a transistor, a channel width in a region where a channel is actually formed (hereinafter, also referred to as an “effective channel width”) corresponds to a channel width illustrated in a top view of the transistor. (Hereinafter, also referred to as “apparent channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and the effect may not be ignored. For example, in a transistor which is minute and has a gate electrode covering a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Therefore, when the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

  In this specification, a simple term "channel width" may refer to an apparent channel width. Alternatively, in this specification, a simple term "channel width" may refer to an effective channel width. The values of the channel length, the channel width, the effective channel width, the apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that a semiconductor impurity refers to, for example, elements other than the main components of the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be regarded as an impurity. When the impurity is contained, for example, the DOS (Density of States) of the semiconductor may be increased, or the crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. And transition metals other than the main components such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water may function as an impurity in some cases. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities, for example. In the case where the semiconductor is silicon, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, and a Group 15 element other than oxygen and hydrogen.

  Note that in this specification and the like, silicon oxynitride has a higher oxygen content than nitrogen as its composition. In addition, silicon nitride oxide has a higher nitrogen content than oxygen as its composition.

  In this specification and the like, the term "insulator" can be referred to as an insulating film or an insulating layer. Further, the term “conductor” can be referred to as a conductive film or a conductive layer. Further, the term “semiconductor” can be referred to as a semiconductor film or a semiconductor layer.

  In this specification and the like, “parallel” refers to a state where two straight lines are arranged at an angle of −10 degrees or more and 10 degrees or less. Therefore, a case where the angle is −5 degrees or more and 5 degrees or less is also included. The term “substantially parallel” refers to a state in which two straight lines are arranged at an angle of −30 degrees or more and 30 degrees or less. “Vertical” means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, a case where the angle is 85 degrees or more and 95 degrees or less is also included. Further, “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

  Note that in this specification, a barrier film refers to a film having a function of suppressing transmission of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. May be called.

  In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors, or simply OSs). For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor in some cases. That is, the term “OS FET” or “OS transistor” can be referred to as a transistor including an oxide or an oxide semiconductor.

In this specification and the like, normally-off means that when a potential is not applied to a gate or a ground potential is applied to a gate, a current per 1 μm of a channel width flowing through a transistor is 1 × 10 ⁻²⁰ at room temperature. A or lower, 1 × 10 ⁻¹⁸ A or lower at 85 ° C., or 1 × 10 ⁻¹⁶ A or lower at 125 ° C.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Transistor structure 1>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described. FIGS. 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention and the periphery of the transistor 200. FIG. 1A is a top view, FIG. 1B is a cross-sectional view taken along a dashed-dotted line A1-A2 shown in FIG. 1A, and FIG. 1C is a cross-sectional view taken along a dashed-dotted line A3-A4. . Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

  The semiconductor device of one embodiment of the present invention includes the transistor 200 and the insulator 212, the insulator 214, the insulator 216, the insulator 280, the insulator 282, the insulator 284, and the insulator 284 each functioning as an interlayer film. Have.

[Transistor 200]
As shown in FIG. 1, the transistor 200 includes a conductor 205 which is provided over a substrate (not shown) and is embedded in the insulator 216, and a transistor 205 over the insulator 216 and the conductor 205. An insulator 222 provided thereon, an insulator 224 provided over the insulator 222, and an oxide 230 provided over the insulator 224 (an oxide 230a, an oxide 230b, and an oxide 230c) , An insulator 250 disposed on the oxide 230, an insulator 252 disposed on the insulator 250, and a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 252 Conductor 240a and conductor 240b in contact with part of the top surface of oxide 230b; part of the top surface of insulator 224; the side surface of oxide 230a; the side surface of oxide 230b; Side, has the upper surface of the conductor 240a, the side surface of the conductor 240b, and an insulator 274 which is arranged in contact with the upper surface of the conductor 240b, a.

  In the transistor 200, the oxide 230 is preferably formed using a metal oxide that functions as a semiconductor (hereinafter, also referred to as an oxide semiconductor). A transistor including an oxide semiconductor in a channel formation region has extremely low leakage current (off current) in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method, an ALD (Atomic Layer Deposition) method, or the like; therefore, the oxide semiconductor can be used for the transistor 200 included in a highly integrated semiconductor device.

  For example, as an oxide semiconductor that can be used for the oxide 230, an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, or germanium , Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or a plurality thereof). In particular, as the element M, aluminum, gallium, yttrium, or tin is preferably used. As an oxide semiconductor that can be used for the oxide 230, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used.

  On the other hand, in a transistor including an oxide semiconductor, its electrical characteristics are likely to change and reliability may be poor due to impurities such as hydrogen, nitrogen, and a metal element in the oxide semiconductor, and oxygen vacancies.

  For example, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancy, an electron serving as a carrier may be generated. Therefore, a transistor including an oxide semiconductor containing oxygen vacancies tends to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies in the oxide semiconductor be reduced as much as possible.

  In addition, oxygen vacancies in an oxide semiconductor may be caused by, for example, absorption of an oxygen atom of the oxide semiconductor into a metal when a metal is used for a structure provided in the vicinity of the oxide semiconductor. is there. Further, a metal that has absorbed an oxygen atom may be oxidized to increase resistance. In addition, oxygen in a structure provided in close proximity to the oxide semiconductor may diffuse into the oxide semiconductor and cause oxygen vacancies in some cases.

  In order to reduce oxygen vacancies in the oxide semiconductor, an oxide containing oxygen at a higher proportion than the stoichiometric composition is preferably provided in the vicinity of the oxide semiconductor. For example, it is preferable that a region in which oxygen is present in excess of the stoichiometric composition (hereinafter, also referred to as an excess oxygen region) be formed in the insulator 250 and the insulator 280. Oxygen vacancies can be compensated by diffusion of the excess oxygen into the oxide semiconductor.

  For example, in the transistor 200 illustrated in FIG. 1, the oxide 230b is in contact with the conductor 240 functioning as a source electrode and a drain electrode. For example, when the conductive material used for the conductor 240 has a property of absorbing oxygen of the oxide 230 or has a property of supplying impurities such as hydrogen, nitrogen, or a metal element to the oxide 230, Oxygen deficiency or diffusion of impurities in a region in contact with the conductor 240 or in the vicinity of the region 230 partially reduces the resistance. Therefore, contact resistance between oxide 230 and conductor 240 can be reduced.

  On the other hand, in the transistor 200 illustrated in FIG. 1, the conductor 260 functioning as a gate electrode overlaps with the oxide 230 through the insulator 250 functioning as a gate insulator and the insulator 252. For example, in the case where the conductor 260 has a property of absorbing oxygen of the oxide 230 or has a property of supplying impurities such as hydrogen, nitrogen, or a metal element to the oxide 230, It is highly probable that the substance 230 deprives oxygen or diffuses impurities.

  Since the region of the oxide 230 which overlaps with the conductor 260 has a region where a channel is formed, the transistor is normally on, a leakage current is increased, or a threshold voltage is increased by application of stress by reduction in resistance. In some cases, the transistor may have poor electrical characteristics such as a shift. In particular, when the transistor 200 is miniaturized, the probability that a short circuit occurs between the source and the drain increases.

  That is, in a transistor including an oxide semiconductor, when impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to be changed and reliability may be deteriorated. Further, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that impurities and oxygen vacancies in the region where the channel of the oxide 230 is formed be reduced as much as possible.

  Therefore, it is preferable that the gate insulator include a film having a barrier property to oxygen, hydrogen, or an impurity. Specifically, the transistor 200 illustrated in FIG. 1 includes an insulator 250 and an insulator 252 that function at least as gate insulators. Here, as the insulator 252 in contact with the conductor 260, a film having a barrier property against oxygen, hydrogen, or an impurity is preferably used.

  Note that in this specification, a film having a function of suppressing impurity diffusion is referred to as a film through which impurities are hardly transmitted, a film with low impurity permeability, a film having a barrier property against impurities, a barrier film with respect to impurities, or the like. May be called. Similarly, a film having a function of suppressing hydrogen or oxygen diffusion, a film having low hydrogen or oxygen permeability, a film having low hydrogen or oxygen permeability, a film having a barrier property against hydrogen or oxygen, hydrogen or It may be called a barrier film against oxygen or the like.

  In particular, in the case where an In-Ga-Zn oxide is used as the oxide 230, the insulator 252 has a higher gallium content than the gallium oxide and the oxide 230b, or an oxide among the In-Ga-Zn oxides. It is preferable to use a material having higher insulating properties than 230b. Since the element included in the insulator 252 and the element included in the oxide 230 are common, for example, even if the element included in the insulator 252 diffuses into the oxide 230, the resistance of the oxide 230 is reduced. Is not a factor.

  Specifically, when an In—Ga—Zn oxide with an In: Ga: Zn = 4: 2: 3 [atomic ratio] is used as the oxide 230b, the insulator 252 becomes In: Ga: Zn = An In—Ga—Zn oxide with a ratio of 1: 3: 4 [atomic ratio] or In: Ga: Zn = 1: 3: 4 [atomic ratio] can be used. Note that as the In—Ga—Zn oxide near In: Ga: Zn = 1: 3: 4 [atomic ratio], for example, In: Ga: Zn = 1: 2.97: 2.61 [atom Number ratio] of In—Ga—Zn oxide.

  In particular, gallium oxide is a high dielectric constant insulating material having a higher dielectric constant than silicon nitride, and is a so-called high-k material. When a transistor is miniaturized and highly integrated, a problem such as a leak current may occur due to thinning of a gate insulator. By using a high-k material for an insulator functioning as a gate insulator, the equivalent oxide thickness (EOT) of the gate insulator can be reduced while the physical thickness is maintained. Therefore, the gate potential during the operation of the transistor can be reduced.

  Note that the insulator 252 is formed over a region where the channel of the oxide 230 is formed. As described later, the channel formation region preferably has crystallinity. Therefore, in the formation of the insulator 252, a film formation method in which film formation damage to the oxide 230 is less likely to occur is preferably used. For example, the ALD method is a film formation method in which damage to a film formation surface hardly occurs. Therefore, by forming the insulator 252 by an ALD method, damage to the oxide 230 that is a deposition target surface can be reduced and crystallinity of the oxide 230 can be maintained.

  The insulator 252 is formed at the bottom and side surfaces of an opening formed in the insulator 280 or the like. It is preferable that the thickness of the insulator 252 functioning as a gate insulator be uniform at the bottom of the opening. The ALD method is a film forming method that is excellent in covering properties for a structure having steps and unevenness. Therefore, by forming the insulator 252 by an ALD method, the thickness of the insulator 252 can be uniform at the bottom of the opening.

  Note that the insulator 250 may be provided between the oxide 230 and the insulator 252. The insulator 250 close to the oxide 230 preferably contains oxygen released by heating (also referred to as excess oxygen). Alternatively, the insulator 250 preferably has a region where the hydrogen concentration is low and oxygen is present in excess of the stoichiometric composition (hereinafter, also referred to as an excess oxygen region). Excess oxygen included in the insulator 250 is diffused into the oxide 230 by heat treatment or heat treatment in a production process, which reduces oxygen vacancies in the oxide 230 and suppresses normally on transistors. Can be.

For example, as the insulator having a low hydrogen concentration and an excess oxygen region, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. Specifically, an insulator having a low hydrogen concentration and an excess oxygen region or excess oxygen has a hydrogen concentration obtained by SIMS of less than 5 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ²⁰ atoms / cm ^3. , More preferably less than 5 × 10 ¹⁹ atoms / cm ³ . Further, in TDS (Thermal Desorption Spectroscopy) analysis, the amount of desorbed oxygen in terms of oxygen molecules is 2.0 × 10 ¹⁴ molecules / cm ² or more, preferably 1.0 × 10 ¹⁵ molecules / cm ² or more. It is. Note that the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C to 700 ° C, or 100 ° C to 500 ° C.

  By forming the insulator that functions as a gate insulator into a stacked structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Becomes Further, a laminated structure which is thermally stable and has a high relative dielectric constant can be obtained.

  Note that the insulator 250 is formed over a region where a channel of the oxide 230 is formed, similarly to the insulator 252. Therefore, it is preferable that the insulator 250 be formed by a film formation method in which film formation damage to the oxide 230 does not easily occur. That is, by forming the insulator 250 by an ALD method, damage to the oxide 230 which is a deposition surface is reduced, and the crystallinity of the oxide 230 can be maintained.

  Further, the thickness of the insulator 250 functioning as a gate insulator is preferably uniform at the bottom of the opening. Therefore, by forming the insulator 250 by an ALD method, the thickness of the insulator 250 can be uniform at the bottom of the opening.

  Further, it is preferable that the insulator 250 and the insulator 252 be successively formed without exposure to an air environment while maintaining a reduced pressure state. When the film is formed without being exposed to the air, impurities or moisture from an atmospheric environment can be prevented from being attached to the insulator 250 and the insulator 252, and the interface or the interface between the insulator 250 and the insulator 252 can be prevented. The vicinity can be kept clean.

  Alternatively, the oxide 230c, the insulator 250, and the insulator 252 may be successively formed without being exposed to an atmospheric environment while maintaining a reduced pressure. When the oxide 230c, the insulator 250, and the insulator 250 can be prevented from being attached to the oxide 230c, the insulator 250, and the insulator 252, the oxide 230c, the insulator 250, At the interface or near the interface and between the insulator 250 and the insulator 252 or near the interface can be kept clean.

  As in the above structure, the insulator serving as a gate insulator, which is provided between the oxide 230 and the conductor 205 serving as a gate electrode, has a barrier property to oxygen, hydrogen, or an impurity. Preferably, a membrane is included. Specifically, the transistor 200 illustrated in FIG. 1 includes an insulator 222 and an insulator 224 that function at least as a gate insulator.

  Therefore, as the insulator 222 in contact with the conductor 205, a film having a barrier property against oxygen, hydrogen, or an impurity is preferably used. On the other hand, the insulator 224 in contact with the oxide 230 preferably contains oxygen released by heating (also referred to as excess oxygen). Alternatively, the insulator 250 preferably has a region where the hydrogen concentration is low and oxygen is present in excess of the stoichiometric composition (hereinafter, also referred to as an excess oxygen region). Further, a material that is thermally stable may be used.

  By forming the insulator that functions as a gate insulator into a stacked structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Becomes Further, a laminated structure which is thermally stable and has a high relative dielectric constant can be obtained.

  As described above, a semiconductor device having stable electric characteristics can be provided. Further, a highly reliable semiconductor device can be provided. Further, a semiconductor device with low power consumption can be provided.

  Hereinafter, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

  First, the oxide 230 having a region functioning as a channel formation region preferably includes an oxide 230a, an oxide 230b, and an oxide 230c. Specifically, the oxide 230a is provided between the oxide 230b and the insulator 224. The oxide 230c is provided between the oxide 230b and the insulator 250.

  When the oxide 230a is provided below the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, when the oxide 230c is provided over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.

  As the oxide 230, a metal oxide functioning as an oxide semiconductor is preferably used. For example, as a metal oxide in a region where a channel is formed, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. With the use of a metal oxide having a large band gap as described above, the off-state current of the transistor can be reduced.

  Note that although the oxide 230a, the oxide 230b, and the oxide 230c are illustrated as a single layer in the drawing, the present invention is not limited to this. For example, a structure in which the oxide 230a, the oxide 230b, and the oxide 230c are provided as a stacked structure of two or more layers may be employed. In particular, the oxide 230c preferably includes a first layer in contact with the oxide 230b and a second layer in contact with the insulator 250.

  For example, an oxide having the same composition as the oxide 230b is used for the first layer of the oxide 230c. On the other hand, the second layer of the oxide 230c is preferably formed using an oxide having a higher barrier property against impurities than the first layer. When an oxide having the same composition as the oxide 230b is used for the first layer of the oxide 230, defects generated on the surface of the oxide 230b can be compensated by a production process. In addition, by using a film having a barrier property against impurities for the second layer, diffusion of impurities into the oxide 230b can be suppressed.

  Further, when the oxide 230c has the above-described stacked structure, oxygen in an excess oxygen region included in the insulator 280 is formed through the first layer of the oxide 230c so that a channel of the oxide 230 Oxygen deficiency generated in the region to be formed can be reduced. On the other hand, the second layer of the oxide 230c can prevent oxygen in an excess oxygen region included in the insulator 280 from diffusing into the conductor 260.

  Note that the transistor 200 has a structure in which the oxide 230 has a three-layer structure of an oxide 230a, an oxide 230b, and an oxide 230c in the channel formation region and in the vicinity thereof; It is not limited to. For example, the oxide 230 may have a single-layer structure of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers. Good.

  Next, the conductor 260 may function as a first gate (also referred to as a top gate) electrode in some cases. In some cases, the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode.

  Further, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260 without being linked. Specifically, the threshold voltage of the transistor 200 can be controlled by the potential applied to the conductor 205. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no negative potential is applied.

  In addition, for example, as illustrated in FIGS. 1A and 1C, when the conductor 205 and the conductor 260 are provided so as to overlap with each other, a potential is applied to the conductor 260 and the conductor 205. In that case, an electric field generated from the conductor 260 and an electric field generated from the conductor 205 are connected to each other, so that a channel formation region formed in the oxide 230 can be covered.

  That is, the channel formation region can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

  Note that FIG. 1 illustrates a structure in which the first conductor of the conductor 205 and the second conductor of the conductor 205 are stacked, but the present invention is not limited to this. For example, a structure in which the conductor 205 is provided as a single layer or a stacked structure of three or more layers may be employed. When the structure has a laminated structure, ordinal numbers may be given in the order of formation to distinguish them.

  As an example, in FIG. 1, the conductor 205 functioning as a second gate is formed by forming a first conductor in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and further inside the second conductor, Are formed. Here, it is preferable that the height of the upper surface of the first conductor and the height of the upper surface of the second conductor be approximately the same.

  For the first conductor of the conductor 205, a conductive material having a function of suppressing diffusion of impurities such as water, oxygen, and a metal element is preferably used. Alternatively, it is preferable to use a conductive material having a function of suppressing at least one diffusion of oxygen.

  When the first conductor of the conductor 205 has a function of suppressing diffusion of oxygen, the second conductor of the conductor 205 can be prevented from being oxidized to lower the conductivity.

  In the case where the conductor 205 also functions as a wiring, the second conductor of the conductor 205 is preferably formed using a conductive material having high conductivity, mainly containing tungsten, copper, or aluminum. Although the second conductor of the conductor 205 is illustrated as a single layer, the conductor 205 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

The conductor 260 functioning as a first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. Like the first conductor of the conductor 205, the conductor 260a includes a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (such as N ₂ O, NO, or NO ₂ ), or a copper atom. It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as impurities. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).

  When the conductor 260a has a function of suppressing diffusion of oxygen, diffusion of excess oxygen from the oxide 230 and the insulator 250 to the conductor 260b is suppressed. Therefore, oxidation of the conductor 260b due to excess oxygen included in the insulator 250 is suppressed, and a decrease in conductivity can be prevented. Further, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed.

  As the conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Further, as the conductor 260a, an oxide semiconductor that can be used as the oxide 230 can be used. In that case, by forming the conductor 260b by a sputtering method, the electric resistance of the conductor 260a can be reduced and the conductor 260b can be formed as a conductor. This can be called an OC (Oxide Conductor) electrode.

  The conductor 260b is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum. In addition, since the conductor 260 functions as a wiring, a conductor with high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

  Subsequently, the insulator 250 and the insulator 252 function as a first gate insulator. In addition, the insulator 222 and the insulator 224 function as a second gate insulator. Details can be referred to the above description.

  Next, in some cases, one of the conductors 240 (the conductor 240a and the conductor 240b) functions as a source electrode and the other functions as a drain electrode.

  As the conductor 240a and the conductor 240b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing this as a main component can be used. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

  Although a single-layer structure is shown in the drawing, a stacked structure of two or more layers may be used. For example, tantalum nitride and a tungsten film may be stacked. Further, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and A two-layer structure in which copper films are stacked may be employed.

  Further, a titanium film or a titanium nitride film, a three-layer structure in which an aluminum film or a copper film is stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film, an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereover. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

  Further, an insulator 274 having a barrier property may be provided over the conductor 240. It is preferable that the insulator 274 be formed using a substance having a barrier property to oxygen or hydrogen. With this structure, the oxygen in the excess oxygen region of the insulator 280 can be prevented from reacting with the conductor 240 and being oxidized, which will be described later in detail.

  For the insulator 274, for example, silicon nitride or a metal oxide can be used. In particular, it is preferable to use an insulating film having a barrier property to oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Alternatively, silicon nitride formed by a CVD method may be used.

  With the insulator 274, the range of material selection for the conductor 240 can be increased. For example, a material having low oxidation resistance and high conductivity such as tungsten or aluminum can be used for the conductor 240. Alternatively, for example, a conductor which can be easily formed or processed can be used.

  Further, oxidation of the conductor 240 can be suppressed, and oxygen released from the insulator 224 and the insulator 280 can be efficiently supplied to the oxide 230. In addition, by using a conductor with high conductivity as the conductor 240, the transistor 200 with low power consumption can be provided.

  Subsequently, the insulator 212, the insulator 214, the insulator 216, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 function as an interlayer film.

As the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) An insulator such as TiO ₃ (BST) can be used in a single layer or a stacked layer. Alternatively, to these insulators, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  For example, the insulator 216 is preferably formed using a so-called Low-k material having a low relative dielectric constant. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

  In addition, the insulator 280 and the insulator 284 are preferably low-k materials having a low relative dielectric constant, like the insulator 216. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

  In particular, for the insulator 280, an oxide containing oxygen at a higher proportion than the stoichiometric composition is preferably used. Since the insulator 280 is in contact with the oxide 230c of the transistor 200, oxygen vacancies generated in a region where a channel is formed in the oxide 230 can be reduced through the oxide 230c. That is, by providing an insulator having an excess oxygen region in an interlayer film in the vicinity of the transistor 200, oxygen vacancies in the oxide 230 included in the transistor 200 can be reduced; thus, reliability can be improved.

  The insulator 282 preferably has a barrier property against oxygen, hydrogen, and water. When the insulator 282 has a barrier property to oxygen, oxygen in an excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 284 side.

  In addition, the insulator 212, the insulator 214, the insulator 282, and the insulator 283 are formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen; With the insulator 280 having the above structure.

  For example, FIG. 10A and FIG. FIG. 10A is a top view of the transistor 200 provided over the substrate 10 according to one embodiment of the present invention and the periphery of the transistor 200. FIG. 10B is a cross-sectional view corresponding to a dashed-dotted line A1-A2 shown in FIG. In FIG. 10, some elements are omitted for clarity.

  The semiconductor device illustrated in FIGS. 10A and 10B includes a transistor 200 provided over a substrate 10, an insulator 12 having a structure surrounding the transistor 200, and an insulator 14 further outside the insulator 12. Having.

  The oxide 230 included in the transistor 200 has a high possibility of change in electric characteristics due to impurities such as hydrogen, water, or a metal oxide; therefore, entry of impurities from the outside is preferably blocked. Therefore, it is preferable that the transistor 200 be sealed with a stacked structure of the insulator 12 and the insulator 14 using an insulator having a barrier property.

  As the insulator 12 and the insulator 14, for example, aluminum oxide, hafnium oxide, or the like can be used. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.

  Note that the insulator 12 and the insulator 14 preferably use different kinds of films. By stacking different types of films, diffusion of more types of impurities can be suppressed with respect to impurities that enter from the outside. Specifically, it is preferable that aluminum oxide be used for the insulator 12 and silicon nitride be used for the insulator 14.

  In addition, the insulator 12 and the insulator 14 may be formed using the same kind of film using different film formation methods. For example, the insulator 12 may be formed by a sputtering method, and the insulator 14 may be formed by an ALD method. With this structure, the insulator 12 formed thicker than the insulator 14 is covered with the insulator 14 which is a dense film, so that sealing can be performed with high yield.

  Further, as illustrated in FIGS. 10C and 10D, a plurality of transistors 200 may be surrounded in a lump. Alternatively, each region where the density of the transistor 200 is different may be surrounded.

  Specifically, the semiconductor device illustrated in FIGS. 10C and 10D includes a region 20 where the density of the transistor 200 is high and a region 30 where the density is low on the substrate 10. In the region 20 where the transistor density is high, the insulators 22 and 24 surround four sides of the plurality of transistors 200. In the region 30 where the transistor density is low, the insulator 32 and the insulator 34 surround four sides of the transistor 200. Here, the number of transistors 200 surrounded by the insulators 22 and 24 is larger than the number of transistors 200 surrounded by the insulators 32 and 34.

  Accordingly, by sealing regions having different transistor densities on the substrate 10 with an insulator having a barrier property, diffusion of impurities into the transistor 200 can be suppressed. Further, variation in the amount of excess oxygen diffused into the transistor 200 can be reduced. Therefore, variation in electric characteristics among the plurality of transistors 200 can be reduced.

  Here, as insulators corresponding to the insulator 12, the insulator 14, the insulator 22, the insulator 24, the insulator 32, and the insulator 34 illustrated in FIG. 10, an insulator 212, an insulator 214, an insulator 282, And an insulator 283 can be used.

  For example, an insulator 212 and an insulator 283 can be provided as the insulator 12, the insulator 22, and the insulator 32. Further, an insulator 214 and an insulator 282 can be provided as the insulator 14, the insulator 24, and the insulator 34. Further, the stacked structure of the insulator 214 and the insulator 216 includes a region where the stacked structure of the insulator 282 and the insulator 283 is in contact with the substrate.

Therefore, the insulator 212, the insulator 214, the insulator 282, and the insulator 283 function as barrier films that prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Specifically, the insulator 212, the insulator 214, the insulator 282, and the insulator 283 are formed using a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO ₂ It is preferable to use an insulating material which has a function of suppressing diffusion of impurities such as copper atoms (the impurities are hardly transmitted). Alternatively, it is preferable to use an insulating material which has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen is hardly permeated). Alternatively, for example, the insulator 212, the insulator 214, the insulator 282, and the insulator 283 may be formed using aluminum oxide, silicon nitride, or the like. With such a structure, diffusion of impurities such as hydrogen and water to the transistor 200 side from above the substrate, the end of the substrate, or the insulator 284 can be suppressed.

  In addition, the insulator 280 that covers the transistor 200 may function as a planarizing film that covers the uneven shape below the transistor 280. With this structure, the coating property of a film provided above the insulator 280 is improved. Therefore, the transistor 200 and the insulator 280 can be sealed without the insulator 282 being disconnected.

  With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which fluctuations in electric characteristics are suppressed, stable electric characteristics are improved, and reliability is improved.

<Transistor structure 2>
FIG. 2 illustrates an example of a semiconductor device including the transistor 200. FIG. 2A illustrates the top surface of the semiconductor device. Note that some films are omitted in FIG. 2A for simplicity of the drawing. 2B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in FIG. 2A, and FIG. 2C is a cross-sectional view corresponding to A3-A4.

  In the semiconductor device shown in FIG. 2, structures having the same functions as those of the semiconductor device shown in FIG. 1 are denoted by the same reference numerals.

  The transistor 200 illustrated in FIG. 2 has a structure in which an insulator 254 is provided between a conductor 260 and an insulator 252. Further, the insulator 250 does not necessarily need to be provided. Similarly, a structure in which an insulator 220 is provided between the conductor 205 and the insulator 224 is provided. Further, the insulator 250 and the insulator 222 are not necessarily provided.

It is preferable that the insulator 254 be an insulator having a low hydrogen concentration and being resistant to heat, for example. As the insulator 254, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. Specifically, an insulator having a low hydrogen concentration and an excess oxygen region or excess oxygen has a hydrogen concentration obtained by SIMS of less than 5 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ²⁰ atoms / cm ^3. , More preferably less than 5 × 10 ¹⁹ atoms / cm ³ .

  Further, as the insulating film 254A, a silicon oxide film is preferably formed by an ALD method. Note that the insulator 252 and the insulator 254 may be continuously formed by an ALD apparatus without being released to the atmosphere by an ALD method. By continuously forming the insulator 252 and the insulator 254 with an ALD apparatus without exposing the insulator to the atmosphere, impurities (typically, moisture or the like) taken in at or near the interface can be reduced. . In addition, when the insulator 252 and the insulator 254 are formed by an ALD method, a film with high coverage and high coverage can be formed.

  By forming the insulator that functions as a gate insulator into a stacked structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Becomes Further, a laminated structure which is thermally stable and has a high relative dielectric constant can be obtained.

  In the case where an In-Ga-Zn oxide is used as the oxide 230 and an insulating material containing more gallium than the oxide 230, such as gallium oxide, is used as the insulator 252, the oxide 230 and the insulator 252 may be used. Are in contact with each other, the density of defect states at the interface between the oxide 230 and the insulator 252 can be reduced. Therefore, the influence of carrier scattering due to interface scattering is small, and the transistor 200 can have high on-state current and high frequency characteristics.

  Further, the insulator 275 may be provided over the insulator 274. The insulator 275 preferably has a barrier property. In the case where the insulator 275 is provided, a different kind of film may be used for the insulator 274. By stacking different types of films, diffusion of more types of impurities can be suppressed with respect to impurities that enter from the outside.

  Alternatively, the insulator 275 may be formed using the same kind of film as the insulator 274 by using a different deposition method. For example, the insulator 274 may be formed by a sputtering method and the insulator 275 may be formed by an ALD method. With this structure, the insulator 274 which is formed to be thicker than the insulator 275 is covered with the insulator 275 which is a dense film, so that sealing can be performed with high yield.

  With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which fluctuations in electric characteristics are suppressed, stable electric characteristics are improved, and reliability is improved.

<Transistor structure 3>
FIG. 3 illustrates an example of a semiconductor device including the transistor 200. FIG. 3A illustrates the top surface of the semiconductor device. Note that some films are omitted in FIG. 3A for simplification of the drawing. 3B is a cross-sectional view corresponding to a dashed-dotted line A1-A2 shown in FIG. 3A, and FIG. 3C is a cross-sectional view corresponding to A3-A4.

  Note that, in the semiconductor device illustrated in FIG. 3, a structure having the same function as the structure included in the semiconductor device illustrated in FIG. 1 or FIG.

  The transistor 200 illustrated in FIGS. 3A and 3B has a stacked structure of a first gate insulator and a second gate insulator. In particular, when different potentials are applied to the conductor 260 functioning as a first gate electrode and the conductor 205 functioning as a second gate electrode, the structure of the first gate insulator and the second gate insulating The body structure may be appropriately selected for each potential.

  For example, as illustrated in FIG. 3, a stacked structure of the insulator 250, the insulator 252, and the insulator 254 can be used for the first gate insulator. On the other hand, as the second gate insulator, a stacked structure of the insulator 221, the insulator 223, and the insulator 225 can be used.

  For example, as the insulator 221 and the insulator 225, a film having a barrier property against oxygen, hydrogen, or an impurity is preferably used.

  In particular, in the case where an In-Ga-Zn oxide is used as the oxide 230, an insulating material containing more gallium than the oxide 230, such as gallium oxide, is preferably used for the insulator 221 and the insulator 225. Since the element included in the insulator 221 and the insulator 225 and the element included in the oxide 230 are common, for example, the element included in the insulator 221 and the element included in the insulator 225 diffused into the oxide 230. This does not cause the oxide 230 to have a low resistance.

  Gallium oxide is a high dielectric constant insulating material having a higher dielectric constant than silicon nitride, and is a so-called high-k material. When a transistor is miniaturized and highly integrated, a problem such as a leak current may occur due to thinning of a gate insulator. By using a high-k material for an insulator functioning as a gate insulator, the equivalent oxide thickness (EOT) of the gate insulator can be reduced while the physical thickness is maintained. Therefore, the gate potential during the operation of the transistor can be reduced.

  On the other hand, so-called high-k materials such as gallium oxide tend to be easily crystallized. In addition, when the crystallinity of the gate insulator is high, the probability that a leak current is generated increases. Therefore, it is preferable to dispose an amorphous insulator 223 between the insulator 221 and the insulator 225. With the use of the insulator 223, generation of a leak current can be suppressed even when the insulator 221 and the insulator 225 have a high crystallinity.

  With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which fluctuations in electric characteristics are suppressed, stable electric characteristics are improved, and reliability is improved.

<Structural materials for semiconductor devices>
Hereinafter, constituent materials that can be used for a semiconductor device will be described.

<< Substrate >>
As a substrate over which the transistor 200 is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, and the like are given. Further, there are a substrate provided with a conductor or a semiconductor on an insulator substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a storage element, and the like.

<< Insulator >>
Examples of the insulator include oxides, nitrides, oxynitrides, nitrided oxides, metal oxides, metal oxynitrides, and metal nitrided oxides having insulating properties.

  For example, when transistors are miniaturized and highly integrated, problems such as leakage current may occur due to thinning of a gate insulator. When a high-k material is used for an insulator functioning as a gate insulator, a voltage can be reduced during operation of a transistor while a physical thickness is maintained. On the other hand, by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.

  Examples of the insulator having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, and silicon and hafnium. Oxynitride or nitride containing silicon and hafnium.

  Insulators having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and voids. There is silicon oxide having a hole, resin, or the like.

  A transistor including an oxide semiconductor is surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen (such as the insulator 214, the insulator 222, the insulator 82, and the insulator 283). In addition, the electrical characteristics of the transistor can be stabilized. Examples of the insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, A metal oxide such as tantalum oxide, a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.

  The insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating. For example, with a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

<< Conductor >>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-described metal element as a component, an alloy in which the above-described metal elements are combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized. A conductive material or a material which maintains conductivity even when oxygen is absorbed is preferable. Alternatively, a semiconductor having high electric conductivity, represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

  Alternatively, a plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be employed. Further, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Further, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

  Note that in the case where an oxide is used for a channel formation region of the transistor, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used for a conductor functioning as a gate electrode is used. Is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

  In particular, as a conductor functioning as a gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed may be captured in some cases. Alternatively, in some cases, hydrogen mixed in from an outer insulator or the like can be captured.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device including the transistor 200 according to one embodiment of the present invention, which is illustrated in FIGS.

  4 to 9, (A) in each drawing shows a top view. FIG. 2B is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, (C) of each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some components are not illustrated in the top view of FIG. 1A for clarity of the drawings.

  First, a substrate (not illustrated) is prepared, and the insulator 212 and the insulator 214 are formed over the substrate. The insulator 212 and the insulator 214 are formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, and a pulsed laser deposition (PLD: Pulsed Laser Deposition). ) Method, ALD method and the like.

  Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. . Further, the method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on a used raw material gas.

  In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (eg, a transistor or a capacitor) included in a semiconductor device may be charged up by receiving charge from plasma. At this time, the accumulated charges may destroy wirings, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, a plasma film having few defects can be obtained because plasma damage does not occur during film formation.

  The CVD method is different from a film formation method in which particles emitted from a target or the like are deposited, and is a film formation method in which a film is formed by a reaction on the surface of an object to be processed. Therefore, the film forming method is less affected by the shape of the object to be processed and has good step coverage.

  In the CVD method, the composition of the obtained film can be controlled by the flow ratio of the source gas. For example, in the CVD method, a film having an arbitrary composition can be formed depending on a flow rate ratio of a source gas. Further, for example, in the CVD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow ratio of the source gas, the time required for film formation is shortened because the time required for transport and pressure adjustment is not required as compared with the case where film formation is performed using a plurality of film formation chambers. can do. Therefore, the productivity of the semiconductor device may be improved in some cases.

  In this embodiment, a silicon nitride film is formed as the insulator 212 by a sputtering method or a CVD method. Further, as the insulator 214, an aluminum oxide film is formed by a sputtering method or a CVD method. Further, for example, a structure in which aluminum oxide is formed by a sputtering method as the insulator 212 and aluminum oxide is formed by an ALD method as the insulator 214 may be employed. Alternatively, a structure in which aluminum oxide is formed by an ALD method as the insulator 212 and aluminum oxide is formed by a sputtering method as the insulator 214 may be employed.

  Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulating film to be the insulator 216, silicon oxide is formed by a CVD method.

  Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove and a slit. In some cases, a region where an opening is formed is referred to as an opening. The opening may be formed by wet etching, but dry etching is more preferable for fine processing. Further, as the insulator 214, an insulator which functions as an etching stopper film when the insulator 216 is etched to form a groove is preferably selected. For example, when a silicon oxide film is used for the insulator 216 that forms the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

  As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having the parallel plate type electrode may be configured to apply a high frequency voltage to one of the parallel plate type electrodes. Alternatively, a configuration in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes may be employed. Alternatively, a configuration in which a high-frequency voltage having the same frequency is applied to each of the parallel plate electrodes may be employed. Alternatively, a configuration in which high-frequency voltages having different frequencies are applied to the respective parallel plate electrodes may be employed. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

  After the formation of the opening, a conductive film serving as a first conductor of the conductor 205 is formed. The conductive film preferably includes a conductor having a function of suppressing transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of a conductor having a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum tungsten alloy can be used. The conductive film serving as the first conductor of the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, a tantalum nitride film or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method as a conductive film serving as a first conductor of the conductor 205. By using a metal nitride as the first conductor of the conductor 205, even if a metal such as copper which is easily diffused is used as a second conductor of the conductor 205 described later, It can be prevented from diffusing out of the one conductor.

  Next, a conductive film serving as the second conductor of the conductor 205 is formed over the conductive film serving as the first conductor of the conductor 205. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as a conductive film serving as a second conductor of the conductor 205.

  Next, by performing a CMP (Chemical Mechanical Polishing) process, part of the conductive film serving as the first conductor of the conductor 205 and part of the conductive film serving as the second conductor of the conductor 205 is removed, The insulator 216 is exposed. As a result, the conductive film serving as the first conductor of the conductor 205 and the conductive film serving as the second conductor of the conductor 205 remain only in the opening. Thus, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 with a flat top surface can be formed (see FIG. 4). Note that part of the insulator 216 may be removed by the CMP treatment.

  Note that after forming the conductor 205, a part of the second conductor of the conductor 205 is removed, a conductive film is formed over the conductor 205 and the insulator 216, and a step of performing CMP treatment is performed. Is also good. By the CMP treatment, part of the conductive film is removed, and the insulator 216 is exposed. Note that part of the second conductor of the conductor 205 is preferably removed by a dry etching method or the like. For the conductive film, a material similar to that of the first conductor of the conductor 205 or the second conductor of the conductor 205 is preferably used.

  Through the above steps, the conductor 205 including the conductive film and having a flat top surface can be formed. By improving the planarity of the upper surfaces of the insulator 216 and the conductor 205, the crystallinity of the CAAC-OS forming the oxides 230b and 230c can be improved.

  Hereinafter, a method for forming the conductor 205 which is different from the above will be described below.

  A conductive film to be the conductor 205 is formed over the insulator 214. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductive film can be a multilayer film. In this embodiment, tungsten is formed as the conductive film.

  Next, the conductive film is processed by a lithography method to form a conductor 205.

  In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developing solution. Next, by performing an etching treatment through the resist mask, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens to perform exposure. Further, an electron beam or an ion beam may be used instead of the above-described light. When an electron beam or an ion beam is used, a mask is not required. Note that the resist mask can be removed by performing dry etching such as ashing, performing wet etching, performing wet etching after dry etching, or performing dry etching after wet etching.

  Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film serving as the conductor 205, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape. A hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during the etching. After etching the conductive film to be the conductor 205, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

  Next, an insulating film to be the insulator 216 is formed over the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the upper surface and the side surface of the conductor 205. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Here, the thickness of the insulating film to be the insulator 216 is preferably greater than or equal to the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less.

  Next, CMP treatment is performed on the insulating film to be the insulator 216, so that part of the insulating film to be the insulator 216 is removed and the surface of the conductor 205 is exposed. Thus, the conductor 205 having a flat top surface and the insulator 216 in contact with the side surface of the conductor 205 can be formed. The above is a different method for forming the conductor 205.

  Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 has a barrier property to hydrogen and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 through the insulator 222 to the inside of the transistor 200 is suppressed. Thus, generation of oxygen vacancies in the oxide 230 can be suppressed.

  In addition, as the insulator 222, an insulator including an oxide having a metal element common to the element included in the oxide 230 may be formed.

  In particular, in the case where an In-Ga-Zn oxide is used as the oxide 230, it is preferable to use an insulating material having a higher gallium content than the oxide 230, such as gallium oxide, as the insulator 222. Since the element included in the insulator 222 and the element included in the oxide 230 are common, for example, even if the element included in the insulator 222 is diffused into the oxide 230, the resistance of the oxide 230 is reduced. Is not a factor.

  The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Note that the insulator 222 is preferably formed by an ALD method described later.

  For example, when a gallium oxide film is formed by an ALD method as the insulator 222, a precursor of gallium is trimethylgallium, triethylgallium, gallium trichloride, tris (dimethylamido) gallium, gallium (III) acetylacetonate, Tris (2,2,6,6-tetramethyl-3,5-heptanedioic acid) gallium, dimethylchlorogallium, diethylchlorogallium and the like can be used.

  Some precursors include one or both of carbon and chlorine in addition to the metal element. An oxide film formed using a precursor containing carbon may contain carbon in some cases. Further, an oxide film formed using a precursor containing chlorine may contain chlorine in some cases.

  Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, in the heat treatment, heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement desorbed oxygen. You may.

  In this embodiment, as the heat treatment, the film is formed in a nitrogen atmosphere at a temperature of 400 ° C. for one hour after the formation of the insulator 222, and then continuously performed in an oxygen atmosphere at a temperature of 400 ° C. for one hour. Perform processing. By the heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Further, heat treatment can be performed at a timing after the insulator 224 is formed.

  Next, an insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 224 by a CVD method.

  Here, in order to form an excess oxygen region in the insulator 224, plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power supply for generating high-density plasma using microwaves, for example. Alternatively, a power supply for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can. Alternatively, after performing plasma treatment including an inert gas using this apparatus, plasma treatment including oxygen may be performed to supplement desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, the heat treatment may not be performed.

  Here, an aluminum oxide film may be formed over the insulator 224 by, for example, a sputtering method, and CMP treatment may be performed on the aluminum oxide until the aluminum oxide reaches the insulator 224. By performing the CMP treatment, the surface of the insulator 224 can be planarized and smoothed. By arranging the aluminum oxide on the insulator 224 and performing the CMP treatment, the end point of the CMP treatment can be easily detected. In addition, in some cases, the insulator 224 is polished by the CMP treatment so that the thickness of the insulator 224 is reduced; however, the thickness of the insulator 224 may be adjusted when the insulator 224 is formed. By performing planarization and smoothing of the surface of the insulator 224, deterioration of the coverage of an oxide to be formed later can be prevented, and reduction in the yield of a semiconductor device can be prevented in some cases. It is preferable that aluminum oxide be formed over the insulator 224 by a sputtering method because oxygen can be added to the insulator 224.

  Next, an oxide film 230A and an oxide film 230B are sequentially formed over the insulator 224 (see FIG. 4). Note that the oxide films 230A and 230B are preferably formed continuously without being exposed to the air environment. When the oxide film 230A and the oxide film 230B are formed without being exposed to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from being attached to the oxide films 230A and 230B, and the vicinity of the interface between the oxide films 230A and 230B can be reduced. Can be kept clean.

  The oxide films 230A and 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that in the case where the oxide films 230A and 230B are formed by an ALD method, the contents described in the above embodiment can be referred to.

  For example, when an In—Ga—Zn oxide film is formed by an ALD method as the oxide films 230A and 230B, trimethyl indium and tris (2, 2, 6, 6-tetramethyl-) are used as indium precursors. Indium 3,5-heptanedioate), cyclopentadienyl indium, or the like is used. As a precursor of gallium, trimethylgallium, triethylgallium, gallium trichloride, tris (dimethylamido) gallium, gallium (III) acetylacetonate, tris (2,2,6,6-tetramethyl-3,5-heptane) Gallium, dimethylchlorogallium, diethylchlorogallium and the like are used. In addition, dimethyl zinc, diethyl zinc, bis (2,2,6,6-tetramethyl-3,5-heptanedioic acid) zinc, or the like is used as a precursor of zinc. In accordance with the characteristics required for the oxide 230a and the oxide 230b, the type and the amount of the precursor used for forming the In-Ga-Zn oxide film may be appropriately combined.

  Some precursors include one or both of carbon and chlorine in addition to the metal element. An oxide film formed using a precursor containing carbon may contain carbon in some cases. Further, an oxide film formed using a precursor containing chlorine may contain chlorine in some cases.

  For example, when the oxide films 230A and 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the above oxide film is formed by a sputtering method, the above-described In-M-Zn oxide target or the like can be used. In addition, an alternating current (AC) power source such as a direct current (DC) power source or a high frequency (RF) power source is connected to the target, and necessary power can be applied according to the electrical conductivity of the target.

  In particular, when the oxide film 230A is formed, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 in some cases. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

  In the case where the oxide film 230B is formed by a sputtering method, the proportion of oxygen contained in a sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less. An object semiconductor is formed. A transistor using an oxygen-excess oxide semiconductor for a channel formation region has relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case where the oxide film 230B is formed by a sputtering method, when the proportion of oxygen contained in a sputtering gas is greater than or equal to 1% and less than or equal to 30%, preferably greater than or equal to 5% and less than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. You. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. In addition, by forming a film while heating the substrate, the crystallinity of the oxide film can be improved.

  In this embodiment, the oxide film 230A is formed by a sputtering method with the use of an In-Ga-Zn oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 4. The oxide film 230B is formed by a sputtering method with the use of an In-Ga-Zn oxide target with an In: Ga: Zn ratio of 4: 2: 4.1 [atomic ratio]. Note that each oxide film may be formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.

  Here, the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are preferably formed without exposure to the air. For example, a multi-chamber deposition apparatus may be used.

  Next, heat treatment may be performed. For the heat treatment, the above-described heat treatment conditions can be used. By the heat treatment, impurities such as water and hydrogen in the oxide films 230A and 230B can be removed. In this embodiment mode, after the treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere, the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere.

  Next, a conductive film 240A is formed over the oxide film 230B. The conductive film 240A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 4). Note that heat treatment may be performed before the formation of the conductive film 240A. The heat treatment may be performed under reduced pressure, and the conductive film 240A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide films 230A and 230B can be further reduced. . The temperature of the heat treatment is preferably from 100 ° C to 400 ° C. In this embodiment, the temperature of the heat treatment is set to 200 ° C.

  Next, the oxide film 230A, the oxide film 230B, and the conductive film 240A are processed into an island shape to form the oxide 230a, the oxide 230b, and the conductive layer 240B (see FIG. 5). Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be small.

  Here, the oxide 230a, the oxide 230b, and the conductive layer 240B are formed so that at least part thereof overlaps with the conductor 205. It is preferable that side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 240B be substantially perpendicular to the top surface of the insulator 224. When the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 240B are substantially perpendicular to the top surface of the insulator 224, the area and the density can be reduced when the plurality of transistors 200 are provided. Become. Alternatively, the angle formed between the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 240B and the top surface of the insulator 224 may be low. In that case, the angle formed between the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 240B and the top surface of the insulator 224 is preferably greater than or equal to 60 ° and less than 70 °. By adopting such a shape, covering properties of the insulator 274 and the like can be improved in a subsequent step, and defects such as voids can be reduced.

  Note that a curved surface is preferably provided between a side surface of the conductive layer 240B and an upper surface of the conductive layer 240B. That is, the end of the side surface and the end of the upper surface are preferably curved. The curved surface has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, for example, at the end of the conductive layer 240B. By not having a corner at the end, coverage of the film in the subsequent film forming process is improved.

  Note that the oxide film 230A, the oxide film 230B, and the conductive film 240A may be processed by a lithography method. In addition, the processing can use a dry etching method or a wet etching method. Processing by dry etching is suitable for fine processing. The processing of the oxide film 230A, the oxide film 230B, and the conductive film 240A may be performed under different conditions.

  Next, an insulating film 274A to be the insulator 274 is formed over the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 240B (see FIG. 6).

  The insulating film 274A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 274A, an insulating film having a function of suppressing transmission of oxygen is preferably used. For example, silicon nitride, silicon oxide, or aluminum oxide is formed by a sputtering method. For the insulator 274, a material that can be used for the oxide 230a and the oxide 230c can be used. For example, as the insulator 274, a metal oxide of In: Ga: Zn = 1: 3: 4 [atomic ratio] may be used.

  The insulating film 274A may have a two-layer structure. The lower layer of the insulating film 274A and the upper layer of the insulating film 274A can be formed by the above method. The lower layer of the insulating film 274A and the upper layer of the insulating film 274A can be formed by the same method. Or different methods may be used. The above material can be used for the lower layer of the insulating film 274A and the upper layer of the insulating film 274A. The lower layer of the insulating film 274A and the upper layer of the insulating film 274A may be the same material or different materials. . For example, an aluminum oxide film may be formed by a sputtering method as a lower layer of the insulating film 274A, and an aluminum oxide film may be formed by an ALD method as an upper layer of the insulating film 274A. Alternatively, an aluminum oxide film may be formed by a sputtering method as a lower layer of the insulating film 274A, and a silicon nitride film may be formed by an ALD method as an upper layer of the insulating film 274A.

  Next, an insulating film 280A is formed over the insulating film 274A. The insulating film 280A may be provided with the same kind of layer by a different film formation method. Specifically, the first film of the insulating film 280A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed by a sputtering method as a first film of the insulating film 280A, and a silicon oxide film is formed by a CVD method as a second film of the insulating film 280A. Note that heat treatment may be performed before the formation of the insulating film 280A. The heat treatment may be performed under reduced pressure and the insulating film may be formed continuously without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating film 274A and the like are removed, and further, the moisture concentration and the hydrogen concentration in the oxide 230a, the oxide 230b, and the insulating film 274A are reduced. be able to. The above heat treatment conditions can be used.

  Next, a CMP process is performed on the insulating film 280A to planarize the upper surface of the insulating film 280A (see FIG. 6).

  Next, part of the insulating film 280A, part of the insulating film 274A, and part of the conductive layer 240B are processed to form openings reaching the oxide 230b. The opening is preferably formed so as to overlap with the conductor 205. With the openings, the conductor 240a, the conductor 240b, the insulator 274, and the insulator 280 are formed (see FIG. 7).

  Processing of part of the insulating film 280A, part of the insulating film 274A, and part of the conductive layer 240B may be performed under different conditions. For example, part of the insulator 280 may be processed by a dry etching method, part of the insulating film 274A may be processed by a wet etching method, and part of the conductive layer 240B may be processed by a dry etching method.

  Here, it is preferable to remove impurities attached to or diffused into the surface of the oxide 230a, the oxide 230b, and the like. As the impurities, components included in the insulator 280, the insulating film 274A, and the conductive layer 240B, components included in a member used in a device used for forming the opening, a gas or liquid used for etching, And those caused by the components contained in. Examples of the impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

  A cleaning process is performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

  As the wet cleaning, a cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning using an aqueous solution, pure water, or carbonated water may be performed. Alternatively, these washings may be appropriately combined and performed. Note that it is preferable to use a frequency of 200 kHz or more, preferably 900 kHz or more for the ultrasonic cleaning. By using the frequency, damage to the oxide 230b and the like can be reduced.

  In the present embodiment, as the above-described cleaning treatment, wet cleaning is performed using diluted hydrofluoric acid or diluted ammonia water, and then wet cleaning is performed using pure water or carbonated water. By performing the cleaning treatment, impurities attached to the surface of the oxide 230a or the oxide 230b or diffused into the inside can be removed. Alternatively, the crystallinity of the oxide 230c over the oxide 230b can be increased.

  Next, heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the oxide film 230C may be formed continuously without exposure to the air. Note that the oxide film 230C may have a single-layer structure or a stacked structure of a plurality of layers (eg, a stacked structure of a first film and a second film). Through this step, moisture and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably from 100 ° C to 400 ° C. In this embodiment, the temperature of the heat treatment is set to 200 ° C.

  The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using the same film formation method as the oxide film 230A or the oxide film 230B, or may be formed using a different film formation method. Note that in the case where the oxide film 230C is formed by an ALD method, the contents described in the above embodiment can be referred to.

  For example, in this embodiment, an In—Ga—Zn oxide film of In: Ga: Zn = 4: 2: 3 [atomic ratio] is formed by an ALD method as a first film of the oxide film 230C. As the second film of the oxide film 230C, an In—Ga—Zn oxide film of In: Ga: Zn = 1: 3: 4 [atomic ratio] is formed by an ALD method. Alternatively, in the case where the oxide film 230C has a single-layer structure, it is preferable that an oxide having a higher proportion of gallium than the oxide 230B be formed by an ALD method as the oxide film 230C.

  By forming the first film of the oxide film 230C and the second film of the oxide film 230C by the ALD method, an oxide film having substantially the same thickness at the bottom surface and the side surface of the opening can be formed. For example, the ratio of the thickness of the first film of the oxide film 230C at the side surface of the opening to the thickness of the first film of the oxide film 230C at the bottom of the opening is 0.5 or more, and preferably 0.1 or less. It can be 7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, the ratio of the thickness of the second film of the oxide film 230C at the side surface of the opening to the thickness of the second film of the oxide film 230C at the bottom of the opening is 0.5 or more, and preferably 0.1 or less. It can be 7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, the ratio of the thickness of the first film of the oxide film 230C on the side surface of the oxide 230b to the thickness of the first film of the oxide film 230C on the upper surface of the oxide 230b is preferably 0.5 or more and 1 or less, more preferably It can be 0.7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, the ratio of the thickness of the second film of the oxide film 230C on the side surface of the oxide 230b to the thickness of the second film of the oxide film 230C on the upper surface of the oxide 230b is preferably 0.5 or more and 1 or less, more preferably It can be 0.7 or more and 1 or less, more preferably 0.9 or more and 1 or less. In the case where the oxide film formed by using the ALD method has a crystal structure, its c-axis can be substantially parallel to the normal direction of the film formation surface.

  In the case where the first film of the oxide film 230C and the second film of the oxide film 230C are formed by a sputtering method, a sputtering gas is used when forming the first film of the oxide film 230C and the second film of the oxide film 230C. May be supplied to the oxide 230a and the oxide 230b in some cases. Therefore, the proportion of oxygen contained in the sputtering gas of the first film of the oxide film 230C and the second film of the oxide film 230C may be 70% or more, preferably 80% or more, more preferably 100%.

  Next, heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the moisture concentration and the hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C are reduced. Can be reduced. The temperature of the heat treatment is preferably from 100 ° C to 400 ° C.

  The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxynitride is formed as the insulating film 250A by a CVD method. Note that the temperature at which the insulating film 250A is formed is preferably 350 ° C. or more and less than 450 ° C., and particularly preferably about 400 ° C. By forming the insulating film 250A at 400 ° C., an insulating film with few impurities can be formed.

  Next, an insulating film 252A is formed over the insulating film 250A. The insulating film 252A has a barrier property against hydrogen and water. Since the insulating film 252A has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 to the inside of the transistor 200 through the insulating film 252A is suppressed. Thus, generation of oxygen vacancies in the oxide 230 can be suppressed.

  Further, as the insulating film 252A, an insulator containing an oxide having a common metal element with an element included in the oxide 230 may be formed. In particular, in the case where an In-Ga-Zn oxide is used as the oxide 230, an insulating material containing more gallium than the oxide 230, such as gallium oxide, is preferably used for the insulating film 252A. Since the element forming the insulating film 252A and the element forming the oxide 230 are common, for example, even if the element forming the insulating film 252A diffuses into the oxide 230, the resistance of the oxide 230 is reduced. Is not a factor.

  The insulating film 252A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulating film 252A is preferably formed by an ALD method, similarly to the insulator 222.

  For example, when a gallium oxide film is formed by an ALD method as the insulating film 252A, as a gallium precursor, trimethylgallium, triethylgallium, gallium trichloride, tris (dimethylamide) gallium, gallium (III) acetylacetonate, Tris (2,2,6,6-tetramethyl-3,5-heptanedioic acid) gallium, dimethylchlorogallium, diethylchlorogallium and the like can be used.

  Some precursors include one or both of carbon and chlorine in addition to the metal element. An oxide film formed using a precursor containing carbon may contain carbon in some cases. Further, an oxide film formed using a precursor containing chlorine may contain chlorine in some cases.

  Next, a conductive film 260A and a conductive film 260B are sequentially formed. The conductive films 260A and 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use a CVD method. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method (see FIG. 8).

  Next, the first film of the oxide film 230C and the second film of the oxide film 230C, the insulating film 250A, the insulating film 252A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. Thus, the oxide 230c, the insulator 250, the insulator 252, and the conductor 260 (the conductor 260a and the conductor 260b) are formed (see FIG. 9). Thus, the oxide 230c is arranged to cover the inner wall (side wall and bottom surface) of the opening reaching the oxide 230b. Further, the insulator 250 and the insulator 252 are provided so as to cover the inner wall of the opening with the oxide 230c interposed therebetween. Further, the conductor 260 is provided so as to fill the opening with the oxide 230c, the insulator 250, and the insulator 252 interposed therebetween.

  Next, heat treatment may be performed. In this embodiment mode, treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere. By the heat treatment, the moisture concentration and the hydrogen concentration in the insulator 250, the insulator 252, and the insulator 280 can be reduced.

  Next, the insulator 282 and the insulator 283 are formed over the oxide 230c, the insulator 250, the insulator 252, the conductor 260, and the insulator 280. The insulator 282 and the insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, similarly to the insulators 212 and 214. As the insulator 282 and the insulator 283, for example, an aluminum oxide film or a silicon nitride film is preferably formed by a sputtering method. By forming an aluminum oxide film or a silicon nitride film by a sputtering method, diffusion of hydrogen of the insulator 282 and the insulator 283 into the oxide 230 can be suppressed. Further, by forming the insulator 282 so as to be in contact with the conductor 260, oxidation of the conductor 260 can be suppressed, which is preferable.

  Further, oxygen can be supplied to the insulator 280 by forming an aluminum oxide film as the insulator 282 by a sputtering method. Oxygen supplied to the insulator 280 may be supplied to the channel formation region included in the oxide 230b through the oxide 230c. Further, when oxygen is supplied to the insulator 280, oxygen contained in the insulator 280 before the formation of the insulator 282 is supplied to the channel formation region included in the oxide 230b through the oxide 230c. In some cases.

  Alternatively, a structure may be employed in which an aluminum oxide film is formed by a sputtering method as the insulator 282 and silicon nitride is formed by a sputtering method on the aluminum oxide film as the insulator 283.

  Next, heat treatment may be performed. For the heat treatment, the above-described heat treatment conditions can be used. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced. Further, oxygen included in the insulator 282 can be injected into the insulator 280.

  Note that as a method for forming the insulator 282 and the insulator 283, first, an aluminum oxide film is formed over the oxide 230c, the insulator 250, the insulator 252, the conductor 260, and the insulator 280 by a sputtering method. Then, heat treatment is performed using the above heat treatment conditions, the aluminum oxide film is removed by CMP treatment, and then insulators 282 and 283 are formed. Is also good. With this method, an excess oxygen region can be formed in the insulator 280 more. Note that in the step of removing the aluminum oxide film, part of the insulator 280, part of the conductor 260, part of the insulator 250, part of the insulator 252, and part of the oxide 230c are removed. In some cases.

  Further, an insulator may be provided between the insulator 280 and the insulator 282. As the insulator, for example, silicon oxide formed by a sputtering method may be used. With the provision of the insulator, an excess oxygen region can be formed in the insulator 280.

  Next, the insulator 284 may be formed over the insulator 282. The insulator 284 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 1).

  According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
One embodiment of the present invention relates to a manufacturing method which can be used for the method for manufacturing the semiconductor device described in the above embodiment, and an apparatus for manufacturing the semiconductor device.

<Metal oxide applicable to oxide semiconductors and gate insulators>
Hereinafter, the metal oxide according to the present invention will be described.

  The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferable that aluminum, gallium, yttrium, tin, or the like be contained in addition thereto. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.

  Here, the case where the oxide semiconductor is InMZnO containing indium, the element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, in some cases, a combination of a plurality of the aforementioned elements may be used as the element M.

  On the other hand, the gate insulator is preferably an oxide containing at least the element I. The element I may include one or more selected from gallium, aluminum, hafnium, boron, titanium, silicon, germanium, zirconium, yttrium, cerium, magnesium, or the like. Note that when the oxide semiconductor is InMZnO, the element I is preferably the same as the element M.

  Note that in this specification and the like, a metal oxide containing nitrogen may be collectively referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as metal oxynitride.

  Here, the case where the metal oxide contains indium, the element M, and zinc is considered. Note that the terms of the atomic ratio of indium, element M, and zinc included in the metal oxide are [In], [M], and [Zn].

  17A, 17B, and 17C illustrate indium, an element M, and zinc included in a metal oxide that can be used for the oxide of one embodiment of the present invention. The preferred range of the atomic ratio of the above will be described. Note that FIGS. 17A, 17B, and 17C do not describe the atomic ratio of oxygen. The terms of the atomic ratios of indium, element M, and zinc included in the metal oxide are [In], [M], and [Zn].

  In FIGS. 17A, 17B, and 17C, a broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. (-1 ≦ α ≦ 1) line, [In]: [M]: [Zn] = (1 + α) :( 1-α): 2 line with atomic ratio, [In]: [M] : [Zn] = (1 + α) :( 1-α): Line having an atomic ratio of 3: 3, [In]: [M]: [Zn] = (1 + α) :( 1-α): 4 atomic number A line representing a ratio and a line representing an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 5 are shown.

  The dash-dot line is a line having an atomic ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), [In]: [M]: [Zn] = 2: Line with an atomic ratio of 1: β, [In]: [M]: [Zn] = 1: 1: Line with an atomic ratio of β, [In]: [M]: [Zn] = 1: A line having an atomic ratio of 2: β, a line having an atomic ratio of [In]: [M]: [Zn] = 1: 3: β, and a line having an atomic ratio of [In]: [M]: [Zn] = 1 : 4: represents a line that represents the atomic ratio of β.

  The atomic ratio [In]: [M]: [Zn] = 0: 2: 1 shown in FIG. 17A, FIG. 17B, and FIG. Metal oxides easily have a spinel-type crystal structure.

  In addition, a plurality of phases may coexist in the metal oxide (such as coexistence of two phases and coexistence of three phases). For example, when the atomic ratio is in the vicinity of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel type crystal structure and a layered crystal structure are likely to coexist. When the atomic ratio is in the vicinity of [In]: [M]: [Zn] = 1: 0: 0, two phases of a bixbite type crystal structure and a layered crystal structure are likely to coexist. When a plurality of phases coexist in a metal oxide, a crystal grain boundary may be formed between different crystal structures.

  A region A illustrated in FIG. 17A illustrates an example of a preferable range of the atomic ratio of indium, the element M, and zinc included in the metal oxide.

  By increasing the indium content of the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide having a high indium content has a higher carrier mobility than a metal oxide having a low indium content.

  On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility is low. Therefore, when the atomic ratio is [In]: [M]: [Zn] = 0: 1: 0 and its vicinity (for example, the region C shown in FIG. 17C), the insulating property is high. .

  For example, the metal oxide used for the channel formation region and the low-resistance region preferably has a high carrier mobility and an atomic ratio shown in a region A in FIG. The metal oxide used for the channel formation region and the low-resistance region may be, for example, In: Ga: Zn = 4: 2: 3 to 4.1 or a value close to 4.1. On the other hand, in the case where a metal oxide is provided so as to surround the channel formation region or the low-resistance region, it is preferable that the metal oxide have a relatively high insulating property and an atomic ratio shown in a region C in FIG. The metal oxide provided to surround the channel formation region and the low-resistance region is, for example, In: Ga: Zn = 1: 3: 4 or In: Ga: Zn = 1: 3: 2. do it. Alternatively, as a metal oxide provided to surround the channel formation region and the low-resistance region, a metal oxide equivalent to the metal oxide used for the channel formation region and the low-resistance region may be used.

  In particular, in the region B shown in FIG. 17B, an excellent metal oxide having high carrier mobility and high reliability can be obtained even in the region A.

  Note that the region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and values in the vicinity thereof. The nearby values include, for example, [In]: [M]: [Zn] = 5: 3: 4. In addition, the region B has [In]: [M]: [Zn] = 5: 1: 6 and its vicinity, and [In]: [M]: [Zn] = 5: 1: 7 and its vicinity. Includes nearby values.

  Further, the atomic ratio of the metal oxide also affects the ease of diffusion or permeation of oxygen in the metal oxide.

  In the region A having a high indium content, particularly in the metal oxide in the region B (hereinafter referred to as a first metal oxide), oxygen is easily diffused, and oxygen absorbed in a material adjacent to the first metal oxide can be absorbed or absorbed. The release of oxygen to the material adjacent to the first metal oxide is easily performed. That is, when the first metal oxide is provided between the first material containing oxygen and the second material having a lower oxygen content than the first material, the oxygen contained in the first material May be supplied to the second material through the first metal oxide. On the other hand, in the metal oxide in the region C (referred to as the second metal oxide), diffusion of oxygen hardly occurs. Therefore, the second metal oxide suppresses the transmission of oxygen and functions as a blocking layer for oxygen. There are cases. That is, by providing the second metal oxide between the third material containing oxygen and the fourth material having a lower oxygen content than the third material, the oxygen contained in the third material can be obtained. In some cases, diffusion may be suppressed by the second metal oxide, and supply to the fourth material may be suppressed.

  As described above, the atomic ratio in the metal oxide is important from the viewpoint of the electric conduction characteristics and the oxygen diffusion characteristics, and should be controlled according to the characteristics required for the metal oxide.

  When a metal oxide is formed by a sputtering method, the atomic ratio of a sputtering target depends on the atomic ratio of a film. In the case where an In-M-Zn oxide is used as the metal oxide, it is preferable to use a target including a polycrystalline In-M-Zn oxide as the sputtering target. Note that the atomic ratio of the metal oxide to be formed includes a variation of ± 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the formed metal oxide is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic ratio]. When the composition of the sputtering target used for the metal oxide is In: Ga: Zn = 5: 1: 7 [atomic ratio], the composition of the metal oxide to be formed is In: Ga: Zn = 5: It may be in the vicinity of 1: 6 [atomic ratio].

  Note that the properties of the metal oxide are not uniquely determined by the atomic ratio. Even with the same atomic ratio, the properties of the metal oxide may be different depending on the formation conditions. For example, when a metal oxide is formed by a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of the target is formed. [Zn] of the film may be smaller than [Zn] of the target depending on the substrate temperature at the time of film formation. Therefore, the illustrated region is a region having an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries between the regions A to C are not strict.

  Here, when a plurality of metal oxides having different atomic ratios are stacked, a plurality of sputtering targets corresponding to the respective atomic ratios and a plurality of chambers in which these are installed are required.

  In addition, in the case of film formation using a sputtering method, particles during film formation are incident on a surface on which a film is to be formed. There is. Here, the film formation damage includes formation of a mixed layer due to the incidence of particles during film formation into the film, and reduction of the crystallization rate of the film when the film has crystals.

  In view of the above problem in film formation using a sputtering method, it is preferable that the atomic ratio of the metal oxide can be adjusted by film formation conditions of the metal oxide. In addition, it is preferable to use a film formation method with reduced film formation damage for forming a metal oxide.

  To solve the above problem, an ALD method can be used as a method for forming a metal oxide.

  The ALD method enables the deposition of atoms one by one by utilizing the self-controllability of the precursor molecules or the atoms contained in the precursor, so that an extremely thin film can be formed, and a film having a high aspect ratio can be formed. It is possible to form a film with few defects such as pinholes, to form a film with excellent coverage, and to form a film at a low temperature. The ALD method also includes a plasma-enhanced ALD (PEALD: Plasma Enhanced ALD) method using a plasma. The use of plasma enables a film formation at a lower temperature, which is preferable in some cases. Some precursors used in the ALD method include elements such as carbon and chlorine. For this reason, a film formed by an ALD method may contain more elements such as carbon and chlorine than a film formed by another film formation method. In addition, the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

  The ALD method is different from a film formation method in which particles emitted from a target or the like are deposited, and is a film formation method in which a film is formed by a reaction on the surface of an object to be processed. Therefore, the film forming method is less affected by the shape of the object to be processed and has good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low deposition rate, it may be preferable to use the ALD method in combination with another deposition method such as a CVD method with a high deposition rate.

  In the ALD method, the composition of the obtained film can be controlled by the amount of the source gas introduced. For example, in the ALD method, a film having an arbitrary composition can be formed depending on the amount of introduced source gas and the number of introductions (also referred to as the number of pulses). Further, for example, in the ALD method, a film whose composition is continuously changed can be formed by changing the source gas while forming the film. When film formation is performed while changing the source gas, the time required for film formation can be shortened as compared with the case of film formation using a plurality of film formation chambers, because the time required for transport and pressure adjustment is not required. it can. Therefore, the productivity of the semiconductor device may be improved in some cases.

<ALD apparatus and film formation method using ALD method>
Here, an ALD apparatus that can be used for forming the metal oxide of one embodiment of the present invention and a film formation method using the ALD method are described.

A film forming apparatus using the ALD method alternates a first source gas (also called a precursor, a precursor, or a metal precursor) and a second source gas (also called a reactant, a reactant, or a non-metal precursor) for a reaction. Then, the film is formed by repeating the introduction of these source gases. The switching of the introduction of the source gas can be performed, for example, by switching the respective switching valves (also referred to as high-speed valves). In addition, when introducing the source gas, an inert gas such as nitrogen (N ₂ ) or argon (Ar) may be introduced into the chamber together with the source gas as a carrier gas. By using a carrier gas, even when the volatility of the raw material gas is low or the vapor pressure is low, it is possible to prevent the raw material gas from being adsorbed inside the piping or the valve and to introduce the raw material gas into the chamber. Become. Further, the uniformity of the formed film is also improved, which is preferable.

An example of a film formation method using the ALD method will be described with reference to FIGS. First, a first source gas is introduced into the chamber (see FIG. 11A), and the precursor 601 is adsorbed on the substrate surface (first step). Here, when the precursor 601 is adsorbed on the substrate surface, a self-stopping mechanism of the surface chemical reaction is activated, and the precursor is not further adsorbed on the precursor layer on the substrate (see FIG. 11B). . Note that the appropriate range of the substrate temperature at which the self-stop mechanism of the surface chemical reaction acts is also referred to as ALD Window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, and the like of the precursor, and is set to 100 ° C. to 500 ° C., preferably 200 ° C. to 400 ° C. Next, excess precursors, reaction products, and the like are discharged from the chamber by vacuum evacuation (second step). Instead of vacuum evacuation, an inert gas (eg, argon or nitrogen) or the like may be introduced into the chamber, and surplus precursor or reaction products may be exhausted from the chamber. This step is also called purging. Next, a reactant 602 (for example, an oxidant (ozone (O ₃ ), oxygen (O ₂ ), water (H ₂ O), and plasma, radicals, ions, and the like thereof)) is supplied as a second source gas to the chamber. (See FIG. 11C), and reacts with the precursor 601 adsorbed on the substrate surface to release some of the components contained in the precursor 601 while adsorbing the constituent molecules of the film on the substrate (third). Step) (see FIG. 11D). Next, excess reactants 602, reaction products, and the like are exhausted from the chamber by evacuation or introduction of an inert gas (fourth step).

  In the following description of the present specification, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or an oxidizing agent, these are not limited to a gas or molecular state, but a plasma state or a radical state. , And in the ionic state. When a film is formed using an oxidizing agent in a plasma state, a radical state, or an ion state, a radical ALD apparatus or a plasma ALD apparatus described later may be used.

  As the oxidizing agent, water is preferably used to remove carbon contained in the precursor. Hydrogen contained in water reacts with carbon contained in the precursor, so that carbon can be efficiently released from the precursor. On the other hand, when it is desired to reduce hydrogen contained in the formed film as much as possible, it is preferable to use ozone or oxygen containing no hydrogen as the oxidizing agent. Further, water is introduced into the chamber as a first oxidizing agent to remove carbon contained in the precursor, and then evacuated, and ozone and oxygen containing no hydrogen are introduced into the chamber as a second oxidizing agent. To remove hydrogen and then perform evacuation. After that, the first to fourth steps are repeated until a desired film thickness is obtained.

  In the above description, an example is shown in which the first source gas is introduced into the chamber and then the second source gas is introduced into the chamber, but the present invention is not limited to this. The first source gas may be introduced into the chamber after the second source gas is introduced into the chamber. That is, first, after the third step and the fourth step, the first step, the second step, the third step, and the fourth step are performed, and thereafter, the first step to the fourth step are repeatedly performed. May be performed. Further, the third step and the fourth step may be repeated a plurality of times, and then the first to fourth steps may be repeatedly performed to form a film.

  As described above, it is preferable that the third step and the fourth step be performed once or plural times before the first step because the film formation atmosphere in the chamber can be controlled. For example, as a third step, by introducing an oxidizing agent, the inside of the chamber can be made to have an oxygen atmosphere. Starting film formation in an oxygen atmosphere can increase the oxygen concentration in the formed film, which is preferable. Further, oxygen can be supplied to an insulator or an oxide which is a base of the film. A semiconductor device formed using such a method has favorable characteristics and high reliability can be obtained.

  Further, after the first step and the second step, the introduction of the second source gas in the third step and the evacuation or introduction of the inert gas in the fourth step may be repeated a plurality of times. That is, the first step, the second step, the third step, the fourth step, the third step, the fourth step, and the third step and the fourth step are repeatedly performed, and then the first step and the second step are performed. You may.

For example, O ₃ and O ₂ may be introduced as oxidizing agents in the third step, and evacuation may be performed in the fourth step, and this step may be repeated a plurality of times.

When the third step and the fourth step are repeated, it is not always necessary to repeat the introduction of the same type of source gas. For example, H ₂ O may be used as the oxidizing agent in the first third step, and O ₃ may be used as the oxidizing agent in the second and subsequent third steps.

  In this way, the introduction of the oxidizing agent and the evacuation (or the introduction of the inert gas) in the chamber are repeated a plurality of times in a short period of time, so that extra hydrogen atoms, carbon atoms, and chlorine are removed from the precursor adsorbed on the substrate surface. Atoms can be more reliably removed and removed outside the chamber. In addition, by increasing the number of types of the oxidizing agents to two, it is possible to remove excess hydrogen atoms and the like from the precursor adsorbed on the substrate surface. In this manner, water and hydrogen contained in the formed film can be reduced by preventing hydrogen atoms from being taken into the film during the film formation.

By using such a method, the desorption amount of water molecules is 1.0 × 10 ¹³ molecular / cm ^{2 in} the surface temperature range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. by TDS analysis. A film having a thickness of 1.0 × 10 ¹⁶ molecular / cm ² or less, more preferably 1.0 × 10 ¹³ molecular / cm ² or more and 3.0 × 10 ¹⁵ molecular / cm ² or less can be formed.

  In this manner, the first single layer can be formed on the surface of the substrate, and the first to fourth steps are performed again, whereby the second single layer is stacked on the first single layer. be able to. By repeating the first to fourth steps a plurality of times while controlling the gas introduction until the film has a desired thickness, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible, which is suitable for manufacturing a fine transistor.

  Further, the film formed by the above method may have a layered structure. Further, when the film formed by the above method has a crystal structure, the c-axis of the film is oriented in a direction substantially parallel to the normal direction of the surface on which the film is to be formed. That is, the c-axis of the film is oriented perpendicular to the film formation surface. Although details are described later, such a crystal structure is referred to as a CAAC structure in this specification, and an oxide semiconductor (metal oxide) having the CAAC structure is referred to as a CAAC-OS in some cases. By using the ALD method, a metal oxide having a CAAC structure can be formed.

  The ALD method is a film formation method performed by reacting a precursor and a reactant using thermal energy. The temperature required for the reaction of the precursor and the reactant is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., and is set to 100 ° C to 500 ° C, preferably 200 ° C to 400 ° C. Further, in addition to the above-described reaction of the precursor and the reactant, the ALD method in which the plasma-excited reactant is introduced into the chamber as the third source gas to perform the treatment may be referred to as a plasma ALD method. In this case, a plasma generating device is provided at the introduction portion of the third source gas. For generation of plasma, inductively coupled plasma (ICP) can be used. On the other hand, the ALD method in which the reaction between the precursor and the reactant is performed with thermal energy may be referred to as a thermal ALD method.

In the plasma ALD method, a reactant excited by plasma in the third step is introduced to form a film. Alternatively, the film formation is performed by introducing the plasma-excited reactant (second reactant) at the same time as repeating the first to fourth steps. In this case, the reactant introduced in the third step is called a first reactant. In the plasma ALD method, the second reactant used for the third source gas can use the same material as the oxidizing agent. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. Further, a nitriding agent may be used as the second reactant in addition to the oxidizing agent. Nitrogen (N ₂ ) or ammonia (NH ₃ ) can be used as the nitriding agent. Further, a mixed gas of nitrogen (N ₂ ) and hydrogen (H ₂ ) can be used as a nitriding agent. For example, a mixed gas of nitrogen (N ₂ ) 5% and hydrogen (H ₂ ) 95% can be used as a nitriding agent. By forming a film while introducing plasma-excited nitrogen or ammonia, a nitride film such as a metal nitride film can be formed.

Further, argon (Ar) or nitrogen (N ₂ ) may be used as a carrier gas of the second reactant. Use of a carrier gas such as argon or nitrogen is preferable because plasma discharge is facilitated and a plasma-excited second reactant is easily generated. Note that in the case where an oxide film such as a metal oxide film is formed by a plasma ALD method, when nitrogen is used as a carrier gas, nitrogen is mixed into the film and a desired film quality may not be obtained. In this case, it is preferable to use argon as the carrier gas.

  The ALD method can form an extremely thin film with a uniform thickness. Further, the surface coverage is high even on a surface having irregularities.

  Further, by forming a film by the plasma ALD method, a film can be formed at a lower temperature as compared with the thermal ALD method. In the plasma ALD method, for example, a film can be formed at a temperature of 100 ° C. or lower without lowering the film formation rate. In addition, in the plasma ALD method, not only an oxidizing agent but also many reactants such as a nitriding agent can be used, so that not only oxides but also many types of films such as nitrides, fluorides, and metals can be formed. Can be.

  In the case where the plasma ALD method is performed, plasma can be generated in a state separated from the substrate, such as inductively coupled plasma (ICP). By generating plasma in this way, plasma damage can be suppressed.

  Through the above method, a film, an oxide film, or a nitride film containing atoms contained in the first source gas as one component can be formed.

  On the other hand, when a film containing a plurality of metals is formed as the metal oxide, a plurality of precursors may be prepared for each metal and introduced into the chamber sequentially.

  When an In-M-Zn oxide is formed as a metal oxide, a source gas including a first precursor including indium is introduced into a chamber, and excess source gas is exhausted (purged). Next, as a reactant, an oxidant is introduced into the chamber, and excess reactant is exhausted. Next, a source gas containing a second precursor containing the element M is introduced into the chamber, and excess source gas is exhausted (purged). Next, as a reactant, an oxidant is introduced into the chamber, and excess reactant is exhausted. Next, a source gas containing a third precursor containing zinc is introduced into the chamber, and excess source gas is exhausted (purged). Next, as a reactant, an oxidant is introduced into the chamber, and excess reactant is exhausted. By repeating the above steps, a metal oxide including a single layer containing indium, a single layer containing element M, and a single layer containing zinc can be formed. Note that the order of introducing the source gases is not limited to the above. After the introduction of the source gas containing the first precursor, the source gas containing the third precursor may be introduced, and then the source gas containing the second precursor may be introduced. Can be appropriately determined. Further, after the introduction of each source gas, the exhaust of the extra source gas, the introduction of the reactant, and the exhaust can be appropriately performed. Note that the metal oxide is not limited to the In-M-Zn oxide. As described above, the metal oxide preferably contains at least indium or zinc, and particularly preferably contains indium and zinc. Further, the number of types of metals contained in the metal oxide may be two or four or more.

  The atomic ratio of the metal contained in the metal oxide can be controlled by adjusting the number of introductions of the source gas containing the precursor containing the desired metal into the chamber and adjusting the film formation temperature. For example, when it is desired to increase the atomic ratio of the element M with respect to indium or zinc, a source gas including the second precursor including the element M is introduced into the chamber, an excess source gas is exhausted, and as a reactant, After introducing the oxidizing agent into the chamber and exhausting the excess reactant, the source gas containing the second precursor containing the element M is introduced again into the chamber, and the excess source gas is exhausted. And then exhaust the excess reactants.

  Further, a plurality of precursors may be introduced into the chamber. For example, a source gas including the first precursor is introduced into the chamber, an excess source gas is exhausted, a reactant is introduced into the chamber, and an extra reactant is exhausted. Then, the source gas including the second precursor and the third precursor is introduced into the chamber, the excess source gas is exhausted, the reactant is introduced into the chamber, and the extra reactant is exhausted, so that the In-M- A metal oxide containing a Zn oxide may be formed. The combination of the precursors introduced into the chamber is not limited to the above. A source gas including the first precursor and the second precursor may be introduced into the chamber, a source gas including the first precursor and the third precursor may be introduced into the chamber, and the first precursor and the third precursor may be introduced into the chamber. May be introduced into the chamber including the precursor of the second precursor, the second precursor, and the third precursor. The practitioner can appropriately determine the properties of the film required.

  Further, source gases containing different precursors may be continuously introduced into the chamber. For example, a source gas containing a first precursor is introduced into a chamber, an excess source gas is exhausted, a reactant is introduced into the chamber, an extra reactant is exhausted, and a source gas containing a second precursor is introduced into the chamber. Then, after exhausting the excess source gas, the reactant is not introduced into the chamber, the source gas including the third precursor is continuously introduced into the chamber, the excess source gas is exhausted, and the reactant is introduced into the chamber. Alternatively, a metal oxide containing an In-M-Zn oxide may be formed by exhausting excess reactants. The order and combination of the precursors continuously introduced into the chamber are not limited to the above. After the source gas containing the third precursor is introduced into the chamber, the source gas containing the second precursor may be introduced into the chamber, or after the source gas containing the first precursor is introduced into the chamber, the reactant gas The source gas containing the second precursor may be introduced into the chamber without being introduced. The practitioner can appropriately determine the properties of the film required.

  Alternatively, a metal oxide may be formed using a precursor containing a plurality of metals. For example, a metal oxide may be formed using a precursor containing indium and element M in one molecule, a precursor containing indium and zinc in one molecule, a precursor containing element M and zinc in one molecule, or the like.

<Structure of metal oxide>
The structure of a Cloud-Aligned Composite (CAC) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

  Note that in this specification and the like, CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be used. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or structure of a material.

  The CAC-OS or CAC-metal oxide has a conductive function in part of a material, an insulating function in part of the material, and a semiconductor function as a whole of the material. Note that in the case where CAC-OS or CAC-metal oxide is used for an active layer of a transistor, a conductive function is a function of flowing electrons (or holes) serving as carriers and an insulating function is a function of flowing electrons (carriers). It is a function that does not flow. A switching function (on / off function) can be given to the CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In the CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be maximized.

  Further, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In some cases, a conductive region and an insulating region are separated at a nanoparticle level in a material. Further, the conductive region and the insulating region may be unevenly distributed in the material. In some cases, the conductive region is blurred at the periphery and observed in a cloud shape.

  In the CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material in a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide includes components having different band gaps. For example, a CAC-OS or a CAC-metal oxide includes a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. Further, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, in the case where the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained when the transistor is on.

  That is, the CAC-OS or the CAC-metal oxide may be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. Semiconductors.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in an ab plane direction and has a strain. Note that the strain refers to a region where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and a region where another lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.

  The nanocrystal is based on a hexagon, but is not limited to a regular hexagon and may be a non-regular hexagon. In addition, distortion may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, it is difficult to confirm a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of distortion. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction, or the substitution distance of a metal element changes the bonding distance between atoms. That's why.

  Further, the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, an (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be referred to as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be referred to as an (In, M) layer.

CAAC-OS is a metal oxide with high crystallinity. On the other hand, in the CAAC-OS, it is difficult to confirm a clear crystal grain boundary; thus, it can be said that electron mobility due to the crystal grain boundary is not easily reduced. Moreover, since the crystallinity of the metal oxide that may be reduced by such generation of contamination and defects impurities, CAAC-OS impurities and defects (oxygen deficiency _(V O:. Oxygen vacancy also referred) etc.) with less metal It can also be called an oxide. Therefore, a metal oxide having a CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.

  The nc-OS has a periodic atomic arrangement in a minute region (for example, a region with a thickness of 1 nm to 10 nm, particularly a region with a size of 1 nm to 3 nm). In the nc-OS, there is no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  Note that indium-gallium-zinc oxide (hereinafter, referred to as IGZO), which is a kind of metal oxide including indium, gallium, and zinc, may have a stable structure by being formed using the above-described nanocrystal. is there. In particular, since IGZO tends to be difficult to grow in the air, it is preferable to use a smaller crystal (for example, the above-described nanocrystal) than a large crystal (here, a crystal of several mm or a crystal of several cm). However, it may be structurally stable.

  The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

  Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

  Note that in the semiconductor device of one embodiment of the present invention, the structure of the oxide semiconductor (metal oxide) is not particularly limited, but preferably has crystallinity. For example, the oxide 230 can have a CAAC-OS structure and the oxide 243 can have a hexagonal crystal structure. When the oxide 230 and the oxide 243 have the above crystal structure, a highly reliable semiconductor device can be obtained.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

In addition, when an alkali metal or an alkaline earth metal is contained in a metal oxide, a defect level may be formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the metal oxide. Specifically, the concentration of an alkali metal or an alkaline earth metal in a metal oxide obtained by SIMS (the concentration obtained by Secondary Ion Mass Spectrometry (SIMS)) is set to 1 × 10 ¹⁸ atoms. / Cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

  In addition, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers are generated in some cases. In addition, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁸ atoms / cm 3. ^{It is} less than ³ and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . When a metal oxide with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electric characteristics can be provided.

  It is preferable to use a thin film with high crystallinity as the metal oxide used for the semiconductor of the transistor. With the use of the thin film, stability or reliability of the transistor can be improved. Examples of the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film. However, forming a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide on a substrate requires a high-temperature or laser heating step. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

  It was reported in Non-Patent Documents 1 and 2 that an In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, crystal grain boundaries are not clearly observed, and can be formed on a substrate at a low temperature. Further, it is reported that a transistor using CAAC-IGZO has excellent electric characteristics and reliability.

  In 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it has been reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less) and that there is no regularity in crystal orientation between different regions. I have.

  Non-Patent Documents 4 and 5 show changes in the average crystal size due to the irradiation of an electron beam to each of the thin films of CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity. In an IGZO thin film having low crystallinity, crystalline IGZO of about 1 nm has been observed even before irradiation with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure in IGZO could not be confirmed. Furthermore, it is shown that the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability to electron beam irradiation than the IGZO thin film having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.

A transistor including a metal oxide has extremely low leakage current in a non-conducting state. Specifically, the off-state current per 1 μm of channel width of the transistor is in the order of yA / μm (10 ⁻²⁴ A / μm). Is shown in Non-Patent Document 6. For example, a low-power-consumption CPU utilizing the characteristic of low leakage current of a transistor including a metal oxide is disclosed (see Non-Patent Document 7).

  In addition, an application of a transistor using a metal oxide to a display device, which utilizes a characteristic of a transistor having low leakage current, has been reported (see Non-Patent Document 8). In the display device, the displayed image is switched several tens of times per second. The number of times the image is switched per second is called a refresh rate. Also, the refresh rate may be called a drive frequency. Such high-speed switching of screens, which is difficult to perceive with human eyes, is considered as a cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of times of rewriting the image. Further, power consumption of the display device can be reduced by driving with a reduced refresh rate. Such a driving method is called idling stop (IDS) driving.

  The discovery of the CAAC structure and the nc structure contributes to improvement in electrical characteristics and reliability of a transistor including a metal oxide having a CAAC structure or an nc structure, reduction in cost of a manufacturing process, and improvement in throughput. In addition, research on application of the transistor to a display device and an LSI utilizing the characteristic of the transistor having a low leak current has been advanced.

  As described above, the ALD method can form a film on a structure having a high aspect ratio, and can form a film with excellent coverage even on the side surface of the structure. By using the ALD method, a metal oxide having a CAAC structure can be easily formed regardless of the direction of a deposition surface. For example, even when the structure has a convex shape or a concave shape, a metal oxide can be formed with good coverage on the top surface, the bottom surface, the side surface, and the inclined surface of the structure. That is, a metal oxide having a substantially constant thickness in the normal direction can be formed on each of the deposition surfaces. In the metal oxide formed on the top surface, the bottom surface, the side surfaces, and the inclined surface of the structure, the ratio of the minimum thickness to the maximum thickness is 0.5 or more and 1 or less, preferably 0.7 or more and 1 or less More preferably, it can be set to 0.9 or more and 1 or less. At this time, when the metal oxide has a crystal structure, its c-axis is oriented in a direction substantially parallel to a normal direction of each film formation surface. That is, the c-axis is oriented perpendicular to the respective deposition surfaces.

  FIG. 12 is a diagram illustrating a metal oxide 51 including an In-M-Zn oxide formed in the structure 50. Here, the structure refers to an element included in a semiconductor device such as a transistor. The structure 50 includes conductors such as a substrate, a gate electrode, a source electrode, and a drain electrode; insulators such as a gate insulating film, an interlayer insulating film and a base insulating film; and semiconductors such as metal oxide and silicon. . FIG. 12A illustrates a case where the deposition surface of the structure body 50 is arranged in parallel with a substrate (or a base, not shown). FIG. 12B is an enlarged view of a region 53 which is a part of the metal oxide 51 in FIG. FIG. 12B illustrates a state in which a layer containing indium and a layer containing element M and zinc are stacked on the top surface or the bottom surface of the structure 50. The layer containing In is arranged in parallel with the film formation surface of the structure 50, and a layer containing the element M and zinc is arranged thereon in parallel with the film formation surface of the structure 50. That is, the a-b plane of the metal oxide 51 is substantially parallel to the film formation surface of the structure 50, and the c-axis of the metal oxide 51 is the normal direction of the film formation surface of the structure 50. And approximately parallel.

  FIG. 12C illustrates a case where the deposition surface of the structure body 50 is arranged perpendicular to a substrate (or a base, not illustrated). FIG. 12D is an enlarged view of a region 54 which is a part of the metal oxide 51 in FIG. FIG. 12D illustrates a state where a layer containing indium and a layer containing element M and zinc are stacked on the side surface of the structure 50. The layer containing In is arranged in parallel with the film formation surface of the structure 50, and a layer containing the element M and zinc is arranged thereon in parallel with the film formation surface of the structure 50. That is, the a-b plane of the metal oxide 51 is substantially parallel to the film formation surface of the structure 50, and the c-axis of the metal oxide 51 is the normal direction of the film formation surface of the structure 50. And approximately parallel.

  Here, a method for forming the metal oxide 51 including an In-M-Zn oxide is described in detail with reference to FIGS. Note that FIG. 13 illustrates an example in which an InO layer is formed as a layer containing indium, and an (M, Zn) O layer is formed thereover as a layer containing an element M and zinc. In this embodiment, Not exclusively. First, an (M, Zn) O layer may be formed, and an InO layer may be formed thereon. Alternatively, one of a layer containing element M and a layer containing zinc may be formed over the InO layer, and the other of the layer containing element M and the layer containing zinc may be formed thereover.

  First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed on the surface of the structure 50 (see FIG. 13A). Here, the source gas includes a carrier gas such as argon and nitrogen in addition to the precursor. As a precursor containing indium, triethylindium, tris (2,2,6,6-tetramethyl-3,5-heptanedioic acid) indium, cyclopentadienylindium, or the like can be used. Next, the inside of the chamber is purged, and surplus precursors, reaction products, and the like are discharged from the chamber. Next, as a reactant, an oxidizing agent is introduced into the chamber, and reacted with the adsorbed precursor to remove components other than indium while adsorbing the indium on the substrate, thereby forming an InO layer in which indium and oxygen are combined. (See FIG. 13B). Ozone, oxygen, water, and the like can be used as the oxidizing agent. Next, the inside of the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

  Next, a source gas containing a precursor containing the element M and a precursor containing zinc is introduced into the chamber, and the precursor is adsorbed on the InO layer (see FIG. 13C). The source gas includes a carrier gas such as argon and nitrogen in addition to the precursor. When gallium is used as the element M, precursors containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris (dimethylamide) gallium, gallium (III) acetylacetonate, and tris (2,2,6,6-tetra Gallium methyl-3,5-heptanedionate, dimethylchlorogallium, diethylchlorogallium and the like can be used. Further, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis (2,2,6,6-tetramethyl-3,5-heptanedioic acid), or the like can be used. Next, the inside of the chamber is purged, and surplus precursors, reaction products, and the like are discharged from the chamber. Next, as a reactant, an oxidizing agent is introduced into the chamber, reacted with the adsorbed precursor, and the elements other than the element M and zinc are desorbed while the element M and zinc are adsorbed on the substrate. Are formed, and a layer (M, Zn) O layer in which zinc and oxygen are combined is formed. Next, the inside of the chamber is purged, and excess reactants and reaction products are discharged from the chamber. By repeating the formation of the (M, Zn) O layer a plurality of times, a (M, Zn) O layer having a desired number of atoms, number of layers, and thickness may be formed (see FIG. 13D). ).

  Next, an InO layer is formed again over the (M, Zn) O layer by the above-described method (see FIG. 13E). By repeating the above method, the metal oxide 51 can be formed on the substrate or the structure.

  Some precursors include one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon in some cases. Further, a film formed using a precursor containing chlorine may contain chlorine in some cases.

  As described above, by forming the metal oxide 51 using the ALD method, a metal oxide having a CAAC structure in which the c-axis is oriented substantially in parallel to the normal direction of the deposition surface can be formed.

  Here, as an example of an apparatus capable of forming a film by using the ALD method, a structure of a film formation apparatus 4000 will be described with reference to FIGS. FIG. 14A is a schematic view of a multi-chamber type film forming apparatus 4000, and FIG. 14B is a cross-sectional view of an ALD apparatus that can be used for the film forming apparatus 4000.

<Configuration example of film forming apparatus>
The film formation apparatus 4000 includes a loading / unloading chamber 4002, a loading / unloading chamber 4004, a transfer chamber 4006, a film formation chamber 4008, a film formation chamber 4009, a film formation chamber 4010, and a transfer arm 4014. Here, the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film forming chambers 4008 to 4010 are independently connected to the transfer chamber 4006. Thus, continuous film formation can be performed without exposure to the air in the film formation chambers 4008 to 4010, and entry of impurities into the film can be prevented. Further, contamination at the interface between the substrate and the film and at the interface between the films is reduced, and a clean interface is obtained.

  Note that the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, and the film formation chambers 4008 to 4010 are filled with an inert gas (nitrogen gas or the like) whose dew point is controlled in order to prevent adhesion of moisture. It is preferable to keep the pressure, and it is desirable to maintain the reduced pressure.

  Further, an ALD apparatus can be used for the film formation chambers 4008 to 4010. Further, a film formation apparatus other than the ALD apparatus may be used in any of the film formation chambers 4008 to 4010. As a film formation apparatus which can be used for the film formation chambers 4008 to 4010, for example, a sputtering apparatus, a plasma enhanced (PECVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, an optical CVD (Photo CVD) apparatus , A metal CVD (MCVD: Metal CVD) device, an organic metal CVD (MOCVD: Metal Organic CVD) device, and the like. Further, an apparatus having a function other than the film formation apparatus may be provided in one or more of the film formation chambers 4008 to 4010. Examples of the device include a heating device (typically, a vacuum heating device) and a plasma generator (typically, a microwave plasma generator).

  For example, in the case where the deposition chamber 4008 is an ALD apparatus, the deposition chamber 4009 is a PECVD apparatus, and the deposition chamber 4010 is a metal CVD apparatus, a metal oxide is used in the deposition chamber 4008 and a gate insulating film is used in the deposition chamber 4009. A functional insulating film and a conductive film functioning as a gate electrode in the deposition chamber 4010 can be formed. At this time, the metal oxide, the insulating film thereon, and the conductive film thereover can be formed continuously without exposing to the atmosphere.

  Further, the film formation apparatus 4000 has a structure including the carry-in / out chamber 4002, the carry-in / out chamber 4004, and the film formation chambers 4008 to 4010; however, the present invention is not limited to this. The number of film forming chambers of the film forming apparatus 4000 may be four or more. In addition, the film formation apparatus 4000 may be a single-wafer type or may be a batch type in which a plurality of substrates are formed at one time.

<ALD device>
Next, a structure of an ALD apparatus that can be used for the film formation apparatus 4000 will be described with reference to FIG. The ALD apparatus includes a film formation chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a and 4021b), a raw material supply unit 4031, high-speed valves 4022a and 4022b that are introduction amount controllers, and a raw material introduction port 4023. (Source inlets 4023a and 4023b), a source inlet 4033, a source outlet 4024, and an exhaust device 4025. The raw material introduction ports 4023a, 4023b, and 4033 installed in the chamber 4020 are connected to the raw material supply units 4021a, 4021b, and 4031 via supply pipes and valves, respectively, and the raw material discharge port 4024 is connected to a discharge pipe and a valve. It is connected to the exhaust device 4025 via a pressure regulator.

  In addition, by connecting a plasma generation device 4028 to the chamber 4020 as illustrated in FIG. 14B, deposition can be performed by a plasma ALD method in addition to a thermal ALD method. The plasma generator 4028 is preferably an ICP type plasma generator using a coil 4029 connected to a high frequency power supply. The high-frequency power supply can output power having a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, more preferably 10 MHz to 60 MHz. For example, power having a frequency of 13.56 MHz or 60 MHz can be output. In the plasma ALD method, a film can be formed without lowering the film formation rate even at a low temperature. Therefore, it is preferable to use a single-wafer film formation apparatus with low film formation efficiency.

  A substrate holder 4026 is provided inside the chamber, and the substrate 4030 is arranged on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or a high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. Further, a heater 4027 is provided on the outer wall of the chamber, and the temperature of the inside of the chamber 4020, the substrate holder 4026, the surface of the substrate 4030, and the like can be controlled. The heater 4027 can control the temperature of the surface of the substrate 4030 at 100 ° C. or more and 500 ° C. or less, preferably 200 ° C. or more and 400 ° C. or less, and can preferably set the temperature of the heater 4027 itself at 100 ° C. or more and 500 ° C. or less.

  In the raw material supply units 4021a, 4021b, and 4031, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, a heating unit, or the like. Alternatively, the raw material supply units 4021a, 4021b, and 4031 may be configured to supply a gaseous raw material gas.

  FIG. 14B illustrates an example in which two source supply sections 4021 and one source supply section 4031 are provided; however, this embodiment is not limited thereto. One or three or more raw material supply units 4021 may be provided. Further, two or more raw material supply units 4031 may be provided. Further, the high-speed valves 4022a and 4022b can be precisely controlled with time, and are configured to control supply of the source gas supplied from the source supply unit 4021a and the source gas supplied from the source supply unit 4021b.

  In the film formation apparatus illustrated in FIG. 14B, the substrate 4030 is carried over the substrate holder 4026, the chamber 4020 is sealed, and then the substrate 4030 is heated to a desired temperature (for example, 100 ° C. or higher and 500 ° C. or lower) by the heater 4027. (Preferably 200 ° C. or more and 400 ° C. or less), supply of the source gas supplied from the source supply unit 4021a, exhaustion by the exhaust unit 4025, supply of the source gas supplied from the source supply unit 4031, and exhaust unit 4025. Is repeated to form a thin film on the substrate surface. In forming the thin film, the supply of the source gas supplied from the source supply unit 4021b and the exhaust by the exhaust device 4025 may be performed. The temperature of the heater 4027 may be appropriately determined according to the type of film to be formed, the source gas, the desired film quality, the substrate, and the heat resistance of the film or element provided therein. For example, the film may be formed by setting the temperature of the heater 4027 to 200 to 300 ° C., or may be set to 300 to 500 ° C.

  By forming a film while heating the substrate 4030 using the heater 4027, heat treatment of the substrate 4030 required in a later step can be omitted. That is, by using the chamber 4020 provided with the heater 4027 or the film formation apparatus 4000, formation of a film over the substrate 4030 and heat treatment of the substrate 4030 can be performed.

  In the film formation apparatus illustrated in FIG. 14B, a metal oxide can be formed by appropriately selecting a raw material supply portion 4021 and a raw material (a volatile organic metal compound or the like) used in the raw material supply portion 4031. In the case where an In—Ga—Zn oxide containing indium, gallium, and zinc is formed as a metal oxide, a film formation apparatus provided with at least three source supply units 4021 and at least one source supply unit 4031 is used. Is preferred. A precursor containing indium is supplied from the first material supply unit 4021, a precursor containing gallium is supplied from the second material supply unit 4021, and a precursor containing zinc is supplied from the third material supply unit 4021. preferable. In the case where a precursor containing gallium and zinc is used for forming the metal oxide, at least two material supply units 4021 may be provided. The precursors described above can be used as a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

  Also, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

  In addition, by appropriately selecting a raw material (a volatile organic metal compound or the like) used in the raw material supply units 4021a, 4021b, and 4031, an oxide containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, and the like ( (Including a composite oxide). Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, an insulating layer containing aluminum silicate, or the like. Can be formed. In addition, by appropriately selecting a raw material (a volatile organic metal compound or the like) used in the raw material supply units 4021a, 4021b, and 4031, a metal layer such as a tungsten layer and a titanium layer, and a nitride layer such as a titanium nitride layer can be formed. A thin film can also be formed.

For example, when a hafnium oxide layer is formed by an ALD apparatus, a first raw material gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium amide such as hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAHf)). And a second source gas of ozone (O ₃ ) and oxygen (O ₂ ) as an oxidizing agent. In this case, the first source gas supplied from the source supply unit 4021a is TDMAHf, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of tetrakisdimethylamidohafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Another material liquid includes tetrakis (ethylmethylamide) hafnium. Further, water can be used as the second source gas.

When an aluminum oxide layer is formed by an ALD apparatus, a first source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (TMA: trimethylaluminum, etc.), ozone (O ₃ ) and oxygen as oxidizing agents A second source gas containing (O ₂ ) is used. In this case, the first source gas supplied from the source supply unit 4021a is TMA, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like. Further, water can be used as the second source gas.

  FIG. 15 illustrates a different structure of an ALD apparatus that can be used for the film formation apparatus 4000. Note that a detailed description of the same configuration and functions of the ALD device illustrated in FIG. 14B may be omitted in some cases.

  FIG. 15A is a schematic diagram illustrating one embodiment of a plasma ALD apparatus. In the plasma ALD apparatus 4100, a reaction chamber 4120 and a plasma generation chamber 4111 are provided above the reaction chamber 4120. Reaction chamber 4120 can be referred to as a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively called a chamber. The reaction chamber 4120 has a material inlet 4123 and a material outlet 4124, and the plasma generation chamber 4111 has a material inlet 4133. Further, a plasma 4131 can be generated in the plasma generation chamber 4111 by applying a high frequency such as RF or a microwave to the gas introduced into the plasma generation chamber 4111 by the plasma generation device 4128. When the plasma 4131 is generated using a microwave, a microwave having a frequency of 2.45 GHz is typically used. Plasma generated using such a microwave may be referred to as ECR (Electron Cyclotron Resonance) plasma. The reaction chamber 4120 has a substrate holder 4126, on which the substrate 4130 is arranged. The source gas introduced from the source inlet 4123 is decomposed by heat from a heater provided in the reaction chamber 4120, and is deposited on the substrate 4130. The source gas introduced from the source inlet 4133 is brought into a plasma state by the plasma generator 4128. The source gas in a plasma state is recombined with electrons and other molecules before reaching the surface of the substrate 4130, and reaches a substrate 4130 in a radical state. Such an ALD apparatus that forms a film using radicals may be referred to as a radical ALD (Radical-Enhanced ALD) apparatus. In the plasma ALD apparatus 4100, the plasma generation chamber 4111 is provided above the reaction chamber 4120; however, this embodiment is not limited to this. The plasma generation chamber 4111 may be provided adjacent to a side surface of the reaction chamber 4120.

  FIG. 15B is a schematic view illustrating one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 has a chamber 4220. The chamber 4220 has an electrode 4213, a material outlet 4224, and a substrate holder 4226, on which the substrate 4230 is arranged. The electrode 4213 has a material introduction port 4223 and a shower head 4214 for supplying the introduced material gas into the chamber 4220. A power supply 4215 to which a high frequency can be applied is connected to the electrode 4213 via a capacitor 4217. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or a high frequency. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode for generating the plasma 4231, respectively. The raw material gas introduced from the raw material introduction port 4223 is decomposed by heat from a heater provided in the chamber 4220 and is deposited on the substrate 4230. Alternatively, the source gas introduced from the source inlet 4223 is in a plasma state between the electrode 4213 and the substrate holder 4226. The source gas in a plasma state enters the substrate 4230 due to a potential difference (also referred to as an ion sheath) generated between the plasma 4231 and the substrate 4230.

  FIG. 15C is a schematic diagram illustrating one embodiment of a plasma ALD device different from that of FIG. The plasma ALD apparatus 4300 has a chamber 4320. The chamber 4320 has an electrode 4313, a material outlet 4324, and a substrate holder 4326, on which the substrate 4330 is arranged. The electrode 4313 has a raw material introduction port 4323 and a shower head 4314 for supplying the introduced raw material gas into the chamber 4320. A power supply 4315 to which a high frequency can be applied is connected to the electrode 4313 via a capacitor 4317. The substrate holder 4326 may be provided with a mechanism to apply a constant potential or a high frequency. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode for generating the plasma 4331, respectively. The plasma ALD apparatus 4300 is different from the plasma ALD apparatus 4200 in that a mesh 4319 to which a power supply 4321 capable of applying a high frequency is connected via a capacitor 4322 is provided between the electrode 4313 and the substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The raw material gas introduced from the raw material introduction port 4323 is decomposed by heat from a heater provided in the chamber 4320, and is deposited on the substrate 4330. Alternatively, the source gas introduced from the source inlet 4323 enters a plasma state between the electrode 4313 and the substrate holder 4326. The source gas in the plasma state is charged by the mesh 4319, and reaches the substrate 4130 in an electrically neutral state such as radicals. Therefore, a film can be formed in which the incidence of ions and the damage due to plasma are suppressed.

<Deposition sequence>
FIG. 16A shows a film formation sequence using the ALD apparatus shown in FIG. First, the substrate 4030 is set on the substrate holder 4026 in the chamber 4020 (S101). Next, the temperature of the heater 4027 is adjusted (S102). Next, the substrate 4030 is held on the substrate holder 4026 so that the temperature of the substrate 4030 becomes uniform in the plane of the substrate (S103). Next, a film is formed by the above-described first to fourth steps. That is, the first source gas and the second source gas are alternately introduced into the chamber 4020, and a film is formed on the substrate 4030 (S104). Further, between S103 and S104, a process of setting the inside of the chamber 4020 to an oxygen atmosphere may be performed. By setting the inside of the chamber 4020 to an oxygen atmosphere after setting and holding the substrate 4030, oxygen may be added to the substrate 4030 and a film provided over the substrate 4030 in some cases. Further, in some cases, hydrogen can be eliminated from the substrate 4030 before film formation and the film provided over the substrate 4030. In some cases, hydrogen in the substrate 4030 or the film reacts with oxygen added to the substrate 4030 or the film to become water (H ₂ O) and is separated from the substrate 4030 or the film.

  FIG. 16B shows a specific example of the film forming sequence. According to S101 to S103, the substrate 4030 is set on the substrate holder 4026, and the temperature of the heater 4027 is adjusted and the substrate 4030 is held.

  Next, a first source gas and a second source gas are alternately introduced to form a film on the substrate 4030 (S104). The introduction of the first source gas and the second source gas is performed in a pulsed manner. In FIG. 16B, the introduction of the first source gas and the introduction of the second source gas are each indicated by ON, and the period in which the source gas is not introduced is indicated by OFF. During a period in which neither the first source gas nor the second source gas is introduced, the inside of the chamber 4020 is exhausted. The pulse time for introducing the first source gas into the chamber 4020 is preferably 0.1 seconds or more and 1 second or less, and more preferably 0.1 seconds or more and 0.5 seconds or less. Further, a period during which the first source gas is not introduced, that is, a time period during which the inside of the chamber 4020 is evacuated is set to 1 second to 15 seconds, preferably 1 second to 5 seconds. The pulse time for introducing the second source gas into the chamber 4020 is preferably from 0.1 to 30 seconds, more preferably from 0.3 to 15 seconds. Further, a period during which the second source gas is not introduced, that is, a time period during which the inside of the chamber 4020 is exhausted is set to be 1 second to 15 seconds, preferably 1 second to 5 seconds.

  The film formation is performed by introducing a first source gas (the first step), exhausting the first source gas (the second step), introducing a second source gas (the third step), The gas exhaustion (the fourth step) is defined as one cycle, and by repeating this, a film having a desired film thickness is formed.

Further, in the case where the inside of the chamber 4020 is subjected to a treatment between the steps S103 and S104 in an oxygen atmosphere, a second source gas may be introduced into the chamber 4020. As the second source gas, it is preferable to introduce one or more selected from ozone (O ₃ ), oxygen (O ₂ ), and water (H ₂ O), which function as an oxidizing agent. In this embodiment mode, ozone (O ₃ ) and oxygen (O ₂ ) are used as the second source gas. At this time, the second source gas is preferably introduced in a pulsed manner as in the method shown in S104, but the present invention is not limited to this. The second source gas may be introduced continuously. During a period in which the second source gas is not introduced, the inside of the chamber 4020 is exhausted. The pulse time for introducing the second source gas into the chamber 4020 is preferably from 0.1 to 30 seconds, more preferably from 0.3 to 15 seconds. Further, a period during which the second source gas is not introduced, that is, a time period during which the inside of the chamber 4020 is exhausted is set to be 1 second to 15 seconds, preferably 1 second to 5 seconds. When the second source gas such as an oxidant is introduced into the chamber 4020, the substrate 4030 or a film provided over the substrate 4030 is exposed to the second source gas such as an oxidant.

  If the temperature adjustment of the heater 4027 is not necessary after the setting of the substrate 4030 (S101), it may be omitted. In addition, after the holding of the substrate 4030 (S103), if it is not necessary to make the inside of the chamber 4020 an oxygen atmosphere, it may be omitted.

  FIG. 16C illustrates an example of a sequence in the case of forming a film using a plurality of types of source gases including a precursor. In FIG. 16C, a source gas including a precursor is referred to as a first source gas, a third source gas, and a fourth source gas, and a source gas including an oxidizing agent is referred to as a second source gas. According to S101 to S103, the substrate 4030 is set on the substrate holder 4026, and the temperature of the heater 4027 is adjusted and the substrate 4030 is held.

  Next, a first source gas, a second source gas, a third source gas, a second source gas, a fourth source gas, and a second source gas are sequentially introduced, and formed on the substrate 4030. A film is formed (S104). The introduction of the first to fourth source gases is performed in a pulsed manner. In FIG. 16C, the introduction of the first to fourth source gases is indicated by ON, and the period in which the source gas is not introduced is indicated by OFF. During a period in which none of the first to fourth source gases is introduced, the inside of the chamber 4020 is exhausted. A pulse time for introducing the first source gas, the third source gas, and the fourth source gas into the chamber 4020 is 0.1 seconds to 1 second, preferably 0.1 seconds to 0.5 seconds. It is preferred that Further, a period during which the first source gas, the third source gas, and the fourth source gas are not introduced, that is, a time during which the inside of the chamber 4020 is exhausted is 1 second to 15 seconds, preferably 1 second or more. 5 seconds or less. The pulse time for introducing the second source gas into the chamber 4020 is preferably from 0.1 to 30 seconds, more preferably from 0.3 to 15 seconds. Further, a period during which the second source gas is not introduced, that is, a time period during which the inside of the chamber 4020 is exhausted is set to be 1 second to 15 seconds, preferably 1 second to 5 seconds.

  The film formation is performed by introducing the first source gas, exhausting the first source gas, introducing the second source gas, exhausting the second source gas, introducing the third source gas, and introducing the third source gas. Exhaust, introduction of the second source gas, exhaust of the second source gas, introduction of the fourth source gas, exhaust of the fourth source gas, introduction of the second source gas, and exhaust of the second source gas One cycle is repeated, and a film having a desired film thickness is formed.

  For example, in the case where the first source gas includes a precursor including indium, the third source gas includes a precursor including gallium, and the fourth source gas includes a precursor including zinc, a sequence illustrated in FIG. Thus, an In—Ga—Zn oxide can be formed.

  Note that in the sequence illustrated in FIG. 16C, the introduction order of the first source gas, the third source gas, and the fourth source gas is not limited to this. In addition, the number of introductions of the first source gas, the third source gas, and the fourth source gas in one cycle is not limited to one. By introducing a certain source gas a plurality of times during one cycle, a film in which the concentration of the metal element contained in the source gas is high can be formed. That is, by changing the number of times of introduction of each gas, the atomic ratio of the formed film can be controlled. Further, a first source gas, a third source gas, a fourth source gas, or two types of source gases selected from these source gases may be simultaneously introduced into the chamber 4020.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments, examples, and the like.

(Embodiment 3)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

[Storage device 1]
FIG. 18 illustrates an example of a semiconductor device (memory device) using the capacitor which is one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistor 200. It is preferable that at least part of the capacitor 100 or the transistor 300 overlap with the transistor 200. Accordingly, the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated. Note that the semiconductor device according to this embodiment includes, for example, a logic circuit represented by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a DRAM (Dynamic Random Access Memory), or an NVM (Non-Volatile Memory). The present invention can be applied to a memory circuit represented by

  Note that as the transistor 200, the transistor 200 described in the above embodiment can be used. Thus, the description in the above embodiment can be referred to for the transistor 200 and the layer including the transistor 200.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be held for a long time by using the transistor 200 in a memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. In addition, the transistor 200 has favorable electrical characteristics at high temperature as compared with a transistor using silicon for the semiconductor layer. For example, the transistor 200 has favorable electrical characteristics even in a temperature range of 125 ° C. to 150 ° C. In the temperature range of 125 ° C. to 150 ° C., the transistor 200 has an on / off ratio of the transistor of 10 digits or more. In other words, as compared with a transistor using silicon for the semiconductor layer, the transistor 200 has more excellent characteristics such as on-state current and frequency characteristics which are examples of transistor characteristics as the temperature increases.

  In the semiconductor device illustrated in FIG. 18, the wiring 1001 is electrically connected to the source of the transistor 300, the wiring 1002 is electrically connected to the drain of the transistor 300, and the wiring 1007 is electrically connected to the gate of the transistor 300. I have. Further, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. The other of the source and the drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100.

  The semiconductor device illustrated in FIGS. 18A and 18B can write, hold, and read data because the switching of the transistor 200 has a characteristic in which electric charge charged in one of the electrodes of the capacitor 100 can be held. The transistor 200 is an element provided with a second gate in addition to a source, a first gate, and a drain. That is, since it is a four-terminal element, a magnetoresistive random access memory (MRAM) utilizing a magnetic tunnel junction (MTJ) characteristic, a random change access memory (ReRAM, a resistive random access memory) such as a ReRAM (Resistant Random Access Memory), and a phase-change memory such as a phase-change memory (Phase change memory). It has a feature that independent control of input and output can be easily performed as compared with the terminal element. Further, in the MRAM, the ReRAM, and the phase change memory, a structural change may occur at an atomic level when information is rewritten. On the other hand, the semiconductor device illustrated in FIGS. 18A and 18B operates by charge or discharge of electrons using a transistor and a capacitor at the time of rewriting information, and thus has features of excellent repetition rewriting resistance and little structural change.

  The semiconductor device illustrated in FIG. 18 can form a memory cell array by being arranged in a matrix. In that case, the transistor 300 can be used as a reading circuit, a driver circuit, or the like connected to the memory cell array. The semiconductor device illustrated in FIG. 18 forms a memory cell array as described above. When the semiconductor device illustrated in FIG. 18 is used as a memory element, for example, an operating frequency of 200 MHz or more can be realized in a driving voltage of 2.5 V and an evaluation environment temperature in a range of −40 ° C. to 85 ° C.

<Transistor 300>
The transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 which is part of the substrate 311, and functions as a source or drain region. The low resistance region 314a and the low resistance region 314b are provided.

  Here, the insulator 315 is provided over the semiconductor region 313, and the conductor 316 is provided over the insulator 315. The transistors 300 formed in the same layer are electrically separated by an insulator 312 functioning as an element isolation insulating layer. As the insulator 312, an insulator similar to an insulator 326 described later or the like can be used. The transistor 300 may be either a p-channel transistor or an n-channel transistor.

  The substrate 311 includes a semiconductor such as a silicon-based semiconductor in a region where a channel of the semiconductor region 313 is formed, a region near the channel, a low-resistance region 314a serving as a source region or a drain region, a low-resistance region 314b, or the like. And preferably contains single crystal silicon. Alternatively, a material including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be formed using HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs.

  The low-resistance regions 314a and 314b have an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor region 313. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, or an alloy including an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and burying property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

  Here, in the transistor 300 illustrated in FIG. 18, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. The conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. Such a transistor 300 is also called a FIN transistor because it utilizes a projection of a semiconductor substrate. Note that an insulator may be provided in contact with an upper portion of the projection and functioning as a mask for forming the projection. Although a case where a part of a semiconductor substrate is processed to form a convex portion is described here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

  Note that the transistor 300 illustrated in FIG. 18 is an example, and there is no limitation on the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.

  As illustrated in FIG. 18, the semiconductor device includes a transistor 300 and a transistor 200 which are stacked. For example, the transistor 300 can be formed using a silicon-based semiconductor material and the transistor 200 can be formed using an oxide semiconductor. As described above, the semiconductor device illustrated in FIG. 18 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers. The semiconductor device illustrated in FIGS. 18A and 18B can be manufactured by a process similar to that of a manufacturing device using a silicon-based semiconductor material, and can be highly integrated.

<Capacitive element>
The capacitor 100 includes an insulator 114 over the insulator 160, an insulator 140 over the insulator 114, a conductor 110 disposed in the insulator 114 and an opening formed in the insulator 140, An insulator 130 over the insulator 110 and the insulator 140, a conductor 120 over the insulator 130, and an insulator 150 over the conductor 120 and the insulator 130 are provided. Here, at least part of the conductor 110, the insulator 130, and the conductor 120 are arranged in openings formed in the insulator 114 and the insulator 140.

  The conductor 110 functions as a lower electrode of the capacitor 100, the conductor 120 functions as an upper electrode of the capacitor 100, and the insulator 130 functions as a dielectric of the capacitor 100. In the capacitor 100, the upper electrode and the lower electrode are opposed to each other not only on the bottom surface but also on the side surfaces of the opening of the insulator 114 and the insulator 140 with a dielectric material interposed therebetween. The capacity can be increased. Therefore, the capacitance of the capacitor 100 can be increased as the depth of the opening is increased. By increasing the capacitance per unit area of the capacitor 100 in this manner, miniaturization or high integration of a semiconductor device can be promoted.

  As the insulator 114 and the insulator 150, an insulator that can be used for the insulator 280 may be used. The insulator 140 preferably functions as an etching stopper when the opening of the insulator 114 is formed, and an insulator that can be used for the insulator 212 may be used.

  The shape of the opening formed in the insulator 114 and the insulator 140 as viewed from above may be a quadrangle, a polygon other than a quadrangle, or a shape in which a corner is curved in a polygon. And a circular shape including an ellipse. Here, it is preferable that the area where the opening and the transistor 200 overlap with each other be large in a top view. With such a structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

  The conductor 110 is provided in contact with the insulator 140 and an opening formed in the insulator 114. It is preferable that the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140. In addition, a conductor 152 provided over the insulator 160 is in contact with the lower surface of the conductor 110. The conductor 110 is preferably formed by an ALD method, a CVD method, or the like; for example, a conductor that can be used for the conductor 205 may be used.

  The insulator 130 is provided so as to cover the conductor 110 and the insulator 140. For example, the insulator 130 is preferably formed by an ALD method, a CVD method, or the like. The insulator 130 is formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or nitrided nitride. Hafnium or the like may be used; For example, as the insulator 130, an insulating film stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

  It is preferable that the insulator 130 be formed using a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material. Alternatively, a stacked structure of a material having a high dielectric strength and a high dielectric constant (high-k) material may be used.

  Gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium are given as insulators of a high dielectric constant (high-k) material (a material having a high relative dielectric constant). , An oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, a nitride containing silicon and hafnium, and the like. By using such a high-k material, the capacitance of the capacitor 100 can be sufficiently ensured even when the thickness of the insulator 130 is increased. By increasing the thickness of the insulator 130, leakage current generated between the conductor 110 and the conductor 120 can be suppressed.

On the other hand, materials having high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and holes. Silicon oxide, resin, and the like. For example, silicon nitride was deposited using ALD _(SiN x), in the order of the plasma ALD method the formed silicon oxide with _(SiO x), silicon nitride was deposited using ALD (SiN _x) A stacked insulating film can be used. By using such an insulator having a large dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

  In addition, the insulator 130 may have a structure similar to that of the first gate insulator or the second gate insulator described in the above embodiment.

  Specifically, in the case where an In-Ga-Zn oxide is used as the oxide 230, a material having higher insulating property than the oxide 230b in the gallium oxide or the In-Ga-Zn oxide is used as the insulator 130. It is preferred to include. Since the element included in the insulator 130 and the element included in the oxide 230 are common, even if the element included in the insulator 130 is diffused into the oxide 230, the resistance of the oxide 230 is reduced. Is not a factor.

  In particular, gallium oxide is a high dielectric constant insulating material having a higher dielectric constant than silicon nitride, and is a so-called high-k material. As the miniaturization and high integration of a semiconductor device progress, problems such as leakage current may occur due to thinning of a dielectric. By using a high-k material for the insulator functioning as a dielectric, the equivalent oxide thickness (EOT) of the dielectric can be reduced while maintaining the physical thickness.

  The insulator 130 is formed at the bottom and side surfaces of an opening formed in the insulator 114 or the like. It is preferable that the thickness of the insulator 130 functioning as a dielectric be uniform at the bottom of the opening and at the attachment surface. The ALD method is a film forming method that is excellent in covering properties for a structure having steps and unevenness. Therefore, when the insulator 130 is formed by an ALD method, the thickness of the insulator 130 can be uniform at the bottom and side surfaces of the opening.

  The conductor 120 is provided so as to fill openings formed in the insulator 140 and the insulator 114. The conductor 120 is electrically connected to the wiring 1005 through the conductor 112 and the conductor 153. The conductor 120 is preferably formed by an ALD method, a CVD method, or the like; for example, a conductor that can be used for the conductor 205 may be used.

  Further, since the transistor 200 has a structure using an oxide semiconductor, it has excellent compatibility with the capacitor 100. Specifically, the transistor 200 including an oxide semiconductor has low off-state current; therefore, when it is used in combination with the capacitor 100, stored data can be held for a long time.

<Wiring layer>
A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided depending on the design. Here, the conductor functioning as a plug or a wiring may be provided with the same reference numeral collectively for a plurality of structures. Further, in this specification and the like, a wiring and a plug that is electrically connected to the wiring may be integrated. That is, a part of the conductor functions as a wiring and a part of the conductor functions as a plug in some cases.

  For example, over the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films. In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 electrically connected to the conductor 153 functioning as a terminal, a conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 function as plugs or wirings.

  Further, the insulator functioning as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 18, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

  The insulator 360, the insulator 362, the insulator 212, and the insulator 216 are provided over the insulator 354 and the conductor 356 in that order. In the insulator 360, the insulator 362, the insulator 212, and the insulator 216, a conductor 366, a conductor included in the transistor 200 (the conductor 205), or the like is embedded. Note that the conductor 366 functions as a plug or a wiring which is electrically connected to the transistor 300.

  In addition, the conductor 112, a conductor (the conductor 120, the conductor 110) included in the capacitor 100, and the like are embedded in the insulator 114, the insulator 140, the insulator 130, the insulator 150, and the insulator 154. Have been. Note that the conductor 112 functions as a plug or a wiring which electrically connects the capacitor 100, the transistor 200, or the transistor 300 to the conductor 153 functioning as a terminal.

  The conductor 153 is provided over the insulator 154, and the conductor 153 is covered with the insulator 156. Here, the conductor 153 is in contact with the upper surface of the conductor 112 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

  Note that examples of an insulator that can be used as an interlayer film include an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide having insulating properties. For example, by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.

  For example, the insulator 320, the insulator 322, the insulator 326, the insulator 352, the insulator 354, the insulator 362, the insulator 114, the insulator 150, the insulator 156, or the like includes an insulator with a low relative dielectric constant. Is preferred. For example, the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes. , A resin or the like. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes. And a resin. Since silicon oxide and silicon oxynitride are thermally stable, they can be combined with a resin to have a stacked structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (eg, nylon and aramid), polyimide, polycarbonate, and acrylic.

In addition, the resistivity of an insulator provided above or below the conductor 152 or the conductor 153 is 1.0 × 10 ¹² Ωcm to 1.0 × 10 ¹⁵ Ωcm, preferably 5.0 × 10 ¹² Ωcm or more. 0.0 × 10 ¹⁴ Ωcm or less, more preferably 1.0 × 10 ¹³ Ωcm or more and 5.0 × 10 ¹³ Ωcm or less. By setting the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 to be in the above range, the insulator maintains the insulating property and the transistor 200, the transistor 300, the capacitor 100, In addition, electric charge accumulated between wirings such as the conductor 152 can be dispersed, which can suppress defective characteristics and electrostatic breakdown of a transistor and a semiconductor device including the transistor due to the electric charge, which is preferable. As such an insulator, silicon nitride or silicon nitride oxide can be used. For example, the resistivity of the insulator 160 or the insulator 154 may be set in the above range.

  In addition, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Therefore, as the insulator 324, the insulator 350, the insulator 360, and the like, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used.

  Examples of the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. A material containing at least one metal element selected from ruthenium and the like can be used. Alternatively, a semiconductor having high electric conductivity, represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

  For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 366, the conductor 112, the conductor 152, the conductor 153, and the like, a metal material, an alloy material, a metal nitride material formed using the above materials. Or a conductive material such as a metal oxide material can be used as a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.

<Wiring or plug in a layer provided with an oxide semiconductor>
Note that in the case where an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the vicinity of the insulator having the excess oxygen region.

  For example, in FIG. 18, an insulator 278 may be provided between the insulator 280 containing excess oxygen (the insulator 280a and the insulator 280b) and the conductor 246. Further, the insulator 278 and the insulator 274 are preferably provided in contact with each other. The conductor 246 and the transistor 200 can be sealed with an insulator 278 having a barrier property and an insulator 274.

  In other words, by providing the insulator 278, excess oxygen included in the insulator 280 can be suppressed from being absorbed by the conductor 246. In addition, with the use of the insulator 278, diffusion of hydrogen which is an impurity into the transistor 200 through the conductor 246 can be suppressed.

  Here, the conductor 246 has a function as a plug or a wiring which is electrically connected to the transistor 200 or the transistor 300.

  The above is the description of the configuration example. With the use of this structure, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, in a semiconductor device including a transistor including an oxide semiconductor, change in electric characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

  Note that FIG. 18 illustrates an example in which the capacitor 100 is provided over the transistor 200; however, the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 19, in an adjacent memory cell, the capacitor 100a may be provided over the transistor 200a and the capacitor 100b may be provided under the transistor 200b.

  In the memory device illustrated in FIG. 19, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003a is electrically connected to one of the source and the drain of the transistor 200a. The other of the source and the drain of the transistor 200a is electrically connected to one of the electrodes of the capacitor 100a, and the wiring 1005a is electrically connected to the other of the electrodes of the capacitor 100a. The wiring 1003b is electrically connected to one of the source and the drain of the transistor 200b. The other of the source and the drain of the transistor 200b is electrically connected to one of the electrodes of the capacitor 100b, and the wiring 1005b is electrically connected to the other of the electrodes of the capacitor 100b.

  FIG. 19 illustrates a transistor 200a and a capacitor 100a and a transistor 200b and a capacitor 100b included in memory cells adjacent to each other. The transistors 200a and 200b have a structure similar to that of the transistor 200. Note that the transistor 200b is different from the transistor 200 in that the conductor 240c is in contact with at least part of the top surface of the conductor 247 through the opening 248. Hereinafter, points different from the transistor 200 will be described.

  The transistor 200b includes a conductor 240d, an opening 248, and a conductor 240c disposed inside the opening 248. Further, the conductor 240c is in contact with at least a part of the upper surface of the conductor 247 through the opening 248. With the connection between the conductor 240c and the conductor 247, electric resistance between the other of the source and the drain of the transistor 200b and the conductor 247 can be reduced.

  The conductor 247 is provided in an opening formed in the insulator 150, the insulator 362, the insulator 212, the insulator 214, and the insulator 216. At least a part of the upper surface of the conductor 247 is exposed from the insulator 216, and the upper surface of the conductor 247 and the upper surface of the insulator 216 preferably substantially coincide with each other.

  Here, the conductor 247 functions as a plug for electrically connecting to one of the electrodes of the capacitor 100b provided below the insulator 362. Note that the conductor 247 may be electrically connected to a gate of a transistor provided below the insulator 362 or electrically connected to a wiring provided below the insulator 362. You may. Note that the conductor 247 may be extended to function as a wiring.

  In the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b, an opening 248 exposing at least a part of the conductor 247 is formed.

  In FIG. 19, the conductor 247 is provided below the conductor 240c; however, the semiconductor device described in this embodiment is not limited to this. For example, a structure in which the conductor 247 is provided below the conductor 240d may be employed, or a structure in which the conductor 247 is provided under both the conductor 240c and the conductor 240d.

  The capacitor 100a and the capacitor 100b have a structure similar to that of the capacitor 100. That is, the capacitor 100a includes the conductor 110a, the insulator 130a, and the conductor 120a, and the capacitor 100b includes the conductor 110b, the insulator 130b, and the conductor 120b. The conductor 110a and the conductor 110b have the same configuration as the conductor 110. The insulator 130a and the insulator 130b have a structure similar to that of the insulator 130. The conductor 120a and the conductor 120b have the same configuration as the conductor 120.

  Here, the capacitor 100a preferably overlaps with the transistor 200a and the transistor 200b. For example, the capacitor 100a preferably overlaps with a channel formation region of the transistor 200a and a channel formation region of the transistor 200b. Further, the capacitor 100b preferably overlaps with the transistor 200a and the transistor 200b; for example, the capacitor 100b preferably overlaps with a channel formation region of the transistor 200a and a channel formation region of the transistor 200b.

  By arranging the capacitor 100a and the capacitor 100b in this manner, without increasing the occupied area of the capacitor 100a, the capacitor 100b, the transistor 200a, and the transistor 200b in a top view, the capacitor 100a and the capacitor 100b Can be increased. Therefore, the semiconductor device according to this embodiment can be miniaturized or highly integrated.

  Further, as illustrated in FIG. 20, a plurality of openings for providing the capacitor 100a and the capacitor 100b may be provided. Here, the conductor 110a may be provided separately at each opening. Similarly, the conductor 110b may be provided separately at each opening. Accordingly, the capacitor 100a and the capacitor 100b can be formed on the side surface of each opening. Therefore, the capacitances of the capacitor 100a and the capacitor 100b illustrated in FIG. 20 can be further increased with the same occupied area as the capacitor 100a and the capacitor 100b illustrated in FIG.

  Note that FIGS. 19 and 20 show examples in which the capacitor 100a and the capacitor 100b are provided above and below the transistor 200a and the transistor 200b, respectively; however, the semiconductor device described in this embodiment is not limited thereto. . For example, a structure in which the capacitor 100b and the transistor 200b are provided without providing the capacitor 100a and the transistor 200a may be employed. Note that at least part of the capacitor 100b or the transistor 300 preferably overlaps with the transistor 200b. Accordingly, the area occupied by the capacitor 100b, the transistor 200b, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

  Note that in some cases, high temperature heat treatment exceeding 700 ° C. is required in the manufacturing process of the capacitor 100b. When such high-temperature heat treatment is performed after formation of the transistor 200b, diffusion of impurities such as hydrogen or water or oxygen diffuses into the oxide 230, which may deteriorate electrical characteristics of the transistor 200b.

  However, as shown in this modification, by forming the transistor 200b over the capacitor 100b, the heat history in the manufacturing process of the capacitor 100b does not affect the transistor 200b. Accordingly, deterioration of electric characteristics of the transistor 200b can be prevented and a semiconductor device having stable electric characteristics can be provided.

[Storage device 2]
FIG. 21 illustrates an example of a semiconductor device (memory device) using the semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 21 includes a transistor 200, a transistor 300, and a capacitor 100, similarly to the semiconductor device illustrated in FIG. Note that the semiconductor device illustrated in FIG. 21 is different from the semiconductor device illustrated in FIG. 18 in that the capacitor 100 is planar and that the transistor 200 and the transistor 300 are electrically connected to each other.

  In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. It is preferable that at least part of the capacitor 100 or the transistor 300 overlap with the transistor 200. Accordingly, the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

  Note that the above transistors 200 and 300 can be used as the transistors 200 and 300. Therefore, the above description can be referred to for the transistor 200, the transistor 300, and a layer including these.

  In the semiconductor device illustrated in FIG. 21, the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300. Further, the wiring 2003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 2004 is electrically connected to the first gate of the transistor 200, and the wiring 2006 is electrically connected to the second gate of the transistor 200. It is connected to the. Further, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 2005 is electrically connected to the other of the electrodes of the capacitor 100. . Note that a node where the gate of the transistor 300, the other of the source and the drain of the transistor 200, and one of the electrodes of the capacitor 100 are connected may be referred to as a node FG hereinafter.

  The semiconductor device illustrated in FIG. 21 has a characteristic in which the potential of the gate (node FG) of the transistor 300 can be held by switching of the transistor 200, so that writing, holding, and reading of data can be performed.

  In addition, by arranging the semiconductor devices illustrated in FIG. 21 in a matrix, a memory cell array can be formed.

  The layer including the transistor 300 has a structure similar to that of the semiconductor device illustrated in FIG. 18; thus, the above description can be referred to for a structure below the insulator 354.

  The insulator 360, the insulator 362, the insulator 212, the insulator 214, and the insulator 216 are provided over the insulator 354. Here, as the insulator 360, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used, like the insulator 350 and the like.

  A conductor 366 is embedded in the insulator 360, the insulator 362, the insulator 212, the insulator 214, and the insulator 216. The conductor 366 functions as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300. For example, the conductor 366 is electrically connected to the conductor 316 functioning as a gate electrode of the transistor 300.

  The conductor 246 functions as a plug or a wiring which is electrically connected to the transistor 200 or the transistor 300. For example, the conductor 246 is formed by electrically connecting the conductor 246b functioning as the other of the source and the drain of the transistor 200 and the conductor 110 functioning as one of the electrodes of the capacitor 100 through the conductor 246. I have.

  In addition, the planar capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Note that for the conductor 110, the conductor 120, and the insulator 130, those described in the above storage device 1 can be used.

  The conductor 153 and the conductor 110 are provided in contact with the upper surface of the conductor 246. The conductor 153 is in contact with the upper surface of the conductor 246 and functions as a terminal of the transistor 200 or the transistor 300.

  The conductor 153 and the conductor 110 are covered with the insulator 130, and the conductor 120 is provided so as to overlap with the conductor 110 with the insulator 130 interposed therebetween. Further, an insulator 114 is provided over the conductor 120 and the insulator 130.

  FIG. 21 illustrates an example in which a planar capacitor is used as the capacitor 100; however, the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 22, a cylindrical capacitor 100 as shown in FIG. 18 may be used as the capacitor 100.

  Here, for the details of the capacitor 100, the description of FIG. 18 can be referred to. However, as illustrated in FIG. 22, a structure in which the conductor 152 is provided over the conductor 246 and the conductor 112 is provided over the conductor 152 is preferable. With such a structure, electrical connection between the conductor 246 and the conductor 112 can be further ensured.

  Further, the insulator 154 is preferably provided over the insulator 150. As the insulator 154, an insulator which can be used for the insulator 160 may be used. Further, a conductor 153 is provided in contact with the upper surface of the conductor 112. The conductor 153 is in contact with the upper surface of the conductor 112 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300. Further, an insulator 156 is provided over the conductor 153 and the insulator 154.

  FIG. 22 illustrates an example in which the gate of the transistor 300 is electrically connected to the other of the source and the drain of the transistor 200 through one of the electrodes of the capacitor 100; The semiconductor device shown is not limited to this. For example, as illustrated in FIG. 23, the gate of the transistor 300 may be electrically connected to one of the electrodes of the capacitor 100 through the other of the source and the drain of the transistor 200. Accordingly, the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

(Embodiment 4)
In this embodiment, a transistor including an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are used with reference to FIGS. Storage device (hereinafter, may be referred to as an OS memory device) will be described. An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a nonvolatile memory.

<Configuration example of storage device>
FIG. 24A illustrates an example of a configuration of an OS memory device. The storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

  The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging a wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described later in detail. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

  A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the storage device 1400. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the storage device 1400. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

  The control logic circuit 1460 processes an external input signal (CE, WE, RE) to generate a control signal for a row decoder and a column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as needed.

  The memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC included in one row, and the like.

  Note that FIG. 24A illustrates an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane; however, this embodiment is not limited to this. For example, as illustrated in FIG. 24B, a memory cell array 1470 may be provided so as to overlap part of the peripheral circuit 1411. For example, a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be employed.

  FIG. 25 illustrates a configuration example of a memory cell applicable to the above-described memory cell MC.

[DOSRAM]
FIGS. 25A to 25C show circuit configuration examples of a memory cell of a DRAM. In this specification and the like, a DRAM including a memory cell of one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 1471 illustrated in FIG. 25A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes called a top gate) and a back gate.

  A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, and a back gate of the transistor M1. Are connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

  The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable that a low-level potential be applied to the wiring CAL during data writing and data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

  Here, the memory cell 1471 illustrated in FIG. 25A corresponds to the storage device illustrated in FIG. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005. Note that the transistor 300 illustrated in FIG. 18 corresponds to the transistor provided in the peripheral circuit 1411 of the memory device 1400 illustrated in FIG.

  Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1472 illustrated in FIG. Further, for example, the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M1 having no back gate, like the memory cell 1473 illustrated in FIG.

  In the case where the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be extremely low. That is, the written data can be held for a long time by the transistor M1, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

  In the DOSRAM, as described above, when the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit line can be shortened. As a result, the bit line capacity is reduced, and the storage capacity of the memory cell can be reduced.

[NOSRAM]
FIGS. 25D to 25G show circuit configuration examples of a gain cell memory cell having two transistors and one capacitor. A memory cell 1474 illustrated in FIG. 25D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (which may be simply referred to as a gate) and a back gate. In this specification and the like, a storage device including a gain cell memory cell including an OS transistor as the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

  A first terminal of the transistor M2 is connected to a first terminal of the capacitor CB, a second terminal of the transistor M2 is connected to a wiring WBL, a gate of the transistor M2 is connected to a wiring WOL, and a back gate of the transistor M2. Are connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to a first terminal of the capacitor CB.

  The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable that a low-level potential be applied to the wiring CAL during data writing, data holding, and data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

  Here, the memory cell 1474 illustrated in FIG. 25D corresponds to the storage device illustrated in FIG. That is, the transistor M2 is the transistor 200, the capacitor CB is the capacitor 100, the transistor M3 is the transistor 300, the wiring WBL is the wiring 2003, the wiring WOL is the wiring 2004, the wiring BGL is the wiring 2006, and the wiring CAL is the wiring CAL. In 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.

  Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1475 illustrated in FIG. For example, the memory cell MC may be a memory cell including a transistor with a single-gate structure, that is, a transistor M2 without a back gate, like the memory cell 1476 illustrated in FIG. For example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined as one wiring BIL as in a memory cell 1477 illustrated in FIG.

  In the case where the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be extremely low. Thus, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is extremely low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

  Note that the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor. In addition, by using a Si transistor as the transistor M3, the transistor M2 can be provided over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.

  Further, the transistor M3 may be an OS transistor. In the case where OS transistors are used for the transistors M2 and M3, a circuit can be formed using the memory cell array 1470 using only n-type transistors.

  FIG. 25H illustrates an example of a gain cell memory cell including three transistors and one capacitor. The memory cell 1478 illustrated in FIG. 25H includes the transistors M4 to M6 and the capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

  The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.

  Note that each of the transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be formed using only n-type transistors.

  In the case where the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. When an OS transistor is used as the transistor M4, the leakage current of the transistor M4 can be extremely low.

  Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

  The structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments and the like.

(Embodiment 5)
In this embodiment, an example of a chip 1200 in which the semiconductor device of the present invention is mounted is described with reference to FIGS. A plurality of circuits (systems) are mounted on the chip 1200. Such a technique of integrating a plurality of circuits (systems) on a single chip may be referred to as a system-on-chip (SoC).

  As shown in FIG. 26A, a chip 1200 includes a CPU 1211, a GPU 1212, one or a plurality of analog operation units 1213, one or a plurality of memory controllers 1214, one or a plurality of interfaces 1215, one or a plurality of network circuits 1216, and the like. Having.

  The chip 1200 is provided with bumps (not shown), and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to the motherboard 1203.

  The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. For example, the NOSRAM described in the above embodiment can be used for the flash memory 1222.

  The CPU 1211 preferably has a plurality of CPU cores. Further, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-described NOSRAM or DOSRAM can be used. In addition, the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the GPU 1212 with an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention, image processing and product-sum operation can be performed with low power consumption.

  In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.

  The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the above-described product-sum operation circuit may be provided in the analog operation unit 1213.

  The memory controller 1214 includes a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.

  The interface 1215 has an interface circuit with an external device such as a display device, a speaker, a microphone, a camera, or a controller. The controller includes a mouse, a keyboard, a game controller, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used as such an interface.

  The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). Further, a circuit for network security may be provided.

  The circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the number of manufacturing processes does not need to be increased, and the chip 1200 can be manufactured at low cost.

  The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.

  Since the GPU module 1204 has the chip 1200 using the SoC technology, the size can be reduced. In addition, since it is excellent in image processing, it is preferably used for portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. In addition, a product-sum operation circuit using the GPU 1212 allows a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network ( Since a technique such as DBN) can be executed, the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.

  The structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments and the like.

(Embodiment 6)
In this embodiment, an application example of a memory device including the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and playback device, a navigation system, and the like). Applicable to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the above embodiment is applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 27 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device described in any of the above embodiments is processed into a packaged memory chip, and used for various storage devices and removable memories.

  FIG. 27A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.

  FIG. 27B is a schematic diagram of the external appearance of the SD card, and FIG. 27C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided over the substrate 1113. Thus, data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.

  FIG. 27D is a schematic diagram of the appearance of the SSD, and FIG. 27E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

(Embodiment 7)
The semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU or a chip. FIG. 28 illustrates a specific example of an electronic device including a processor or a chip such as a CPU or a GPU according to one embodiment of the present invention.

<Electronic equipment and systems>
The GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic device include a relatively large screen such as a television device, a monitor for a desktop or notebook type information terminal, a digital signage (digital signage), and a large game machine such as a pachinko machine. Digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproducers, and the like. In addition, by providing a GPU or a chip according to one embodiment of the present invention in an electronic device, artificial intelligence can be mounted on the electronic device.

  The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with the antenna, display of images, information, and the like can be performed on the display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for wireless power transmission.

  The electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (Including a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

  The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), a wireless communication It can have a function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 28 illustrates an example of an electronic device.

[Information terminal]
FIG. 28A illustrates a mobile phone (smartphone) which is a kind of information terminal. The information terminal 5100 includes a housing 5101 and a display portion 5102. A touch panel is provided in the display portion 5102 as an input interface, and buttons are provided in the housing 5101.

  The information terminal 5100 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the content of the conversation on a display unit 5102, and recognizes a character, a graphic, and the like input by a user on a touch panel provided in the display unit 5102. An application displayed on the display portion 5102, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.

  FIG. 28B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display portion 5202, and a keyboard 5203.

  The notebook information terminal 5200 can execute an application utilizing artificial intelligence by applying the chip of one embodiment of the present invention, similarly to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. In addition, by using the notebook-type information terminal 5200, a new artificial intelligence can be developed.

  Note that, in the above description, a smartphone and a notebook-type information terminal are illustrated as examples in FIGS. 28A and 28B, respectively, but an information terminal other than the smartphone and the notebook-type information terminal is applied. be able to. Examples of the information terminal other than the smartphone and the notebook information terminal include a PDA (Personal Digital Assistant), a desktop information terminal, and a workstation.

[game machine]
FIG. 28C illustrates a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection portion 5305 provided in the housing 5301 to another housing (not shown), an image output to the display portion 5304 can be output to another video device (not shown). it can. At this time, the housing 5302 and the housing 5303 can each function as an operation portion. Thereby, a plurality of players can play the game at the same time. The chip described in the above embodiment can be incorporated in a chip or the like provided over the substrate of the housing 5301, the housing 5302, and the housing 5303.

  FIG. 28D illustrates a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

  By applying the GPU or the chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 or the stationary game machine 5400, a game machine with low power consumption can be realized. In addition, heat generation from a circuit can be reduced by low power consumption, so that influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

  Further, by applying the GPU or the chip of one embodiment of the present invention to the portable game machine 5300, the portable game machine 5300 having artificial intelligence can be realized.

  Originally, the expression of the progress of the game, the behavior of the creature appearing in the game, the phenomenon occurring in the game, etc. is determined by the program of the game, but by applying artificial intelligence to the portable game machine 5300, Thus, expressions that are not limited to game programs are possible. For example, it is possible to express such a content that a player asks a question, a progress of a game, a time, a behavior of a person appearing in the game changes.

  In addition, when playing a game that requires a plurality of players on the portable game machine 5300, the game player can be configured as an anthropomorphic person by artificial intelligence. Can play games.

  28C and 28D illustrate a portable game machine and a stationary game machine as an example of the game machine, but a game machine to which the GPU or the chip of one embodiment of the present invention is applied is not shown. It is not limited to. As a game machine to which the GPU or the chip of one embodiment of the present invention is applied, for example, an arcade game machine installed in an entertainment facility (a game center, an amusement park, or the like), a pitching machine installed in a sports facility for batting practice, or the like Is mentioned.

[Large computer]
The GPU or chip of one embodiment of the present invention can be applied to a large computer.

  FIG. 28E illustrates a supercomputer 5500 which is an example of a large-sized computer. FIG. 28F illustrates a rack-mounted computer 5502 included in the supercomputer 5500.

  The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are stored in a rack 5501. The computer 5502 is provided with a plurality of substrates 5504, and the GPU or the chip described in the above embodiment can be mounted on the substrates.

  The supercomputer 5500 is a large computer mainly used for scientific and technical calculations. In scientific calculations, enormous calculations must be processed at high speed, so that power consumption is high and chip heat generation is large. By applying the GPU or the chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, heat generation from a circuit can be reduced by low power consumption, so that influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

  28E and 28F illustrate a supercomputer as an example of a large computer; however, a large computer to which the GPU or the chip of one embodiment of the present invention is applied is not limited thereto. Examples of a large-sized computer to which the GPU or the chip of one embodiment of the present invention is applied include a computer (server) that provides a service, a large-sized general-purpose computer (mainframe), and the like.

[Mobile]
The GPU or the chip of one embodiment of the present invention can be applied to an automobile which is a mobile object and a periphery of a driver's seat of the automobile.

  FIG. 28G is a diagram illustrating the vicinity of a windshield in a vehicle, which is an example of a moving object. FIG. 28G illustrates a display panel 5701 attached to a pillar in addition to a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard.

  The display panels 5701 to 5703 can provide various kinds of information such as a speedometer, a tachometer, a traveling distance, a refueling amount, a gear state, and setting of an air conditioner. Further, display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, so that design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

  By displaying an image from an imaging device (not shown) provided in a car on the display panel 5704, a field of view (blind spot) blocked by the pillar can be complemented. That is, by displaying an image from the imaging device provided outside the automobile, blind spots can be compensated for and safety can be improved. In addition, by displaying an image that complements the invisible part, it is possible to more naturally confirm safety without a sense of incongruity. The display panel 5704 can be used as a lighting device.

  Since the GPU or the chip of one embodiment of the present invention can be applied as a component of artificial intelligence, the chip or the chip can be used for an automatic driving system of an automobile, for example. Further, the chip can be used in a system for performing road guidance, danger prediction, and the like. The display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.

  In the above description, a car is described as an example of a moving body, but the moving body is not limited to a car. For example, a moving object includes a train, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), and the like. The chip of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be provided.

[Electric appliances]
FIG. 28H illustrates an electric refrigerator-freezer 5800 which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a refrigerator door 5803, and the like.

  By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 has a function of automatically generating menus based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, and the like, and is stored in the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature to the food material.

  Although an electric refrigerator-freezer has been described as an example of the electric appliances, other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, a heating and cooling appliance including an air conditioner, Examples include a washing machine, a dryer, and an audiovisual device.

  The electronic device described in this embodiment, functions of the electronic device, application examples of artificial intelligence, effects thereof, and the like can be combined with descriptions of other electronic devices as appropriate.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

  In this example, a semiconductor device including the transistor 200 illustrated in FIG. 2, which is one embodiment of the present invention, was manufactured as the sample 1A, and a reliability test of the transistor 200 was performed.

<Sample preparation method>
Hereinafter, a method for manufacturing the sample 1A will be described.

First, the transistor 200 was designed to have a channel length of 60 nm and a channel width of 60 nm. In Sample 1A, a plurality of transistors 200 was formed in the same step. Note that the transistor density was 2.0 transistors / μm ² .

  Note that as the oxides 230a, 230b, and 230c, In—Ga—Zn oxide films were formed by a sputtering method. The oxide 230a was formed to a thickness of 5 nm with the use of a target having an atomic ratio of In: Ga: Zn = 1: 3: 4. The oxide 230b was formed to a thickness of 15 nm with the use of a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. The oxide 230c was formed to a thickness of 8 nm with the use of a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio].

  Subsequently, an In-Ga-Zn oxide was formed as the insulator 252 by a sputtering method. The insulator 252 was formed to a thickness of 8 nm with the use of a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].

  Thus, Sample 1A was produced.

<Transistor reliability>
Next, a GBT (Gate Bias Temperature) stress test was performed on one sample of the sample 1A in order to examine the reliability of the transistor. The GBT stress test is a kind of reliability test and can evaluate a change in transistor characteristics caused by long-term use.

  First, Id-Vg characteristics were measured as electrical characteristics of Sample 1A. Note that in the measurement of the Id-Vg characteristics, a potential (hereinafter, also referred to as a gate potential (Vg)) applied to the conductor 260 functioning as a first gate electrode of the transistor 200 is changed from a first value to a second value. The change in current (hereinafter, also referred to as drain current (Id)) between the conductor 240a functioning as a source electrode and the conductor 240b functioning as a drain electrode when the change is made is measured.

  Here, the potential between the conductor 240a and the conductor 240b (hereinafter, also referred to as drain potential Vd) is +0.1 V and +3.3 V, and the potential between the conductor 240a and the conductor 260 is -3. The change in drain current (Id) when changing from 3V to + 3.3V was measured.

  Note that in this measurement, the potential of the conductor 205 functioning as a second gate electrode (back gate electrode) (hereinafter, also referred to as a back gate potential (Vbg)) is 0.00 V, -1.00 V, or- The voltage was set to 3.00 V, and each case was measured.

  In the GBT stress test, the substrate on which the transistor is formed is kept at a constant temperature, the source potential and the drain potential of the transistor are the same, and the first gate potential is a potential different from the source potential and the drain potential. Give time. In this example, the acceleration test was performed by maintaining the temperature of the substrate on which the samples 1A and 1B were formed at 150 ° C. Further, the source potential and the drain potential of the transistor were set to 0.00 V, and the first gate potential was set to +3.63 V.

  In the GBT stress test, the Id-Vg characteristics were measured under the above-described conditions when an arbitrary time had elapsed. Note that the back gate potential was set to 0.00V.

  FIG. 29 shows the result of the GBT stress test in this example.

Note that a temporal change (hereinafter, also referred to as ΔVsh) of a threshold voltage (hereinafter, also referred to as Vsh) of the transistor was used as an index of a variation in electric characteristics of the transistor. Note that Vsh is defined as the value of Vg when Id = 1.0 × 10 ⁻¹² [A] in the Id-Vg characteristics. Here, for example, assuming that Vsh at the start of stress is +0.50 V and Vsh at the time of 100 seconds of stress is −0.55 V, ΔVsh at the time of 100 seconds of stress is −1.05 V. Become.

  According to FIG. 29, the change amount | ΔVsh | of the threshold voltage of the transistor of Sample 1A achieved 100 mV or less until 336 hours.

  From the above, it was confirmed that the transistor using one embodiment of the present invention was a semiconductor device including a transistor having excellent reliability.

  This embodiment can be implemented in combination with at least part of the embodiments as appropriate in another embodiment described in this specification.

  In this example, as the sample 2A, a transistor 200 including an oxide semiconductor according to one embodiment of the present invention, a transistor 300 including silicon, and a semiconductor device including the capacitor 100 are manufactured. Hereinafter, it is also referred to as rewriting endurance). Hereinafter, the measurement method and the result will be described with reference to FIG.

<Sample preparation method>
Hereinafter, a method for manufacturing the transistor 200 in the sample 2A is described.

  First, the transistor 200 was designed to have a channel length of 60 nm and a channel width of 60 nm. In Sample 2A, a plurality of transistors 200 was formed in the same step.

  Note that as the oxides 230a, 230b, and 230c, In—Ga—Zn oxide films were formed by a sputtering method. The oxide 230a was formed to a thickness of 5 nm with the use of a target having an atomic ratio of In: Ga: Zn = 1: 3: 4. The oxide 230b was formed to a thickness of 15 nm with the use of a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. The oxide 230c was formed to a thickness of 8 nm with the use of a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio].

  Subsequently, an In-Ga-Zn oxide was formed as the insulator 252 by a sputtering method. The insulator 252 was formed to a thickness of 8 nm with the use of a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].

  Thus, Sample 2A was produced.

<Circuit configuration and measurement method of sample>
The sample 2A is a semiconductor device having a circuit configuration illustrated in FIG. Note that a capacitor 100 having a capacitance value of 2 fF was used.

By examining a change in the potential (V _SN ) of the node SN when information retention and information writing were repeated a predetermined number of times, the rewriting durability of the sample 2A was measured. Further, an acceleration test was performed by maintaining the temperature of the substrate of Sample 2A at 85 ° C.

First, I _RBL −V _SN (V _WBL ) characteristics were measured as initial characteristics. A voltage of 2.5 V was applied to the wiring WWL and a voltage of −3 V was applied to the wiring BG1 to make the transistor 200 conductive, and the potential of the wiring WBL was supplied to a node SN corresponding to the gate of the transistor 300. Subsequently, a voltage of 1.2 V was applied to the wiring SL and a voltage of 0 V was applied to the wiring RBL. Therefore, by measuring the change in the drain current _{(I RBL)} of the transistor 300 when the potential of the wiring WBL was swept from -0.3V to + _1.5V, to obtain a I _RBL -V SN _{(V WBL)} properties .

  Subsequently, data0 or data1 was repeatedly written to the node SN in accordance with the input signal pattern shown in FIG.

  Note that data 0 or data 1 is written by applying 0 V or 1.2 V to the wiring WBL shown in FIG. 30A every 10 nsec and applying -0.8 V or 2.5 V to the wiring WWL for 5 nsec. The test was performed by applying each time. When a voltage of -0.8 V is applied to the wiring WWL, the transistor 200 is off and thus holds the potential applied to the node SN. In addition, when the potential of the wiring WWL is 2.5 V, the transistor 200 is on, so that the potential of the wiring WBL is supplied to the node SN.

Here, data0 or data1 when writing, in the state held as the potential _{V SN} node SN,, the current was measured _{I RBL.} Using the measured current I _RBL , the potential V _SN of the node SN was determined from the previously measured I _RBL −V _SN (V _WBL ) characteristic curve.

FIG. _30C illustrates the potential V _{SN of the} node SN with respect to the number of times of rewriting. In the graph illustrated in FIG. 30C, the vertical axis represents the potential V _SN [V] of the node SN, and the horizontal axis represents the number of rewrites [number of times]. FIG. 30C shows that the sample 2A can be written 1 × 10 ¹³ times. Therefore, it can be inferred that the semiconductor device does not deteriorate before and after writing 1 × 10 ¹³ times.

As described above, it has been found that the characteristics of the semiconductor device according to one embodiment of the disclosed invention are not changed even when holding and writing are repeated as many as 1 × 10 ¹³ times, and the rewriting durability is extremely high. Thus, according to one embodiment of the present invention, a highly reliable semiconductor device can be realized.

  This embodiment can be implemented in combination with at least part of the embodiments as appropriate in another embodiment described in this specification.

  10 substrate, 12 insulators, 14 insulators, 20 regions, 22 insulators, 24 insulators, 30 regions, 32 insulators, 34 insulators, 200 transistors, 205 conductors, 212 insulators, 214 insulators, 216 insulators Body, 220 insulator, 221 insulator, 222 insulator, 223 insulator, 224 insulator, 225 insulator, 230 oxide, 230a oxide, 230A oxide film, 230b oxide, 230B oxide film, 230c oxide, 230C oxide film, 240 conductor, 240a conductor, 240A conductive film, 240b conductor, 240B conductive layer, 250 insulator, 250A insulating film, 252 insulator, 252A insulating film, 260 conductor, 260a conductor, 260A conductor Film, 260b conductor, 260B conductive film, 274 insulator, 274A Insulating film, 275 insulator, 280 insulator, 280A insulating film, 282 insulator, 283 insulator, 284 insulator

Claims (15)

A transistor including an oxide semiconductor in a channel formation region,
The transistor has a gate, a source, and a drain,
A first insulator is formed below the oxide semiconductor;
A second insulator is formed between the gate and the oxide semiconductor;
One or both of the first insulator and the second insulator are:
Having a layer containing silicon and a layer containing gallium,
A transistor characterized by the above-mentioned. A transistor including an oxide semiconductor in a channel formation region,
The transistor has a first gate, a second gate, a source, and a drain,
A first insulator is formed between the second gate and the oxide semiconductor;
A second insulator is formed between the first gate and the oxide semiconductor;
One or both of the first insulator and the second insulator are:
Having a layer containing silicon and a layer containing gallium,
A transistor characterized by the above-mentioned. In any one of claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the oxide semiconductor contains indium, zinc, and gallium. In any one of claims 1 to 8,
The method for manufacturing a semiconductor device, wherein the oxide semiconductor and the layer containing gallium have a crystal structure. A transistor according to claim 1,
And a capacitor element,
The capacitance element is
A semiconductor device having a layer containing silicon and a layer containing gallium included in the transistor. In claim 5,
The capacitive element is formed above the transistor;
A semiconductor device characterized by the above-mentioned. In claim 5,
The capacitor is formed below the transistor.
A semiconductor device characterized by the above-mentioned. A transistor according to any one of claims 1 to 7,
A semiconductor device having a third insulator and a fourth insulator,
The third insulator has aluminum and oxygen,
The fourth insulator has silicon and nitrogen,
Any one or more of an upper surface, a lower surface, and a side surface of the transistor,
Covered by the third insulator, and the fourth insulator,
A semiconductor device characterized by the above-mentioned. In claim 8,
The third insulator is located inside the fourth insulator.
A semiconductor device characterized by the above-mentioned. A method for manufacturing a transistor including an oxide semiconductor in a channel formation region,
The transistor includes the oxide semiconductor, a first insulator, a gate, a source, and a drain,
The first insulator has a layer containing gallium and a layer containing silicon,
The method for manufacturing the transistor is at least
Forming the oxide semiconductor;
Forming the source and the drain on the oxide semiconductor;
Forming the first insulator on the top surface of the oxide semiconductor, and the side surfaces of the source and the drain;
Forming the gate on the first insulator;
In the step of forming the first insulator,
A method for manufacturing a transistor, wherein the layer containing gallium and the layer containing silicon are continuously formed under reduced pressure. In claim 10,
The transistor further has a second insulator and a second gate,
The method for manufacturing the transistor is at least
Forming the second gate;
Forming the second insulator on the second gate;
Forming the oxide semiconductor;
Forming the source and the drain on the oxide semiconductor;
Forming the first insulator on the top surface of the oxide semiconductor, and the side surfaces of the source and the drain;
Forming the gate on the first insulator;
In the step of forming the first insulator,
A method for manufacturing a transistor, wherein the layer containing gallium and the layer containing silicon are continuously formed under reduced pressure. In any one of claim 10 or claim 11,
The oxide semiconductor includes indium, zinc, and gallium,
The oxide semiconductor is formed by a sputtering method;
A method for manufacturing a transistor, comprising: In any one of claims 10 to 12,
The oxide semiconductor, and the layer containing gallium,
Formed to have crystallinity,
A method for manufacturing a transistor, comprising: In any one of claims 10 to 13,
The oxide semiconductor, and the layer containing gallium,
Formed by heating at a temperature of 100 ° C. or higher,
A method for manufacturing a transistor, comprising: In any one of claims 10 to 14,
The first insulator is formed by an ALD method;
A method for manufacturing a semiconductor device, comprising:

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