JP2019212027A - Image processing system, control method therefor, and program - Google Patents

Abstract

To solve a problem that processing efficiency of an entire device decreases due to occurrence of a bus master access restriction despite a period during which real-time processing can be maintained by a buffer function of a buffering buffer even if a usage rate of a memory bandwidth is large.SOLUTION: An image processing system, which has a plurality of bus masters accessing a main memory, detects access to the main memory by the plurality of bus masters to acquire a bus band, and acquires a data amount of a buffering buffer provided between a bus master requiring real-time processing and the main memory. The image processing system compares, when the acquired bus bandwidth exceeds a first threshold, the acquired data amount of the buffering buffer with a second threshold and restricts the access to the main memory by a bus master having a lowest priority among the plurality of bus masters.SELECTED DRAWING: Figure 11

Description

  The present invention relates to an image processing apparatus, a control method thereof, and a program.

  An image processing apparatus such as a digital multi-function peripheral having a scanner function, a printer function, a copy function, and the like is known. The operation of the digital multifunction peripheral is normally controlled by a controller in which an ASIC (Application Specific Integrated Circuit) for performing image processing and image input / output control is mounted.

  In recent years, in order to reduce the size and cost, a CPU and a plurality of function processing units that realize various functions are integrated into one ASIC. In addition, the memory used by the CPU as a work area and the memory used for transferring image data when realizing various functions have been integrated into the main memory, and the amount of data access to the main memory has increased greatly. Yes.

  Furthermore, as a factor that increases the amount of data access to the main memory, it is also possible to increase the scanning performance and printing performance. The processes such as scan and print are essential processes that cannot be stopped once the operation is started until the input / output of the image data of the page being processed is completed. Normally, in such real-time processing, even if a temporary reduction in the processing speed of the controller occurs, the data is temporarily stored so that the image data transfer to the scanner or printer can be continued normally. A short buffer to save is provided. This short buffer is a buffer buffer mounted in the scan processing unit and print processing unit in the ASIC, and data transfer with the scanner and printer is performed via this short buffer.

  Patent Document 1 describes an image processing apparatus having a bus arbitration unit that monitors the operation state of each bus master and restricts data transfer of the bus master when the utilization rate of the obtained memory bandwidth reaches the memory bandwidth limit value. . Furthermore, the cited document 1 describes a configuration that allows a memory bandwidth limit value of a plurality of bus masters to be set dynamically.

JP 2013-196667 A

  However, the data transfer in the real-time processing of scanning and printing not only via the bus for the main memory but also via the short buffer. For example, in the technique described in Patent Document 1, only the operation state of each bus master is monitored, and when the utilization rate of the memory bandwidth increases, a certain bus master is restricted from being accessed. For this reason, even if the utilization rate of the memory bandwidth is large, the access restriction of the bus master occurs despite the period in which the real-time processing can be maintained by the buffer function of the short buffer. As a result, there has been a problem that the non-real-time processing speed is reduced. The period in which real-time processing can be maintained by the buffer function of the short buffer is a period in which the amount of data stored in the short buffer is small in the scan process, and a period in which the amount of data stored in the short buffer is large in the print process. It is.

  An object of the present invention is to solve at least one of the problems of the prior art.

  It is an object of the present invention to minimize the speed reduction of non-real-time processing while maintaining real-time processing so as not to restrict bus master access when real-time processing can be maintained by a buffer buffer.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention has the following arrangement. That is,
An image processing apparatus having a plurality of bus masters accessing a main memory,
Band monitoring means for detecting access to the main memory by the plurality of bus masters and acquiring a bus band;
An acquisition means for acquiring a data amount of a buffer provided between the bus master and the main memory for which real-time processing is required;
The bus bandwidth acquired by the bandwidth monitoring unit exceeds the first threshold value, and the highest priority is selected from the plurality of bus masters according to the comparison between the buffer buffer data amount acquired by the acquisition unit and the second threshold value. And control means for controlling to restrict access to the main memory by a bus master having a lower rank.

  According to the present invention, even when the bus bandwidth is equal to or greater than a predetermined value, when the buffer buffer effect can be exerted, the access restriction of the bus master having a low priority can be avoided, so that the performance degradation of the device can be prevented. .

  Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, the same or similar components are denoted by the same reference numerals.

The accompanying drawings are included in the specification, constitute a part thereof, show an embodiment of the present invention, and are used together with the description to explain the principle of the present invention.
1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention. The figure which shows the example of calculation of a memory band. FIG. 3 is a block diagram illustrating a configuration of a scan processing unit in the image processing apparatus according to the first embodiment. The figure which shows an example of the bus master management table which the bus arbitration part which concerns on Embodiment 1 uses for bus arbitration. 5 is a flowchart for explaining initialization processing of a bus master management table in the image processing apparatus according to the first embodiment. 5 is a flowchart for explaining bus bandwidth control processing when starting a job in the image processing apparatus according to the first embodiment. 5 is a flowchart for explaining processing when image processing by an image processing unit ends in the image processing apparatus according to the first embodiment. In the image processing apparatus according to the first embodiment, a flowchart (A) illustrating a process for determining whether or not a bandwidth control process is necessary, and a flowchart (B) illustrating a bus master access control process in S805 of FIG. . The block diagram explaining the structure of the image processing apparatus which concerns on Embodiment 2 of this invention. FIG. 9 is a block diagram illustrating an example of a configuration of a print processing unit according to an image processing apparatus according to a second embodiment. 9 is a flowchart for describing processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the second embodiment. FIG. 9 is a block diagram illustrating a configuration of a print processing unit in an image processing apparatus according to a third embodiment. 9 is a flowchart for describing processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the third embodiment. The block diagram explaining the structure of the image processing apparatus which concerns on Embodiment 4 of this invention. 9 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the fourth embodiment. FIG. 10 is a block diagram illustrating a configuration of a print processing unit in an image processing apparatus according to a fifth embodiment. 10 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the fifth embodiment. FIG. 10 is a block diagram illustrating a configuration of a print processing unit 170 in an image processing apparatus according to a sixth embodiment. 14 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the sixth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the present invention. .

  First, the premise of the embodiment will be briefly described. The image data from the scanner is once written in the short buffer, and the scan processing unit reads the image data from the short buffer and performs image processing. In the normal state, the scan processing unit can process the image data at the same speed as the transfer speed of the scanner, so that the amount of residual data in the short buffer is small without storing the image data in the short buffer. On the other hand, for example, if the scan processing unit can process image data only at a speed lower than the transfer speed of the scanner due to a temporary lack of bus bandwidth in the main memory, the residual data amount in the short buffer gradually increases. To do. However, even if the bus bandwidth is temporarily short in this way, the data transfer from the scanner to the scan processing unit is not interrupted by the buffer function of the short buffer. When the temporary shortage of the bus bandwidth is resolved, the scan processing unit can process the image data stored in the short buffer at a speed exceeding the transfer speed of the image data from the scanner. As a result, the residual data amount in the short buffer gradually decreases, and the residual data amount stored in the short buffer settles to a small state.

  The image data processed by the print processing unit is once written in the short buffer, and the image data read from the short buffer is sent to the printer. At this time, before starting data transfer to the printer, the print processing unit fills the short buffer with image data. This is to prevent data from being interrupted immediately after the start of data transfer to the printer. In the normal state, the print processing unit can process the image data at a speed similar to the transfer speed of the printer, so that the amount of residual data in the short buffer remains large without reducing the image data from the short buffer. However, when the print processing unit can process image data only at a speed lower than the transfer speed of the printer due to a temporary bus bandwidth shortage in the main memory, the residual data amount in the short buffer gradually decreases. However, even when the bus bandwidth temporarily falls short as described above, the transfer of the image data to the printer is not interrupted by the buffer function of the short buffer. When the temporary shortage of the bus bandwidth is resolved, the print processing unit can process the image data at a speed exceeding the data transfer speed to the printer and store it in the short buffer. As a result, the amount of residual data in the short buffer gradually increases, and settles with a large amount of residual data stored in the short buffer.

  Further, the print processing unit uses an area on the main memory as a ring buffer in order to buffer a large amount of data. The print processing unit writes the processed image data sequentially from the beginning of the ring buffer area, and when the image data is written at the end of the ring buffer area, it is overwritten with subsequent data from the beginning of the ring buffer area. repeat. The print processing unit sequentially reads data from the beginning of the ring buffer area and transfers the data to the printer. When the print processing unit reads data from the end of the ring buffer area, it repeatedly reads data from the beginning of the ring buffer area. The print processing unit has a write pointer indicating the position of the ring buffer area to which data is written and a read pointer indicating the position of the ring buffer area from which data is read. The print processing unit controls the read pointer to follow the write pointer and controls the write pointer not to pass the read pointer.

  In a controller that controls these, it is desirable that access to the main memory for image processing that requires real-time processing always guarantees a certain transfer bandwidth and that non-real-time processing functions are operated in parallel as much as possible. That is, the controller is designed so as not to cause a situation in which the transfer bandwidth of access to the main memory for image processing that requires real-time processing cannot be guaranteed.

  To ensure a sufficient transfer bandwidth for memory access even when all functions are operated simultaneously, a high-frequency, multi-bit memory device must be used and sufficient memory transfer performance must be ensured. I must. However, using a high-frequency memory device increases the cost of the memory and increases the power consumption, and using a multi-bit width memory increases the cost of the chip due to an increase in the number of pins of the chip. Connected. Therefore, a method for securing a transfer band to the main memory of the real-time processing function while suppressing increase in frequency and multi-bit of the memory is proposed. For this purpose, it is conceivable to monitor the operation state of each bus master with respect to the main memory and control the access of each bus master. Hereinafter, embodiments will be described in detail with reference to the drawings.

[Embodiment 1]
FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to the first embodiment of the present invention. The image processing apparatus according to the embodiment includes a controller (control unit) 10 for performing image processing and image input / output control, an operation unit 105 for a user to perform various operations and setting changes, and an operation unit 105 And a scanner unit 161 that reads a document in accordance with an instruction. The scanner unit 161 includes a CPU (not shown) that controls the scanner unit 161, an illumination lamp (not shown), a scanning mirror, and the like for reading a document.

  The controller 10 has a ROM 103 in which a boot program executed by the CPU 101 is stored. The CPU 101 reads out the contents stored in the ROM 103 via the ROM I / F 102. Further, the CPU 101 controls the operation unit 105 via the operation unit I / F 104 to detect a user operation. Furthermore, the controller 10 has a main memory 152 which is a system work memory for the operation of the CPU 101 and also an image memory for temporarily storing image data. The memory controller 151 arbitrates access to the main memory 152 from the CPU 101, the scanner unit 161, and the image processing units 111 to 115, and performs read / write control on the main memory 152. The controller 10 includes a scan processing unit 160 that inputs and processes image data from the scanner unit 161 and transfers the processed image data to the main memory 152.

  The controller 10 also includes image processing units A to E (111 to 115) that input image data from the main memory 152, perform image processing, and transfer the processed image data to the main memory 152. These image processing units 111 to 115 serve as a bus master, and perform reading and writing with respect to the main memory 152. Access to the main memory 152 by the image processing units 111 to 115 is arbitrated by the bus arbitration unit 130 and is transmitted to the memory controller 151 via the bus 142. Note that the number of image processing units is five only as an example. Further, the controller 10 includes a bandwidth monitor (bandwidth monitoring unit) 150 that monitors the amount of transfer data of the bus 141, the bus 142, and the bus 143 connected to the memory controller 151 and calculates the total bandwidth of the transfer data.

  Next, the band monitor 150 will be described. The transfer speed (memory bandwidth) between the memory controller 151 and the main memory 152, that is, the memory side of the memory controller 151 is substantially determined by the operating frequency, data bit width, and data transfer efficiency of the main memory 152. The data transfer efficiency is the ratio of the actually available data transfer amount to the theoretical maximum data transfer amount. In general, when there are many accesses to distributed addresses, the data transfer efficiency is low, and when there are many cases where successive addresses are accessed in order, the data transfer efficiency is high. The calculation method of the memory bandwidth is expressed by the following formula.

Memory bandwidth [MB / s] = (memory operating frequency [MHz]) × (memory bus width [bit]) × (memory data transfer efficiency [%]) / 8
FIG. 2 is a diagram illustrating an example of calculating the memory bandwidth.

  The bandwidth monitor 150 monitors the transfer data amount of the bus 141, the bus 142, and the bus 143. When the total bandwidth (bus bandwidth) of the calculated transfer data is lower than the memory bandwidth, the access from each bus is not delayed. Data is sent to the memory 152. On the other hand, when the value of the bus bandwidth matches or is close to the value of the memory bandwidth, the data transfer amount on the memory side of the memory controller 151 is close to the limit. There is a high possibility of waiting time. Therefore, the access speed to the main memory 152 of the scan processing unit 160 connected to the bus 143 that requires real-time processing decreases, and the real-time processing required for the scan processing may be broken.

  Therefore, when the bus bandwidth value calculated by the bandwidth monitor 150 exceeds the threshold value with the memory bandwidth value or a value slightly smaller than the threshold value, the bus bandwidth control for preventing the real-time processing from breaking down. Therefore, the following control is performed.

  FIG. 3 is a block diagram illustrating the configuration of the scan processing unit 160 in the image processing apparatus according to the first embodiment.

  The scan processing unit 160 includes a scan image processing unit 301 that processes data from the scanner unit 161 and a short buffer 302 that is used as a buffer buffer. The scan processing unit 160 once writes the image data from the scanner unit 161 in the short buffer 302. As long as image data is stored in the short buffer 302, the scan processing unit 160 reads out the image data and sends it to the scan image processing unit 301 to perform image processing. Further, the scan processing unit 160 sends the image data processed by the scan image processing unit 301 to the memory controller 151 via the bus 143.

  The scan processing unit 160 includes a short buffer monitor 303 that monitors the amount of data stored in the short buffer 302. For monitoring the amount of data stored in the short buffer 302 by the short buffer monitor 303, for example, a counter (not shown) indicating the amount of data stored in the short buffer 302 is provided in the short buffer monitor 303. The counter can measure the amount of data written to the short buffer 302 and the amount of data read from the short buffer 302. At this time, the short buffer monitor 303 increments a counter indicating the amount of data when data writing is detected, and decrements the counter when data reading is detected. Then, the value of this counter is assigned to a register, and the CPU 101 reads the register, whereby the data amount of the short buffer 302 can be acquired. Further, if the short buffer 302 is constituted by, for example, an SRAM, the amount of data stored in the short buffer 302 is acquired from the difference between the write address for writing data next and the address for reading data next. May be.

  FIG. 4 is a diagram illustrating an example of a bus master management table used by the bus arbitration unit 130 according to the first embodiment for bus arbitration. The index is not a part of the bus master management table, but is for explaining processing in which the CPU 101 described later refers to the bus master management table in order from the top.

  Here, the bus master E has the highest priority, and the bus master D has the lowest priority. In the initial state, none of the bus masters is in operation and no access restriction occurs.

  FIG. 5 is a flowchart for explaining initialization processing of the bus master management table in the image processing apparatus according to the first embodiment. This process is a flowchart showing the initialization process of the bus master management table after the image processing apparatus is powered on. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152.

  First, in step S501, the CPU 101 creates a bus master management table as shown in FIG. This bus master management table is used by the CPU 101 to manage the usage status of each bus master. Here, the CPU 101 creates rows of the bus master management table in the order of lower priority, in other words, in the order of less adverse effects on the real-time processing.

  In step S <b> 502, the CPU 101 initializes the “in operation” column of all bus masters in the bus master management table to “No”. In step S503, the CPU 101 initializes the “access restriction” column of all bus masters in the bus master management table to “No”, and ends this process. FIG. 4 shows a state in which the bus master management table is created and initialized in this way.

  FIG. 6 is a flowchart for explaining bus bandwidth control processing when starting a job in the image processing apparatus according to the first embodiment. Processing executed when a job is started according to an instruction from the operation unit 105 is shown. It is a flowchart. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152.

  First, in step S <b> 601, the CPU 101 acquires a bus master used in the job from the job instructed by the operation unit 105. In step S602, the CPU 101 updates the “active” column of the bus master acquired in step S601 in the bus master management table to “Yes”. In step S603, the CPU 101 updates the “access restriction” column of the bus master acquired in step S601 to “No” in the bus master management table. In step S604, the CPU 101 releases the access restriction of the bus master used in the instructed job, and starts image processing by the image processing unit corresponding to the job. The access restriction of the corresponding bus master will be described later.

  Thus, image processing corresponding to the instructed job and access to the main memory 152 by the corresponding bus master are executed.

  FIG. 7 is a flowchart for explaining processing when image processing by the image processing unit ends in the image processing apparatus according to the first embodiment. Processing for interrupting processing from each of the image processing units 111 to 115 and the like. A control process that is executed when the process is completed will be described. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152.

  In step S <b> 701, the CPU 101 identifies an image processing unit that has completed processing from an interrupt factor and acquires a bus master corresponding to the image processing unit. The process advances to step S702, and the CPU 101 updates the “active” column of the bus master acquired in step S701 in the bus master management table to “No”, and ends this process.

  As a result, information on the bus master whose processing has been completed in the bus master management table is updated.

  FIG. 8A is a flowchart for explaining processing for determining whether or not the bandwidth control processing is necessary in the image processing apparatus according to the first embodiment. In order to monitor the bus bandwidth acquired by the bandwidth monitor 150, a certain time is shown. It is executed repeatedly at intervals. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152.

  First, in step S <b> 801, the CPU 101 acquires a bus bandwidth value detected by the bandwidth monitor 150. In step S802, the CPU 101 compares the bus bandwidth value acquired in step S801 with a first predetermined value (first threshold value). If the bus bandwidth value exceeds the first threshold value, that is, if access restriction of the bus master may be necessary, the process proceeds to S803, and if not, the process flow ends. Here, as described above, the first threshold value is a value of the memory bandwidth or a value slightly smaller than the value.

  In step S <b> 803, the CPU 101 acquires the remaining data amount stored in the short buffer 302 from the short buffer monitor 303. In step S804, the CPU 101 compares the residual data amount acquired in step S803 with a second predetermined value (second threshold). If the remaining data amount exceeds the second threshold value, that is, if access restriction of the bus master is necessary, the process proceeds to S805, and if not, this process ends. The process of monitoring the bus bandwidth is repeatedly executed at regular time intervals, but the short buffer 302 must not overflow with data from the scanner unit 161 between the monitoring processes. From this time interval and the data transfer rate of the scanner unit 161, the amount of data transferred to the short buffer 302 between the monitoring processes can be known. The second threshold value here may be a value such that the free space in the short buffer 302 becomes the amount of data to be transferred or a larger amount.

  In step S <b> 805, the CPU 101 performs processing for restricting access of a bus master having a low priority, and this processing will be described with reference to a flowchart of FIG. 8B.

  FIG. 8B is a flowchart for explaining the access control processing of the bus master in S805 of FIG.

  First, in step S810, the CPU 101 initializes a variable INDEX (provided in the main memory 152) for sequentially referring to the bus master management table to “0”. In step S811, the CPU 101 refers to the bus master management table, and acquires the contents of the “active” and “access restriction” columns of the bus master corresponding to the value of the variable INDEX. In step S812, the CPU 101 determines whether “in operation” is “Yes” and “access restriction” is “No”. If “in operation” is “Yes” and “access restriction” is “No”, the bus master is actually operating, and the process proceeds to S813. Otherwise, the process proceeds to S815.

  In step S813, the CPU 101 updates the “access restriction” column of the bus master corresponding to the value of the variable INDEX in the bus master management table to “Yes”. In step S814, the CPU 101 restricts access of the bus master corresponding to the value of the variable INDEX in the bus master management table, and ends this process. In this case, the access restriction is provided by providing a register for instructing access restriction to the image processing units 111 to 115, and the image processing units 111 to 115 instructed to restrict access widen the access interval for the corresponding buses 121 to 125. realizable. Further, the access restriction may be performed by controlling the arbitration priority for the buses 121 to 125 of the bus arbitration unit 130, that is, by reducing the arbitration priority for the bus of the bus master whose access is to be restricted.

  On the other hand, if the CPU 101 determines that “in operation” is “No” or “access restriction” is “Yes” in S812, the process proceeds to S815. In step S815, the CPU 101 next increments the variable INDEX to refer to the bus master information. In step S816, the CPU 101 compares the value of the variable INDEX with the number of bus masters registered in the bus master management table. If the value of the variable INDEX is smaller than the number of bus masters, that is, if there is a bus master that is not referenced in the bus master management table, the process returns to S811, and the bus master management table is continuously referenced. On the other hand, if this is not the case, the process is terminated.

  In this way, in the bus master access control process, the bus master with the lowest priority is checked for the operating state of the bus master and whether there is an access restriction, and the bus master that is in operation and has no access restrictions is determined as the target of the access control process. . Then, an access control process is executed for the determined bus master.

  As described above, according to the first embodiment, even if the value of the bus bandwidth detected by the bandwidth monitor exceeds the threshold value, the residual data amount of the short buffer that requires real-time processing is the threshold value. If it does not exceed, access restriction of the bus master is not performed. As a result, useless bus master access restrictions are suppressed, and performance degradation of the image processing apparatus is suppressed.

  Also, when performing bus master access restriction, the bus master management table is referenced to determine the bus master to be subject to access restriction. Thus, the bus master having the lowest priority among the bus masters that are in operation and are not subject to access restrictions can be determined as the bus master that is subject to access restriction.

[Embodiment 2]
FIG. 9 is a block diagram illustrating the configuration of the image processing apparatus according to the second embodiment of the present invention. The difference from the apparatus configuration of the image processing apparatus according to the first embodiment is that there is no scanner unit and a printer unit 171 exists.

  The image processing apparatus according to the second embodiment includes a controller 10 for performing image processing and image input / output control, an operation unit 105 for a user to perform various operations and setting changes, and an image according to instructions from the operation unit 105. A printer unit 171 for printing data on paper. The printer unit 171 includes a CPU (not shown) for controlling the printer unit 171 and a photosensitive drum (not shown) and a fixing device for image formation and fixing. The controller 10 includes a print processing unit 170 that processes image data stored in the main memory 152 and transfers the image data to the printer unit 171. Since other configurations are the same as the configuration of the image processing apparatus according to the first embodiment, description thereof is omitted.

  FIG. 10 is a block diagram illustrating an example of the configuration of the print processing unit 170 according to the image processing apparatus according to the second embodiment.

  The print processing unit 170 includes a print image processing unit 1001 that processes image data received from the memory controller 151 via the bus 144. In addition, the print processing unit 170 includes a ring buffer write control unit 1002 that writes image data from the print image processing unit 1001 in a ring buffer area on the main memory 152. Further, a ring buffer read control unit 1003 for reading image data stored in the ring buffer area is provided. The print processing unit 170 has a short buffer 1004 used as a buffer buffer, and the image data read from the ring buffer by the ring buffer read control unit 1003 is sent to the printer unit 171 via the short buffer 1004.

  The ring buffer write control unit 1002 has a write pointer, the ring buffer read control unit 1003 has a read pointer, the ring buffer write control unit 1002 refers to the read pointer, and the ring buffer read control unit 1003 refers to the write pointer. When the ring buffer write control unit 1002 determines that there is an empty space in the ring buffer area from the values of the write pointer and the read pointer, it writes data in the ring buffer area. On the other hand, the ring buffer read control unit 1003 reads data when it is determined that data exists in the ring buffer area from the values of the write pointer and the read pointer. At this time, the read pointer is controlled to follow the write pointer, and the write pointer is controlled not to overtake the read pointer.

  The print processing unit 170 further includes a short buffer monitor 1005 that monitors the amount of data stored in the short buffer 1004. The monitoring of the amount of data stored in the short buffer 1004 is realized, for example, by providing a counter (not shown) indicating the amount of data in the short buffer monitor 1005 and monitoring the writing and reading of data with respect to the short buffer 1004. At this time, the short buffer monitor 1005 increments a counter indicating the amount of data when a write is detected, and decrements the counter when a read is detected. Then, the value of this counter is assigned to a register, and the CPU 101 can know this by reading the register.

  Further, if the short buffer 1004 is composed of SRAM, the amount of data stored in the short buffer 1004 may be calculated from the difference between the write address to be written next and the read address to be read next.

  FIG. 11 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the second embodiment. In order to monitor the bus bandwidth acquired by the bandwidth monitor 150, the processing is repeated at regular time intervals. Executed. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152. In the second embodiment, the initialization control flow related to the bus bandwidth control process after power-on is the same as that of the image processing apparatus according to the first embodiment shown in FIG. In the second embodiment, the control flow executed when a job is started by an instruction from the operation unit 105 is the same as that of the image processing apparatus according to the first embodiment shown in FIG. Further, in the second embodiment, the control flow executed when a certain image process is ended by a process end interrupt from each of the image processing units 111 to 115 is the same as that of the image processing apparatus according to the first embodiment in FIG. .

  Next, a control flow repeatedly executed at regular time intervals in order to monitor the bus bandwidth calculated by the bandwidth monitor 150 will be described using the flowchart of FIG. In the figure, S1103 and S1104 are different processes from those in the first embodiment.

  In step S <b> 1101, the CPU 101 acquires a bus bandwidth value from the bandwidth monitor 150. In step S1102, the CPU 101 compares the bus bandwidth value acquired in step S1101 with the first threshold value. If the bus bandwidth value exceeds the first threshold value, that is, if access restriction of the bus master may be necessary, the process proceeds to S1103, and if not, the process ends. Here, as described above, the first threshold value is a value of the memory bandwidth or a value slightly smaller than the value.

  In step S <b> 1103, the CPU 101 acquires the remaining data amount stored in the short buffer 1004 from the short buffer monitor 1005. In step S1104, the CPU 101 compares the residual data amount with the second threshold value. If the remaining data amount is below the second threshold value, that is, if access restriction of the bus master is necessary, the process proceeds to S1105, and if not, this process ends. The process of monitoring the bus bandwidth is repeatedly executed at regular time intervals, but the data output to the printer unit 171 must not be cut off from the short buffer 1004 between the monitoring processes. From this time interval and the data transfer rate of the printer unit 171, the amount of data read from the short buffer 1004 can be known between the monitoring processes. The second threshold value here may be a value such that the data amount of the short buffer 1004 is equal to or larger than the read data amount.

  In step S1105, the CPU 101 performs processing for restricting access by a bus master having a low priority, and this processing is the same as the processing described with reference to FIG. The first threshold value and the second threshold value in the second embodiment may be the same as the first threshold value and the second threshold value in the first embodiment, or may be different from each other.

  As described above, according to the second embodiment, even if the bus bandwidth value from the bandwidth monitor exceeds the threshold value, the data amount of the buffer buffer that temporarily stores the data to be output to the printer falls below the threshold value. Otherwise, the bus master access is not restricted. As a result, useless bus master access restrictions are suppressed, and performance degradation of the image processing apparatus is suppressed.

  Further, when performing bus master access restriction, the bus master for which access restriction is performed is determined with reference to the bus master management table. This makes it possible to determine the bus master having the lowest priority as the bus master subject to the bandwidth restriction among the bus masters that are in operation and are not subject to the access restriction.

[Embodiment 3]
The apparatus configuration of the image processing apparatus according to the third embodiment of the present invention is the same as the apparatus configuration of the image processing apparatus according to the second embodiment.

  In the image processing apparatus according to the second embodiment, when the printing operation is not performed, the short buffer 1004 in the print processing unit 170 is empty (the amount of stored data is zero). If the printing operation is not performed, that is, if the real-time processing is not performed, naturally the bus master should not be restricted. However, as is apparent from the flowchart of FIG. 11, if the bus bandwidth value of the bandwidth monitor 150 exceeds the threshold value, if the printing operation is not performed, the process branches from S1104 to S1005, and the bus master access restriction process. Will be executed. The image processing apparatus according to the third embodiment solves such a problem.

  First, after the short buffer 1004 is filled with image data by the print image processing unit 1001, data transfer to the printer unit 171 is started. This is to prevent the data transfer from being interrupted immediately after the start of the data transfer. That is, until the data transfer to the printer unit 171 is started, the remaining data amount in the short buffer 1004 is not considered.

  Further, during the data transfer to the printer unit 171, after the last image data of the page, that is, the final data of the data transfer to the printer unit 171 is written in the short buffer 1004, the residual data amount in the short buffer 1004 is It decreases toward zero. However, in this case, the data transfer to the printer unit 171 is not interrupted by the decrease in the residual data amount in the short buffer 1004.

  FIG. 12 is a block diagram illustrating the configuration of the print processing unit 170 in the image processing apparatus according to the third embodiment. In FIG. 12, the same reference numerals are given to the portions common to the configuration of FIG. 10 described above, and description thereof will be omitted.

  The print processing unit 170 includes a print image processing unit 1001 that processes image data received from the memory controller 151 via the bus 144. The print processing unit 170 includes a ring buffer write control unit 1002 that writes image data from the print image processing unit 1001 in the ring buffer area of the main memory 152 and a ring buffer read control unit 1003 that reads out image data stored in the ring buffer area. Have. The print processing unit 170 includes a short buffer 1004 used as a buffer buffer, and image data read from the ring buffer by the ring buffer read control unit 1003 is sent to the printer unit 171 via the short buffer 1004.

  The ring buffer write control unit 1002 has a write pointer, and the ring buffer read control unit 1003 has a read pointer. The ring buffer write control unit 1002 refers to the read pointer, and the ring buffer read control unit 1003 refers to the write pointer. The ring buffer write control unit 1002 writes data when it is determined from the values of the write pointer and the read pointer that there is an empty space in the ring buffer area. On the other hand, the ring buffer read control unit 1003 reads data when it is determined from the write pointer and the read pointer value that data exists in the ring buffer area. At this time, the read pointer is controlled to follow the write pointer, and the write pointer is controlled not to overtake the read pointer.

  The print processing unit 170 includes a short buffer monitor 1005 that monitors the amount of data stored in the short buffer 1004. Monitoring the amount of data stored in the short buffer 1004 is realized, for example, by providing a counter (not shown) indicating the amount of data in the short buffer monitor 1005 and monitoring writing and reading of data to the short buffer 1004. Of course, the short buffer monitor 1005 increments a counter indicating the amount of data upon detection of data writing, and decrements the counter upon detection of data reading. Then, the value of the counter is assigned to a register, and the CPU 101 reads the register, whereby the stored data amount can be acquired. Further, if the short buffer 1004 is composed of SRAM, the amount of data stored in the short buffer 1004 may be acquired from the difference between the write address to be written next and the read address to be read next.

  Further, the print processing unit 170 includes a data transfer state monitoring unit 1201 that monitors the data transfer state of the printer unit 171, which is a feature of the third embodiment. The data transfer state monitoring unit 1201 has a real-time flag (not shown) indicating whether or not a period for which real-time processing is necessary, and the CPU 101 can know this by reading a predetermined register.

  The transfer state monitoring unit 1201 first initializes the real-time flag to “0”. The transfer state monitoring unit 1201 refers to a signal indicating the start of data transfer of the printer unit 171 and, when detecting the start of data transfer, sets the real-time flag to “1”. Then, the transfer state monitoring unit 1201 receives a write notification signal for the final data of the page to the short buffer 1004 from the ring buffer read control unit 1003, and resets the real-time flag to “0” by writing the final data of the page. In this way, the transfer state monitoring unit 1201 controls the real-time flag, so that the real-time flag becomes “1” only during a period in which real-time processing is necessary.

  FIG. 13 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the third embodiment. In order to monitor the bus bandwidth acquired by the bandwidth monitor 150, the processing is repeated at regular time intervals. Executed. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152. Note that the initialization control related to the bus bandwidth control processing after the power is turned on is the same as the flowchart according to the first embodiment of FIG. Control executed when a job is started by an instruction from the operation unit 105 is the same as the flowchart according to the first embodiment in FIG. Furthermore, the control executed when a certain image process is ended by a process end interrupt or the like from each of the image processing units 111 to 115 is the same as the flowchart according to the first embodiment of FIG.

  Next, in order to monitor the bus bandwidth calculated by the bandwidth monitor 150, control executed repeatedly at regular time intervals will be described with reference to the flowchart of FIG. In the figure, the difference from the second embodiment is that the processes of S1303 and S1304 are added.

  In step S <b> 1301, the CPU 101 acquires a bus bandwidth value from the bandwidth monitor 150. In step S1302, the CPU 101 compares the bus bandwidth value with the first threshold value. If the bus bandwidth value exceeds the first threshold value, that is, if access restriction of the bus master may be necessary, the process proceeds to S1303. If not, the process ends. Here, as described above, the first threshold value is a value of the memory bandwidth or a value slightly smaller than the value.

  In step S <b> 1303, the CPU 101 acquires the contents of the real time flag from the data transfer state monitoring unit 1201. In step S1304, the CPU 101 determines whether the content of the real-time flag is “1”. If the content of the real-time flag is “1”, that is, if real-time processing is required, the process proceeds to S1305. If not, the process flow ends.

  In step S <b> 1305, the CPU 101 acquires the remaining data amount stored in the short buffer 1004. In step S1306, the CPU 101 compares the residual data amount with the second threshold value. If the remaining data amount is below the second threshold value, that is, if access restriction of the bus master is necessary, the process proceeds to S1307. Otherwise, the process flow ends. The process of monitoring the bus bandwidth is repeatedly executed at regular time intervals, but data to the printer unit 171 must not be removed from the short buffer 1004 between the monitoring processes. From this time interval and the data transfer rate of the printer unit 171, the amount of data read from the short buffer 1004 can be known between the monitoring processes. The threshold value here may be a value such that the data amount of the short buffer 1004 is equal to or larger than the read data amount. In step S1307, the CPU 101 performs processing for restricting access by a bus master having a low priority, and this processing is the same as the processing in FIG. 8B.

  As described above, according to the third embodiment, even if the value of the bus bandwidth from the bandwidth monitor exceeds the threshold, if the real time property is not required in the print processing, the bus master access restriction is performed. Is not done. Further, even if the real time property is required in the print processing, the bus master access is not restricted unless the residual data amount in the buffer buffer falls below the threshold value. As a result, useless bus master access restrictions are suppressed, so that performance degradation of the image processing apparatus can be suppressed. Further, when performing bus master access restriction, the bus master for which access restriction is performed is determined with reference to the bus master management table. As a result, the bus master with the lowest priority can be selected from the bus masters that are in operation and are not subject to access restrictions. The first threshold value and the second threshold value in the third embodiment may be the same as the first threshold value and the second threshold value in the first embodiment described above, or may be different from each other.

[Embodiment 4]
FIG. 14 is a block diagram illustrating a configuration of an image processing apparatus according to the fourth embodiment of the present invention. The difference between the image processing apparatus according to the fourth embodiment and the configuration of the image processing apparatus according to the first or second embodiment is that both the scanner unit 161 and the printer unit 171 exist. Here, parts common to the configuration of the image processing apparatus according to Embodiments 1 to 3 described above are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 15 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the fourth embodiment. In order to monitor the bus bandwidth acquired by the bandwidth monitor 150, the processing is repeated at regular time intervals. Executed. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152. Note that the initialization control related to the bus bandwidth control processing after power-on is the same as the flowchart of FIG. Control executed when a job is started by an instruction from the operation unit 105 is the same as the flowchart of FIG. Furthermore, the control executed when a certain image processing is ended by a processing end interrupt or the like from each of the image processing units 111 to 115 is the same as the flowchart of FIG.

  Next, a control flow that is repeatedly executed at regular time intervals in order to monitor the bus bandwidth calculated by the bandwidth monitor 150 will be described with reference to the flowchart of FIG. In the same figure, S1503 to S1506 are processes different from those of the first and second embodiments.

  In step S <b> 1501, the CPU 101 acquires a bus bandwidth value from the bandwidth monitor 150. In step S1502, the CPU 101 compares the acquired bus bandwidth value with the first threshold value. If the bus bandwidth value exceeds the first threshold value, that is, if access restriction of the bus master may be necessary, the process proceeds to S1503, and if not, this processing flow ends. Here, as described above, the first threshold value is a value of the memory bandwidth or a value slightly smaller than the value.

  In step S <b> 1503, the CPU 101 acquires the residual data amount stored in the short buffer 302 of the scan processing unit 160. In step S1504, the CPU 101 compares the residual data amount with the second threshold value. If the remaining data amount exceeds the second threshold, that is, if access restriction of the bus master is necessary, the process proceeds to S1507, and the bus master access restriction process is performed. If not, go to the next step.

  If the residual data amount does not exceed the second threshold value in S1504, the process advances to S1505, and the CPU 101 acquires the residual data amount stored in the short buffer 1004 of the print processing unit 170. In step S1506, the CPU 101 compares the residual data amount with the third threshold value. If the remaining data amount is below the third threshold, that is, if access restriction of the bus master is necessary, the process proceeds to S1507, and if not, this process is terminated. In step S <b> 1507, the CPU 101 performs processing for restricting access of a bus master having a low priority, and this processing is the same as the processing described with reference to FIG. 8B.

  Here, the first and second threshold values may be the same as or different from the first and second threshold values in the above-described embodiment. Further, the third threshold value may be the same as or different from the first and second threshold values in the above-described embodiment.

  As described above, according to the fourth embodiment, even if the bus bandwidth value from the bandwidth monitor exceeds the threshold value, the residual data amount of the short buffer of the scan processing unit does not exceed the threshold value, and the print If the remaining data amount in the short buffer of the processing unit does not fall below the threshold value, the bus master access is not restricted. As a result, useless bus master access restrictions are suppressed, and performance degradation of the image processing apparatus is suppressed.

  When performing bus master access restriction, the bus master subject to access restriction is determined with reference to the bus master management table. As a result, the bus master with the lowest priority among the bus masters that are in operation and are not subject to access restrictions can be selected as the band master subject to bandwidth restriction.

[Embodiment 5]
Next, a fifth embodiment of the present invention will be described. Since the configuration of the image processing apparatus according to the fifth embodiment is the same as the configuration of the image processing apparatus according to the second embodiment, the description thereof is omitted.

  FIG. 16 is a block diagram illustrating the configuration of the print processing unit 170 in the image processing apparatus according to the fifth embodiment. In FIG. 16, parts common to the configuration of the print processing unit 170 according to the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The print processing unit 170 includes a ring buffer monitor 1601 that monitors the amount of data stored in the ring buffer area. The amount of data stored in the ring buffer area can be calculated from the write pointer and read pointer values of the ring buffer write control unit 1002 and the ring buffer read control unit 1003. The calculated value is assigned to the register, and the CPU 101 can read the register to know the data amount stored in the ring buffer area.

  In the image processing apparatus according to the fifth embodiment, the initialization control related to the bus bandwidth control process after power-on is the same as the flowchart of FIG. Control executed when a job is started by an instruction from the operation unit 105 is the same as the flowchart of FIG. Furthermore, the control executed when a certain image processing is ended by a processing end interrupt or the like from each of the image processing units 111 to 115 is the same as the flowchart of FIG.

  FIG. 17 is a flowchart for describing processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the fifth embodiment. The processing is repeated at regular time intervals to monitor the bus bandwidth acquired by the bandwidth monitor 150. Executed. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152.

  In step S <b> 1701, the CPU 101 acquires a bus bandwidth value from the bandwidth monitor 150. In step S1702, the CPU 101 compares the bus bandwidth value acquired in step S1701 with the first threshold value. If the bus bandwidth value exceeds the first threshold value, that is, if access restriction of the bus master may be necessary, the process proceeds to S1703. If not, the process ends. Here, as described above, the first threshold value is a value of the memory bandwidth or a value slightly smaller than the value.

  In step S <b> 1703, the CPU 101 acquires the remaining data amount stored in the ring buffer area from the ring buffer monitor 1601. In step S1704, the CPU 101 compares the residual data amount with the second threshold value. If the remaining data amount exceeds the second threshold value, that is, if sufficient data is stored in the ring buffer area, the process proceeds to S1705, and if not, the process proceeds to S1706, and the flowchart of FIG. The process indicated by is executed.

In step S1705, the CPU 101 restricts write access to the ring buffer area. This write access restriction can be realized by providing a register for instructing access restriction to the ring buffer write control unit 1002, and the ring buffer write control unit 1002 instructed to restrict access widens the write access interval. Further, access restriction may be performed by controlling the arbitration priority for the write on the bus 144 of the memory controller 151.
In step S806, the CPU 101 performs a process of restricting access of a bus master having a low priority, and this process is performed in a short-circuit from step S8061 to step S8067 in FIG.

  As described above, according to the fifth embodiment, when the value of the bus bandwidth detected by the bandwidth monitor 150 exceeds the threshold, if the remaining data amount in the ring buffer area exceeds the threshold, the access restriction of the bus master is Not done. Instead, by restricting write access to the ring buffer area, the value of the bus bandwidth is lowered, but the speed of non-real-time processing is not lowered. As a result, useless access restrictions of the bus master are suppressed, and performance degradation of the image processing apparatus is suppressed. Further, when performing bus master access restriction, the bus master for which access restriction is performed is determined with reference to the bus master management table. As a result, the bus master having the lowest priority among the bus masters that are in operation and are not subject to access restrictions can be determined as the access restriction target bus master. Note that the first threshold value and the second threshold value in the fifth embodiment may be the same as the first threshold value and the second threshold value in the above-described embodiment, or may be different from each other.

[Embodiment 6]
FIG. 18 is a block diagram illustrating the configuration of the print processing unit 170 in the image processing apparatus according to the sixth embodiment. 18, parts common to the configuration of the print processing unit 170 of FIG. 16 according to the above-described fifth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the image processing apparatus according to the above-described embodiment, the ring buffer area is empty (the amount of stored data is zero) at the start of the printing operation. If the printing operation is not performed, that is, if the real-time processing is not performed, naturally the bus master should not be restricted. However, as is apparent from the flowchart of FIG. 17, if the bus bandwidth value of the bandwidth monitor 150 exceeds the threshold value, if the printing operation is not performed, the process branches to S1704, and the bus master access restriction process is executed. Will be. The image processing apparatus according to the sixth embodiment solves such a problem.

  After the ring buffer area is filled with the image data from the print image processing unit 1001, data transfer to the printer unit 171 is started. This is to prevent the data transfer from being interrupted immediately after the start of the data transfer. That is, the remaining data amount in the ring buffer area is not considered until data transfer to the printer unit 171 is started. During the data transfer to the printer unit 171, after the last image data of the page, that is, the final data of the data transfer to the printer unit 171 is written in the ring buffer area, the residual data amount in the ring buffer area becomes zero. It decreases toward. However, in this case, the data transfer to the printer unit 171 is not interrupted by the decrease in the remaining data amount in the ring buffer area. In FIG. 18, a data transfer state monitoring unit 1801 is added to the configuration of the print processing unit 170 of FIG.

  The print processing unit 170 includes a ring buffer monitor 1601 that monitors the amount of data stored in the ring buffer area. The amount of data stored in the ring buffer area can be calculated from the write pointer and read pointer values of the ring buffer write control unit 1002 and the ring buffer read control unit 1003. The calculated value is assigned to a register, and the CPU 101 can read the register to know the amount of data stored in the ring buffer. The print processing unit 170 further includes a data transfer state monitoring unit 1801 that monitors the data transfer state of the printer unit 171. The data transfer state monitoring unit 1801 has a real-time flag (not shown) indicating whether or not it is a period that requires real-time processing, and the CPU 101 can know the value of the flag by reading a predetermined register. it can.

  The transfer state monitoring unit 1801 first initializes the real-time flag to “0”. The transfer state monitoring unit 1801 refers to a signal indicating the start of data transfer of the printer unit 171 and, when detecting the start of data transfer, sets the real time flag to “1”. The transfer state monitoring unit 1801 receives a notification signal for writing the final data of the page to the ring buffer from the ring buffer write control unit 1002, and returns the real-time flag to “0” when the final data of the page is written. The transfer state monitoring unit 1801 controls the real-time flag in this way, so that the real-time flag becomes “1” only during a period in which real-time processing is necessary.

  FIG. 19 is a flowchart for explaining processing for determining whether or not bandwidth control processing is necessary in the image processing apparatus according to the sixth embodiment. In order to monitor the bus bandwidth acquired by the bandwidth monitor 150, the processing is repeated at regular time intervals. Executed. Note that the processing shown in this flowchart is executed by the CPU 101 executing a program developed from the ROM 103 to the main memory 152.

  In the image processing apparatus according to the sixth embodiment, the initialization control related to the bus bandwidth control process after power-on is the same as the flowchart of FIG. Control executed when a job is started by an instruction from the operation unit 105 is the same as the flowchart of FIG. Furthermore, the control executed when a certain image processing is ended by a processing end interrupt or the like from each of the image processing units 111 to 115 is the same as the flowchart of FIG.

  First, in step S1901, the CPU 101 acquires a bus bandwidth value from the bandwidth monitor 150. In step S1902, the CPU 101 compares the acquired bus bandwidth value with the first threshold value. If the bus bandwidth value exceeds the first threshold value, that is, if access restriction of the bus master may be necessary, the process proceeds to S1903. If not, the process ends. Here, as described above, the first threshold value is a value of the memory bandwidth or a value slightly smaller than the value.

  In step S <b> 1903, the CPU 101 acquires the contents of the real time flag from the data transfer state monitoring unit 1801. The process advances to step S1904, and the CPU 101 determines whether or not the real time flag is “1”. If the real-time flag is “1”, it means that real-time processing is necessary, so that the process proceeds to S1905. If not, the process ends.

  In step S1905, the CPU 101 acquires the remaining data amount stored in the ring buffer area from the ring buffer monitor 1607. In step S1906, the CPU 101 compares the remaining data amount with the second threshold value. If the remaining data amount is below the second threshold, that is, if access restriction of the bus master is necessary, the process proceeds to S1907, and if not, the process proceeds to S1908. In step S1907, the CPU 101 restricts write access to the ring buffer area. This write access restriction can be realized by providing a register for instructing access restriction to the ring buffer write control unit 1002, and the ring buffer write control unit 1002 instructed to restrict access widens the write access interval. Further, access restriction may be performed by controlling the arbitration priority for the write on the bus 144 of the memory controller 151. On the other hand, in step S1908, the CPU 101 performs processing for restricting access of a bus master having a low priority. This process is as described with reference to the flowchart of FIG.

  As described above, according to the sixth embodiment, even if the value of the bus bandwidth detected by the bandwidth monitor exceeds the threshold value, the bus master access is restricted if the real-time property is not required in the print processing. I will not. Further, if the real time property is required in the print processing, the bus master access is not restricted unless the remaining data amount in the ring buffer area falls below the threshold value. As a result, useless access restrictions of the bus master are suppressed, and performance degradation of the image processing apparatus is suppressed.

  Further, when performing bus master access restriction, the bus master for which access restriction is performed is determined with reference to the bus master management table. As a result, the bus master having the lowest priority among the bus masters that are in operation and are not subject to access restrictions can be selected as the bus master to be restricted.

  In the above-described embodiment, each embodiment has been described independently. However, the configuration of each embodiment may be appropriately combined. For example, the real-time flag according to the third embodiment may be applied to the scan processing unit 160 according to the first embodiment, or the scan processing unit 160 and the print processing unit 170 according to the fourth embodiment. Note that the first threshold value and the second threshold value in the sixth embodiment may be the same as the first threshold value and the second threshold value in the above-described embodiment, or may be different from each other.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to make the scope of the present invention public, the following claims are attached.

  DESCRIPTION OF SYMBOLS 101 ... CPU, 105 ... Operation part, 130 ... Bus arbitration part, 150 ... Bandwidth monitor, 152 ... Main memory, 160 ... Scan processing part, 161 ... Scanner part, 170 ... Print processing part, 171 ... Printer part, 302,1004 ... Short buffer, 303, 1005 ... Short buffer monitor

Claims (14)

An image processing apparatus having a plurality of bus masters accessing a main memory,
Band monitoring means for detecting access to the main memory by the plurality of bus masters and acquiring a bus band;
An acquisition means for acquiring a data amount of a buffer provided between the bus master and the main memory for which real-time processing is required;
The bus bandwidth acquired by the bandwidth monitoring unit exceeds the first threshold value, and the highest priority is selected from the plurality of bus masters according to the comparison between the buffer buffer data amount acquired by the acquisition unit and the second threshold value. Control means for controlling to limit access to the main memory by a bus master having a lower rank;
An image processing apparatus comprising: The bus master that requires real-time processing is a bus master that processes data from the scanner,
When the bus bandwidth acquired by the bandwidth monitoring unit exceeds a first threshold and the data amount of the buffer buffer acquired by the acquiring unit is larger than the second threshold, the control unit is configured to output the plurality of bus masters. The image processing apparatus according to claim 1, wherein access to the main memory by a bus master having the lowest priority is restricted. The bus master that requires real-time processing is a bus master that processes data to be output to a printer,
When the bus bandwidth acquired by the bandwidth monitoring unit exceeds a first threshold value and the data amount of the buffer buffer acquired by the acquisition unit is smaller than the second threshold value, the control unit is configured to output the plurality of bus masters. The image processing apparatus according to claim 1, wherein access to the main memory by a bus master having the lowest priority is restricted. It further has setting means for setting information indicating whether or not the real-time processing is necessary.
The image processing apparatus according to claim 3, wherein the control unit executes the control when the information indicates a period in which the real-time processing is necessary. Storage means for storing data to be output to the printer;
The setting means sets the information to information indicating a period in which the real-time processing is necessary from the start of data transfer from the storage means to the printer until the last data is written to the storage means. The image processing apparatus according to claim 4. The storage means comprises a ring buffer;
A write control unit that controls writing of data to the ring buffer; and a read control unit that controls reading of data from the ring buffer;
The write control means has a write pointer indicating a write position when writing data to the ring buffer, and the read control means has a read pointer indicating a position for reading data from the ring buffer, and the write control 6. The means according to claim 5, wherein said means and said read control means are controlled so that said read pointer follows said write pointer, and said write pointer is controlled so as not to overtake said read pointer. Image processing device. An image processing apparatus having a plurality of bus masters accessing a main memory,
Band monitoring means for detecting access to the main memory by the plurality of bus masters and acquiring a bus band;
Storage means for storing data for the real-time processing by a bus master that requires real-time processing;
Obtaining means for obtaining the amount of data stored in the storage means;
The bus bandwidth acquired by the bandwidth monitoring unit exceeds a first threshold, and the lowest priority among the plurality of bus masters according to a comparison between the data amount acquired by the acquisition unit and a second threshold. Control to restrict access to the main memory by the bus master,
Control means for controlling to limit writing of data to the storage means when the amount of data acquired by the acquisition means is greater than the second threshold;
An image processing apparatus comprising: The bus master that requires real-time processing is a bus master that processes data to be output to a printer,
When the bus bandwidth acquired by the bandwidth monitoring unit exceeds a first threshold and the amount of data acquired by the acquisition unit is equal to or smaller than the second threshold, the control unit The image processing apparatus according to claim 7, wherein access to the main memory by a bus master having the lowest priority among the bus masters is restricted. It further has setting means for setting information indicating whether or not the real-time processing is necessary.
The image processing apparatus according to claim 8, wherein the control unit executes the control when the information indicates a period in which the real-time processing is necessary.   The setting means sets the information to information indicating a period in which the real-time processing is necessary from the start of data transfer from the storage means to the printer until the last data is written to the storage means. The image processing apparatus according to claim 9, wherein the apparatus is an image processing apparatus. The storage means comprises a ring buffer;
A write control unit that controls writing of data to the ring buffer; and a read control unit that controls reading of data from the ring buffer;
The write control means has a write pointer indicating a write position when writing data to the ring buffer, and the read control means has a read pointer indicating a position for reading data from the ring buffer, and the write control 11. The means and the read control means are controlled so that the read pointer follows the write pointer, and is controlled so that the write pointer does not overtake the read pointer. The image processing apparatus according to any one of the above. A control method for controlling an image processing apparatus having a plurality of bus masters accessing a main memory,
A bandwidth monitoring step of detecting access to the main memory by the plurality of bus masters to acquire a bus bandwidth;
An acquisition step of acquiring a data amount of a buffer provided between the bus master and the main memory for which real-time processing is required;
The bus bandwidth acquired in the bandwidth monitoring step exceeds a first threshold value, and the highest priority is selected from the plurality of bus masters according to the comparison between the buffer buffer data amount acquired in the acquisition step and the second threshold value. A control step for controlling access to the main memory by a bus master having a lower rank;
A control method characterized by comprising: A control method for controlling an image processing apparatus having a plurality of bus masters accessing a main memory,
A bandwidth monitoring step of detecting access to the main memory by the plurality of bus masters to acquire a bus bandwidth;
A bus master for which real-time processing is required, a storage step of storing data for the real-time processing in a memory;
An acquisition step of acquiring the amount of data stored in the memory;
The bus bandwidth acquired in the bandwidth monitoring step exceeds a first threshold, and the lowest priority among the plurality of bus masters according to the comparison between the data amount acquired in the acquisition step and a second threshold. Control to restrict access to the main memory by the bus master,
A control step of controlling to limit writing of data to the memory when the amount of data acquired in the acquisition step is larger than the second threshold;
A control method characterized by comprising:   The program for functioning a computer as each means of the image processing apparatus of any one of Claims 1 thru | or 11.

Images