JP2019161337A - Capacitive load bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the charging time and improve the filter characteristics of a capacitor constituting a filter connected to a capacitive load. SOLUTION: A bootstrap circuit 52 provided between a gate of a semiconductor element 2 for a switch and an output stage of a voltage output circuit 50 is connected in series in a diode-connected state using a MOS transistor. It has semiconductor elements 3a and 3b for switch control. One end corresponding to the anode of the diode in the series connection row is connected to the output stage of the voltage output circuit 50, while the other end is connected to the gate of the switch semiconductor element 2. When a capacitive load is connected to the connection point between the switch semiconductor element 2 and the capacitor 4, the gate voltage of the switch semiconductor element 2 is temporarily increased to increase the conduction time of the switch semiconductor element 2. It is possible to shorten the charging time of 4. [Selection diagram] Fig. 1

Description

  The present invention relates to a capacitive load bias circuit for supplying a bias voltage to a capacitive load such as a MEMS microphone or a touch panel, and more particularly to an improvement in output characteristics.

  As a conventional capacitive load bias circuit, for example, one having a configuration as shown in FIG. 6 is well known (see, for example, Patent Document 1).

The conventional circuit will be described below with reference to FIG.
This capacitive load bias circuit generates a desired bias voltage and outputs it between a voltage output circuit (indicated as “V-GEN” in FIG. 6) 50A and the output stage of this voltage output circuit 50A and the ground. The ESD protection element 1A is provided with a low-pass filter 51A provided between the voltage output circuit 50A and the output terminal 22A.

  In such a conventional circuit, noise included in the output voltage of the voltage output circuit 50A is caused by the OFF resistances and capacitors (referred to as “D2” and “D3” in FIG. 6) 31a and 31b, respectively. This is removed by a low pass filter 51A having a cutoff frequency determined by 32).

Japanese Patent No. 5970241

However, in the above-described conventional circuit, the voltage output circuit 50A operates after the power is turned on and charging of the capacitor 32 is started. However, since the OFF resistances of the diodes 31a and 31b are increased, it takes time until the voltage is stabilized. There was a problem that it took.
For this reason, when this circuit is used to supply a bias voltage for the MEMS microphone, the sensitivity of the MEMS microphone gradually increases after power-on, and there is a problem that the rise characteristic becomes slow.

  Further, when the voltage output circuit 50A is configured by using a circuit that has an output voltage nearly 10 times the power supply voltage, such as a charge pump circuit, it is easily provided between a load such as a MEMS microphone and the output terminal 22A. There was a problem that the switch could not be provided.

  The present invention has been made in view of the above circumstances, and provides a capacitive load bias circuit that shortens the charging time of a capacitor constituting a filter circuit connected to a capacitive load and improves filter characteristics. is there.

In order to achieve the above object of the present invention, a capacitive load bias circuit according to the present invention comprises:
A voltage output circuit that generates and outputs a desired bias voltage, an overvoltage protection element connected between the output stage of the voltage output circuit and the ground, and a low-pass filter connected to the output stage of the voltage output circuit Have
The low-pass filter includes a switch semiconductor element using a MOS transistor and a capacitor.
The switch semiconductor element is provided in a forward direction with respect to the output voltage of the voltage output circuit in a diode connection state, and the capacitor is provided between a terminal on the output side of the voltage output circuit and the ground. On the other hand, a switch signal can be applied to the gate of the switch semiconductor element from the outside, and a bootstrap circuit is provided between the gate and the output stage of the voltage output circuit,
In the bootstrap circuit, a plurality of switch control semiconductor elements using MOS transistors are in a diode-connected state and connected in series, and an end corresponding to the anode of the diode of the series-connected switch control semiconductor element array is One end of the voltage output circuit is connected to the output stage, and the other end is connected to the gate of the switch semiconductor element.
When a capacitive load is connected to a connection point between the switch semiconductor element and the capacitor, the bootstrap circuit temporarily raises the gate voltage of the switch semiconductor element so that the switch semiconductor switch becomes conductive. The time can be increased.

According to the present invention, the capacitor constituting the low-pass filter can be reliably charged in a short time by the switch semiconductor element, and the filter characteristics can be improved.
In addition, by providing a plurality of low-pass filters composed of switch semiconductor elements and capacitors connected in cascade, the order of the filters can be increased, and noise can be further reduced.
Furthermore, by providing a diode in antiparallel with the switching semiconductor element, it is possible to further improve the ESD resistance, and it is possible to reliably suppress and prevent the destruction of the switching semiconductor element.

It is a circuit diagram which shows the 1st circuit structural example of the capacitive load bias circuit in embodiment of this invention. It is a circuit diagram which shows the 2nd circuit structural example of the capacitive load bias circuit in embodiment of this invention. It is a circuit diagram which shows the 3rd circuit structural example of the capacitive load bias circuit in embodiment of this invention. It is a circuit diagram which shows the 4th circuit structural example of the capacitive load bias circuit in embodiment of this invention. It is a circuit diagram which shows the 5th circuit structural example of the capacitive load bias circuit in embodiment of this invention. It is a circuit diagram which shows the circuit structural example of a conventional circuit.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first circuit configuration example will be described with reference to FIG.
The capacitive load bias circuit generates a desired bias voltage and outputs it between a voltage output circuit (indicated as “V-GEN” in FIG. 1) 50 and an output stage of the voltage output circuit 50 and the ground. An ESD protection element (overvoltage protection element) 1 provided, a low-pass filter 51 provided between the voltage output circuit 50 and the output terminal 22, and a bootstrap circuit 52 are broadly configured. is there.

The voltage output circuit 50 generates and outputs a desired voltage as a bias voltage, and basically has a configuration similar to that of the prior art.
Specifically, the voltage output circuit 50 is configured using, for example, a charge pump circuit, and can generate and output a high desired voltage based on the power supply voltage.

The ESD protection element 1 is provided in series between the output stage of the voltage output circuit 50 and the ground. The ESD protection element 1 is for protecting the voltage output circuit 50 from an overvoltage caused by electrostatic discharge generated at the output terminal 22, and is basically the same as the conventional one.
The ESD protection element 1 is in a conductive state when an overvoltage due to electrostatic discharge occurs at the output terminal 22, and protects the voltage output circuit 50 by releasing the current generated by the overvoltage to the ground.

The low pass filter 51 includes a switch semiconductor element (indicated as “M1” in FIG. 1) 2 and a filter capacitor (indicated as “C1” in FIG. 1) 4.
In the embodiment of the present invention, an N-channel MOS FET (hereinafter referred to as “NMOS”) is used as the switching semiconductor element 2.

The switching semiconductor element 2 has a drain connected to the output terminal 22, a back gate and a source connected to each other, and is connected to an output stage of the voltage output circuit 50. Thus, the switch semiconductor element 2 is provided in a diode connection state.
In the embodiment of the present invention, when the switch semiconductor element 2 is turned on by an external switch signal SW, the gate voltage of the switch semiconductor element 2 is raised by the bootstrap circuit 52 to shorten the filter capacitor 4. Charging in time is possible (details will be described later). On the other hand, when the charging is completed, the switch semiconductor element 2 is quickly turned off, so that the filter capacitor 4 and a good filter can be formed in a high resistance state (details will be described later).

The boot slap circuit 52 includes first and second switch control semiconductor elements (indicated as “M2” and “M3” in FIG. 1) 3a and 3b, respectively.
In the embodiment of the present invention, NMOSs are used as the first and second switch control semiconductor elements 3a and 3b, respectively.

Thus, the drain and gate of the first switch control semiconductor element 3a are connected to each other, and the gate of the switch semiconductor element 2 and the DC cut capacitor (denoted as “C2” in FIG. 1) 5 are provided. Connected to one end.
The other end of the DC cut capacitor 5 is connected to the switch signal input terminal 21.

  The source of the first switch control semiconductor element 3a is connected to the drain of the second switch control semiconductor element 3b, and the back gate together with the back gate of the second switch control semiconductor element 3b. The source of the element 2 is connected.

The gate and drain of the second switch control semiconductor element 3b are connected to each other, and the source of the first switch control semiconductor element 3a is connected to the connection point as described above. .
The source of the second switch control semiconductor element 3 b is connected to the source of the first switch semiconductor element 2.

As described above, the first and second switch control semiconductor elements 3a and 3b are respectively connected in series between the gate and the source of the switch semiconductor element 2 in a diode connection state.
In the embodiment of the present invention, the drain of one end of the first and second switch control semiconductor elements 3 a and 3 b connected in series is connected to the gate of the switch semiconductor element 2 via the DC cut capacitor 5. The switch signal input terminal 21 is connected.
The source of the other end of the first and second switch control semiconductor elements 3 a and 3 b connected in series is connected to the source of the switch semiconductor element 2.

  In the embodiment of the present invention, two NMOSs are provided in series as the first and second switch control semiconductor elements 3a and 3b, but the number of switch control semiconductor elements connected in series is the same. It is not necessary to be limited to two, and any number of three or more switch control semiconductor elements may be connected in series.

Next, the operation in this configuration will be described.
First, when the switch signal input terminal 21 is at a voltage level corresponding to the logic value Low and the voltage output circuit 50 is turned on, the voltage output circuit immediately after turning on the power is connected to the gate of the switch semiconductor element 2. Since the output voltage V0 of 50 is supplied via the drain / back gate of the first and second switch control semiconductor elements 3a and 3b in the diode connection state, the voltage becomes V0-VF. Here, VF is the ON voltage of the NMOS in the diode connection state.
The BIAS voltage output to the output terminal 22 is supplied via the back gate of the switching semiconductor element 2 and thus becomes V0−VF.

Next, when a voltage level corresponding to the logical value High, for example, a VDD switch signal is applied to the switch signal input terminal 21, the gate voltage of the switching semiconductor element 2 rises to V0-VF + VDD.
However, the first and second switch control semiconductor elements 3a and 3b in the diode connection state are provided in the opposite directions with respect to this switch signal. Therefore, the upper limit of the gate voltage of the switching semiconductor element 2 is limited to V0 + (Vth × N). Here, Vth is the threshold voltage of the MOS FET, and N is the number of switch control semiconductor elements connected in series. In the embodiment of the present invention, N = 2.

Therefore, when the switch signal becomes a voltage corresponding to the logical value High, the gate voltage of the semiconductor element 2 for switching rises, but it cannot be avoided that it decreases with time, so the gate voltage is lowered and the ON state is maintained. become unable.
In the embodiment of the present invention, as described above, the gate voltage of the switching semiconductor element 2 is temporarily set by the first and second switch controlling semiconductor elements 3a and 3b connected in series as compared with the prior art. Therefore, the ON time of the switch semiconductor element 2 can be increased, and the ON state can be maintained for a longer time.

  The first and second switch control semiconductor elements 3a and 3b are connected in series in a diode connection state, but since the back gates are common, the diodes that are opposite to the polarity of the switch signal are: There is only one between the drain and the back gate. Therefore, the initial gate voltage of the switching semiconductor element 2 can be maintained at a high voltage of V0-VF.

Next, a second configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
The second configuration example includes a plurality of low-pass filters 51-1 to 51-n having the same configuration as the low-pass filter 51 including the switch semiconductor element 2 and the filter capacitor 4 shown in the first configuration example. Are provided in cascade connection between the output stage of the voltage output circuit 50 and the output terminal 22. In the second configuration example, n low-pass filters 51-1 to 51-n are provided.

  Each of the first to n-th switching semiconductor elements (indicated as “M1-1” to “M1-n” in FIG. 2) 2-1 to 2-n has a back gate and a source connected to each other. Thus, they are connected in series in a diode connection state.

  The source of the first switch semiconductor element 2-1 that is one end of the series connection row of the first to n-th switch semiconductor switches 2-1 to 2-n connected in series is the voltage output circuit 50. The drain of the n-th switching semiconductor element 2-n, which is the other end of the series connection row, is connected to the output terminal 22.

  The switch semiconductor element located between the first switch semiconductor element 2-1 and the nth switch semiconductor element 2-n has a source and a back gate on the output stage side of the voltage output circuit 50, and an output terminal 22 The drains are respectively connected in series between the first switch semiconductor element 2-1 and the n-th switch semiconductor element 2-n so that the drains are located on the side.

The gates of the first to nth switch semiconductor elements 2-1 to 2-n are connected to the drain of the first switch control semiconductor element 3a.
The first to nth filter capacitors 4-1 to 4-n are connected between the drains of the corresponding first to nth switch semiconductor elements 2-1 to 2-n and the ground, respectively. ing.

  The operation in this configuration is basically the same as that of the first configuration example shown in FIG. 1, but the order of the filter is reduced by the first to nth low-pass filters 51-1 to 51-n connected in series. Therefore, noise can be further reduced.

Next, a third configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 or FIG. 2 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This third configuration example is provided with a protective diode 6 (denoted as “D1” in FIG. 3) 6 connected in reverse parallel to the switching semiconductor element 2.

That is, the anode of the protective diode 6 is connected to the drain of the switching semiconductor element 2, while the cathode is connected to the source of the switching semiconductor element 2.
By providing such a protective diode 6, ESD tolerance can be increased, and circuit protection in the inflow direction of the current flowing from the output terminal 22 can be enhanced.

  Further, it is possible to prevent a high voltage from being applied to both ends of the switch semiconductor element 2. That is, when the supply of the power supply voltage is stopped, the charge at the output terminal 22 is leaked from the voltage output circuit 50 side because there is no leakage path, but the switching semiconductor element 2 is in the OFF state, and its drain / source There may be a voltage remaining in the capacitor of the voltage output circuit 50 between them. When the desired bias voltage is a high voltage as in the MEMS microphone, there is a risk of destruction unless the switching semiconductor element 2 has a high breakdown voltage characteristic. The breakdown can be prevented without using the switch semiconductor element 2 having a high drain-source breakdown voltage.

Next, a fourth configuration example will be described with reference to FIG.
The same components as those shown in any of FIGS. 1, 2, and 3 are denoted by the same reference numerals, and detailed description thereof is omitted. Hereinafter, the different points will be mainly described. explain.
The fourth configuration example is different from the first configuration example in that a PMOS (P-channel MOS FET) is used instead of the NMOS in the first configuration example, and only the type of semiconductor element is different. This is the same as the configuration example 1.

Hereinafter, a specific circuit configuration will be described focusing on differences from FIG.
A switching semiconductor element (indicated as “M4” in FIG. 4) 2A using PMOS corresponds to the switching semiconductor element 2 in FIG.
Similarly, the first switch control semiconductor element (referred to as “M5” in FIG. 4) 7a using PMOS is a second switch using PMOS as the first switch control semiconductor element 3a in FIG. The control semiconductor element (indicated as “M6” in FIG. 4) 7b corresponds to the second switch control semiconductor element 3b in FIG.
Since the circuit operation in such a configuration is basically the same as that of the first configuration example, detailed description thereof is omitted here.

Next, a fifth configuration example will be described with reference to FIG.
The same components as those shown in any of FIGS. 1, 2, 3, and 4 are denoted by the same reference numerals, and detailed description thereof is omitted. The explanation will be focused on.
In the fifth configuration example, the bootstrap circuit 52 and the multistage low-pass filter 53 are used as a set of filter circuit blocks 41, and a plurality of filter circuit blocks 41, that is, in the configuration example shown in FIG. The filter circuit blocks 41-1 to 41-n are connected in cascade.

First, the multistage low-pass filter 53 is configured by cascading two low-pass filters 51-1 and 51-2.
The cascade connection of the two low-pass filters 51-1 and 51-2 is a configuration in which n = 2 in the cascade connection of the low-pass filters 51-1 to 51-n in the second configuration example shown in FIG. Is the same.

Switch signals SW1 to SWn are separately input to the filter circuit blocks 41-1 to 41-n, respectively.
These switch signals SW1 to SWn may be simultaneously at a voltage level corresponding to the logical value High, or may be any voltage level corresponding to the logical value High individually.

  In the case of the second configuration example, as described above, in the switching semiconductor element 2-n of the final-stage filter 51-1, the gate voltage is V0-VF, whereas the source voltage Becomes V0-nVF. Therefore, the withstand voltage required for the switching semiconductor element 2-n increases as the number of connection stages of the low-pass filter 51 increases.

  On the other hand, in the case of the fifth configuration example, the source voltage of the switching semiconductor element 2-2 of the multistage low-pass filter 53 is V0-2 × regardless of the number of stages of the filter circuit blocks 41-1 to 41-n. Since it is VF, it becomes possible to use the switching semiconductor element 2-2 having a lower withstand voltage than the second configuration example.

In the case of this fifth configuration example, it is possible to charge the filter capacitors 4-1 and 4-2 quickly compared to the case where the number of low-pass filters 51-1 to 51-n is large in the second configuration example. Become.
The basic circuit operation of the fifth configuration example is the same as that of the first configuration example, and thus detailed description thereof is omitted here.

  In the embodiment of the present invention, the description has been made on the assumption that the MEMS microphone is used as the load. However, the load of the capacitive load bias circuit according to the present invention is not limited to the MEMS microphone. Is applicable.

  The present invention can be applied to a capacitive load bias circuit in which it is desired to shorten the charging time of the capacitor constituting the filter circuit connected to the capacitive load and to improve the filter characteristics.

2. Switch semiconductor element 3a ... First switch control semiconductor element 3b ... Second switch control semiconductor element 4 ... Filter capacitor 50 ... Voltage output circuit 51 ... Low pass filter 52 ... Bootstrap circuit

Claims (4)

A voltage output circuit that generates and outputs a desired bias voltage, an overvoltage protection element connected between the output stage of the voltage output circuit and the ground, and a low-pass filter connected to the output stage of the voltage output circuit Have
The low-pass filter includes a switch semiconductor element using a MOS transistor and a capacitor.
The switch semiconductor element is provided in a forward direction with respect to the output voltage of the voltage output circuit in a diode connection state, and the capacitor is provided between a terminal on the output side of the voltage output circuit and the ground. On the other hand, a switch signal can be applied to the gate of the switch semiconductor element from the outside, and a bootstrap circuit is provided between the gate and the output stage of the voltage output circuit,
In the bootstrap circuit, a plurality of switch control semiconductor elements using MOS transistors are in a diode-connected state and connected in series, and an end corresponding to the anode of the diode of the series-connected switch control semiconductor element array is One end of the voltage output circuit is connected to the output stage, and the other end is connected to the gate of the switch semiconductor element.
When a capacitive load is connected to a connection point between the switch semiconductor element and the capacitor, the bootstrap circuit temporarily raises the gate voltage of the switch semiconductor element so that the switch semiconductor switch becomes conductive. Capacitive load bias circuit characterized in that time can be increased.   The low-pass filter is provided with a plurality of switch semiconductor elements connected in series in a diode connection state, and the gates of the plurality of switch semiconductor elements are connected to each other so that the switch signal can be applied. The capacitive load bias circuit according to claim 1.   2. The capacitive load bias circuit according to claim 1, wherein a diode is connected in parallel to the switch semiconductor element in a direction opposite to a forward direction of the switch semiconductor element.   The low-pass filter is cascaded in two stages to form a multi-stage low-pass filter, the multi-stage low-pass filter and the bootstrap circuit are set as a set of filter circuit blocks, and a plurality of the filter circuit blocks are cascaded to provide the switch signal. The capacitive load bias circuit according to claim 1, wherein: can be input for each filter circuit block.

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