JP2019075189A - Semiconductor device, test program and test method - Google Patents

Abstract

When performing a screening test at room temperature instead of a low-temperature screening test for SRAM, overkill is reduced and the risk of defective outflow due to local variations is suppressed. In an SRAM including a word line, a bit line pair, a memory cell, and a drive circuit for driving the bit line pair, when data is written to the memory cell, one of the bit line pairs The bit line is driven at a high level (VDD) potential, and the other bit line is driven at an intermediate potential (VSS + several tens of mV to hundreds of mV) slightly higher than the low level (VSS) potential in normal writing. Provide functions that can be performed. [Selection] Figure 7

Description

  The present invention relates to a semiconductor device, a test program, and a test method, and is particularly suitable for a test technique for selecting a defect at a low temperature of a static random access memory (SRAM) mounted on the semiconductor device It can be used.

  Conventionally, for inexpensive semiconductor products, the test cost may be reduced by omitting the test at a low temperature (for example, 0 ° C. or less) in the sorting test for product shipment. This is because, in the semiconductor manufacturing process up to now, in SRAM memory cells, many circuit operation failures due to manufacturing such as lack of static noise margin (SNM) tend to occur at high temperature, and the above-mentioned low temperature There is no problem even if I omit the test of. For test items where the operation at the low temperature is the most severe, there is provided a technique for finding in advance a power supply voltage or the like that provides the same operating condition at room temperature and replacing it by the room temperature test.

  In Patent Document 1, the word line potential changes to a voltage corresponding to the temperature to be measured based on a temperature-word line potential conversion table describing the correspondence between the temperature and the word line potential, which is prepared and provided in advance. Testing techniques are disclosed.

JP, 2010-244659, A

  As a result of the present inventor examining Patent Document 1, it was found that there were the following new problems.

  FIG. 1 shows a circuit of a general six-transistor SRAM memory cell. The memory cell MC is connected to a word line WL, a bit line pair (BT and BB), and a power supply line VDD for supplying power and a ground line VSS. Memory cell MC includes two inverters of which two storage nodes (node A and node B) have their inputs respectively connected to the other outputs, and two transfer gates (MN3 and MN4). Configured Each of the two inverters is composed of P-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) (MP1 and MP2) and N-channel MOSFETs (MN1 and MN2). The P-channel MOSFETs (MP1 and MP2) are called load MOSs, and the N-channel MOSFETs (MN1 and MN2) are called drive MOSs. Two transfer gates have gate electrodes connected to word line WL, source electrodes connected to two storage nodes (node A and node B), and drains forming two bit lines forming a bit line pair. It consists of two N-channel MOSFETs (MN3 and MN4) connected to (BT and BB) respectively. Note that in the MOSFET referred to in the present specification, the source electrode and the drain electrode are electrically symmetrical and may be called in reverse. When one of the source electrode or the drain electrode is called a source electrode, the other is only called a drain electrode.

  FIG. 2 is a waveform diagram showing an operation when data is written to SRAM memory cell MC of FIG. A selection signal is asserted on the word line WL, and a voltage corresponding to the write data is complementarily applied to the bit line pair (BT and BB). In the memory cell MC selected by the word line WL, voltages applied to the storage nodes (node A and node B) from the bit line pair (BT and BB) are written. FIG. 2 shows an example in which a high level is applied to bit line BT and a low level is applied to bit line BB, and the levels held in storage nodes (node A and node B) are inverted. In the non-defective product, the node A transitions from the power supply (VDD) potential at high level to the ground (VSS) potential at low level, and the node B transitions from the VSS potential to the VDD potential.

  In this circuit, when a fault occurs in the path between node B (node B) and power supply line VDD, the data whose high level is held at node B is written in the operation of writing data to memory cell MC. There is a defect that the potential of the node B does not rise to the same potential as the power supply VDD and remains at the intermediate potential (see “defective storage node” in FIG. 2). As a failure, it is assumed that the threshold voltage of the P-channel MOSFET (MP2), which is a load MOS, is abnormally high and the on-current is small, or that a high resistance portion due to a half break or the like exists on the path. This failure is particularly noticeable at low temperatures. In order to sort out this defect, the test was conducted at a low temperature or the power supply voltage was lowered to a voltage which causes a failure at normal temperature.

  In the case of carrying out a low temperature sorting test, a facility etc. is required to bring the semiconductor element to be tested to a low temperature (for example -20 ° C to -40 ° C), and the sorting test is carried out at three temperatures: high temperature, normal temperature and low temperature The test time is longer because of the need to do so, resulting in the problem of higher test costs.

  By carrying out the screening test at normal temperature instead of the low temperature screening test, the problem of the increase in the test cost is solved. When the low temperature sorting test is carried out at room temperature, it is necessary to provide a guard band at a voltage. FIG. 3 is a characteristic diagram showing the temperature dependency of the transistor current in a general transistor (MOSFET). The horizontal axis is the power supply voltage VDD, and the vertical axis is the transistor current (Tr Current; drain current in the case of MOSFET). With respect to this transistor, when the lower limit voltage of operation on the specification is VDD_MIN, the transistor current at low temperature (for example, target current of −40 ° C.) at this lower limit voltage VDD_MIN and the transistor current at normal temperature (eg, 25 ° C.) The transistor current at room temperature is larger. In order to match the transistor current at normal temperature to the transistor current at low temperature, it is necessary to provide a guard band that lowers the power supply voltage by αV more than VDD_MIN. Here, αV is generally several tens of mV.

  The inventors of the present invention examined the screening test at such a normal temperature, which is an alternative to the low temperature screening test, and found that there are the following new problems.

  By providing the guard band for reducing the power supply voltage, not only the transistors for which the current drive capability needs to be reduced but also the current drive capabilities of all the transistors are reduced. For this reason, a semiconductor chip which causes an operation error due to a cause other than the original test item is generated, and even a semiconductor chip which is originally a good product other than a defective semiconductor chip to be eliminated is judged as a defective product. It has been found that the problem of causing For example, in the SRAM memory cell MC shown in FIG. 1, a defect as shown in the “defective storage node” of FIG. 2 due to a decrease in current drive capability of the P-channel MOSFET (MP2) which is a load MOS is detected. If a test is performed in which a guard band is provided to lower the power supply voltage in order to reduce the power supply voltage, the cell current at the time of memory read may be reduced due to the influence thereof, and the sense amplifier sensitivity may be reduced.

  Furthermore, it has been found that the overkill is more remarkable when the miniaturization of the semiconductor element progresses. That is, in the recent miniaturization process, it has been found that the circuit operation failure caused by the manufacture of the SRAM memory cell occurs in large numbers even at a low temperature due to the influence of the increase of the local variation.

  FIG. 4 is an explanatory view schematically showing the relationship between the transistor current and the local variation and the temperature dependency. The horizontal axis is the transistor current, and the vertical axis is the local variation, and the characteristics at normal temperature (25 ° C.) and low temperature (−40 ° C.) are shown. In the process in which local variations dominate, the temperature dependence of the transistor characteristics near the median (Median; 0σ) and the transistor characteristics in a region (6σ) with large variations is different. It was found that the local variation of the transistor current is larger at low temperature (−40 ° C.) than at normal temperature (25 ° C.). For this reason, it was found that in the screening test in which the guard band is set on the basis of the characteristics near the median (0σ), the risk of defective outflow increases.

  The means for solving such problems will be described below, but other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, in an SRAM including a word line, a bit line pair, a memory cell, and a drive circuit for driving the bit line pair, when data is written to the memory cell, one bit line of the bit line pair Is driven at a high level potential, and the other bit line can be driven at an intermediate potential higher than the low level potential in the case of normal writing and lower than the high level potential.

  The effects obtained by the one embodiment will be briefly described as follows.

  That is, when performing the sorting test at normal temperature instead of the low temperature sorting test on the SRAM, it is possible to reduce the overkill and to suppress the risk of the failure outflow due to the local variation.

FIG. 1 is a circuit diagram of a general six-transistor SRAM memory cell. FIG. 2 is a waveform diagram showing an operation when data is written to the SRAM memory cell of FIG. FIG. 3 is a characteristic diagram showing the temperature dependency of the transistor current in a general transistor. FIG. 4 is an explanatory view schematically showing the relationship between the transistor current and the local variation and the temperature dependency. FIG. 5 is a block diagram showing a configuration example of an SRAM module to be tested. FIG. 6 is a block diagram showing an example of the circuit configuration of an I / O circuit and a memory cell drawn focusing on one memory cell. FIG. 7 is a waveform diagram showing an operation when data is written to the SRAM memory cell of FIG. FIG. 8 is a waveform diagram showing a modification of the operation when data is written to the SRAM memory cell of FIG. 6 (a read cycle is added immediately after the write cycle). FIG. 9 is a circuit diagram showing a configuration example of a write driver. FIG. 10 is a waveform diagram showing an operation example of the write driver shown in FIG. FIG. 11 is a waveform diagram showing an operation example in the normal operation mode of the write driver shown in FIG. FIG. 12 is a waveform diagram showing an operation example in the pseudo low temperature sorting test mode of the write driver shown in FIG. FIG. 13 is a waveform diagram showing another operation example in the pseudo low temperature sorting test mode of the write driver shown in FIG. FIG. 14 is a configuration diagram showing another example of the circuit configuration of the I / O circuit and the memory cell drawn focusing on one memory cell. FIG. 15 is a waveform diagram showing a stress operation immediately after writing by the circuit configuration of FIG. FIG. 16 is a waveform diagram showing a stress operation immediately after writing by the circuit configuration of FIG. FIG. 17 is a circuit diagram of a dual port SRAM memory cell of 8-transistor configuration. FIG. 18 is a block diagram showing a configuration example of a dual port SRAM module to be tested. FIG. 19 is a diagram showing a layout configuration of the semiconductor chip in the fifth embodiment.

  The embodiment will be described in detail.

Embodiment 1
FIG. 5 is a block diagram showing a configuration example of the SRAM module 1 to be tested. In the first embodiment, a single-port SRAM module 1 of M words × N bits (M and N are integers) will be described. The SRAM module 1 includes memory cells MC00 to MC_ (M−1) (N−1), I / O circuits 4_LSB (LSB: Least Significant Bit) and 4_MSB (MSB: Most Significant Bit), and word line drivers 3_0 to 3_M−. 1, a control circuit and an address decoder 5, and a test mode control circuit 6. The SRAM module 1 includes word lines WL_0 to WL_M-1, bit line pairs BT_0 to BT_N-1 and BB_0 to BB_N-1, and memory cells MC00 to MC_ (where the word lines and bit line pairs intersect). M-1) (N-1) is connected. Word line drivers 3_0 to 3_M-1 select word selection signals for one word line selected based on the decode result of address decoder 5 among word lines WL_0 to WL_M-1 connected thereto. Assert. When the memory cell MC includes, for example, a transfer gate of an N-channel MOSFET as illustrated in FIG. 1, “to assert a word select signal” means to drive the word line at a high level (usually VDD potential). Say. I / O circuit 4_LSB is connected to memory cells MC00 to MC_ (M-1) 0, MC01 to MC_ (M-1) 1, ... on the lower bit (LSB) side, and I / O circuit 4_ MSB is the upper bit (MSB) , MC 0 (N−2) to MC_ (M−1) (N−2, MC 0 (N−1) to MC_ (M−1) (N−1). / O circuits 4_LSB and 4_MSB are connected to control circuit and address decoder 5 for read / write control, and further controlled by test mode switching signal T_MODE to control whether the normal operation mode or the test mode A test mode signal TEST is supplied from the mode control circuit 6.

  The memory cell MC and the I / O circuit 4 will be described in more detail.

  FIG. 6 is a block diagram showing an example of the circuit configuration of the I / O circuit 4 and the memory cell MC drawn focusing on one memory cell. Among the I / O circuit 4 connected to one memory cell MC focused on, the write driver 7 connected to the memory cell MC, the sense amplifier 8, and the column I / O circuit 9 are shown. The column I / O circuit 9 further includes a precharge circuit 10, a write column switch 11, a read column switch 12, and a column I / O control circuit 13. CTW and CBW are common write bit line pairs, CTR and CBR are common read bit line pairs, Y0 and Y1 are Y address selection signals, CPC is a precharge control signal, CWSE is a write switch control signal, and CRSE is a read switch control signal. is there.

  Although not shown in FIG. 6, SRAM module 1 includes control circuit, address decoder 5 and word line drivers 3_0 to 3_M-1, as shown in FIG. 2, and is shown in FIG. Only one word line WL driven by the word line driver 3 is illustrated, and the other word lines and the memory cells MC connected thereto are not illustrated. The same applies to the column direction. Although only two bits of the I / O circuit 4 are shown in FIG. 6, they may be further arranged in the column direction. Further, FIG. 6 shows an example in which two column I / O circuits 9 are provided per one I / O circuit 4. That is, although the circuit of MUX2 is illustrated, it can also be changed to the composition of more selection circuits, for example, MUX4 and MUX8. Test mode signal TEST is input to write driver 7. In the test mode, drive is performed by floating the level on the low side of bit line pair BT and BB to a potential (intermediate potential) higher than VSS. Circuits that can do this are provided.

  The intermediate potential is a potential which is detected as a defect even at room temperature with respect to the memory cell MC which becomes a good product at normal temperature in the normal operation mode and becomes a defect at low temperature. The potential is set based on circuit simulation and experiments, and is higher by a few tens mV to a few tens mV (for example, 20 mV to 120 mV) than VSS and lower than VDD. As shown in FIG. 6, two inverters in which each input is connected to the other output in two storage nodes (node A and node B), and two transfer gates (MN 3 and MN 4) In the memory cell MC including the above, it is determined as defective if the potential of the storage node to be originally inverted is not inverted by the potential input from the bit line pair BT and BB through the transfer gates (MN3 and MN4). Be done. In such a memory cell MC, as described above, as a failure, the threshold voltage of the P-channel MOSFETs (MP1 and MP2), which are load MOSs, is abnormally high and the on current is small, It is assumed that there is a resistance point. This defect is remarkable particularly at a low temperature. Therefore, in the normal operation mode, although it operates normally at normal temperature, it becomes a defect at low temperature. In the test mode, by driving the low level side of bit line pair BT and BB at a potential (intermediate potential) higher than VSS, the drive capability for transitioning the storage node from low level to high level is weakened. , Writing is inhibited. Therefore, this test mode is a pseudo low temperature test mode, and the test is called a pseudo low temperature sorting test. At this time, stress can be selectively applied to a write that causes the storage node to transition from the low level to the high level, and no stress is applied to other circuits such as a sense amplifier. As described above, stress is selectively applied to the device to be tested as compared with the conventional test in which stress is applied by lowering the power supply voltage of the entire memory module and the low temperature condition is simulated in the normal temperature test. Since this can be performed, it is possible to suppress the occurrence of overkill where peripheral circuits other than the element are inhibited from normal operation due to stress and are detected as defects.

  The operation of the SRAM module 1 will be described in more detail.

  FIG. 7 is a waveform diagram showing an operation when data is written to SRAM memory cell MC of FIG.

  In the write operation in the normal operation mode, write driver 7 outputs a signal for writing to bit line pair BT and BB via common write bit line pair CTW and CBW (not shown in FIG. 7), One of the line pairs is driven at a high level (VDD potential) and the other is driven at a low level (VSS potential). Almost simultaneously, the word line driver 3 is driven to raise the word line WL. This is the assertion of the word line select signal, and the data is written by inverting the levels of node A and node B (node A and node B) which are storage nodes of the selected memory cell MC. Be After writing is completed, the word line WL is lowered to precharge the bit line pair BT and BB, thereby completing one cycle. In this write operation, the potential of the bit line set to the low side of bit line pair BT and BB is set to the VSS (GND) level in the normal operation.

  On the other hand, in the pseudo low temperature test mode, the bit line potential on the low side is floated by several tens of mV to one hundred and several tens of mV with respect to the VSS (GND) level (VSS + ΔV). As a result, as shown in FIG. 7, the internal node A, which is on the low side after rewriting, does not fall to the VSS (GND) level, and becomes the floating potential (VSS + ΔV). Since the floating potential (VSS + ΔV) is also applied to the gate (node A) of the P-channel MOSFET (MP2) which is the load MOS in the memory cell MC of FIG. 6, for the case where VSS (GND) is applied, The on-resistance between the source and the drain of the P-channel MOSFET (MP2) is increased, which prevents the node B from being pulled high.

  As described above, by inhibiting the writing, when there is not enough writing capability (when there is a failure (fault) in the path for supplying current from the power supply VDD to the node B, writing stress is applied, and normal writing can not be performed) Therefore, defective products that normally operate at normal temperature but fail at low temperature can be eliminated by screening in a test at normal temperature.

  Furthermore, in order to make the defect more apparent, it is preferable to perform the read operation to the same address immediately after the above-described stressed write (next cycle).

  FIG. 8 is a waveform diagram showing a modification of the operation when data is written to the SRAM memory cell of FIG. 6 (a read cycle is added immediately after the write cycle).

  In the normal operation mode, in the read cycle added immediately after the write cycle, the word line WL is raised again to the same memory cell MC as the memory cell MC to which the writing is performed (assertion of the word select signal). Accordingly, the level of node A which is a storage node is read to bit line BB, and the level of node B is read to bit line BT. In the above example, since the node A is at the low level and the node B is at the high level, the low level is read from the node A to the bit line BB and the potential of the bit line BB is lowered. At this time, the potential of the node A slightly rises because current flows from the precharged bit line BB.

  Even in the pseudo low temperature test mode, in the read cycle added immediately after the write cycle, the word line WL is raised again to the same memory cell MC as the memory cell MC to which the writing is performed (assertion of word selection signal) Accordingly, the level of node A, which is a storage node, is read to bit line BB, and the level of node B is read to bit line BT. At this time, when the memory cell MC has a failure at low temperature and the internal writing has not been sufficiently completed, the level of the node A can not fall to the VSS (GND) level and the level of the node B can not rise to VDD. . At this time, a read cycle is performed on the same memory cell MC, and rising of word line WL causes nodes A and B to transfer gate (MN3) to precharged bit line pair BB and BT, respectively. And MN4) are connected. In the normal operation mode, the potential of node A slightly rises due to the current flowing from the precharged bit line BB, but the level of node A is not completed when the internal writing is not sufficiently completed. It is inverted by the current flowing from bit line BB, and the level of node B is also inverted accordingly. As described above, in the memory cell MC having a failure at low temperature and a small static noise margin (SNM), data stored in the write operation is volatilized by the read operation immediately after, and is selected and rejected as a defective product. be able to. As described above, in the memory cell MC having a small SNM, when a certain time passes after the write operation, the level of the node A falls to the VSS (GND) level, and the level of the node B rises completely to VDD and is stabilized. In the read operation, there are cases where it can not be sorted out and rejected as a defect. By adding the read cycle immediately after the write cycle in the pseudo low temperature test mode, even such unstable failures can be properly eliminated.

  The above test method uses a predetermined control language in a test program and is described as a test pattern. The test method is executed by the semiconductor tester executing the test program on a test target of the semiconductor chip on which the SRAM is mounted. Instead of execution by the semiconductor tester, a test circuit that executes an equivalent test sequence may be incorporated in the semiconductor chip. The same applies to the following embodiments.

  As described above, at the time of writing to the SRAM memory cell, the write potential is insufficient by floating the potential of the low side of the bit line pair by several tens of mV to one hundred and several tens of mV from that at the time of normal operation. It is possible to perform a low temperature sorting test on a defective memory cell in a pseudo manner at normal temperature, and by performing the same power supply voltage as a normal room temperature test, overkill can be prevented. Furthermore, by reading the same address in the next cycle after writing in the stress mode, stress for writing can be applied more significantly, and even an unstable defect can be appropriately eliminated.

Second Embodiment
A configuration example of the write driver 7 will be described which has a function of floating the potential on the low side of the bit line pair by several tens of mV to one hundred and several tens of mV compared to that of the normal operation at the time of writing to the SRAM memory cell.

  FIG. 9 is a circuit diagram showing a configuration example of the write driver 7. Of the write driver 7, only one bit is shown. The input D is write data, BWE is a bit write mask control signal, TEST is a test mode signal, WE is a write enable signal, CLK is a clock, and the output CTW and CBW are a common write bit line pair. The write data D and the bit write mask control signal BWE are taken into the corresponding flip flops FF_D and FF_BWE in synchronization with the clock CLK. The write data D captured by the flip flop FF_D is output to the common write bit line pair CTW and CBW at complementary logic levels by the logic gates G4 to G8. However, in a state where the bit write mask control signal BWE is asserted, the write data D is masked, and a high level is output to both the common write bit line pair CTW and CBW. This bit write mask function can also be omitted. FIG. 9 shows an example in which one bit write mask control signal BWE is input for one bit, but one bit write mask control signal BWE is grouped for each of a plurality of bits such as 8 bits or 9 bits, for example. It may be configured to be input. The byte by byte grouping provides a byte write mask function.

  The write driver 7 includes two inverters for inverting the levels of the input nodes NT and NB and outputting them to the common write bit line pair CTW and CBW, as in the normal write driver. The two inverters are composed of a P-channel MOSFET (MP9) and an N-channel MOSFET (MN10), a P-channel MOSFET (MP8) and an N-channel MOSFET (MN9). The write driver 7 of this embodiment is a two low voltage test mode, in which two N channel MOSFETs (MN9) connect the common write bit line pair CTW and CBW to the power supply VDD when the test mode signal TEST becomes high. And MN 10).

  The drive capabilities of two N-channel MOSFETs (MN9 and MN10) controlled by test mode signal TEST are represented by their channel widths W2B and W2, respectively, and two N-channel MOSFETs (MN7 and MN8) constituting two inverters. The drive capability of the channel is represented by the channel widths W1B and W1, respectively. In the pseudo low temperature test mode in which test mode signal TEST is asserted, the inverter for driving common write bit line pair CTW and CBW to the low level competes with the N channel MOSFET (MN7 or MN8) and is connected to the common write bit line pair The low level side of the bit line pair to be selected can be floated (set to an intermediate potential) by several tens of mV to one hundred and several tens of mV than the VSS (GND) potential. When a low level is output to CTW and a high level is output to CBW, the N channel MOSFET (MN10) connected to the CTW to which the low level is output is also turned on, so the actual CTW potential (intermediate potential) is N channel It is defined by the difference between the channel width W2 of the MOSFET (MN10) and the channel width W1 of the N-channel MOSFET (MN8) constituting the inverter. Conversely, when a high level is output to CTW and a low level is output to CBW, the N channel MOSFET (MN9) connected to CBW to which the low level is output is also turned on, so the actual potential (intermediate potential) of CBW is It is defined by the difference between the channel width W2B of the N-channel MOSFET (MN9) and the channel width W1B of the N-channel MOSFET (MN7) constituting the inverter.

  The above describes the method of adjusting the channel widths W1, W2, W1B, and W2B to set the low side of the bit line pair in the pseudo low temperature test mode to a desired intermediate potential. You may adjust. The adjustment of the channel length may be realized by connecting two MOSFETs of a normal channel length (L) in series instead of actually providing a double channel length 2L MOSFET.

  Thus, stress is applied at the time of writing to the SRAM memory cell only by adding two N-channel MOSFETs (MN9 and MN10) controlled by test mode signal TEST to the normal write buffer (bit line It is possible to realize a write driver 7 having a function of floating the potential on the low side of the pair by several tens of mV to one hundred and several tens of mV compared to that in the normal operation.

  The operation of the write driver 7 will be described in more detail.

  10 and 11 to 13 are waveform diagrams showing an operation example of the write driver 7 shown in FIG.

  In the write operation in the normal operation mode shown in FIGS. 10 and 11, when the clock CLK rises, the input signal D is taken into the flip flop FF_D, and the bit write mask control signal BWE is taken into the flip flop FF_BWE. When BWE is enabled (low level), data D captured by flip-flop FF_D is written to memory cell MC (the first half of FIG. 10) and when BWE is disabled (high level), writing is not performed. (The second half of Figure 10).

  The write enable signal WE is at the high level in the initial stage, and the internal nodes NT and NB at this time are both at the low level, and the common write bit line pair CTW and CBW are both at the high level.

  Next, when the write enable signal WE goes low, one of the internal nodes NT and NB goes high and the other goes low according to the input signal D, and the common write bit line pair CTW and CBW correspondingly goes low. The other is high level.

  Thereafter, when the write enable signal WE becomes high level, the internal nodes NT and NB both become low level, and the common write bit line pair CTW and CBW are both precharged to high level.

  When BWE is enabled (low level) and data D is written to memory cell MC, as shown in FIG. 11, write enable signal WE falls and internal node NT based on data D taken in flip-flop FF_D. / NB changes, and the common write bit line pair CTW / CBW is driven accordingly. Since the test mode signal TEST is at the low level and the two N channel MOSFETs (MN9 and MN10) of FIG. 9 are both off in the normal operation mode, the high side of the common write bit line pair CTW / CBW is The low side is driven to the VDD potential, and the low side is driven to the VSS (GND) potential.

  On the other hand, in the pseudo low temperature sorting test mode, as shown in FIG. 12, the test mode signal TEST is asserted before the write enable signal WE rises, and the two N channel MOSFETs of FIG. Since both MN9 and MN10 are turned on, the common write bit line pair CTW / CBW is both pulled up to the VDD potential. The write enable signal WE falls, the internal node NT / NB changes based on the data D taken into the flip flop FF_D, and the common write bit line pair CTW / CBW is driven accordingly. At this time, on the low side of common write bit line pair CTW / CBW, a signal conflict occurs between MN9 or MN10 and MN7 or MN8 which is an N-channel MOSFET of an inverter outputting a low level, as described above. It becomes an intermediate potential determined by their driving ability. Thereby, stress can be applied by floating the bit line on the low side by several tens of millivolts to one hundred and several tens of millivolts at the time of writing.

  As shown in FIG. 12, the test mode signal TEST is controlled in the reverse phase of the write enable signal WE. The transition timing is such that the rise of the test mode signal TEST is made simultaneous with or earlier than the rise of the write enable signal WE, and the fall is made simultaneous with the write enable signal WE.

  On the other hand, as shown in FIG. 13, the test mode signal TEST may be fixed at the high level. In the example shown in FIG. 12, control can be made to switch between the pseudo low temperature sorting test mode and the normal room temperature sorting test mode by the test mode signal TEST during the test mode. On the other hand, in the example shown in FIG. 13, the test mode signal TEST can be used also as a switching control signal of the normal operation mode and the test mode, and the switching control circuit of the operation mode is simplified.

  As described above, at the time of writing to the SRAM memory cell, the potential on the low side of the bit line pair is floated by several tens of mV to one hundred and several tens of millivolts from the time of normal operation to inhibit writing, pseudo-low temperature screening test A circuit configuration suitable for the write driver 7 for realizing the mode is provided. That is, two N-channel MOSFETs (MN9 and MN10) whose source side is connected to VDD and drain side is connected to bit line pair respectively and whose gate is connected to test mode signal TEST in order to float the bit line are the ride drivers 7 Is added to The drivability of the two N-channel MOSFETs (MN9 and MN10) is weaker than that of the N-channel MOSFETs (MN7 and MN8) which drive the bit line pair low, and the potential of floating the bit line on the low side (Intermediate potential) can be determined. Thus, the stress circuit can be realized only by adding two N-channel MOSFETs (MN9 and MN10).

Third Embodiment
FIG. 14 is a configuration diagram showing another example of the circuit configuration of the I / O circuit 4 and the memory cell MC drawn focusing on one memory cell. The difference between the first embodiment and the configuration example shown in FIG. 6 is that a precharge enable signal PE is added. The logic gate to which the precharge enable signal PE is input is changed from the inverter G2 to the NOR gate G9. The other configuration is the same as the configuration example shown in FIG.

  FIG. 15 is a waveform diagram showing a stress operation immediately after writing by the circuit configuration of FIG.

  In the operation example described with reference to FIG. 8 in the first embodiment, the read cycle is added immediately after the write cycle, and a total of two cycles are required. On the other hand, in the operation example of the third embodiment shown in FIG. 15, the write period and the stress period due to the pseudo read are included in one access period to the memory cell MC.

  The write period is a stressed write, similar to the write cycle of FIG. 8 of the first embodiment. That is, the writing is performed with the potential on the low side of the bit line pair BT / BB floating by several tens of mV to one hundred and several tens of mV from that in the normal operation. During this period, the precharge enable signal PE is negated to turn off the precharge.

  In the stress period, the word line WL does not fall even after the write period is completed, and the precharge enable signal PE is asserted to continuously turn on the precharge of the target bit line pair for the same memory cell MC. Set / BB to VDD level. As a result of memory cell MC having a failure at a low temperature and internal writing not sufficiently completed as a result of precharging of target bit line pair BT / BB with word line WL raised, storage level at internal node A / B. Will evaporate. In this manner, stress can be applied to the data retention characteristics of the memory cell MC, so that defects can be made apparent and it becomes easier to sort out defective samples.

  Although the precharge enable signal PE is added in the circuit configuration shown in FIG. 14, the Y address selection signals Y0 and Y1 are also used as the precharge control signal instead of the configuration shown in FIG. It is also possible.

  FIG. 16 is a waveform diagram showing a stress operation immediately after writing by the circuit configuration of FIG.

  The write period is a stressed write as in the write period of FIG. That is, the writing is performed with the potential on the low side of the bit line pair BT / BB floating by several tens of mV to one hundred and several tens of mV from that in the normal operation. In the precharge period prior to the write period, all the bits are precharged by not selecting Y address selection signals Y0 and Y1 instead of asserting the precharge enable signal PE. In the write period, the precharge is turned off by setting the Y address select signal Y0 or Y1 of the selected column to the selected state.

  In the stress period, as in the stress period of FIG. 15, the word line WL does not fall after the write period is completed, but both Y address selection signals Y0 and Y1 are not selected instead of asserting the precharge enable signal PE. Thus, the bit line pair BT / BB is precharged to the VDD level.

  Thereby, the same effect as the operation shown in FIG. 15 can be achieved only by changing the control circuit.

  As described above, in the pseudo low-temperature sorting test mode, the potential on the low side of the bit line pair is floated by several tens mV to one hundred and several tens mV from the time of normal operation when writing to the SRAM memory cell. The stressed write and the subsequent dummy read operation can be continuously performed by one command. Since two stress tests can be performed by a normal write command, a special test pattern can be eliminated and the test pattern in the sorting test can be simplified. In addition, since the test time is shortened, the test cost can be reduced.

Embodiment 4
The above has been described by taking only a single port SRAM as an example, but the same can be applied to a multiport SRAM. An embodiment applied to a dual port SRAM will be described as an example.

  FIG. 17 is a circuit diagram of a dual port SRAM memory cell MC-DP having an eight transistor configuration. The word lines are WL-A and WL-B, and the bit line pair is BT-A / BB-A and BT-B / BT-B, as compared to the general 6-transistor SRAM memory cell shown in FIG. The two N-channel MOSFETs (MN11 and MN12) are added to the respective two ports and function as transfer gates. The other configuration and operation are the same as those of the single-port SRAM memory cell, and thus the description thereof is omitted.

  FIG. 18 is a block diagram showing a configuration example of a dual port SRAM module to be tested. Similar to FIG. 5, the configuration is M words × N bits (M and N are integers), and the memory cells are replaced with dual port SRAM memory cells MC-DP00 to MC-DP_ (M−1) (N−1). ing. A port side I / O circuits 4-A_LSB and 4-A_MSB, word line drivers 3-A_0 to 3-A_M-1, control circuit and address decoder 5-A, B port side I / O circuits 4-B_LSB and It comprises a 4-B_MSB, word line drivers 3-B_0 to 3-B_M-1, a control circuit and an address decoder 5-B, and a test mode control circuit 6. The same circuits are mounted on the A port side and the B port side of the I / O circuit 4, the word line driver 3, and the control circuit and the address decoder 5, and each operates in the same manner as the single port SRAM described in the first embodiment. Do. Only one test mode control circuit 6 may be provided in total, and one test mode signal TEST is supplied to one I / O circuit, for example, the I / O circuit 4-A_LSB of port A side as shown in FIG. It is supplied only to -A_MSB. The I / O circuits 4-A_LSB and 4-A_MSB on the port A side are in the pseudo low temperature test mode as illustrated in FIG. 7, and the bit line potential on the low side is several tens of mV with respect to the VSS (GND) level. A circuit that floats up to a hundred and several tens of millivolts is mounted. On the other hand, in the I / O circuits 4-B_LSB and 4-B_MSB on the port B side, the above circuits for the pseudo low temperature test mode are omitted. This is because it is sufficient to be able to carry out the screening test in the pseudo low temperature test mode from one of the ports because a defect that becomes noticeable at low temperatures is caused by a failure of the memory cell.

  On the other hand, even if I / O circuits 4-B_LSB and 4-B_MSB on the port B side are also equipped with similar circuits, it is configured to carry out screening test in the pseudo low temperature test mode from both ports. good. For example, if a failure caused by a bit line pair or a word line causes a remarkable defect at low temperatures, the defective products may flow out by performing a screening test in a pseudo low temperature test mode from both ports. Can be prevented.

Fifth Embodiment
The single-port and multi-port SRAM modules described in the first to fourth embodiments can be incorporated into a semiconductor chip 20 in which a system including an SoC (System-on-a-Chip) and a microcomputer is formed. FIG. 19 is a view showing a layout configuration of the semiconductor chip 20 in the fifth embodiment. In FIG. 19, a semiconductor chip 20 includes a CPU (Central Processing Unit) 21, single port SRAMs (SP-SRAMs) 1_1 to 1_6, dual port SRAMs (DP-SRAMs) 2_1 to 2_2 and logic circuits (LOGICs) 22_1 to 22_3. Have. Here, the single port SRAMs (SP-SRAMs) 1_1 to 1_6 are the single port SRAMs described in the first to fourth embodiments, and the dual port SRAMs (DP-SRAMs) 2_1 to 2_2 are the dual ports described in the fourth embodiment. It is a port SRAM. Note that in addition to the SRAM, another storage element such as an EEPROM (Electrically Erasable Programmable Read Only Memory) may be included, or an analog circuit or the like may be incorporated.

  The CPU 21 is also called a central processing unit and corresponds to the heart of a computer or the like. The CPU 21 reads and decodes an instruction from a storage device, and performs various operations and controls based on the instruction. A CPU core (CPU core) is built in the CPU 21. An SRAM is built in the CPU core. A high performance SRAM is used as the SRAM inside the CPU core, and it is preferable to use the SRAM described in the first to fourth embodiments. Of course, the SRAMs described in detail in the first to fourth embodiments may be used for the single port SRAMs (SP-SRAMs) 1_1 to 1_6 and dual port SRAMs (DP-SRAMs) 2_1 to 2_2.

  As described above, the characteristics can be improved by incorporating the SRAM described in the first to fourth embodiments into the semiconductor chip 20 in which a system including an SoC and a microcomputer is formed. In addition, if the low temperature screening test is not necessary for other circuits such as the CPU 21 and the logic circuits (LOGIC) 22_1 to 22_3, it is remarkable only for the mounted SRAM that causes remarkable defects at low temperatures. By applying the first to fourth embodiments to all the SRAMs mounted on the semiconductor chip 20, it is possible to prevent the problem of overkill and defective outflow while omitting the low temperature sorting test of the entire chip.

  Although the invention made by the inventors of the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.

MC memory cell MC-DP dual port memory cell MP1 to 7 P channel MOSFET
MN1 to 12 N channel MOSFET
FF flip flop G1 to G8 logic gate VDD power supply line VSS ground line WL word line BT, BB bit line pair T_MODE test mode switching signal TEST test mode signal CTW, CBW common write bit line pair CTR, CBR common read bit line pair Y0, Y1 Y address selection signal CPC precharge control signal PE precharge enable signal CWSE write switch control signal CRSE read switch control signal D write data BWE bit write mask control signal WE write enable signal CLK clock 1 single port SRAM module 2 dual port SRAM module 3 Word line driver 4 I / O circuit 5 Control circuit & address decoder 6 Test mode control circuit 7 Write driver 8 Sense amplifier 9 column I / O circuit 10 precharge circuits 11 write column switch 20 semiconductor chips 21 CPU (Central Processing Unit)
22 Logic circuit (LOGIC)

Claims (9)

With word lines,
A bit line pair extending in a direction different from the word line;
A memory cell connected to the word line and the bit line pair;
A driving circuit for supplying data to the memory cell by supplying a predetermined potential to the bit line pair;
A first potential and a second potential higher than the first potential are supplied to the memory cell;
A semiconductor device having a first operation mode and a second operation mode different from the first operation mode, the semiconductor device comprising:
The drive circuit is
A test mode signal line for transmitting a test mode signal,
A first transistor electrically connected to one bit line of the bit line pair and a second power supply line supplying the second potential;
A second transistor electrically connected to the other bit line of the bit line pair and the second power supply line,
The gate electrode of the first transistor and the gate electrode of the second transistor are electrically connected to the test mode signal line,
In the first operation mode, the drive circuit supplies the first potential to one bit line of the bit line pair and supplies the second potential to the other bit line of the bit line pair. ,
In the second operation mode,
The first transistor and the second transistor are turned on in response to a test mode signal,
The drive circuit supplies the first potential to one bit line of the bit line pair, and the other bit line of the bit line pair is higher than the first potential and higher than the second potential Also supply a low third potential,
Semiconductor device. A first power supply line for supplying the first potential;
A third transistor electrically connected to one bit line of the bit line pair and the first power supply line;
The semiconductor device according to claim 1, further comprising: a fourth transistor electrically connected to the other bit line of said bit line pair and said first power supply line.   The semiconductor device according to claim 2, wherein the drivability of the third transistor and the fourth transistor is larger than the drivability of the first transistor and the second transistor.   The semiconductor device according to claim 2, wherein the first to fourth transistors are N-channel MOSFETs.   The semiconductor device according to claim 4, wherein gate widths of the third and fourth transistors are larger than gate widths of the first and second transistors.   5. The semiconductor device according to claim 4, wherein gate lengths of the third and fourth transistors are larger than gate lengths of the first and second transistors. The memory cell is connected to the first and second power supply lines, has first and second storage nodes, and includes first and second P-channel MOSFETs and fifth to eighth N-channel MOSFETs. Including and
A drain electrode of the fifth P-channel MOSFET, a drain electrode of the first N-channel MOSFET, a source electrode of the third N-channel MOSFET, a gate electrode of the second P-channel MOSFET, and The gate electrodes of the six N channel MOSFETs are connected to the first storage node,
The source electrode of the first P-channel MOSFET and the source electrode of the second P-channel MOSFET are connected to the second power supply line,
The drain electrode of the second P-channel MOSFET, the drain electrode of the sixth N-channel MOSFET, the source electrode of the eighth N-channel MOSFET, the gate electrode of the first P-channel MOSFET, and The gate electrode of the 5 N-channel MOSFET is connected to the second storage node,
The source electrode of the first P-channel MOSFET and the source electrode of the second P-channel MOSFET are connected to the second power supply line,
The source electrode of the fifth N-channel MOSFET and the source electrode of the sixth N-channel MOSFET are connected to the first power supply line,
The gate electrode of the seventh N-channel MOSFET and the gate electrode of the eighth N-channel MOSFET are connected to the word line,
The drain electrode of the seventh N-channel MOSFET is connected to one bit line of the bit line pair,
The semiconductor device according to claim 1, wherein a drain electrode of the eighth N-channel MOSFET is connected to the other bit line of the bit line pair. The word line is defined as a first word line, and the bit line pair is defined as a first bit line pair
The semiconductor device includes a second word line and a second bit line pair,
The memory cell further includes ninth and tenth N-channel MOSFETs,
The gate electrode of the seventh N-channel MOSFET and the gate electrode of the eighth N-channel MOSFET are connected to the first word line,
The drain electrode of the seventh N-channel MOSFET is connected to one bit line of the bit line pair,
The drain electrode of the eighth N-channel MOSFET is connected to the other bit line of the bit line pair,
The gate electrode of the ninth N-channel MOSFET and the gate electrode of the tenth N-channel MOSFET are connected to the second word line,
The drain electrode of the ninth N-channel MOSFET is connected to one bit line of the bit line pair,
The drain electrode of the tenth N-channel MOSFET is connected to the other bit line of the second bit line pair,
In the first operation mode, the drive circuit supplies the first potential to one bit line for each of the first bit line pair and the second bit line pair, and the bit Supplying the second potential to the other bit line of the line pair,
In the second operation mode, the drive circuit supplies the third potential to one bit line for each of the first bit line pair and the second bit line pair, and the other bit The semiconductor device according to claim 6, wherein the second potential is supplied to a line.   A memory circuit including the word line, the bit line pair, the memory cell, and the drive circuit; a bus for supplying data to be written to the memory cell by the drive circuit in the first operation mode; The semiconductor device according to claim 1, wherein a test circuit for supplying data to be written to the memory cell in the second operation mode is provided on one semiconductor substrate.

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