JP2019062113A - Manufacturing method of wiring layer - Google Patents

Abstract

To provide a method that can manufacture a wiring layer more efficiently than before.SOLUTION: The present disclosure relates to a manufacturing method of a wiring layer. The manufacturing method includes (A) exposing a part of a first photosensitive resin layer, (B) providing a second photosensitive resin layer on the surface of the first photosensitive resin layer, (C) exposing a part of the second photosensitive resin layer, (D) developing the first and second photosensitive resin layers separately or collectively to form a first opening penetrating the first and second photosensitive resin layers and form a second opening whose bottom surface is the surface of the first photosensitive resin layer, and (E) filling the first and second openings with a conductive material.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to a method of manufacturing a wiring layer, and more particularly, to a method of manufacturing a wiring layer that is useful for efficiently and inexpensively manufacturing a semiconductor device having high demands for miniaturization and densification.

  In order to achieve high density and high performance of semiconductor packages, there has been proposed a mounting form in which chips of different performances are mixed in one package. In this case, a high-density interconnect technology between chips, which is superior in cost, is important (see, for example, Patent Document 1).

  Non-Patent Documents 1 and 2 describe an aspect of a package on package (PoP: Package on Package) in which different packages are connected by stacking them by flip chip mounting. This PoP is an aspect widely adopted in smartphones, tablet terminals and the like.

  As another form for mounting a plurality of chips at high density, package technology (organic interposer) using an organic substrate having high density wiring, fan-out type package having through mold via (TMV: Through Mold Via) Technology (FO-WLP), package technology using silicon or glass interposer, package technology using through silicon via (TSV: Through Silicon Via), chip-to-chip transmission embedded in a substrate Package technology and the like used for

  In particular, when semiconductor chips are mounted on an organic interposer and an FO-WLP, a fine wiring layer is required to electrically connect the semiconductor chips at high density (see, for example, Patent Document 2).

Japanese Patent Application Publication No. 2012-529770 U.S. Patent Application Publication No. 2011/0221071

Jinseong Kim et al. , "Application of Through Mold Via (TMV) as PoP Base Package", Electronic Components and Technology Conference (ECTC), p. 1089-1092 (2008) S. W. Yoon et al. "Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology", ECTC, p. 1250-1254 (2012)

  A wiring layer having a laminate (organic insulating laminate) in which a plurality of organic insulating layers are laminated is used for a buildup substrate, a wafer level package (WLP), a fan-out type PoP bottom package, etc. is there. For example, in the case where a plurality of fine wirings having a line width and a space width of 5 μm or less are arranged in the organic insulating laminate, the wirings are formed by using a trench method. The trench method is a method of forming a metal layer to be a wiring in a trench (groove) formed on the surface of an organic insulating layer by a plating method or the like. Therefore, the shape of the wiring formed on the organic insulating layer conforms to the shape of the groove.

  FIGS. 9 (a) to 9 (e) and FIGS. 10 (a) to 10 (e) schematically show the process of forming a wiring layer on a substrate by a conventional semi-additive method (SAP method). In the semi-additive method, a step of forming a seed layer, a step of forming a resist having a desired pattern on the seed layer, a step of thickening an exposed portion of the seed layer by electrolytic plating method or the like, and a step of removing the resist And etching the seed layer to form a desired wiring.

  First, as shown in FIG. 9A, the first photosensitive resin layer 41A is formed on the surface of the substrate 40 having the metal layer 40a. Thereafter, the first organic insulating layer 41 having the opening 41a is formed by exposure and development of the first photosensitive resin layer 41A (FIG. 9 (b)). Next, a seed layer 41b for power supply for forming the metal layer 41c by electrolytic plating is formed on the surfaces of the first organic insulating layer 41 and the opening 41a (FIG. 9C). The metal layer 41c is formed on the surface of the seed layer 41b by electrolytic plating (FIG. 9 (d)). After the step of flattening the metal layer 41c, the first wiring layer 41e having the wiring 41d is formed (FIG. 9 (e)).

  Subsequently, as shown in FIG. 10A, the second photosensitive resin layer 42A is formed on the surface of the first wiring layer 41e. Thereafter, the second organic insulating layer 42 having the opening 42a is formed by exposure and development of the second photosensitive resin layer 42A (FIG. 10 (b)). Then, a seed layer 42b for power supply for forming the metal layer 42c by electrolytic plating is formed on the surfaces of the second organic insulating layer 42 and the opening 42a (FIG. 10 (c)). A metal layer 42c is formed on the surface of the seed layer 42b by electrolytic plating (FIG. 10 (d)). After the step of flattening the metal layer 42c, the second wiring layer 42e having the wiring 42d is formed (FIG. 10 (e)).

  When the wiring layer of the multilayer structure is formed by the above semi-additive method, it is necessary to repeat the process of forming the seed layer, electrolytic plating and planarization, and it takes a long time to form the wiring layer. In addition to this, the damage to the wiring when etching the seed layer is large, and it is difficult to secure the adhesion strength of the wiring to the photosensitive resin layer. Furthermore, since the etching process and the like are repeated, the surface on which a fine structure is to be formed is roughened or anunrollment occurs, which causes problems in cost and yield. In the case of forming a fine wiring having a line width and a space width of, for example, 5 μm or less by using the semi-additive method, the yield tends to be greatly reduced.

  The present disclosure has been made to solve the above-described problems, and an object of the present disclosure is to provide a method capable of efficiently manufacturing a wiring layer as compared with the prior art.

  The present disclosure relates to a method of manufacturing a wiring layer. This manufacturing method comprises the steps of: (A) exposing a portion of the first photosensitive resin layer; (B) providing a second photosensitive resin layer on the surface of the first photosensitive resin layer; (C) exposing a part of the second photosensitive resin layer, and (D) developing the first and second photosensitive resin layers separately or collectively. Forming a first opening penetrating the photosensitive resin layer of the above, and forming a second opening whose bottom surface is the surface of the first photosensitive resin layer; (E) first and second steps Filling the opening of the conductive material with the conductive material.

  According to the above manufacturing method, the first and second openings formed through the steps (A) to (D) are filled with the conductive material at one time in the step (E), thereby forming the wiring. It can be formed. Therefore, the conventional method shown in FIGS. 9 and 10, that is, the method in which the formation of the metal layer by seed layer and electrolytic plating and the series of processes for planarizing the metal layer had to be repeated can be simplified. .

  When the said (D) process is a process which develops the 1st and 2nd photosensitive resin layer separately, the (D) process is the 1st implemented between the (A) process and the (B) process. And a second developing step for the second photosensitive resin layer performed between the (C) step and the (E) step. It should be a thing. In this case, it is preferable to further include a step of curing the first photosensitive resin layer between the first developing step and the step (B). By curing the first photosensitive resin layer prior to the step (B), either positive or negative type can be suitably used as the second photosensitive resin layer.

  When a negative photosensitive resin layer is used as the first photosensitive resin layer, it is preferable to develop the first and second photosensitive resin layers collectively in the step (D). In this case, the step of curing the first photosensitive resin layer prior to the step (B) can be omitted. For example, when both of the first and second photosensitive resin layers are negative, the unexposed portions of the first and second photosensitive resin layers may be removed at once in the step (D). When a negative photosensitive resin layer is used as the first photosensitive resin layer and a positive photosensitive resin layer is used as the second photosensitive resin layer, in the step (D), the unexposed area of the first photosensitive resin layer and the second photosensitive resin layer are exposed. And the exposed portion of the conductive resin layer may be removed at one time.

  In the present disclosure, a composition including, for example, a photoacid generator and a compound having a tertiary amino group or a nitrogen-containing heterocyclic ring can be used as the first and second photosensitive resin layers. Preferably, the composition further comprises an alkali soluble resin.

  According to the present disclosure, there is provided a method capable of efficiently manufacturing a wiring layer as compared to the prior art.

FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor package. FIG. 2 is a cross-sectional view showing the wiring layer shown in FIG. FIG. 3A to FIG. 3D are cross-sectional views schematically showing a process of forming a wiring layer according to an embodiment of the present disclosure. FIG. 4A to FIG. 4D are cross-sectional views schematically showing a process of forming a wiring layer according to an embodiment of the present disclosure. FIG. 5A and FIG. 5B are cross-sectional views schematically showing a process of forming a wiring layer according to an embodiment of the present disclosure. FIG. 6 is a cross-sectional view schematically showing a wiring layer provided on a substrate by the manufacturing method according to an embodiment of the present disclosure. FIGS. 7A and 7B are cross-sectional views schematically showing a wiring and a wiring layer including a barrier layer covering the wiring. 8 (a) is a cross-sectional view schematically showing a state in which a third organic insulating layer having an opening is formed on the surface of the second organic insulating layer, and FIG. 8 (b) is a cross-sectional view of FIG. It is sectional drawing which shows typically the state which filled the electroconductive material in the opening part shown to a). FIGS. 9A to 9E are cross-sectional views schematically showing the process of forming the first wiring layer in the conventional method (semi-additive method). 10 (a) to 10 (e) are cross-sectional views schematically showing the process of laminating the second wiring layer on the first wiring layer in the conventional method (semi-additive method).

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same or corresponding parts will be denoted by the same reference numerals and redundant description will be omitted. Further, the positional relationship such as upper, lower, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratio in the drawings is not limited to the illustrated ratio.

  When terms such as “left”, “right”, “front”, “back”, “upper”, “lower”, “upper” and “lower” are used in the description and claims of this embodiment, These are intended to be illustrative and do not necessarily mean they are permanently at this relative position. Moreover, in addition to the structure of the shape currently formed in the whole surface, a "layer" and a "film | membrane" also include the structure of the shape currently formed in one part, when it observes as a top view. In addition, the term "process" is included in the term if the intended purpose of the process is achieved, even if it is not only an independent process but can not be clearly distinguished from other processes. Moreover, the numerical range shown using "-" shows the range which includes the numerical value described before and after "-" as the minimum value and the maximum value, respectively. In addition, in the numerical range described step by step in the specification, the upper limit or the lower limit of the numerical range of one step may be replaced with the upper limit or the lower limit of the numerical range of another step.

  FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor package. The semiconductor package 100 shown in the figure includes the wiring layer 10A (first and second organic insulating layers 21 and 22 and the wiring 13 and the wiring 15A) manufactured by the method according to the present embodiment. The wiring layer 10 is formed through the process of forming the third organic insulating layer 23 and the like on the surface of the wiring layer 10A, and the semiconductor chip 2A and 2B is mounted on the surface of the wiring layer 10 and the like. The package 100 is completed. The wiring layer 10 is preferably used in a package form in which an interposer for mixing different types of chips is required, and is particularly suitable in a form in which miniaturization and multiple pins are required.

  As described above, the semiconductor package 100 is a device in which the semiconductor chips 2A and 2B are mounted on the wiring layer 10 provided on the substrate 1. The semiconductor chips 2A and 2B are respectively fixed on the wiring layer 10 by the underfills 3A and 3B, and are electrically connected to each other through the surface wiring 16 provided in the wiring layer 10.

  The substrate 1 is a sealing body formed by sealing the semiconductor chips 2C and 2D and the electrodes 5A and 5B with the insulating material 4. The semiconductor chips 2C and 2D in the substrate 1 can be connected to an external device through the electrodes exposed from the insulating material 4. The electrodes 5A and 5B function as, for example, conductive paths for electrically connecting the wiring layer 10 and an external device to each other. The insulating material 4 is, for example, a curable resin having an insulating property.

  Each of the semiconductor chips 2A to 2D is, for example, a graphic processing unit (GPU), a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory such as a flash memory. , RF chips, silicon photonics chips, MEMS (Micro Electro Mechanical Systems), sensor chips, etc. Each of the semiconductor chips 2A to 2D may have a TSV, or, for example, a semiconductor element may be stacked. In this case, semiconductor devices stacked using TSV can be used. The thickness of the semiconductor chips 2A and 2B is, for example, 200 μm or less. From the viewpoint of thinning the semiconductor package 100, the thickness of the semiconductor chips 2A and 2B is preferably 100 μm or less. Further, in terms of handling, the thickness of the semiconductor chips 2A and 2B is more preferably 30 μm or more.

  The underfills 3A and 3B are, for example, capillary underfill (CUF), mold underfill (MUF), paste underfill (NCP), film underfill (NCF), or photosensitive underfill. The underfills 3A and 3B are each composed mainly of a liquid curable resin (for example, an epoxy resin).

  Next, the wiring layer 10 will be described in detail with reference to FIG. The wiring layer 10 is an organic substrate supporting a semiconductor element or the like, and for example, a buildup substrate, a wafer level package substrate, a coreless substrate, a seal in which a glass cloth or a material (prepreg) in which a carbon fiber is impregnated with a resin is laminated. A substrate produced by heat curing a plug material, a substrate in which a chip is sealed or embedded. The shape of the wiring layer 10 corresponds to the shape of the substrate 11 described later, and may be wafer-like (substantially circular in plan view) or panel-like (substantially rectangular in plan view). In addition, it is preferable that the thermal expansion coefficient of the wiring layer 10 is 40 ppm / degrees C or less, for example from a viewpoint of curvature suppression. From the viewpoint of insulation reliability of the wiring layer 10, the thermal expansion coefficient is preferably 20 ppm / ° C. or less.

  As shown in FIG. 2, the wiring layer 10 is provided on the substrate 11. The wiring layer 10 includes an organic insulating laminate 12 including a plurality of organic insulating layers, a plurality of wires 13 arranged in the organic insulating laminate 12, and a through wire 15 penetrating the organic insulating laminate 12. A surface wiring 16 formed on the surface of the organic insulating laminate 12 and in the vicinity thereof is provided.

  The substrate 11 is a support for supporting the wiring layer 10. The shape of the substrate 11 in plan view is, for example, circular or rectangular. When circular, the substrate 11 has a diameter of, for example, 200 mm to 450 mm. In the case of a rectangular shape, one side of the substrate 11 is, for example, 300 mm to 700 mm.

  The substrate 11 is, for example, a silicon substrate, a glass substrate, or a peelable copper foil. Further, the substrate 11 may be, for example, a buildup substrate, a wafer level package substrate, a coreless substrate, a substrate manufactured by heat curing a sealing material, or a substrate in which a chip is sealed or embedded. When a silicon substrate, a glass substrate, or the like is used as the substrate 11, a temporary fixing layer (not shown) for temporarily fixing the wiring layer 10 and the substrate 11 may be provided. In this case, the substrate 11 can be easily peeled off from the wiring layer 10 by removing the temporary fixing layer. In addition, peelable copper foil is the laminated body which the support body, the peeling layer, and copper foil overlapped in order. In the peelable copper foil, the support corresponds to the substrate 11 and the copper foil corresponds to the material of a part of copper wiring included in the through wiring 15.

  The organic insulating laminate 12 includes a first organic insulating layer 21 (cured product of first photosensitive resin layer), a second organic insulating layer 22 (cured product of second photosensitive resin layer), and a second And three organic insulating layers 23, and these layers are stacked in this order from the substrate 11 side. The organic insulating laminate 12 has an opening H in which the through wiring 15 is provided, and a groove T in which the wiring 13 is provided. The first and second organic insulating layers 21 and 22 have an opening Ha (a part of the opening H) in which the wiring 15A (a part of the through wiring 15) is provided (see FIG. 2).

  The groove portion T is provided on the surface of the second organic insulating layer 22 opposite to the substrate 11. In the cross section along the direction orthogonal to the extending direction of the groove T, the groove T has a substantially rectangular shape. That is, the trench T has a bottom surface formed of the surface of the first organic insulating layer 21 and a side surface extending from there to the third organic insulating layer 23. The plurality of grooves T have a predetermined line width L and space width S. Each of the line width L and the space width S is, for example, 0.5 μm to 10 μm, preferably 0.5 μm to 5 μm, and more preferably 2 μm to 5 μm. From the viewpoint of realizing high density transmission of the wiring layer 10, the line width L is preferably 1 μm to 5 μm. The line width L and the space width S may be set to be the same as each other, or may be set to be different from each other. The line width L corresponds to the width (width L in FIG. 2) of the groove T in the direction orthogonal to the extending direction of the groove T. The space width S corresponds to the distance between adjacent groove portions T (width S in FIG. 2). The depth of the trench T corresponds to, for example, the thickness of the second organic insulating layer 22. The cross-sectional shape of the groove T is not limited to the substantially rectangular shape, but may be another shape (for example, a substantially semicircular shape).

  The surface roughness of the inner surface of the groove T is preferably 0.01 μm to 0.1 μm. When the surface roughness is 0.01 μm or more, the adhesion of the object in close contact with the first and second organic insulating layers 21 and 22 in the trench T and the temperature cycle resistance become good. The term "temperature cycle resistance" as used herein refers to resistance to volume change, performance deterioration, breakage and the like caused by temperature change. Further, when the surface roughness is 0.1 μm or less, a short circuit of the wiring 13 can be suppressed, and the high frequency characteristics of the wiring 13 can be improved. The surface roughness of the inner surface of the groove T is calculated, for example, by observing the cross section of the groove T with an electron microscope. In addition, the said surface roughness is arithmetic mean roughness (Ra) prescribed | regulated by JISB06012001, and let the following "surface roughness" be all "surface roughness Ra."

  The storage elastic modulus at room temperature of the first and second organic insulating layers 21 and 22 is, for example, 500 MPa to 1000 GPa. The term "room temperature" as used herein indicates about 25 ° C. When the storage elastic modulus is 500 MPa or more, stretching of the organic insulating layers 21 and 22 can be suppressed. For example, in the process of grinding the organic insulating layer 22, the organic insulating layer 22 stretched along with the grinding can be prevented from covering the wiring 13. Further, when the storage elastic modulus is 10 GPa or less, for example, breakage of the grinding blade can be prevented, and as a result, the surface of the second organic insulating layer 22 or the like can be prevented from being excessively rough.

  The thickness of the first and second organic insulating layers 21 and 22 is, for example, 0.5 μm to 10 μm, respectively. When the thickness of each of the first and second organic insulating layers 21 and 22 is 0.5 μm or more, the first and second organic insulating layers 21 and 22 contribute to stress relaxation in the organic insulating laminate 12. The temperature cycle resistance of the organic insulating laminate 12 may be improved. When the thickness of the first and second organic insulating layers 21 and 22 is 10 μm or less, warpage of the organic insulating laminate 12 is suppressed. For example, when the organic insulating laminate 12 is ground, wiring is easily performed. Etc. can be exposed. From the viewpoint of forming the wiring 13 having a width of 3 μm or less by performing exposure and development, the thickness of the second organic insulating layer 22 is preferably 7 μm or less.

  The first, second and third organic insulating layers 21, 22, 23 are each made of a cured product of a photosensitive resin composition. From the viewpoint of the flatness and the production cost of these layers, it is preferable to use a material (a film-like organic insulating material) previously formed in a film-like shape for the formation of these layers. In this case, for example, even if the surface roughness of the substrate 11 is 300 μm or more, a layer having a sufficiently small surface roughness value can be formed. Preferably, the film-like organic insulating material is capable of being laminated at 40 ° C to 120 ° C. By setting the temperature that can be laminated to 40 ° C. or higher, it is possible to suppress the increase in tackiness (tackiness) of the organic insulating material at room temperature and to maintain good handleability. By setting the temperature that can be laminated to 120 ° C. or less, the occurrence of warpage in the organic insulating laminate 12 can be suppressed.

  The thermal expansion coefficient of the organic insulating material after curing is, for example, 80 ppm / ° C. or less from the viewpoint of suppressing the warpage of the organic insulating layers 21, 22, 23 (and the organic insulating laminate 12). From the viewpoint of insulation reliability of the wiring layer 10, the thermal expansion coefficient is preferably 70 ppm / ° C. or less. Moreover, it is more preferable that the said thermal expansion coefficient is 20 ppm / degrees C or more from the viewpoint of the stress relaxation property of an organic insulating material, and a process precision.

Although the photosensitive resin composition for forming the 1st, 2nd and 3rd organic insulation layers 21, 22, 23 may employ either a negative type or a positive type, it has mechanical reliability. It is preferable to adopt a negative type from the viewpoint of simplification of the production process. As the photosensitive resin composition, a layer (thickness 5 μm) comprising the composition is irradiated with light of 365 nm at 850 mJ / cm ² and heated at 80 ° C. for 4 minutes, and the melt viscosity at 40 ° C. is 1.0. × ¹⁰ 3 Pa · s or higher (more preferably ^{1.0 × 10 3 ~1.0 × 10 9} Pa · s) is. By adopting a photosensitive resin composition that satisfies this condition, after exposing a part of the layer (for example, the first organic insulating layer (uncured)) made of the composition, the exposed area is Layer (for example, a second organic insulating layer (uncured)) can be laminated. After exposing a part of the next layer, it becomes possible to develop two layers (for example, the first and second organic insulating layers (uncured)) together.

  Examples of the photosensitive resin composition for forming the organic insulating layers 21, 22, and 23 include a composition containing at least a photoacid generator and a compound having a tertiary amino group or a nitrogen-containing heterocyclic ring. Preferably, the composition further comprises an alkali soluble resin. Such a photosensitive resin composition can be prepared to be either negative or positive.

  It will not specifically limit, if it is a compound which generate | occur | produces an acid by light irradiation as a photo-acid generator. From the viewpoint of efficiently generating an acid, the photoacid generator is preferably, for example, an onium salt compound or a sulfoneimide compound. As an onium salt compound, an iodonium salt or a sulfonium salt is mentioned, for example. Specific examples include diphenyliodonium trifluoromethanesulfonate, diphenyliodonium p-toluenesulfonate, diphenyliodonium hexafluoroantimonate, diphenyliodonium hexafluorophosphate, diaryliodonium salts such as diphenyliodonium tetrafluoroborate, triphenylsulfonium trifluoromethanesulfonate, and triphenylsulfonium trifluoromethanesulfonate Triarylsulfonium salts such as phenylsulfonium p-toluenesulfonate, triphenylsulfonium hexafluoroantimonate, 4-tert-butylphenyl-diphenylsulfonium p-toluenesulfonate, 4,7-di-n-butoxynaphthyltetrahydrothiophenium trifluoride And methanesulfonate and the like. Specific examples of sulfonimide compounds include N- (trifluoromethylsulfonyloxy) succinimide, N- (trifluoromethylsulfonyloxy) phthalimide, N- (trifluoromethylsulfonyloxy) diphenylmaleimide, N- (trifluoromethylsulfonyl) Oxy) bicyclo [2.2.1] hept-5-ene-2,3-dicarboximide, N- (trifluoromethylsulfonyloxy) naphthalimide, N- (p-toluenesulfonyloxy) -1,8- Naphthalimide, N- (10-camphorsulfonyloxy) -1,8-naphthalimide and the like can be mentioned.

  From the viewpoint of resolution, a compound having a trifluoromethanesulfonate group, a hexafluoroantimonate group, a hexafluorophosphate group, or a tetrafluoroborate group may be used as the photoacid generator.

  Examples of compounds having a tertiary amino group or nitrogen-containing heterocycle include dimethylaminopropylamine, diethylaminopropylamine, di-n-propylaminopropylamine, dibutylaminopropylamine, dimethylaminoethylamine, diethylaminoethylamine, N-methylpiperazine and the like. Amine compounds of the formula: primary or secondary amines having a tertiary amino group in the molecule, such as imidazole compounds such as 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole etc. 2-Dimethylaminoethanol, 1-methyl-2-dimethylaminoethanol, 1-phenoxymethyl-2-dimethylaminoethanol, 2-diethylaminoethanol, 1-butoxymethyl-2-dimethylamino Tanol, 1- (2-hydroxy-3-phenoxypropyl) -2-methylimidazole, 1- (2-hydroxy-3-phenoxypropyl) -2-ethyl-4-methylimidazole, 1- (2-hydroxy-3) -Butoxypropyl) -2-methylimidazole, 1- (2-hydroxy-3-butoxypropyl) -2-ethyl-4-methylimidazole, 1- (2-hydroxy-3-phenoxypropyl) -2-phenylimidazoline, 1- (2-hydroxy-3-butoxypropyl) -2-methylimidazoline, 2- (dimethylaminomethyl) phenol, 2,4,6-tris (dimethylaminomethyl) phenol, N-β-hydroxyethyl morpholine, 2 -Dimethylaminoethanethiol, 2-mercaptopyridine, 2-benzoimida Zole, benzotriazole, diethylaminobenzophenone, 2-mercaptobenzoimidazole, 2-mercaptobenzothiazole, 4-mercaptopyridine, N, N-dimethylaminobenzoic acid, N, N-dimethylglycine, nicotinic acid, isonicotinic acid, picolinic acid Alcohols having a tertiary amino group in the molecule, such as N, N-dimethylglycine hydrazide, N, N-dimethylpropionic acid hydrazide, nicotinic acid hydrazide, isonicotinic acid hydrazide, etc .; phenols, thiols, carbonic acid Acids and hydrazides, etc., 1,3,4,6-tetrakis (methoxymethyl) glycoluril, isocyanuric acid EO modified epoxy and epoxys such as diacrylate and triacrylate, acrylates, methylols, etc., but limited thereto Also Not.

  The alkali-soluble resin is not particularly limited as long as it has a phenolic hydroxyl group and / or carboxyl group, but polyester resins, polyether resins, polyimide resins, polyamide resins, polyamideimide resins, polyetherimide resins, polyurethane resins, Polyurethane imide resin, polyurethane amide imide resin, siloxane polyimide resin, polyester imide resin, and copolymers of these and their precursors (polyamic acid etc.), polybenzoxazole resin, phenoxy resin, polysulfone resin, poly Ether sulfone resin, polyphenylene sulfide resin, polyester resin, polyether resin, polycarbonate resin, polyether ketone resin, (meth) acrylic copolymer, novolac resin, and fe Lumpur resins and the like although not limited thereto.

  The photosensitive resin composition is preferably soluble in a 2.38 mass% tetramethylammonium aqueous solution (TMAH aqueous solution). From the viewpoint of resolution, storage stability, and insulation reliability of the photosensitive resin composition, the photosensitive resin composition preferably contains a compound having a phenolic hydroxyl group. Examples of compounds having a phenolic hydroxyl group include phenol / formaldehyde condensation novolak resin, cresol / formaldehyde condensation novolac resin, phenol-naphthol / formaldehyde condensation novolac resin, polyhydroxystyrene and its polymer, phenol-xylylene glycol condensation resin, cresol- Xylylene glycol condensation resin, phenol-dicyclopentadiene condensation resin, etc. are mentioned.

  The photosensitive resin composition preferably contains a thermosetting resin. As a thermosetting resin, for example, acrylate resin, epoxy resin, cyanate ester resin, maleimide resin, allyl nadiimide resin, phenol resin, urea resin, melamine resin, alkyd resin, unsaturated polyester resin, diallyl phthalate resin, silicone resin , Resorcinol formaldehyde resin, triallyl cyanurate resin, polyisocyanate resin, resin containing tris (2-hydroxyethyl) isocyanurate, resin containing triallyl trimellitate, thermosetting resin synthesized from cyclopentadiene Can be mentioned. From the viewpoint of the resolution of the photosensitive resin composition, the insulation reliability, and the adhesion to a metal, the thermosetting resin is more preferably a compound having any of a methylol group, an alkoxyalkyl group, and a glycidyl group. preferable.

  The photosensitive resin composition may further contain a cohesion aid. As a close_contact | adherence adjuvant, a silane coupling agent, a triazole or tetrazole type compound is mentioned, for example.

  The first, second and third organic insulating layers 21, 22, 23 may contain a filler. The content of the filler in each layer is preferably less than 1% by mass. The average particle diameter of the filler is, for example, 500 nm or less from the viewpoint of processability and processing accuracy. More preferably, the first, second and third organic insulating layers 21, 22, 23 do not contain a filler.

  The plurality of wires 13 are provided in the corresponding grooves T as described above, and function as conductive paths in the wiring layer 10. For this reason, the width of the wiring 13 substantially coincides with the line width L of the groove T, and the interval between the adjacent wirings 13 substantially coincides with the space width S of the groove T. The wiring 13 preferably contains a metal material having high conductivity from the viewpoint of exhibiting the function as a conductive path well. The metal material having high conductivity is, for example, copper, aluminum or silver. These metal materials tend to diffuse into the organic insulating laminate 12 by heating. From the viewpoint of conductivity and cost, the metal material contained in the wiring 13 is preferably copper.

  The wiring 13 is preferably covered with a barrier metal film 14 for suppressing diffusion of the metal material constituting the wiring into the organic insulating laminate 12. The barrier metal film 14 is a first barrier metal film 31 provided between the wiring 13 and the inner surface of the trench T, and a second barrier metal film provided between the wiring 13 and the third organic insulating layer 23. And 32. The first barrier metal film 31 is provided to separate the wiring 13 and the inner surface of the trench T (the first organic insulating layer 21 and the second organic insulating layer 22). The second barrier metal film 32 is provided to separate the wiring 13 and the third organic insulating layer 23.

  The first barrier metal film 31 contains, for example, at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold as a metal material that does not easily diffuse into the organic insulating layer. From the viewpoint of adhesion with the inner surface of the groove T, the first barrier metal film 31 is preferably a titanium film or an alloy film containing titanium. Further, from the viewpoint of forming the first barrier metal film 31 by sputtering, the first barrier metal film 31 is at least any of a titanium film, a tantalum film, a tungsten film, a chromium film, or titanium, tantalum, tungsten, and chromium. It is preferable that it is an alloy film containing a carbon.

  The thickness of the first barrier metal film 31 is less than half the width of the groove T and less than the depth of the groove T, and is, for example, 0.001 μm to 0.5 μm. From the viewpoint of preventing the diffusion of the metal material in the wiring 13, the thickness of the first barrier metal film 31 is preferably 0.01 μm to 0.5 μm. Further, from the viewpoint of increasing the flatness of the first barrier metal film 31 and increasing the amount of current flowing through the wiring 13, the thickness of the first barrier metal film 31 is preferably 0.001 μm to 0.3 μm. . From the above, the thickness of the first barrier metal film 31 is most preferably 0.01 μm to 0.3 μm.

  The second barrier metal film 32 contains, for example, at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, cobalt, and gold as a metal material that does not easily diffuse into the organic insulating layer. The second barrier metal film 32 may be a laminate of different metal films.

  The second barrier metal film 32 is preferably a plating film (for example, an electroless plating film) using the wiring 13 as a seed layer. Therefore, the second barrier metal film 32 should be a nickel plating film, a palladium plating film, a cobalt plating film, a gold plating film, or an alloy plating film containing at least one of nickel, palladium, cobalt, and gold. preferable. A nickel plating film or a palladium plating film is preferable from the viewpoint of adhesion to the wiring 13 and temperature cycle resistance.

  Examples of the nickel plating film include electroless nickel-phosphorus alloy plating film containing phosphorus, electroless nickel-boron alloy plating film containing boron, and electroless nickel-nitrogen alloy plating film containing nitrogen. . The nickel content of the nickel plating film is preferably 80% by mass or more. When the nickel content is 80% by mass or more, the effect of improving the insulation reliability of the wiring layer 10 by the second barrier metal film 32 is well exhibited. The nickel plating film is preferably an electroless nickel-phosphorus alloy plating film from the viewpoint of insulation reliability.

  The second barrier metal film 32 is preferably an electroless palladium plating film from the viewpoint of obtaining good insulation reliability with a thickness of 0.1 μm or less. As the electroless palladium plating film, for example, a substituted palladium plating film, an electroless palladium plating film using a formic acid compound as a reducing agent, a palladium-phosphorus alloy plating film using hypophosphorous acid or phosphorous acid as a reducing agent Or a palladium-boron alloy plated film using a boron compound.

  The thickness of the second barrier metal film 32 is, for example, 0.001 μm to 1 μm. From the viewpoint of the yield of the second barrier metal film 32, the thickness of the second barrier metal film 32 is preferably 0.01 μm to 1 μm. In addition, from the viewpoint of improving the production tact of the second barrier metal film 32, thinning, and temperature cycle resistance, the thickness is more preferably 0.001 μm to 0.5 μm. From the viewpoint of thinning of the second barrier metal film 32 and resolution of the photosensitive resin composition, the thickness is more preferably 0.001 μm to 0.3 μm. From the above viewpoint, the thickness of the second barrier metal film 32 is most preferably 0.01 μm to 0.3 μm.

  The surface roughness Ra of the second barrier metal film 32 is, for example, 0.01 μm to 1 μm. When the surface roughness Ra of the second barrier metal film 32 is 0.01 μm or more, reliability such as adhesion between the second barrier metal film 32 and the third organic insulating layer 23 and temperature cycle resistance is obtained. It becomes possible to secure. When the surface roughness Ra of the second barrier metal film 32 is 1 μm or less, disconnection and the like in the wiring layer 10 due to the unevenness generated at the time of formation of the third organic insulating layer 23 can be suppressed and the organic insulating laminate A reduction in resolution of 12 can be suppressed. From the viewpoint of adhesion to the third organic insulating layer 23, the surface roughness Ra of the second barrier metal film 32 is preferably 0.03 μm or more. From the viewpoint of temperature cycle resistance, the surface roughness Ra of the second barrier metal film 32 is preferably 0.5 μm or less. From the viewpoint of high frequency characteristics, the surface roughness Ra of the second barrier metal film 32 is more preferably 0.1 μm or less. From the above viewpoint, the surface roughness Ra of the second barrier metal film 32 is most preferably 0.03 μm to 0.1 μm.

  Moreover, in the wiring layer 10, surface roughness Ra of the surface which combined the 2nd organic insulating layer 22 and the 2nd barrier metal film 32 is 0.01 micrometer-1 micrometer, for example. When the surface roughness Ra of the above surface is 0.01 μm or more, the adhesion between the second organic insulating layer 22 (and the second barrier metal film 32) and the third organic insulating layer 23 is good. Become. Moreover, when the surface roughness of the said surface is 1 micrometer or less, the curvature of the organic insulation laminated body 12 is suppressed, for example, when grinding the organic insulation laminated body 12, wiring etc. can be exposed easily. The surface roughness Ra of the surface is, for example, 100 × including both the second organic insulating layer 22 and the second barrier metal film 32 using a laser microscope (“LEXT OLS 3000” manufactured by Olympus Corporation). Calculated by scanning a 100 μm range.

  The surface roughness Ra of the above-described surface including the second organic insulating layer 22 and the second barrier metal film 32 can be controlled by planarizing the wiring 13 and the second organic insulating layer 22. As a planarization process to the said surface, a chemical mechanical polishing method (CMP: Chemical Mechanical Polishing) or a fly-cut method is mentioned, for example. From the viewpoint of suppressing the occurrence of dishing on the wiring 13, it is preferable to use a fly-cut method. The fly-cut method is a method of physically grinding an object using a grinding device such as a surface planar.

  The through wiring 15 is a wiring embedded in the opening H of the organic insulating laminate 12 and functions as a connection terminal to an external device. The through wiring 15 is composed of a plurality of metal layers 15 a to 15 c stacked on one another. The metal layer 15 b includes a wire 15 A formed simultaneously with the wire 13 and a metal film formed simultaneously with the barrier metal film 14. The through wiring 15 preferably has a via shape, and the via diameter is, for example, 1 μm to 20 μm, preferably 1 μm to 5 μm, and more preferably 2 μm to 5 μm.

  The surface wiring 16 is a wiring for electrically connecting the semiconductor chips mounted on the wiring layer 10. Therefore, both ends of the surface wiring 16 are exposed from the wiring layer 10, and the surface wiring 16 other than the both ends is embedded in the wiring layer 10 (more specifically, the third organic insulating layer 23). It is done. For this reason, the third organic insulating layer 23 includes at least two organic insulating layers.

  Hereinafter, a method of manufacturing the wiring layer 10A will be described with reference to FIGS. 3 to 5. The manufacturing method according to the present embodiment includes (A) exposing a part of the first photosensitive resin layer 21A, and (B) a second photosensitive resin on the surface of the first photosensitive resin layer 21A. The step of providing the layer 22A, (C) the step of exposing a part of the second photosensitive resin layer 22A, and (D) developing the first and second photosensitive resin layers 21A and 22A collectively Thereby forming the opening Ha penetrating the first and second photosensitive resin layers 21A and 22A and forming the groove Ta having the surface of the first photosensitive resin layer 21A as the bottom surface; E) filling the opening Ha and the groove Ta with a conductive material.

  The first and second photosensitive resin layers 21A and 22A are layers to be the first and second organic insulating layers 21 and 22 by being subjected to curing treatment, and the first and second photosensitive layers The opening Ha penetrating the resin layers 21A and 22A is a part of the opening H, and the groove Ta having a bottom surface of the first photosensitive resin layer 21A is a groove T.

  According to the above manufacturing method, in the step (E), the wiring is formed by collectively filling the conductive material into the opening Ha and the groove Ta formed through the steps (A) to (D). be able to. Therefore, the conventional method shown in FIGS. 9 and 10, that is, the method in which the formation of the metal layer by seed layer and electrolytic plating and the series of processes for planarizing the metal layer had to be repeated can be simplified. .

  A method of manufacturing the wiring layer 10A will be specifically described. Note that FIGS. 3 to 5 illustrate the configuration in a simplified manner as compared to the wiring layer 10A shown in FIG. 2 so as to make it easier to compare with the conventional method shown in FIGS.

  First, as shown in FIG. 3A as the first step, the metal layer 15 a is formed on the substrate 11. The metal layer 15 a is formed by patterning a metal film formed on the substrate 11. In the first step, the metal film is formed by, for example, a coating method, a physical vapor deposition method (PVD method) such as vacuum deposition or sputtering, a printing method using metal paste or a spray method, or various plating methods. . In the present embodiment, copper foil is used as the metal film.

  When a temporary fixing layer (not shown) is provided between the substrate 11 and the metal layer 15a, the temporary fixing layer may be, for example, a resin containing a nonpolar component such as polyimide, polybenzoxazole, silicon, fluorine, etc., heating Alternatively, it contains a resin containing a component that expands or foams by UV (ultraviolet light), a resin containing a component that causes a crosslinking reaction to proceed by heating or UV, or a resin that generates heat by light irradiation. Examples of the method for forming the temporary fixing layer include spin coating, spray coating, and lamination. From the viewpoint of achieving a high degree of compatibility between the handling property and the carrier releasability, the temporary fixing layer is preferably easy to be peeled off by an external stimulus such as light or heat. From the viewpoint of being separable so that the temporary fixing layer does not remain in the wiring layer 10 to be manufactured later, the temporary fixing layer most preferably contains a resin that expands in volume due to heat treatment.

  When the temporary fixing layer is provided between the substrate 11 and the metal layer 15a, the metal layer 15a may be formed of a copper foil of peelable copper foil. In this case, the substrate 11 corresponds to the support of the peelable copper foil, and the temporary fixing layer corresponds to the release layer of the peelable copper foil.

  As a second step, as shown in FIG. 3B, a first photosensitive resin layer 21A made of a negative photosensitive resin composition is formed on the substrate 11 so as to cover the metal layer 15a.

  In the third step, a photomask is disposed on the first photosensitive resin layer 21A, and the first photosensitive resin layer 21A is exposed except for the area to be the opening H (step (A)). Thereby, as FIG.3 (c) shows, the exposure part 21a and the unexposed part 21b are formed in 21A of 1st photosensitive resin layers. As a method of exposing the first photosensitive resin layer 21A, a known projection exposure method, a contact exposure method, a direct drawing exposure method or the like can be used.

  As a fourth step, as shown in FIG. 3D, the second photosensitive resin layer 22A is formed on the surface of the first photosensitive resin layer 21A after the exposure processing (step (B)).

  As a fifth step, a photomask is disposed on the second photosensitive resin layer 21A, and the second photosensitive resin layer 22A is exposed except for the area to be the opening H and the groove T (step (C)). As a result, as shown in FIG. 4A, the exposed portion 22a and the unexposed portion 22b are formed in the second photosensitive resin layer 22A. As a method of exposing the second photosensitive resin layer 22A, a known projection exposure method, a contact exposure method, a direct drawing exposure method or the like can be used.

  As shown in FIG. 4B, the first and second photosensitive resin layers 21A, 21A, and 21A are developed by collectively developing the first and second photosensitive resin layers 21A and 22A as the sixth step. While forming the opening part Ha which penetrates 22A, groove part Ta which uses the surface of the 1st photosensitive resin layer 21A as a bottom face is formed in the 2nd photosensitive resin layer 22A ((D) process). For development processing (removal of unexposed portions 21b and 22b), for example, an alkaline aqueous solution such as sodium carbonate or TMAH, an organic solvent such as propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), or cyclopentanone Can be used.

  As a seventh step, the first and second photosensitive resin layers 21A and 22A after development are cured by heating. For example, the heating temperature is set to 100 to 200 ° C., and the heating time is set to 30 minutes to 3 hours. As a result, as shown in FIG. 4C, the first and second photosensitive resin layers 21A and 22A become the first and second insulating resin layers 21 and 22, respectively.

  As the eighth step, as shown in FIG. 4D, the first barrier metal film 31 is formed to cover the surface of the second insulating resin layer 22 and the inner surfaces of the opening Ha and the groove T. In the eighth step, the first barrier metal film 31 is formed by, for example, a coating method, a PVD method, a printing method using a metal paste or a spray method, or various plating methods. In the case of the application method, the first barrier metal film 31 is formed by applying a complex of palladium or nickel followed by heating. When a metal paste is used, a paste containing metal particles such as nickel or palladium is applied onto the surface of the second insulating resin layer 22 and the inner surface of the opening Ha and the groove T and then sintered. A barrier metal film 31 is formed.

  As a ninth step, as shown in FIG. 5A, the metal layer 13A is formed on the first barrier metal film 31 so as to fill the opening Ha and the groove T. In the ninth step, the metal layer 13A is formed by, for example, a method using a metal paste or a plating method using the first barrier metal film 31 as a seed layer. The thickness of the metal layer 13A is preferably 0.5 to 3 times the total thickness of the first and second organic insulating layers 21 and 22. When the thickness of the metal layer 13A is 0.5 times or more, the expansion of the surface roughness Ra of the wiring 13 formed in the later step can be suppressed. When the thickness of the metal layer 13A is 3 times or less, the warp of the metal layer 13A is suppressed, and the metal layer 13A tends to adhere well to the second organic insulating layer 22.

  As shown in FIG. 5B as the tenth step, the second organic insulating layer 22 is exposed by removing the metal layer 13A on the second organic insulating layer 22 and the first barrier metal film 31. . Wiring 15A is formed by filling metal in opening Ha. Wiring 13 is formed by filling the inside of trench T with metal. After removing the metal layer 13A and the first barrier metal film 31, a process of planarizing the surface of the second organic insulating layer 22 may be performed. In this case, CMP or a fly-cut method may be employed.

  When CMP is used in the tenth step, for example, a slurry containing alumina generally used for polishing a resin, and hydrogen peroxide and silica used for polishing the first barrier metal film 31 are blended. And the slurry containing hydrogen peroxide and ammonium persulfate used for polishing the metal layer 13A. From the viewpoint of reducing the cost and controlling the surface roughness Ra to 0.01 μm to 1 μm, the second organic insulating layer 22, the first barrier metal film 31, and the metal layer 13A can be formed using a slurry containing alumina. It is preferable to grind (wiring 13). When the second organic insulating layer 22, the first barrier metal film 31 and the metal layer 13A (the interconnections 13 and 15A) are simultaneously planarized, the differences in the polishing rate cause dishing in the interconnections 13 and 15A. The flatness of the combined surface of the second organic insulating layer 22 and the wires 13 and 15A tends to be greatly impaired. Therefore, from the viewpoint of setting the surface roughness Ra of the above surface to 0.03 μm to 0.1 μm, the second organic insulating layer 22, the first barrier metal film 31 and the metal layer are formed by the fly-cut method using a surface planar. It is more preferable to grind 13A (wirings 13, 15A).

  Through the above steps, the wiring layer 10A having a multilayer structure shown in FIG. 5B can be formed on the substrate 11. The wiring layer shown in FIG. 5 (b) can be manufactured by a simple process as compared with the wiring layer of the multilayer structure shown in FIG. 10 (e). Further, the wiring layer shown in FIG. 5B has an advantage of being able to form the wiring 15A having excellent conductivity as compared with the wiring layer shown in FIG. 10E. That is, while the wiring 15A shown in FIG. 5 (b) is made of metal filled in the opening Ha in one process, the through wiring shown in FIG. 10 (e) is formed through two processes. The sheet layer remains inside.

  FIG. 6 is a diagram showing in detail the configuration after the first and second organic insulating layers 21 and 22 and the wiring 15A and the wiring 13 are formed on the substrate 11 through the above steps. From the state shown in this figure, through the following steps, a member including the wiring layer shown in FIG. 2 is manufactured.

  As shown in FIGS. 7A and 7B, a second barrier metal film 32 is formed so as to cover the wiring 13 formed in the trench T. In this step, for example, the second barrier metal film 32 is formed by a PVD method, a method using a metal paste, or a plating method using the wiring 13 as a seed layer. From the viewpoint of forming the second barrier metal film 32 with high selectivity on the wiring 13, it is preferable to form the second barrier metal film 32 by plating using the wiring 13 as a seed layer. Before the plating process, the exposed second organic insulating layer 22 may be cleaned with an acid or protected with a benzotriazole or the like. Note that the metal layer 15b is formed on the metal layer 15a by passing through this step.

  In this step, the second barrier metal film 32 is preferably formed on the portion of the first barrier metal film 31 in contact with the side surface of the trench T in addition to the wiring 13. In this case, the wiring 13 can be covered without gaps by the first barrier metal film 31 and the second barrier metal film 32.

  After a third photosensitive resin layer (not shown) is formed by applying a photosensitive resin composition on the surface of the second organic insulating layer 21, exposure and development processes thereof are performed, as shown in FIG. 8 (a). As shown in FIG. 5, the third organic insulating layer 23 having the opening 23a is formed. Further, as shown in FIG. 8B, the wiring layer 10 is manufactured by forming the metal layer 15c in the opening 23a and forming the surface wiring 16 (see FIG. 2) and the like. When the temporary fixing layer is provided, the wiring layer 10 may be peeled off from the substrate 11. By repeating the above-described steps, a plurality of wiring layers 10A (layers formed of the wiring 13, the metal layer 15b, and the first and second organic insulating layers 21 and 22) shown in FIG. It is also good.

  As mentioned above, although embodiment of this indication was described, this indication is not limited to embodiment mentioned above, You may change suitably in the range which does not deviate from the meaning. For example, in the above embodiment, a negative type photosensitive resin composition is used as the photosensitive resin composition for forming the first and second photosensitive resin layers 21A and 22A, and the development processing of these layers is collectively performed. Although the case where it carries out was illustrated, while using a positive thing as a photosensitive resin composition which comprises at least one of these layers, it is after the exposure processing of the 1st photosensitive resin layer 21A, and 2nd photosensitive property Before the exposure process of the resin layer 22A, the development process of the first photosensitive resin layer 21A and the curing process may be performed as needed.

  The present invention is further described in detail by the following examples, but the present invention is not limited to these examples.

(Photosensitive resin composition)
1,3,4,6-Tetrakis (methoxymethyl) glycoluril (30 parts by mass), trimethylolpropane triglycidyl ether (40 parts by mass) based on cresol novolak resin TR-4020G (100 parts by mass) manufactured by Asahi Organic Materials Co., Ltd. Part), triaryl sulfonium salt CPI-310B (8 mass parts), and PGMEA (100 mass parts) were mix | blended, and the photosensitive resin composition was obtained.

Example 1
(Formation of first layer via pattern)
A photosensitive resin composition is applied by spin coating on the surface of an 8-inch silicon wafer on which alignment marks have been formed so that the film thickness after drying is 3 μm, and then heat dried on a hot plate at 100 ° C. for 5 minutes Thus, the first photosensitive resin layer was formed. An i-line at 850 mJ / cm ² through a mask designed to form a via with an opening diameter of 7 μm on the obtained photosensitive resin layer using an i-line stepper exposure machine (UX74101 manufactured by Ushio Inc.) Irradiated. The photosensitive resin layer after exposure was heated on a hot plate at 85 ° C. for 4 minutes, and then paddle developed at 25 ° C. for 50 seconds using a 2.38% aqueous TMAH solution. The resulting sample was heat cured at 180 ° C. for 1 hour.

(Formation of second layer via and trench pattern)
The photosensitive resin composition is applied by spin coating on the surface of the photosensitive resin layer after development and curing treatment in the above sample so that the film thickness after drying is 3 μm, and heated at 100 ° C. for 5 minutes on a hot plate. It was dry. A via with an opening diameter of 9 μm and a trench (line width L: 2 μm, space width S: 2 μm) are formed in the obtained photosensitive insulating layer using an i-line stepper exposure machine (UX74101 manufactured by Ushio Inc.) The i-line was irradiated at 850 mJ / cm ² through the designed mask. The photosensitive resin layer after exposure was heated on a hot plate at 85 ° C. for 4 minutes, and then paddle developed at 25 ° C. for 50 seconds using a 2.38% aqueous TMAH solution. The resulting sample was heat cured at 180 ° C. for 1 hour. In the irradiation of the i-line, alignment is performed so that the central portions of the via (opening diameter 7 μm) of the first photosensitive resin layer and the via (opening diameter 9 μm) of the second photosensitive resin layer coincide with each other. did.

(Metal layer formation)
Using a sputtering apparatus, a target vacuum pressure is 5 × 10 ⁻⁴ Pa, sputtering pressure is 0.9 Pa, sputtering power is DC 3000 W, reverse sputtering condition is 1000 W for 5 minutes, 50 nm thick titanium layer, then 200 nm thick Copper layer was formed. Then, it is immersed in a 100 mL / L aqueous solution of ICP clean S-135 (Okuno Pharmaceutical Industry Co., Ltd.) which is an acidic degreasing solution for 1 minute at 50 ° C., 1 minute with 50 ° C. pure water, and 1 minute with 25 ° C. pure water. After washing with water, it was immersed in 10% sulfuric acid at 25 ° C. for 1 minute. Then, copper sulfate _{(CuSO 4 · 5H 2 O)} 120g / L, 96% aqueous solution of 7.3L of sulfuric acid 220 g / L, hydrochloric acid 0.25 mL, TOP LUCINA GT-3 (manufactured by Okuno Chemical Industries Co., Ltd.) 10 mL, TOP LUCINA Electrolytic copper plating was performed using a copper sulfate bath prepared by adding 1 mL of GT-2 (Okuno Pharmaceutical Industries Co., Ltd.) at a liquid temperature of 25 ° C., a current density of 1.5 A / dm ² , and a plating time of 30 minutes. . After plating, it was washed with pure water and dried on an 80 ° C. hot plate for 5 minutes. Annealed at 180 ° C. for 60 minutes in a clean oven. When the cross section of the wiring layer formed through these steps was enlarged and observed, it was confirmed that the vias and the trenches were opened without any problem and these were filled with copper.

Example 2
(1st layer via pattern exposure)
A photosensitive resin composition is applied by spin coating on the surface of an 8-inch silicon wafer on which alignment marks have been formed so that the film thickness after drying is 3 μm, and then heat dried on a hot plate at 100 ° C. for 5 minutes Thus, the first photosensitive resin layer was formed. An i-line at 850 mJ / cm ² through a mask designed to form a via with an opening diameter of 7 μm on the obtained photosensitive insulating layer using an i-line stepper exposure machine (UX74101 manufactured by Ushio Inc.) Irradiated. The exposed photosensitive resin layer was heated at 85 ° C. for 4 minutes on a hot plate.

(Formation of second layer via and trench pattern)
The photosensitive resin composition is applied by spin coating on the surface of the photosensitive resin layer after exposure post-treatment in the above sample so that the film thickness after drying is 3 μm, and heat drying is performed at 100 ° C. for 5 minutes did. A via with an opening diameter of 9 μm and a trench (line width L: 2 μm, space width S: 2 μm) are formed in the obtained photosensitive insulating layer using an i-line stepper exposure machine (UX74101 manufactured by Ushio Inc.) The i-line was irradiated at 850 mJ / cm ² by aligning the centers of the 7 μm vias exposed in the first layer and the 9 μm vias in the second layer through a mask designed in. The photosensitive resin layer after exposure was heated on a hot plate at 85 ° C. for 4 minutes, and then paddle developed at 25 ° C. for 50 seconds using a 2.38% aqueous TMAH solution. The resulting sample was heat cured at 180 ° C. for 1 hour. In the irradiation of the i-line, alignment is performed so that the central portions of the via (opening diameter 7 μm) of the first photosensitive resin layer and the via (opening diameter 9 μm) of the second photosensitive resin layer coincide with each other. did.

(Metal layer formation)
Also in this example, a metal layer was formed in the same manner as in Example 1. When the cross section of the wiring layer formed through the process of forming the metal layer was enlarged and observed, it was confirmed that the vias and the trenches were opened without any problem and these were filled with copper.

21A: first photosensitive resin layer 22A: second photosensitive resin layer Ta: groove (first opening) Ha: opening (second opening) 13, 15A: wiring (conductive) Material)

Claims (6)

(A) exposing a part of the first photosensitive resin layer;
(B) providing a second photosensitive resin layer on the surface of the first photosensitive resin layer;
(C) exposing a part of the second photosensitive resin layer;
(D) The first and second photosensitive resin layers are separately or collectively developed to form a first opening penetrating the first and second photosensitive resin layers. Forming a second opening having a bottom surface of the first photosensitive resin layer as a bottom surface;
(E) filling the first and second openings with a conductive material;
A method of manufacturing a wiring layer, including:   The step (D) is a step of developing the first and second photosensitive resin layers separately, and the first photosensitive resin is carried out between the steps (A) and (B). Claim: A first developing step for the layer, and a second developing step for the second photosensitive resin layer performed between the (C) step and the (E) step. The manufacturing method of 1.   The manufacturing method according to claim 2, further comprising the step of curing the first photosensitive resin layer between the first developing step and the step (B).   The manufacturing method according to claim 1, wherein the first photosensitive resin layer is a negative type, and in the step (D), the first and second photosensitive resin layers are collectively developed.   The preparation according to any one of claims 1 to 4, wherein the first and second photosensitive resin layers contain a photoacid generator and a compound having a tertiary amino group or a nitrogen-containing heterocyclic ring. Method.   The method according to claim 5, wherein the first and second photosensitive resin layers further contain an alkali-soluble resin.

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