JP2019050460A - Laminate type electronic component - Google Patents

Abstract

To achieve a compact laminate type electronic component including a bandpass filter and a balun without worsening a property.SOLUTION: A laminate type electronic component 1 comprises a laminate 30 in which dielectric layers and conductor layers are laminated; and a bandpass filter 10 and a balun 20 which are configured by using the laminate 30. The bandpass filter 10 includes a plurality of resonators R1, R2, R3 and R4. The balun 20 includes a plurality of inductors L11, L12, L21 and L22, and a plurality of capacitors C11, C21 and C22. The laminate 30 includes a ground conductor layer 331 disposed in a position closer to a bottom face 30A of the laminate 30 in comparison to the plurality of inductors. There is no ground conductor layer over the plurality of inductors. The plurality of capacitors are disposed between the plurality of inductors and the ground conductor layer 331 in a lamination direction of the plurality of dielectric layers.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a multilayer electronic component including a band pass filter and a balun.

  There is a band pass filter as one of the electronic components that can be used for communication devices such as a small mobile communication device represented by a cellular phone and a smartphone, a communication device for television broadcasting, a wireless LAN communication device and the like. In communication devices, there are cases where it is desirable to connect a circuit that handles balanced signals to a band pass filter that handles unbalanced signals. In this case, a balun is generally provided between the band pass filter and the circuit handling the balanced signal to perform conversion between the unbalanced signal and the balanced signal.

  On the other hand, particularly in small mobile communication devices, multifunctionalization and miniaturization are progressing, and along with that, miniaturization of electronic parts and densification of mounting are progressing.

  In a band pass filter and a communication device that requires a balun connected thereto, if the band pass filter and the balun configured as separate electronic components are provided, the occupied area of these becomes large and the mounting of the electronic components becomes high. It is against the density.

  Therefore, as described in, for example, Patent Document 1, a multilayer electronic component in which a band pass filter and a balun are integrated has been proposed. In the multilayer electronic component described in Patent Document 1, a band pass filter and a balun are provided in a multilayer body including a plurality of stacked dielectric layers and a plurality of conductor layers. The band pass filter has a first resonator and a second resonator electromagnetically coupled. The balun includes a first coil, a second coil, a third coil, and a fourth coil. One end of the first coil is connected to the band pass filter. The other end of the first coil is connected to one end of the second coil. The third coil is electromagnetically coupled to the first coil and the fourth coil is electromagnetically coupled to the second coil. One end of the third coil and one end of the fourth coil are grounded. The other end of the third coil and the other end of the fourth coil are connected to the pair of balancing terminals. This balun is a so-called merchant balun.

  In the multilayer electronic component described in Patent Document 1, the band pass filter and the balun are offset in the direction orthogonal to the stacking direction of the plurality of dielectric layers of the multilayer, that is, in the horizontal direction.

Unexamined-Japanese-Patent No. 2003-258585

  In the balun in the multilayer electronic component described in Patent Document 1, the first and third sets of coupled coils and the second and fourth sets of coupled coils are arranged horizontally offset. . Therefore, in this multilayer electronic component, the area occupied by the balun increases, and there is a problem that it is difficult to miniaturize the multilayer electronic component.

  In the balun of the multilayer electronic component described in Patent Document 1, when the first and third coil pairs and the second and fourth coil pairs are arranged in the stacking direction, they are inherently coupled Coupling occurs between the two coils that should not be, and the characteristics deteriorate.

  Further, in the balun in the multilayer electronic component described in Patent Document 1, each of the first to fourth coils needs to be combined with other coils, so that it is necessary to configure substantially the entire one layer. is there. Also from this point, the occupied area of the balun is increased.

  The present invention has been made in view of the above problems, and an object thereof is a multilayer electronic component including a band pass filter and a balun, which can be miniaturized without deteriorating the characteristics. It is in providing parts.

  The multilayer electronic component of the present invention includes a multilayer body including a plurality of stacked dielectric layers and a plurality of conductive layers, and a band pass filter and a balun configured using the multilayer body. The band pass filter and the balun are arranged at different positions in the direction orthogonal to the stacking direction of the plurality of dielectric layers.

  The band pass filter includes a first input / output terminal, a second input / output terminal, and a plurality of resonators provided between the first input / output terminal and the second input / output terminal in the circuit configuration. Contains. In the present application, the expression “in circuit configuration” is used to indicate an arrangement on a circuit diagram, not an arrangement in a physical configuration.

  The balun includes an unbalanced input / output terminal connected to the second input / output terminal, a first balanced input / output terminal, a second balanced input / output terminal, and an unbalanced input / output terminal and a first And a second phase shift circuit provided between the unbalanced input / output terminal and the second balanced input / output terminal in terms of circuit configuration And contains.

  The first phase shift circuit includes a first path that includes a first inductor and connects the unbalanced input / output end and the first balanced input / output end, and in terms of circuit configuration, between the first path and ground. And a first capacitor provided on the The second phase shift circuit includes a second path including a second capacitor and connecting the unbalanced input / output end and the second balanced input / output end, and in terms of circuit configuration, between the second path and the ground. And a second inductor provided on the

  The stacked body has a bottom surface facing the mounted body when the multilayer electronic component is mounted on the mounted body, and a top surface opposite to the bottom surface. The plurality of conductor layers include ground conductor layers connected to the ground. The ground conductor layer is disposed closer to the bottom than the first and second inductors and at a position overlapping the first and second inductors when viewed in the stacking direction of the plurality of dielectric layers. The laminate is disposed closer to the upper surface than the first and second inductors, and is disposed at a position overlapping the first and second inductors when viewed from the stacking direction of the plurality of dielectric layers, and connected to the ground Does not include any conductive layers. The first and second capacitors are disposed between the first and second inductors and the ground conductor layer in the stacking direction of the plurality of dielectric layers.

  In the multilayer electronic component of the present invention, at least one of the first inductor and the second inductor is two or more conductor layers of the plurality of conductor layers, and the positions differ in the lamination direction of the plurality of dielectric layers The two or more conductor layers arranged in may be connected and configured.

  In the multilayer electronic component of the present invention, the first path may further include a third inductor connected in series to the first inductor. In this case, the first capacitor is provided between the connection point of the first inductor and the third inductor and the ground in the circuit configuration. The third inductor may be disposed closer to the upper surface than the first and second capacitors and at a position overlapping the ground conductor layer when viewed in the stacking direction of the plurality of dielectric layers. .

  Further, the third inductor is configured by connecting two or more conductor layers which are two or more conductor layers among the plurality of conductor layers and arranged at different positions in the stacking direction of the plurality of dielectric layers. It may be done.

  In the multilayer electronic component of the present invention, the second path may further include a third capacitor connected in series to the second capacitor. In this case, the second inductor is provided between the connection point of the second capacitor and the third capacitor and the ground in the circuit configuration. The third capacitor may be disposed between the first and second inductors and the ground conductor layer in the stacking direction of the plurality of dielectric layers.

  Also, the third capacitor may be provided between the second capacitor and the second balanced input / output terminal in terms of circuit configuration. In this case, the second phase shift circuit may further include a fourth inductor provided between the second balanced input / output end and the ground in terms of circuit configuration. The fourth inductor may be disposed closer to the upper surface than the first and second capacitors and at a position overlapping the ground conductor layer when viewed in the stacking direction of the plurality of dielectric layers.

  Further, the fourth inductor is configured by connecting two or more conductor layers which are two or more conductor layers among the plurality of conductor layers and arranged at different positions in the stacking direction of the plurality of dielectric layers. It may be done.

  In the multilayer electronic component of the present invention, the balun includes the first and second inductors and the first and second capacitors. According to the present invention, it is possible to dispose the first and second inductors and the first and second capacitors by effectively utilizing the space of the laminate. Further, according to the present invention, it is possible to sufficiently widen the space through which the magnetic flux generated by the first and second inductors passes. From the above, according to the present invention, it is possible to miniaturize the laminated electronic component including the band pass filter and the balun without deteriorating the characteristics.

FIG. 1 is a perspective view of a multilayer electronic component according to an embodiment of the present invention. It is a perspective view which shows the inside of the laminated body shown in FIG. It is a top view which shows the inside of the laminated body shown in FIG. It is a side view which shows the inside of the laminated body shown in FIG. FIG. 2 is a circuit diagram showing a circuit configuration of a multilayer electronic component according to an embodiment of the present invention. It is explanatory drawing which shows the pattern formation surface of the 3rd-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 4th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 5th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 6th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 7th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 8th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 9th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 10th through 16th dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 17th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 18th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 19th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 20th-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 21st-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 22nd-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 23rd-layer dielectric material layer in the laminated body shown in FIG. It is explanatory drawing which shows the pattern formation surface of the 28th-layer dielectric material layer in the laminated body shown in FIG. It is a characteristic view which shows the frequency characteristic of the insertion loss of the band pass filter in the laminated type electronic component which concerns on one embodiment of this invention, and a reflection loss. FIG. 7 is a characteristic diagram showing frequency characteristics of insertion loss and reflection loss of the multilayer electronic component according to the embodiment of the present invention. It is a characteristic view showing the amplitude balance characteristic of the balun in the multilayer electronic component concerning the 1 embodiment of the present invention. It is a characteristic view showing the amplitude balance characteristic of the lamination type electronic component concerning a 1 embodiment of the present invention. It is a characteristic view showing the phase balance characteristic of the balun in the multilayer electronic component concerning the 1 embodiment of the present invention. It is a characteristic view showing the phase balance characteristic of the lamination type electronic component concerning a 1 embodiment of the present invention.

  Hereinafter, a multilayer electronic component according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a perspective view of a multilayer electronic component according to the present embodiment. As shown in FIG. 1, the multilayer electronic component 1 according to the present embodiment includes a multilayer body 30. As will be described in detail later, the stack 30 includes a plurality of stacked dielectric layers and a plurality of conductor layers.

  FIG. 2 is a perspective view showing the inside of the stacked body 30. As shown in FIG. FIG. 3 is a plan view showing the inside of the stacked body 30. As shown in FIG. FIG. 4 is a side view showing the inside of the stacked body 30. As shown in FIG.

  Here, as shown in FIG. 1, an X direction, a Y direction, and a Z direction are defined. The X, Y and Z directions are orthogonal to one another. In the present embodiment, the stacking direction of the plurality of dielectric layers is taken as the Z direction.

  The stacked body 30 has a rectangular parallelepiped shape. The stacked body 30 has a bottom surface 30A that faces the mounted object when the multilayer electronic component 1 is mounted on a mounting substrate or the like, a top surface 30B opposite to the bottom surface 30A, a bottom surface 30A, and a top surface 30B. And four side surfaces 30C, 30D, 30E, and 30F connecting the two. The bottom surface 30A and the top surface 30B are located at both ends of the stack 30 in the Z direction. The side surfaces 30C and 30D are located at both ends of the stack 30 in the Y direction. The side surfaces 30E and 30F are located at both ends of the stack 30 in the X direction.

  The multilayer electronic component 1 further includes six terminals 61, 62, 63, 64, 65, 66 integrated with the multilayer body 30. The three terminals 61, 62, 63 are in contact with the bottom surface 30A, the side surface 30C, and the top surface 30B of the stacked body 30, respectively. The three terminals 64, 65 and 66 are in contact with the bottom surface 30A, the side surface 30D and the top surface 30B of the laminate 30, respectively.

  FIG. 5 is a circuit diagram showing a circuit configuration of the multilayer electronic component 1 according to the present embodiment. As shown in FIG. 5, the multilayer electronic component 1 includes a band pass filter 10 and a balun 20. The band pass filter 10 and the balun 20 are both configured using the laminate 30.

  The band pass filter 10 is provided between the first input / output end T1 and the second input / output end T2 in terms of circuit configuration. And a plurality of resonators. Particularly in the present embodiment, the band pass filter 10 includes four resonators R1, R2, R3, and R4 as a plurality of resonators.

  The resonators R1 to R4 are configured such that two resonators adjacent to each other in circuit configuration are electromagnetically coupled. Specifically, in the resonators R1 to R4, the resonators R1 and R2 are electromagnetically coupled adjacent to each other in circuit configuration, and the resonators R2 and R3 are electromagnetically coupled adjacent to each other in circuit configuration, and the resonators R3 and R4 are electrically coupled. Are configured to be electromagnetically coupled adjacent to each other in circuit configuration.

  Each of the resonators R1 to R4 has a first end and a second end opposite to each other in the circuit configuration. The first end of the resonator R1 is connected to the first input / output end T1. The first end of the resonator R4 is connected to the second input / output end T2. The second end of each of the resonators R1 to R4 is connected to the ground.

  The band pass filter 10 further includes capacitors C1, C2, C3, C4, C5, C6, C7, and C8.

  The capacitor C1 is provided between the first end of the resonator R1 and the ground in the circuit configuration. The capacitor C2 is provided between the first end of the resonator R2 and the ground in the circuit configuration. The capacitor C3 is provided between the first end of the resonator R3 and the ground in the circuit configuration. The capacitor C4 is provided between the first end of the resonator R4 and the ground in the circuit configuration.

  The capacitor C5 is provided between the first end of the resonator R1 and the first end of the resonator R2 in terms of circuit configuration. The capacitor C6 is provided between the first end of the resonator R2 and the first end of the resonator R3 in terms of circuit configuration. The capacitor C7 is provided between the first end of the resonator R3 and the first end of the resonator R4 in terms of circuit configuration. The capacitor C8 is provided between the first end of the resonator R1 and the first end of the resonator R4 in terms of circuit configuration.

  The balun 20 includes an unbalanced input / output terminal T10 connected to the second input / output terminal T2 of the bandpass filter 10, a first balanced input / output terminal T11, a second balanced input / output terminal T12, and a first And a second phase shift circuit 22.

  The first phase shift circuit 21 is provided between the unbalanced input / output terminal T10 and the first balanced input / output terminal T11 in terms of circuit configuration. The second phase shift circuit 22 is provided between the unbalanced input / output terminal T10 and the second balanced input / output terminal T12 in terms of circuit configuration.

  The first phase shift circuit 21 includes a first path P1 connecting the unbalanced input / output end T10 and the first balanced input / output end T11. The first path P1 includes an inductor L11 and an inductor L12 connected in series. The inductor L12 is provided between the inductor L11 and the first balanced input / output terminal T11 in terms of circuit configuration.

  The first phase shift circuit 21 further includes a capacitor C11 provided between the first path P1 and the ground in terms of circuit configuration. In particular, the capacitor C11 is provided between the connection point of the inductor L11 and the inductor L12 and the ground.

  The inductor L11 corresponds to the first inductor in the present invention. The inductor L12 corresponds to the third inductor in the present invention. The capacitor C11 corresponds to the first capacitor in the present invention.

  The first path P1 may not include the inductor L12.

  The second phase shift circuit 22 includes a second path P2 connecting the unbalanced input / output end T10 and the second balanced input / output end T12. The second path P2 includes a capacitor C21 and a capacitor C22 connected in series. The capacitor C22 is provided between the capacitor C21 and the second balanced input / output terminal T12 in the circuit configuration.

  The second phase shift circuit 22 further includes an inductor L21 provided between the second path P2 and the ground in terms of circuit configuration. The inductor L21 is particularly provided between the connection point of the capacitor C21 and the capacitor C22 and the ground.

  The second phase shift circuit 22 further includes an inductor L22 provided between the second balanced input / output terminal T12 and the ground in the circuit configuration.

  The capacitor C21 corresponds to the first capacitor in the present invention. The capacitor C222 corresponds to the third capacitor in the present invention. The inductor L21 corresponds to the second inductor in the present invention. The inductor L22 corresponds to the fourth inductor in the present invention.

  The second path P2 may not include the capacitor C22 and the inductor L22.

  The first phase shift circuit 21 is designed to delay the phase of the signal of the frequency within the pass band of the band pass filter 10 by a value close to or at 90 degrees. The second phase shift circuit 22 is designed to advance the phase of the signal of the frequency within the pass band of the band pass filter 10 by a value close to or at 90 degrees.

  The terminal 66 shown in FIG. 1 corresponds to the first input / output terminal T1 shown in FIG. The terminal 63 shown in FIG. 1 corresponds to the first balanced input / output terminal T11 shown in FIG. The terminal 64 shown in FIG. 1 corresponds to the second balanced input / output terminal T12 shown in FIG. The terminals 61, 62, 65 shown in FIG. 1 are connected to the ground.

  Here, the operation of the multilayer electronic component 1 according to the present embodiment will be described. The band pass filter 10 selectively passes a signal of a frequency in the pass band among the signals applied to one of the first input / output terminal T1 and the second input / output terminal T2 to obtain the first input. It outputs from the other of the output end T1 and the second input / output end T2.

  In the balun 20, an unbalanced signal is input / output at the unbalanced input / output terminal T10, and a first balanced element signal is input / output at the first balanced input / output terminal T11, and a second balanced input / output terminal T12 The balance element signal of is input / output. The first balanced element signal and the second balanced element signal constitute a balanced signal. The balun 20 converts between an unbalanced signal and a balanced signal.

  In the balun 20, when a signal having a frequency within the pass band of the band pass filter 10 is input to the unbalanced input / output terminal T10, the first output from the first and second balanced input / output terminals T11 and T12 And the second balanced element signal have a phase difference of 180 degrees or near.

  Next, with reference to FIG. 6 to FIG. 21, configurations of a plurality of dielectric layers constituting the stacked body 30, a plurality of conductor layers formed in the plurality of dielectric layers, and a plurality of through holes will be described. . The laminate 30 has 28 laminated dielectric layers. Hereinafter, the twenty-eight dielectric layers are referred to as the first to twenty-eighth dielectric layers in order from the bottom. The first to twenty-eighth dielectric layers are denoted by reference numerals 31 to 58, respectively.

  Conductor layers and through holes are not formed in the first dielectric layer 31 and the second dielectric layer 32.

  FIG. 6 shows the pattern formation surface of the third dielectric layer 33. A ground conductor layer 331 is formed on the patterned surface of the dielectric layer 33. The ground conductor layer 331 is connected to the terminals 61, 62, 65, and is connected to the ground through the terminals 61, 62, 65. In the dielectric layer 33, through holes 33T1, 33T2, 33T3, 33T4, 33T5, 33T6 connected to the ground conductor layer 331 are formed.

  FIG. 7 shows the patterned surface of the fourth dielectric layer 34. Conductor layers 341, 342, 343, 344, 345 for capacitors are formed on the patterned surface of the dielectric layer 34. The conductor layer 344 includes a rectangular main portion 344A and a branch portion 344B laterally projecting from the main portion 344A.

  In the dielectric layer 34, through holes 34T1, 34T2, 34T3, 34T4, 34T5, 34T6, 34T7, 34T8, 34T11, 34T12, 34T13, 34T14 are formed. The through hole 34T7 is connected to the branch portion 344B of the conductor layer 344. The through hole 34T8 is connected to the conductor layer 345. The through holes 34T11, 34T12, 34T13 and 34T14 are connected to the conductor layers 341, 342, 343 and 344 respectively.

  The through holes 33T1, 33T2, 33T3, 33T4, 33T5 and 33T6 shown in FIG. 6 are connected to the through holes 34T1, 34T2, 34T3, 34T4 and 34T5, 34T6, respectively.

  FIG. 8 shows the pattern formation surface of the fifth dielectric layer 35. Conductor layers 351, 352, 353, and 354 for capacitors are formed on the patterned surface of the dielectric layer 35.

  In the dielectric layer 35, through holes 35T1, 35T2, 35T3, 35T4, 35T5, 35T6, 35T7, 35T8, 35T11, 35T12, 35T13, 35T14 are formed. The through holes 35T12 and 35T13 are connected to the conductor layers 351 and 352, respectively.

  Through holes 34T1, 34T2, 34T3, 34T4, 34T5, 34T6, 34T7, 34T11, 34T12, 34T13, 34T14 shown in FIG. 7 are respectively through holes 35T1, 35T2, 35T3, 35T4, 35T5, 35T6, 35T7, 35T8. , 35T11, 35T12, 35T13, and 35T14.

  FIG. 9 shows the patterned surface of the sixth dielectric layer 36. Conductor layers 361 and 362 for capacitors are formed on the pattern formation surface of the dielectric layer 36.

  In the dielectric layer 36, through holes 36T1, 36T2, 36T3, 36T4, 36T5, 36T6, 36T7, 36T8, 36T11, 36T12, 36T13, 36T14 are formed. The through holes 36T11 and 36T14 are connected to the conductor layers 361 and 362, respectively.

  Through holes 35T1, 35T2, 35T3, 35T5, 35T5, 35T6, 35T8, 35T11, 35T12, 35T13, 35T14 shown in FIG. 8 are respectively through holes 36T1, 36T2, 36T3, 36T4, 36T5, 36T6, 36T7, 36T8. , 36T11, 36T12, 36T13, 36T14.

  FIG. 10 shows the pattern formation surface of the seventh dielectric layer 37. Conductor layers 371 and 372 and a conductor layer 373 for a capacitor are formed on the pattern formation surface of the dielectric layer 37. The conductor layer 373 includes a rectangular main portion 373A and a branch portion 373B laterally projecting from the main portion 373A.

  In the dielectric layer 37, through holes 37T1, 37T2, 37T3, 37T4, 37T5, 37T6, 37T7, 37T8, 37T9, 37T11, 37T12, 37T13, 37T14 are formed. The through hole 37T7 is connected to the branch portion 373B of the conductor layer 373. The through holes 37T9 and 37T11 are connected to the conductor layers 372 and 371, respectively.

  The conductor layer 371 is connected to the terminal 66 shown in FIG. The conductor layer 372 is connected to the terminal 64 shown in FIG.

  Through holes 36T1, 36T2, 36T3, 36T4, 36T5, 36T6, 36T8, 36T11, 36T12, 36T13, 36T14 shown in FIG. 9 are respectively through holes 37T1, 37T2, 37T3, 37T4, 37T5, 37T6, 37T7, 37T8. , 37T11, 37T12, 37T13, and 37T14.

  FIG. 11 shows the patterned surface of the eighth dielectric layer 38. A conductor layer 381 for a capacitor is formed on the patterned surface of the dielectric layer 38.

  In the dielectric layer 38, through holes 38T1, 38T2, 38T3, 38T4, 38T5, 38T6, 38T7, 38T8, 38T9, 38T10, 38T11, 38T12, 38T13, 38T14 are formed. The through holes 38T10 are connected to the conductor layer 381.

  Through holes 37T1, 37T2, 37T3, 37T4, 37T5, 37T6, 37T7, 37T9, 37T11, 37T12, 37T13, 37T14 shown in FIG. 10 are respectively through holes 38T1, 38T2, 38T3, 38T4, 38T5, 38T6, 38T7. , 38T8, 38T9, 38T11, 38T12, 38T13, 38T14.

  FIG. 12 shows the pattern formation surface of the ninth dielectric layer 39. Conductor layers 391 and 392 for capacitors are formed on the patterned surface of the dielectric layer 39.

  In the dielectric layer 39, through holes 39T1, 39T2, 39T3, 39T4, 39T5, 39T6, 39T7, 39T8, 39T9, 39T10, 39T11, 39T12, 39T13, 39T14 are formed. The through holes 39T7 and 39T9 are connected to the conductor layers 391 and 392, respectively.

  The through holes 38T1, 38T2, 38T3, 38T5, 38T6, 38T7, 38T9, 38T10, 38T11, 38T12, 38T13, 38T14 shown in FIG. 11 are respectively through holes 39T1, 39T2, 39T2, 39T3, 39T4, 39T5, 39T6. , 39T7, 39T8, 39T9, 39T10, 39T11, 39T12, 39T13, 39T14.

  FIG. 13 shows the patterned surface of the tenth to sixteenth dielectric layers 40 to 46. Through holes 40T1, 40T2, 40T2, 40T3, 40T4, 40T5, 40T7, 40T8, 40T9, 40T10, 40T11, 40T12, 40T13, 40T14 are formed in each of the dielectric layers 40-46.

  The through holes 39T1, 39T2, 39T2, 39T4, 39T5, 39T6, 39T8, 39T9, 39T10, 39T11, 39T12, 39T13, 39T14 shown in FIG. 12 are formed in the tenth dielectric layer 40 respectively. The through holes 40T1, 40T2, 40T3, 40T4, 40T5, 40T6, 40T7, 40T8, 40T9, 40T10, 40T11, 40T12, 40T13 and 40T14 are connected. In the dielectric layers 40 to 46, through holes adjacent in the upper and lower direction are connected to each other.

  FIG. 14 shows the pattern formation surface of the seventeenth dielectric layer 47. A conductor layer 478 for an inductor is formed on the patterned surface of the dielectric layer 47. The conductor layer 478 has a first end and a second end located at opposite ends.

  In the dielectric layer 47, through holes 47T1, 47T2, 47T3, 47T4, 47T5, 47T6, 47T7, 47T8, 47T9, 47T10, 47T11, 47T12, 47T13, 47T14 are formed. The through hole 47T9 is connected to a portion of the conductor layer 478 near the first end.

  Through holes 40T1, 40T2, 40T2, 40T4, 40T5, 40T6, 40T8, 40T10, 40T11, 40T12, 40T13 and 40T14 formed in the sixteenth dielectric layer 46 are respectively through holes 47T1, 47T2, 47T3, 47T4, 47T5, 47T6, 47T7, 47T8, 47T10, 47T11, 47T12, 47T13, 47T14 are connected. The through hole 40T9 formed in the sixteenth dielectric layer 46 is connected to a portion of the conductor layer 478 near the second end.

  FIG. 15 shows the pattern formation surface of the eighteenth dielectric layer 48. Conductor layers 485 and 488 for inductors are formed on the patterned surface of the dielectric layer 48. Each of the conductor layers 485, 488 has a first end and a second end located at opposite ends.

  In the dielectric layer 48, through holes 48T1, 48T2, 48T3, 48T4, 48T5, 48T6, 48T7, 48T8, 48T9, 48T10, 48T11, 48T12, 48T13, 48T14, 48T15 are formed. The through hole 48T8 is connected to a portion of the conductor layer 485 near the first end. The through hole 48T15 is connected to a portion of the conductor layer 485 near the second end. The through hole 48T9 is connected to a portion of the conductor layer 488 near the first end.

  The through holes 47T1, 47T2, 47T3, 47T4, 47T5, 47T6, 47T7, 47T10, 47T11, 47T12, 47T13, 47T14 shown in FIG. 14 are respectively through holes 48T1, 48T2, 48T3, 48T4, 48T5, 48T6, 48T7. , 48T8, 48T10, 48T11, 48T12, 48T13, 48T14. The through hole 47T9 shown in FIG. 14 is connected to a portion of the conductor layer 488 near the second end.

  FIG. 16 shows the pattern formation surface of the nineteenth dielectric layer 49. Conductor layers 495 and 498 for inductors are formed on the patterned surface of the dielectric layer 49. Each of the conductor layers 495 and 498 has a first end and a second end located at opposite ends.

  In the dielectric layer 49, through holes 49T1, 49T2, 49T3, 49T4, 49T5, 49T6, 49T7, 49T8, 49T9, 49T10, 49T11, 49T12, 49T13, 49T14, 49T15 are formed. The through hole 49T9 is connected to a portion of the conductor layer 498 near the first end. The through hole 49T15 is connected to a portion of the conductor layer 495 near the first end.

  The through holes 48T1, 48T2, 48T3, 48T4, 48T5, 48T7, 48T8, 48T10, 48T12, 48T12, 48T13, 48T14 shown in FIG. 15 are respectively through holes 49T1, 49T2, 49T3, 49T4, 49T5, 49T5, 49T7. , 49T8, 49T10, 49T11, 49T12, 49T13, and 49T14.

  The through hole 48T9 shown in FIG. 15 is connected to a portion of the conductor layer 498 near the second end. Through hole 48T15 shown in FIG. 15 is connected to a portion of conductor layer 495 near the second end.

  FIG. 17 shows the pattern formation surface of the twentieth dielectric layer 50. Conductor layers 501, 502, 503, and 504 for a resonator and conductor layers 505, 506, and 508 for an inductor are formed on the pattern formation surface of the dielectric layer 50. Each of the conductor layers 501, 502, 503, 504, 505, 506, 508 has a first end and a second end located at opposite ends.

  In the dielectric layer 50, through holes 50T1, 50T2, 50T3, 50T4, 50T5, 50T6, 50T7, 50T8, 50T9, 50T10, 50T11, 50T12, 50T13, 50T14, 50T15 are formed.

  The through holes 50T1, 50T2, 50T3, and 50T4 are connected to portions of the conductor layers 501, 502, 503, and 504 near the first end, respectively. The through holes 50T11, 50T12, 50T13, and 50T14 are connected to portions of the conductor layers 501, 502, 503, and 504 near the second end, respectively.

  The through hole 50T8 is connected to a portion of the conductor layer 506 near the first end. The through hole 50T9 is connected to a portion of the conductor layer 508 near the first end. The through hole 50T15 is connected to a portion of the conductor layer 505 near the first end.

  The through holes 49T1, 49T2, 49T3, 49T4, 49T5, 49T7, 49T10, 49T11, 49T12, 49T13, 49T14 shown in FIG. 16 are respectively through holes 50T1, 50T2, 50T3, 50T4, 50T5, 50T5, 50T7, 50T10. , 50T11, 50T12, 50T13, and 50T14.

  The through hole 49T8 shown in FIG. 16 is connected to a portion of the conductor layer 506 near the second end. The through hole 49T9 shown in FIG. 16 is connected to a portion of the conductor layer 508 near the second end. The through hole 49T15 shown in FIG. 16 is connected to a portion of the conductor layer 505 near the second end.

  FIG. 18 shows the pattern formation surface of the twenty-first dielectric layer 51. Conductor layers 511, 512, 513, and 514 for a resonator and conductor layers 515, 516, 517, and 518 for an inductor are formed on the pattern formation surface of the dielectric layer 51. Each of the conductor layers 511 to 518 has a first end and a second end located at opposite ends.

  In the dielectric layer 51, through holes 51T1, 51T2, 51T3, 51T4, 51T5, 51T5, 51T8, 51T10, 51T11, 51T12, 51T13, 51T14, 51T15 are formed.

  The through holes 51T1, 51T2, 51T3, and 51T4 are connected to portions of the conductor layers 511, 512, 513, and 514 near the first end, respectively. The through holes 51T11, 51T12, 51T13, and 51T14 are connected to portions of the conductor layers 511, 512, 513, and 514 near the second end, respectively.

  The through hole 51T5 is connected to a portion of the conductor layer 517 in the vicinity of the first end. The through hole 51T8 is connected to a portion of the conductor layer 516 near the first end. The through hole 51T15 is connected to a portion of the conductor layer 515 in the vicinity of the first end.

  Through holes 50T1, 50T2, 50T3, 50T4, 50T7, 50T10, 50T11, 50T12, 50T13 and 50T14 shown in FIG. 17 are respectively through holes 51T1, 51T2, 51T2, 51T3, 51T4, 51T10, 51T10, 51T11, 51T12, 51T13, 51T14. It is connected to the.

  Through hole 50T5 shown in FIG. 17 is connected to a portion of conductor layer 517 in the vicinity of the second end. Through hole 50T6 shown in FIG. 17 is connected to a portion of conductor layer 518 near the first end. Through hole 50T8 shown in FIG. 17 is connected to a portion of conductor layer 516 near the second end. Through hole 50T9 shown in FIG. 17 is connected to a portion of conductor layer 518 near the second end. Through hole 50T15 shown in FIG. 17 is connected to a portion of conductor layer 515 in the vicinity of the second end.

  FIG. 19 shows the pattern formation surface of the 22nd dielectric layer 52. Conductor layers 521, 522, 523 and 524 for a resonator and conductor layers 525, 526 and 527 for an inductor are formed on the patterned surface of the dielectric layer 52. Each of the conductor layers 521 to 527 has a first end and a second end located at opposite ends.

  In the dielectric layer 52, through holes 52T5, 52T7, 52T8, 52T10, 52T15 are formed.

  The through hole 52T5 is connected to a portion of the conductor layer 527 in the vicinity of the first end. The through hole 52T8 is connected to a portion of the conductor layer 526 near the first end. The through hole 52T15 is connected to a portion of the conductor layer 525 in the vicinity of the first end.

  Through holes 51T7 and 51T10 shown in FIG. 18 are connected to through holes 52T7 and 52T10, respectively.

  The through holes 51T1, 51T2, 51T3 and 51T4 shown in FIG. 18 are connected to portions of the conductor layers 521, 522, 523 and 524 near the first end, respectively. Through holes 51T11, 51T12, 51T13, and 51T14 shown in FIG. 18 are connected to portions of the conductor layers 521, 522, 523, and 524 near the second end, respectively.

  Through hole 51T5 shown in FIG. 18 is connected to a portion of conductor layer 527 near the second end. Through hole 51T8 shown in FIG. 18 is connected to a portion of conductor layer 526 near the second end. Through hole 51T15 shown in FIG. 18 is connected to a portion of conductor layer 525 in the vicinity of the second end.

  FIG. 20 shows the pattern formation surface of the 23rd dielectric layer 53. A conductor layer 537 for an inductor and conductor layers 536 and 539 are formed on the patterned surface of the dielectric layer 53. The conductor layer 536 is connected to the terminal 63 shown in FIG. Each of the conductor layers 537, 539 has a first end and a second end located at opposite ends.

  Through hole 52T5 shown in FIG. 19 is connected to a portion of conductor layer 537 near the first end. Through hole 52T7 shown in FIG. 19 is connected to a portion of conductor layer 539 near the first end. The through holes 52T8 shown in FIG. 19 are connected to the conductor layer 536. Through hole 52T10 shown in FIG. 19 is connected to a portion in the vicinity of the second end in conductor layer 537. Through hole 52T15 shown in FIG. 19 is connected to a portion of conductor layer 539 near the second end.

  Conductor layers and through holes are not formed in the twenty-fourth to twenty-seventh dielectric layers 54 to 57.

  FIG. 21 shows the patterned surface of the twenty-eighth dielectric layer 58. A conductor layer 581 used as a mark is formed on the patterned surface of the dielectric layer 58.

  The laminate 30 is configured by laminating first to 28th dielectric layers 31 to 58 such that one surface of the first dielectric layer 31 is a bottom surface 30A. The surface of the twenty-eighth dielectric layer 58 opposite to the patterned surface is the upper surface 30 B of the laminate 30.

  Hereinafter, the correspondence between the components of the circuit of the multilayer electronic component 1 shown in FIG. 5 and the components of the laminate 30 shown in FIGS. 6 to 21 will be described.

  First, the band pass filter 10 will be described. The resonator R1 is configured by connecting the conductor layers 501, 511, and 521 shown in FIGS. 17 to 19 by through holes 50T1, 51T1, 50T11, and 51T11. The resonator R2 is configured by connecting the conductor layers 502, 512, 522 shown in FIGS. 17 to 19 by through holes 50T2, 51T2, 50T12, 51T12. The resonator R3 is configured by connecting the conductor layers 503, 513, and 523 shown in FIGS. 17 to 19 by through holes 50T3, 51T3, 50T13, and 51T13. The resonator R4 is configured by connecting the conductor layers 504, 514, 524 shown in FIGS. 17 to 19 by through holes 50T4, 51T4, 50T14, 51T14.

  The capacitor C1 is composed of the conductor layer 341 shown in FIG. 7, the ground conductor layer 331 shown in FIG. 6, and the dielectric layer 33 shown in FIG. The capacitor C2 is configured of the conductor layer 342, the ground conductor layer 331, and the dielectric layer 33 shown in FIG. The capacitor C3 is configured of the conductor layer 343 shown in FIG. 7, the ground conductor layer 331, and the dielectric layer 33. The capacitor C4 is composed of the conductor layer 344 shown in FIG. 7, the ground conductor layer 331, and the dielectric layer 33.

  The capacitor C5 is composed of the conductor layer 341 shown in FIG. 7, the conductor layer 351 shown in FIG. 8, and the dielectric layer 34 shown in FIG. The capacitor C6 is composed of the conductor layers 342 and 343 shown in FIG. 7, the conductor layer 353 shown in FIG. 8, and the dielectric layer 34. The capacitor C7 is composed of the conductor layer 344 shown in FIG. 7, the conductor layer 352 shown in FIG. 8, and the dielectric layer 34. The capacitor C8 is configured of the conductor layers 341 and 344 shown in FIG. 7, the conductor layer 354 shown in FIG. 8, the conductor layers 361 and 362 shown in FIG. 9, and the dielectric layers 34 and 35.

  One end of each of the resonator R1 and the capacitors C1, C5, and C8 is connected to a terminal 66 corresponding to the first input / output end T1 via a plurality of through holes and the conductor layer 371 shown in FIG. .

  The conductor layer 504 forming the resonator R4 and the conductor layer 344 forming the capacitors C4, C7, and C8 are connected to the through holes 34T7 shown in FIG.

  Next, the balun 20 will be described. The inductor L11 is configured by connecting the conductor layers 485, 495, 505, 515, 525 shown in FIGS. 15 to 19 in series by a plurality of through holes. The inductor L12 is configured by connecting the conductor layers 506, 516, and 526 shown in FIGS. 17 to 19 in series by a plurality of through holes. The inductor L21 is configured by connecting the conductor layers 517, 527, 537 shown in FIG. 18 to FIG. 20 in series by a plurality of through holes. The inductor L22 is configured by connecting the conductor layers 478, 488, 498, 508, and 518 shown in FIGS. 14 to 18 in series by a plurality of through holes.

  The capacitor C11 is composed of the conductor layer 345 shown in FIG. 7, the ground conductor layer 331 shown in FIG. 6, and the dielectric layer 33 shown in FIG. The capacitor C21 is composed of the conductor layers 373, 381, and 391 shown in FIGS. 10 to 12 and the dielectric layers 37 and 38 shown in FIGS. The capacitor C22 is composed of the conductor layers 372, 381, and 392 shown in FIGS. 10 to 12 and the dielectric layers 37 and 38.

  The conductor layer 525 constituting the inductor L11 is connected to the through hole 37T7 shown in FIG. 10 via the conductor layer 539 shown in FIG. 20 and the plurality of through holes. The conductor layer 373 constituting the capacitor C21 is also connected to the through hole 37T7.

  The branch portion 344B of the conductor layer 344 shown in FIG. 7, the branch portion 373B of the conductor layer 373 shown in FIG. 10, and the through holes 34T7, 35T7, 36T7 between them are the second input / output end T2 and It corresponds to the balanced input / output terminal T10.

  The conductor layer 526 forming the inductor L12 is connected to the terminal 63 corresponding to the first balanced input / output terminal T11 through the through hole 52T8 and the conductor layer 536 shown in FIG.

  The conductor layer 372 constituting the capacitor C22 is connected to the terminal 64 corresponding to the second balanced input / output terminal T12. The conductor layer 472 constituting the inductor L22 is connected to the terminal 64 via the plurality of through holes and the conductor layer 372.

  Next, structural features of the multilayer electronic component 1 according to the present embodiment will be described. As shown in FIG. 4, the band pass filter 10 and the balun 20 are disposed at different positions in the X direction which is a direction perpendicular to the stacking direction of the plurality of dielectric layers of the multilayer body 30, ie, the Z direction.

  The ground conductor layer 331 is disposed at a position closer to the bottom surface 30A than the inductors L11, L12, L21, and L22 and at a position overlapping the inductors L11, L12, L21, and L22 when viewed from the Z direction.

  Laminated body 30 is disposed at a position closer to upper surface 30B than inductors L11, L12, L21, and L22, and is disposed at a position overlapping with inductors L11, L12, L21, and L22 when viewed from the Z direction and connected to ground. It does not contain any conductor layer.

  Capacitors C11, C21 and C22 are arranged between inductors L11, L12, L21 and L22 and ground conductor layer 331 in the Z direction. In other words, the inductors L11, L12, L21, L22 are arranged closer to the top surface 30B than the capacitors C11, C21, C22 and at positions overlapping the ground conductor layer 331 when viewed from the Z direction.

  Each of the inductors L11, L12, L21, L22 is two or more conductor layers among the plurality of conductor layers included in the stacked body 30, and two or more conductor layers arranged at different positions in the Z direction Are connected and configured.

  Next, the effects of the multilayer electronic component 1 according to the present embodiment will be described. The balun 20 in the present embodiment is not a merchant balun, but is configured by a first phase shift circuit 21 and a second phase shift circuit 22. Each of the first and second phase shift circuits 21 and 22 is an LC circuit including at least one inductor and at least one capacitor.

  In the present embodiment, as understood from the above description of the structural features, a plurality of inductors and a plurality of capacitors constituting the balun 20 are disposed by effectively utilizing the space in the stacked body 30. Can.

  Further, in the present embodiment, the plurality of capacitors constituting the balun 20 are disposed between the plurality of inductors constituting the balun 20 and the ground conductor layer 331. Therefore, while arranging the plurality of inductors and the plurality of capacitors constituting the balun 20 effectively utilizing the space in the stacked body 30 as described above, the distance between the plurality of inductors and the ground conductor layer 331 It can be enlarged. Also, above the plurality of inductors, there is no conductor layer disposed at a position overlapping with the plurality of inductors when viewed from the Z direction and connected to the ground. From these facts, according to the present embodiment, the space through which the magnetic flux generated by each of the plurality of inductors can pass can be made sufficiently wide.

  From the above, according to the present embodiment, the multilayer electronic component 1 including the band pass filter 10 and the balun 20 can be miniaturized without deteriorating the characteristics.

  In addition, as described above, in the present embodiment, each of the plurality of inductors constituting balun 20 is two or more conductor layers among the plurality of conductor layers included in stacked body 30 in the Z direction. Two or more conductor layers arranged at different positions are connected and configured. Each of the plurality of inductors constituting the balun 20 in the present embodiment does not need to be coupled to other inductors, and therefore, two or more conductor layers disposed at different positions in the Z direction as in the present embodiment Can be connected and configured. Thereby, the occupied area of each of the plurality of inductors can be reduced. From this point as well, according to the present embodiment, the multilayer electronic component 1 can be miniaturized.

  In the case where the band pass filter 10 and the balun 20 are arranged side by side in the Z direction in the stacked body 30, each of the plurality of inductors constituting the balun does not increase the dimension in the Z direction of the stacked body 30 too much. It is difficult to make the space through which the generated magnetic flux passes sufficiently wide.

  In addition, if the band pass filter 10 is configured by an LC circuit, desired characteristics can not be obtained, or a large number of inductors and capacitors are required to obtain the desired characteristics, and the multilayer electronic component 1 is enlarged. Problems will arise. As in the present embodiment, by configuring the band pass filter 10 to include a plurality of resonators, the band pass filter 10 having desired characteristics can be realized without increasing the size of the multilayer electronic component 1. Becomes possible.

  Next, an example of the characteristics of the multilayer electronic component 1 obtained by simulation will be described. FIG. 22 shows the frequency characteristics of the insertion loss and the reflection loss of the band pass filter 10 alone when the balun 20 is not connected. Here, a single-ended S-parameter representing the response of the high frequency signal output from the second input / output terminal T2 when the high frequency signal is input to the first input / output terminal T1 and the insertion loss of the band pass filter 10 alone. Express using. In addition, the reflection loss of the band pass filter 10 is determined using a single-ended S parameter representing the response of the high frequency signal output from the first input / output terminal T1 when the high frequency signal is input to the first input / output terminal T1. It represents. In FIG. 22, the horizontal axis shows frequency, and the vertical axis shows insertion loss and reflection loss. Further, in FIG. 22, the line denoted by reference numeral 101 indicates the frequency characteristic of insertion loss, and the line denoted by reference numeral 102 indicates the frequency characteristic of reflection loss.

  FIG. 23 shows the frequency characteristics of the insertion loss and the reflection loss of the multilayer electronic component 1 including the band pass filter 10 and the balun 20. Here, when an unbalanced signal is input to the first input / output terminal T1, the first and second balanced input / output terminals T11, T12 output the insertion loss of the multilayer electronic component 1 It is represented using mixed mode S-parameters representing the response of the difference signal of two balanced element signals. In addition, a single-ended S parameter representing the response of the high frequency signal output from the first input / output terminal T1 when the high frequency signal is input to the first input / output terminal T1 is used as the reflection loss of the multilayer electronic component 1. Use to represent. In FIG. 23, the horizontal axis represents frequency, and the vertical axis represents insertion loss and reflection loss. Further, in FIG. 23, the line denoted by reference numeral 111 indicates the frequency characteristic of insertion loss, and the line denoted by reference numeral 112 indicates the frequency characteristic of reflection loss.

  From FIGS. 22 and 23, it can be seen that both the band pass filter 10 alone and the multilayer electronic component 1 function as a band pass filter having a pass band of about 3400 to 4600 MHz.

  FIG. 24 shows the amplitude balance characteristic of the balun 20 alone when the band pass filter 10 is not connected. Here, the amplitude balance characteristic of the balun 20 alone and the first and second balanced input / output terminals T11 and T12 output when the unbalanced signal is input to the unbalanced input / output terminal T10. This is expressed using the difference in amplitude of the balanced element signal (hereinafter referred to as "amplitude difference"). The amplitude difference is expressed as a positive value when the amplitude of the second balanced element signal is larger than the amplitude of the first balanced element signal, and the amplitude of the second balanced element signal is the amplitude of the first balanced element signal. If it is smaller than this, it is represented by a negative value. In FIG. 24, the horizontal axis indicates frequency, and the vertical axis indicates amplitude difference.

  FIG. 25 shows the amplitude balance characteristics of the multilayer electronic component 1 including the band pass filter 10 and the balun 20. Here, the amplitude balance characteristic of the multilayer electronic component 1 is determined according to the first and second balanced input and output ends T11 and T12 when an unbalanced signal is input to the first input and output end T1. Expressed using the difference in amplitude (amplitude difference) of the second balanced element signal. In FIG. 25, the horizontal axis represents frequency, and the vertical axis represents amplitude difference.

  In both of FIG. 24 and FIG. 25, the amplitude difference in the above-mentioned pass band is close to 0 (dB). Therefore, the amplitude balance characteristic of the balun 20 alone and the amplitude balance characteristic of the multilayer electronic component 1 are both good.

  FIG. 26 shows the phase balance characteristics of the balun 20 alone when the band pass filter 10 is not connected. Here, the phase balance characteristic of the balun 20 alone, the unbalanced signal input to the unbalanced input / output terminal T10, and the first and second balanced input / output terminals T11 and T12 output from the first and second It represents using the difference in phase of the balanced element signal (hereinafter referred to as phase difference). The phase difference represents the amount by which the phase of the second balanced element signal is advanced with respect to the phase of the first balanced element signal. In FIG. 24, the horizontal axis represents frequency, and the vertical axis represents phase difference.

  FIG. 27 shows phase balance characteristics of the multilayer electronic component 1 including the band pass filter 10 and the balun 20. As shown in FIG. Here, the phase balance characteristic of the multilayer electronic component 1 is determined by comparing the first and second balanced input / output terminals T11 and T12 when an unbalanced signal is input to the first input / output terminal T1. This is expressed using the phase difference (phase difference) of the second balanced element signal. In FIG. 27, the horizontal axis represents frequency, and the vertical axis represents phase difference.

  In both of FIG. 26 and FIG. 27, the phase difference in the above-mentioned pass band is close to 180 degrees (deg). Therefore, the phase balance characteristics of the balun 20 alone and the phase balance characteristics of the multilayer electronic component 1 are both good.

  The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the embodiment, the band pass filter 10 includes four resonators, but the number of resonators included in the band pass filter in the present invention may be two or more.

  DESCRIPTION OF SYMBOLS 1 ... Stacked type electronic component, 10 ... Band pass filter, 20 ... Balun, 21 ... 1st phase shift circuit, 22 ... 2nd phase shift circuit, 30 ... Laminated body.

Claims (8)

A laminate including a plurality of stacked dielectric layers and a plurality of conductor layers;
A multilayer electronic component comprising a band pass filter and a balun configured using the above laminate, comprising:
The band pass filter and the balun are disposed at different positions in a direction orthogonal to the stacking direction of the plurality of dielectric layers,
The band pass filter is
A first input / output terminal,
A second input / output terminal,
The circuit configuration includes a plurality of resonators provided between the first input / output terminal and the second input / output terminal,
The balun is
An unbalanced input / output terminal connected to the second input / output terminal;
A first balanced input / output terminal,
A second balanced input / output terminal,
In terms of circuit configuration, a first phase shift circuit provided between the unbalanced input / output terminal and the first balanced input / output terminal;
The circuit configuration includes a second phase shift circuit provided between the unbalanced input / output terminal and the second balanced input / output terminal,
The first phase shift circuit includes a first path that includes a first inductor and connects the unbalanced input / output end and the first balanced input / output end, and in terms of circuit configuration, the first path And a first capacitor provided between the ground and
The second phase shift circuit includes a second path that includes a second capacitor and connects the unbalanced input / output end and the second balanced input / output end, and in terms of circuit configuration, the second path And a second inductor provided between the ground and the
The laminated body has a bottom surface facing the mounting target when the multilayer electronic component is mounted on the mounting target, and a top surface opposite to the bottom surface.
The plurality of conductor layers include a ground conductor layer connected to ground,
The ground conductor layer is closer to the bottom surface than the first and second inductors, and overlaps the first and second inductors when viewed in the stacking direction of the plurality of dielectric layers. Placed
The laminate is disposed at a position closer to the upper surface than the first and second inductors and at a position overlapping the first and second inductors when viewed from the laminating direction of the plurality of dielectric layers. Does not include any conductor layers that are connected to ground,
The first and second capacitors are disposed between the first and second inductors and the ground conductor layer in the stacking direction of the plurality of dielectric layers. parts.   At least one of the first inductor and the second inductor is two or more conductor layers of the plurality of conductor layers and arranged at different positions in the stacking direction of the plurality of dielectric layers The multilayer electronic component according to claim 1, wherein one or more conductor layers are connected. The first path further includes a third inductor connected in series to the first inductor,
The first capacitor is provided between the connection point of the first inductor and the third inductor and the ground in the circuit configuration.
The third inductor is disposed at a position closer to the upper surface than the first and second capacitors and at a position overlapping the ground conductor layer when viewed in the stacking direction of the plurality of dielectric layers. The laminated electronic component according to claim 1 or 2, characterized in that   The third inductor is connected to two or more conductor layers of the plurality of conductor layers, the two or more conductor layers disposed at different positions in the stacking direction of the plurality of dielectric layers. The multilayer electronic component according to claim 3, wherein the multilayer electronic component is configured. The second path further includes a third capacitor connected in series to the second capacitor,
The circuit according to any one of claims 1 to 4, wherein the second inductor is provided between a connection point of the second capacitor and the third capacitor and the ground in terms of circuit configuration. Multilayer electronic components.   The lamination according to claim 5, wherein the third capacitor is disposed between the first and second inductors and the ground conductor layer in the lamination direction of the plurality of dielectric layers. Type electronic components. The third capacitor is provided between the second capacitor and the second balanced input / output terminal in the circuit configuration.
The second phase shift circuit further includes a fourth inductor provided between the second balanced input / output terminal and the ground in the circuit configuration,
The fourth inductor is disposed at a position closer to the upper surface than the first and second capacitors and at a position overlapping the ground conductor layer when viewed in the stacking direction of the plurality of dielectric layers. The laminated electronic component according to claim 5 or 6, characterized in that   The fourth inductor is connected to two or more conductor layers of the plurality of conductor layers, the two or more conductor layers disposed at different positions in the stacking direction of the plurality of dielectric layers. The laminated electronic component according to claim 7, characterized in that it is configured.

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