JP2019047003A - Resistance change element, semiconductor device and manufacturing method - Google Patents

Abstract

To provide a semiconductor device with resistance change element of metal deposition type, capable of suppressing a voltage required for switch operation and its variations.SOLUTION: The resistance change element includes: a resistance change film of metal deposition type; a first electrode for supplying metal ions to the resistance change film in contact with one surface of the resistance change film; a second electrode in contact with the other surface of the resistance change film.The first electrode has barrier metal at its outer periphery, and the barrier metal is in contact with the resistance change film through an insulator.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having a metal deposition type variable resistance element in a wiring layer formed on a semiconductor substrate, and a method of manufacturing the same.

  In order to expand the use of semiconductor devices having programmable logic circuits to electronic devices etc. by increasing the functionality of programmable logic circuits, the size of the switch that switches the connection between logic cells is reduced and the on resistance thereof is increased. It is necessary to make it smaller. It is known that a switch based on a variable resistance element utilizing deposition of metal in an ion conductive layer to which metal ions are conductive is smaller in size and smaller in on resistance than existing semiconductor switches.

  As switches based on this metal deposition type resistance change element, there are a two-terminal switch disclosed in Patent Document 1 and a three-terminal switch disclosed in Patent Document 2. The two-terminal switch has a structure in which an ion conductive layer is sandwiched between a first electrode supplying metal ions and a second electrode not supplying metal ions. Between the two electrodes, it turns on / off due to the formation and disappearance of metal crosslinks due to the deposition of metal in the ion conduction layer. The two-terminal switch has a simple structure, so that the manufacturing process is simple, and the element size can be reduced to the nanometer order. On the other hand, the three-terminal switch has a structure in which the second electrodes of two two-terminal switches are shared, and has high reliability in switch operation.

  As the ion conductive layer, a porous polymer containing silicon, oxygen and carbon as main components is desirable. Patent Document 3 discloses that the porous polymer ion conductive layer can maintain high breakdown voltage even when metal crosslinks are formed, and thus is excellent in operation reliability.

  In order to use this metal deposition type resistance change element as a wiring switching switch of a programmable logic circuit, it is necessary to miniaturize the element to achieve high density and simplify the manufacturing process. Copper is mainly used as the wiring material of the semiconductor devices at the leading edge, and it is desirable to efficiently form the variable resistance element in the copper wiring. Patent Document 4 discloses a technology for forming the two-terminal switch and Patent Document 5 for forming the three-terminal switch in copper wiring. According to Patent Documents 4 and 5, the first electrode supplying metal ions is also used as a copper wiring. According to this structure, the process for separately forming the first electrode is unnecessary. Therefore, a photomask for forming the first electrode is not necessary, and the resistance change element can be formed in the copper wiring only by adding two photomasks.

  At this time, when the ion conduction layer is formed directly on the copper wiring, the surface of the copper wiring is oxidized to increase the leak current. For this reason, Non-Patent Document 1 discloses a structure in which a metal thin film functioning as an oxidation sacrificial layer is sandwiched between a copper wiring and an ion conductive layer. The metal thin film is oxidized by oxygen contained in the ion conduction layer and becomes a part of the ion conduction layer. Moreover, the metal which comprises an oxidation sacrificial layer forms an alloy layer in an interface with copper, and when metal bridge | crosslinking is formed by voltage application, the said metal is taken in in metal bridge | crosslinking. And the retention stability (retention) improves by the heat stability of bridge | crosslinking improving by the said metal diffused in metal bridge | crosslinking. On the other hand, the generation efficiency of Joule heat is improved by incorporating the metal into the metal crosslink, so that the current required at the transition from on to off does not increase.

  Furthermore, in Patent Document 6, the end portion of the copper wiring which is the first electrode is connected to the ion conductive layer, so that the electric field is concentrated on the end portion of the copper wiring, and the voltage required for the switch operation Techniques for reducing the variation are disclosed. Furthermore, Patent Document 7 discloses a structure having a portion dug in the in-plane vertical direction in the surface of the copper wiring which is the first electrode, and in contact with the ion conductive layer at the portion dug in. . Thereby, when forming a via connected to the resistance change element, it is possible to reduce plasma damage to the element.

Japanese Patent Application Publication No. 2002-536840 International Publication No. 2012/043502 International Publication No. 2011/058947 Patent No. 5382001 International Publication No. 2011/158821 Patent No. 6112106 gazette JP 2017-107911 A

M. Tada, T .; Sakamoto, N .; Banno, K. Okamoto, N .; Iguchi, H .; Hada, and M. Miyamura, "Improved ON-State Reliability of Atom Switch Using Alloy Electrodes", IEEE Transactions on Electron Devices, Vol. 60, pp. 3534-3540, 2013.

  By the way, in a switch using a metal deposition type resistance change element, in order to reduce the voltage required for the switch operation and the variation thereof, the end portion of the copper wiring which is the first electrode is connected to the ion conduction layer. In this case, the barrier metal present on the outer periphery of the copper wiring is also connected to the ion conduction layer. At this time, when the thickness of the ion conductive layer is the same in the portion in contact with copper and the portion in contact with the barrier metal, or when the portion in contact with the barrier metal becomes thinner, the electric field concentrates on the barrier metal during copper switching operation. Do. As a result, electric field concentration in the copper wiring can not be performed, and the voltage required for the switch operation and the variation thereof can not be reduced. And the method of solving this problem is not disclosed by patent documents 1-7 or nonpatent literature 1. FIG.

  The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device having a metal deposition type resistance change element in which a voltage required for a switch operation and a variation thereof are reduced.

  The variable resistance element according to the present invention includes a metal deposition type variable resistance film, a first electrode for supplying metal ions to the variable resistance film in contact with one surface of the variable resistance film, and the other of the variable resistance film. And a second electrode in contact with the surface of the first electrode. The first electrode has a barrier metal on the outer periphery, and the barrier metal is in contact with the resistance change film through an insulator.

  A semiconductor device according to the present invention includes a metal deposition type resistance change film, a first electrode for supplying metal ions to the resistance change film in contact with one surface of the resistance change film, and the other of the resistance change film. A second electrode in contact with the surface, the first electrode having a barrier metal on the outer periphery, and the barrier metal being in contact with the resistance change film via an insulator, a copper wire, and a copper wire And the copper wiring doubles as the first electrode.

  In the method of manufacturing a resistance change element according to the present invention, a wiring is formed in a wiring trench provided in an interlayer insulating film formed on a semiconductor substrate via a barrier metal, and the wiring and the interlayer insulating film are formed. Forming an insulating barrier film having at least the barrier metal and an opening through which the wire is exposed, forming an insulator on a surface of the barrier metal exposed to the opening, and inserting at least the opening through the opening; A resistance change film and an upper electrode are sequentially formed on the surface of the insulator and the wiring.

  According to the present invention, it is possible to provide a semiconductor device having a metal deposition type resistance change element in which the voltage required for the switch operation and the variation thereof are reduced.

It is a cross-sectional schematic diagram which shows the structure of the resistance change element of the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows the structure of the semiconductor device of the 2nd Embodiment of this invention. It is a figure which shows the switch operation characteristic of the resistance change element of the 2nd Embodiment of this invention. It is a figure which shows the switch operation characteristic of the resistance change element of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 1 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 2 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 3 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 4 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 5 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 6 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 7 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 8 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 9 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 10 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 11 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the process 12 of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows the structure of the modification of the semiconductor device of the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows another structure of the semiconductor device of the 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the embodiments described below are technically preferable limitations for carrying out the present invention, but the scope of the invention is not limited to the following.
First Embodiment
FIG. 1 is a schematic cross-sectional view showing the structure of the variable resistance element according to the first embodiment of the present invention. The resistance change element 1 of the present embodiment includes a metal deposition type resistance change film 11, and a first electrode 12 which supplies metal ions to the resistance change film 11 in contact with one surface of the resistance change film 11. And a second electrode 13 in contact with the other surface of the resistance change film 11. Furthermore, the first electrode 12 has a barrier metal 14 on the outer periphery, and the barrier metal 14 is in contact with the resistance change film 11 via an insulator 15.

  According to the resistance change element 1 of the present embodiment, the barrier metal 14 is in contact with the resistance change film 11 via the insulator 15, so that electric field concentration at the barrier metal 14 is prevented, and electric field concentration at the first electrode 12 Is possible. As a result, it is possible to reduce the voltage required for the switch operation of the variable resistance element 1 and the variation thereof.

As described above, according to the present embodiment, it is possible to provide a semiconductor device having a metal deposition type variable resistance element in which the voltage required for the switch operation and the variation thereof are reduced.
Second Embodiment
FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device of the second embodiment of the present invention. The semiconductor device 10 of the present embodiment has a three-terminal variable resistance element 100 formed in a multilayer wiring layer on a semiconductor substrate 101 such as a silicon substrate. An element such as a transistor may be formed on the semiconductor substrate.

  The multilayer wiring layer is formed on the semiconductor substrate 101, the interlayer insulating film 102, the low-k film 103, the interlayer insulating film 104, the barrier insulating film 107, the protective insulating film 114, the interlayer insulating film 115, the low-k film 116, the interlayer insulating It is provided in the laminated structure of the film 117 and the barrier insulating film 121. The multilayer wiring layer is formed in the wiring groove formed in the interlayer insulating film 104 and the low-k film 103 via the first barrier metal A 106 a, the first barrier metal B 106 b, and the first barrier metal C 106 c. The first wiring B 105 b and the first wiring C 105 c are embedded.

  Further, in the multilayer wiring layer, the second wiring A118a and the second wiring B118b are formed in the wiring trench formed in the interlayer insulating film 117 and the low-k film 116 via the second barrier metal A120a and the second barrier metal B120b. It is embedded. Further, vias A119a and B119b are embedded in the lower holes formed in the interlayer insulating film 115, the protective insulating film 114, and the hard mask films 112 and 113 via the second barrier metal A 120a and the second barrier metal B 120b. ing. The second wiring A118a and the via A119a, and the second wiring B118b and the via B119b are integrated. The side surfaces and the bottom surfaces of the second wiring A118a, the via A119a, the second wiring B118b, and the via B119b are covered with a second barrier metal A120a and a second barrier metal B120b.

  The multilayer wiring is not limited to the first wiring A 105 a, the first wiring B 105 b, the first wiring C 105 c, the second wiring A 118 a, and the second wiring B 118 b described above. The number of multilayer interconnections can be any number according to the circuit configuration.

  The resistance change element 100 uses the first wiring A 105 a and the first wiring B 105 b as a first electrode for supplying metal ions to the resistance change film, and the first ion conduction layer 109 a and the second ion conduction layer 109 b as a resistance change film (ion The lower second electrode 110 and the upper second electrode 111 are used as a second electrode.

  An opening is formed in the barrier insulating film 107. In the opening portion, the end portion of the first wiring A 105 a and the first wiring B 105 b, the oxidized portion 108 where the first barrier metal A 106 a and the first barrier metal B 106 b are oxidized, the first barrier metal A 106 a and the first barrier metal B 106 b The interlayer insulating film 104 is exposed. The first ion conductive layer 109a and the second ion conductive layer 109b, and the lower second electrode 110 and the upper second electrode 111 are formed so as to cover the opening and the wall surface of the opening and a part of the barrier insulating film 107. It is done. Furthermore, on the upper second electrode 111, hard mask films 112 and 113 are formed when the first ion conductive layer 109a and the second ion conductive layer 109b, and the lower second electrode 110 and the upper second electrode 111 are patterned. It is done. Furthermore, the upper surface or the side surface of the laminate of the first ion conductive layer 109 a and the second ion conductive layer 109 b, the lower second electrode 110 and the upper second electrode 111, and the hard mask films 112 and 113 is covered with a protective insulating film 114. It is

  By using a part of the first wiring A 105 a and the first wiring B 105 b as the lower electrode of the variable resistance element 100, a low resistance lower electrode can be formed while simplifying the number of steps. Then, the resistance change element 100 can be formed in the multilayer wiring layer by an additional step using two photomasks in the copper damascene wiring process which is a normal multilayer wiring process, and the resistance reduction and the reduction of the element can be achieved. Costing can be achieved simultaneously.

  In the resistance change element 100, the first ion conductive layer 109 a is in contact with the first wiring A 105 a and the first wiring B 105 b at an opening formed in the barrier insulating film 107. For this reason, the metal which comprises the 1st ion conduction layer 109a diffuses into the 1st wiring A105a and the 1st wiring B105b, and forms the alloy layer. In the variable resistance element 100, the upper second electrode 111 and the via A119a are electrically connected via the second barrier metal A120a. Resistance change element 100 uses electric field diffusion of metal ions supplied from the metal forming first interconnection A 105 a and first interconnection B 105 b to first ion conduction layer 109 a and second ion conduction layer 109 b to turn on / off. Do the off.

  The first wiring A 105 a and the first wiring B 105 b may be dug down in the depth direction at the opening of the barrier insulating film 107. At this time, the interlayer insulating film 104 sandwiched between the first wiring A 105 a and the first wiring B 105 b is also dug down. The portion where the interlayer insulating film 104 is dug down is lower in the depth direction than the heights of the first wire A 105 a and the first wire B 105 b being dug down. That is, in the opening, regions of two different levels of height are formed in the ion conductive layer 109. The first ion conductive layer 109a is in contact with the upper surfaces of the first wiring A 105a and the first wiring B 105b, and the oxidized portions 108 of the first barrier metal A 106a and the first barrier metal B 106b.

  On the other hand, the resistance change element 100 is not interposed between the first wiring C105c and the via B119b, and the via B119b is in contact with the first wiring C105c via the second barrier metal B120b.

  An oxidized portion 108 in which the barrier metal is oxidized is formed at a portion in contact with the first ion conduction layer 109 a of the first barrier metal A 106 a and the first barrier metal B 106 b. The oxidized portion 108 is formed by an etching process when forming the opening of the barrier insulating film 107. When a voltage is applied between the lower second electrode 110 and the first wiring A 105 a or the first wiring B 105 b, the oxidizing unit 108 can prevent the concentration of the electric field on the first barrier metal A 106 a and the first barrier metal B 106 b.

  The semiconductor substrate 101 is a substrate on which a semiconductor element is formed. As the semiconductor substrate 101, for example, a substrate such as a silicon substrate, a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, or a substrate for manufacturing a liquid crystal can be used.

  The interlayer insulating film 102 is an insulating film formed on the semiconductor substrate 101. For the interlayer insulating film 102, for example, a silicon oxide film, an SiOC film, or the like can be used. The interlayer insulating film 102 may be a stack of a plurality of insulating films.

  The low-k film 103 is an insulating film with a low dielectric constant interposed between the interlayer insulating film 102 and the interlayer insulating film 104. The low-k film 103 is a low dielectric constant film having a relative dielectric constant lower than that of a silicon oxide film, and an SiOCH film or the like can be used, for example. In the low-k film 103, wiring trenches for embedding the first wiring A 105a, the first wiring B 105 b, and the first wiring C 105 c are formed. In the wiring trench, a first wiring A 105 a, a first wiring B 105 b, and a first wiring C 105 c are embedded via the first barrier metal A 106 a, the first barrier metal B 106 b, and the first barrier metal C 106 c.

  The interlayer insulating film 104 is an insulating film formed on the low-k film 103. For the interlayer insulating film 104, for example, a silicon oxide film, an SiOC film, or the like can be used. The interlayer insulating film 104 may be a stack of a plurality of insulating films. In the interlayer insulating film 104, a wiring trench for embedding the first wiring A 105a, the first wiring B 105 b, and the first wiring C 105 c is formed. A first wiring A 105 a, a first wiring B 105 b, and a first wiring C 105 c are embedded in the wiring trench via the first barrier metal A 106 a, the first barrier metal B 106 b, and the first barrier metal C 106 c.

  The portion sandwiched between the first wiring A 105 a and the first wiring B 105 b of the interlayer insulating film 104 is further lower in the depth direction than the dug portion of the end of the first wiring A 105 a and the first wiring B 105 b surrounding this portion. Being dug down. The portions where the interlayer insulating film 104, the first wiring A 105a, and the first wiring B 105b are dug down are simultaneously formed when the oxidized portion 108 is formed.

  The first wiring A 105 a and the first wiring B 105 b are wirings embedded in the wiring grooves formed in the interlayer insulating film 104 and the low-k film 103 via the first barrier metal A 106 a and the first barrier metal B 106 b. The first wiring A 105 a and the first wiring B 105 b also serve as the lower electrode of the resistance change element 100 and are in contact with the first ion conductive layer 109 a. The upper surface of the first ion conductive layer 109 a is in contact with the second ion conductive layer 109 b, and the upper surface of the second ion conductive layer 109 b is in contact with the lower second electrode 110.

  For the metal constituting the first wiring A 105 a, a metal that can be diffused and ion-conductive in the ion conduction layer 109 is used, and copper or the like can be used, for example. The metal (for example, copper) which comprises 1st wiring A105a and 1st wiring B105b may be alloyed with aluminum.

  The first wiring A 105 a and the first wiring B 105 b may be dug down in the depth direction on the opening surface of the barrier insulating film 107. In this case, the first wiring A 105 a and the first wiring B 105 b are in contact with the first ion conductive layer 109 a via the digging portion. An alloy layer with a metal constituting a first ion conductive layer 109a described later is formed at the interface between the digging portion and the first ion conductive layer 109a. The alloy layer is not formed entirely on the first wiring A 105 a and the first wiring B 105 b, but is formed only on the opening surface of the barrier insulating film 107.

  The formation of the digging portion is performed after the formation of the opening surface of the barrier insulating film 107 in contact with the first wiring A 105 a and the first wiring B 105 b. At this time, plasma using halogen gas, inert gas, fluorocarbon gas, and mixed gas thereof is incident on the substrate including the first wiring A 105 a, the first wiring B 105 b, and the interlayer insulating film 104 in the dry etching apparatus. Do. At this time, although the barrier insulating film 107 is also etched, the first wiring C 105 c in which the resistance change element 100 is not formed is not exposed to plasma and can not be dug down.

  The first wiring C 105 c is a wiring embedded in a wiring trench formed in the interlayer insulating film 104 and the low-k film 103 via the first barrier metal C 106 c. The first wiring C 105 c is in direct contact with the via B 119 b and the second barrier metal B 120 b at another opening of the barrier insulating film 107.

  The first barrier metal A106a, the first barrier metal B106b, and the first barrier metal C106c prevent the metal forming the first wiring A105a, the first wiring B105b, and the first wiring C105c from diffusing into the interlayer insulating film 104 or the lower layer Do. For this purpose, the conductive film has a barrier property by covering the side surface or the bottom surface of each wiring. When each wiring is made of a metal element containing copper as a main component, each barrier metal may be tantalum, tantalum nitride, titanium nitride, high melting point metal such as tungsten carbonitride, nitride thereof, or a laminated film thereof. It can be used.

  The first barrier metal A 106 a and the first barrier metal B 106 b have an oxidized portion 108 in which the barrier metal is oxidized in a portion in contact with the first ion conductive layer 109 a in the opening of the barrier insulating film 107. The oxidized portion 108 may be oxidized as long as the surface in contact with the first ion conductive layer 109 a is left, and a non-oxidized portion may remain on the side of the first wiring A 105 a or the first wiring B 105 b of the barrier metal. At this time, copper in a portion of the first wiring A 105 a and the first wiring B 105 b in contact with the first ion conductive layer 109 a is not oxidized.

  The formation of the oxide portion 108 is performed by using an etching gas containing oxygen in a dry etching step of opening the barrier insulating film 107. For example, a mixed gas of fluorocarbon, argon and oxygen is used. The formation of the oxidized portion 108 may be performed by inserting an oxygen plasma ashing step after the opening of the barrier insulating film 107 is performed. It is preferable that the upper surface of the oxidation portion 108 be disposed vertically below the upper surface of the copper forming the first wiring A 105 a or the first wiring B 105 b.

  The barrier insulating film 107 is formed on the interlayer insulating film 104 including the first wiring A 105 a, the first wiring B 105 b, and the first wiring C 105 c. The barrier insulating film 107 prevents oxidation of the metal (for example, copper) forming the first wiring A 105 a, the first wiring B 105 b, and the first wiring C 105 c, and prevents diffusion of the metal into the interlayer insulating film 115. The barrier insulating film 107 also serves as an etching stop layer when the upper second electrode 111, the lower second electrode 110, and the ion conductive layer 109 are processed. For the barrier insulating film 107, for example, a SiC film, a silicon carbonitride film, a silicon nitride film, a stacked structure thereof, or the like can be used. The barrier insulating film 107 is preferably made of the same material as the protective insulating film 114 and the hard mask film 112 described later.

  The first ion conductive layer 109 a and the second ion conductive layer 109 b are films whose resistance changes. The resistance of the first ion conductive layer 109a and the second ion conductive layer 109b changes due to the action (diffusion, ion conduction, etc.) of metal ions generated from the metal forming the first wiring A 105 a and the first wiring B 105 b. Materials can be used. When the resistance change to the "on" state is performed by metal deposition by reduction of metal ions, an ion conductive membrane is used.

  The second ion conductive layer 109 b is formed by plasma CVD. The raw material cyclic organic siloxane and helium as a carrier gas flow into the reaction chamber, the supply of both is stabilized, and when the pressure in the reaction chamber becomes constant, the application of RF power is started. The feed rate of the source can be 10 to 200 sccm, and the feed rate of helium can be 500 sccm via the source vaporizer.

  In the first ion conductive layer 109a, the metal forming the first wiring A 105a and the first wiring B 105b diffuses into the second ion conductive layer 109b by heating or plasma while depositing the second ion conductive layer 109b. Have a role to prevent that. Furthermore, it has a role of preventing the first wiring A 105 a and the first wiring B 105 b from being oxidized and easily promoted to be diffused to the second ion conductive layer 109 b.

  The metal that forms the first ion conductive layer 109a is exposed to an oxygen atmosphere under reduced pressure in the film formation chamber of the second ion conductive layer 109b after the film formation of the metal that constitutes the first ion conductive layer 109a. And become part of the ion conduction layer 109. The film formation of the first ion conductive layer 109 a is preferably performed by sputtering. The metal atoms or ions obtained energy by sputtering rush into the first wiring A 105 a and the first wiring B 105 b and diffuse to form an alloy layer. The thickness of the metal film forming the first ion conductive layer 109a is preferably 0.5 to 1 nm.

  The metal forming the first ion conductive layer 109a has a standard Gibbs energy of generation of noble metal which is equivalent to or higher than the metal forming the first barrier metal A106a and the first barrier metal B106b, and forms the first electrode. It is a more noble metal. For example, zirconium, hafnium, indium, lanthanum, manganese, molybdenum, niobium, tungsten can be used.

  When copper on the surfaces of the first wiring A 105 a and the first wiring B 105 b is oxidized in the step of forming the oxidized portion 108 of the barrier metal, the oxygen in the copper is not exposed to the annealing process or the process temperature. As it moves (reduces) to the ion conductive layer 109a, only the copper oxide layer can be selectively removed. At this time, the oxidized portion 108 of the barrier metal formed of tantalum having a small standard Gibb's energy of oxide (large in the negative direction) remains oxidized without being reduced.

The standard Gibbs energy of formation at 298.15 K of tantalum pentoxide (Ta ₂ O ₅ ), which is a preferable oxide of tantalum as a material of the first barrier metal A106a and the first barrier metal B106b, is -1911.3 kJ / mol . A metal whose standard Gibbs energy is larger than that and smaller than the standard Gibbs energy of copper oxide (CuO) minus 129.5 kJ / mol is preferable as the metal constituting the first ion conductive layer 109a. Specifically, zirconium, hafnium, indium, lanthanum, manganese, molybdenum, niobium and tungsten are preferable. Also, for the purpose of strengthening the reducing power, that is, reducing the standard Gibbs energy of the first ion conduction layer 109a, a metal such as tantalum, titanium, which forms an oxide whose standard Gibbs energy is similar to that of tantalum pentoxide. It may be an alloy with aluminum or a laminated structure. At this time, in order to suppress the reduction of the oxidized portion 108 of the barrier metal, the content of tantalum, titanium and aluminum in the first ion conductive layer 109 a is preferably less than 50%.

  The ion conductive layer 109 is formed on the surface of the interlayer insulating film 104 sandwiched between the first wiring A 105 a, the first wiring B 105 b, the first wiring A 105 a, and the first wiring B 105 b, and the oxidized portion 108. Furthermore, the ion conductive layer 109 is formed on the tapered surface of the digging portion formed in the opening of the barrier insulating film 107, the tapered surface of the opening of the barrier insulating film 107, or the barrier insulating film 107.

  The lower second electrode 110 is a lower electrode of the upper electrode of the resistance change element 100, and is in contact with the second ion conductive layer 109b. For the lower second electrode 110, an alloy of ruthenium and titanium, tantalum, zirconium, hafnium, aluminum or the like can be used. Ruthenium is a metal that is more difficult to ionize than the metal that forms the first wiring A 105 a and the first wiring B 105 b, and that is difficult to diffuse or conduct ions in the second ion conductive layer 109 b. In addition, titanium, tantalum, zirconium, hafnium, aluminum or the like is a metal having good adhesion to the metal forming the first wiring A 105 a and the first wiring B 105 b.

  In the ruthenium alloy used to form the lower second electrode 110, the metal added to ruthenium is preferably a metal having a larger Gibb's energy of formation in the negative direction of ruthenium in the process of forming metal ions (oxidation process). The titanium, tantalum, zirconium, hafnium, and aluminum, which generate a standard Gibbs energy in the process of generating metal ions, are larger in the negative direction than ruthenium, showing that the chemical reaction is more likely to occur spontaneously than ruthenium, and therefore highly reactive. . For this reason, by forming an alloy with ruthenium, the adhesion to the metal cross-link formed of the metal forming the first wiring A 105 a and the first wiring B 105 b is improved.

  On the other hand, when the lower second electrode 110 is formed only of titanium, tantalum, zirconium, hafnium, aluminum or the like which does not contain ruthenium, the reactivity becomes too high and the transition to the “off” state is not made. The transition from the "on" state to the "off" state proceeds by the oxidation reaction (dissolution reaction) of the metal bridge. When the metal forming the lower second electrode 110 is larger than the metal forming the first wiring A 105 a and the first wiring B 105 b in the negative direction in the standard generation Gibbs energy in the process of forming metal ions (oxidation process), the first The oxidation reaction of the lower second electrode 110 proceeds more than the oxidation reaction of the metal bridge formed of the metal forming the wiring A 105 a and the first wiring B 105 b. For this reason, it can not transition to the "off" state. Therefore, the metal used to form the lower second electrode 110 needs to be an alloy with ruthenium whose standard Gibbs energy of formation in the process of generating metal ions is smaller in the negative direction than copper.

  Furthermore, if copper, which is a component of metal cross-linking, is mixed into the lower second electrode 110, the effect of adding a large metal in the negative direction of the standard Gibbs energy is diminished, so that the metal added to ruthenium is a barrier against copper and copper ions. Preferred materials are For example, tantalum, titanium or the like. On the other hand, the larger the amount of added metal, the more the "on" state is stabilized, and the 5 at. % Addition also improves the stability. In particular, when the additive metal is titanium, the lower second electrode 110 is made of an alloy of ruthenium and titanium and has a titanium content of 20 at. % To 30 at. It is preferable to make it the range of%. The content ratio of ruthenium in the ruthenium alloy is 60 at. % Or more, 90 at. % Or less is preferable.

  Sputtering is preferably used to form the lower second electrode 110. When forming an alloy film by sputtering, a method using an alloy target of ruthenium and additive metal, cosputtering method in which a ruthenium target and a target of additive metal are simultaneously sputtered in the same chamber, a thin film of additive metal is formed in advance. On top of that, there is an intermixing method in which ruthenium is deposited using a sputtering method and alloyed with the energy of collision atoms. The composition of the alloy can be varied using co-sputtering and intermixing methods. When employing the intermixing method, it is preferable to apply a heat treatment at 400 ° C. or less after completion of the ruthenium film formation, in order to make the mixed state uniform.

  As a more preferable method of forming the lower second electrode 110, co-sputtering using two of a ruthenium target electrode and an additive metal target electrode is preferable. In the case of using an alloy target consisting of ruthenium and an additive metal, since the sputtering yield of each material is different, the composition will be deviated when used continuously, so the composition of the film to be formed should be strictly controlled. Becomes difficult. On the other hand, in the co-sputtering method, the composition of the film can be strictly controlled by individually setting the power applied to each target electrode in advance. The effect is large particularly when titanium or tantalum is used as the additive metal.

  The upper second electrode 111 is an upper electrode of the upper electrode of the resistance change element 100, and is formed on the lower second electrode 110. The upper second electrode 111 has a role of protecting the lower second electrode 110. That is, by protecting the lower second electrode 110 by the upper second electrode 111, damage to the lower second electrode 110 during the process can be suppressed, and the switching characteristics of the variable resistance element 100 can be stabilized. For the upper second electrode 111, for example, tantalum, titanium, tungsten, or a nitride thereof can be used.

  The upper second electrode 111 also has a function as an etching stop film when the via A 119 a is electrically connected to the lower second electrode 110. Therefore, it is preferable that the etching rate be lower than that of the fluorocarbon gas plasma used for the etching of the interlayer insulating film 115. In particular, titanium, tantalum, zirconium, hafnium, and aluminum nitrides which function as an etching stop film and have conductivity are preferable.

  If a metal other than nitride is used for the upper second electrode 111, part of the metal diffuses into the lower second electrode 110 due to heating or plasma damage during the process. As a result, defects may occur in the lower second electrode 110, and the dielectric breakdown voltage of the ion conductive layer 109 may be reduced from these defects. By using a conductive and stable nitride for the upper second electrode 111, diffusion of metal to the lower second electrode 110 can be prevented.

  In particular, it is preferable to use the same metal as the metal of the nitride forming the upper second electrode 111 and the additive metal forming an alloy with ruthenium forming the lower second electrode 110. This makes it possible to more efficiently prevent the diffusion failure of the metal that forms an alloy with ruthenium. For example, when the lower second electrode 110 is an alloy of ruthenium and titanium, the upper second electrode 111 is preferably made of titanium nitride. Alternatively, when the lower second electrode 110 is an alloy of ruthenium and tantalum, the upper second electrode 111 is tantalum nitride. By matching the metal components constituting the lower second electrode 110 and the upper second electrode 111, it becomes difficult to form a defect even if the metal of the upper second electrode 111 diffuses into the lower second electrode 110.

  At this time, the ratio of the metal to the nitrogen of the nitride constituting the upper second electrode 111 is made larger than the ratio of the additive metal to the ruthenium of the ruthenium alloy constituting the lower second electrode 110. Thereby, the metal constituting the lower second electrode 110 can be diffused into the nitride constituting the upper second electrode 111, and the composition of the ruthenium alloy constituting the lower second electrode 110 can be prevented from changing. Specifically, the content of titanium is 60 at. % Or more, 80 at. It is more preferable that the content is less than%.

  Sputtering is preferably used to form the upper second electrode 111. In the case of forming a nitride film by a sputtering method, it is preferable to use a reactive sputtering method in which a metal target is evaporated using plasma of a mixed gas of nitrogen and argon. The metal evaporated from the metal target reacts with nitrogen to form a nitride on the substrate.

  The hard mask films 112 and 113 are films serving as a hard mask film / passivation film when the upper second electrode 111, the lower second electrode 110, the first ion conductive layer 109a, and the second ion conductive layer 109b are etched. . For the hard mask film 112, for example, a silicon nitride film, a silicon oxide film, or the like, or a stacked layer thereof can be used. For the hard mask film 113, for example, a silicon oxide film can be used. The hard mask film 113 may be lost during etching. The hard mask film 112 preferably contains the same material as the protective insulating film 114 and the barrier insulating film 107. That is, by surrounding the periphery of the variable resistance element 100 with the same material, the material interface is integrated, so that it is possible to prevent the entry of moisture and the like from the outside and to prevent the detachment of the elements constituting the variable resistance element 100.

  The protective insulating film 114 is an insulating film which has a function of preventing desorption of oxygen from the second ion conductive layer 109 b without damaging the resistance change element 100. For the protective insulating film 114, a silicon nitride film, a silicon carbonitride film, or the like can be used, for example. The protective insulating film 114 is preferably the same material as the hard mask film 112 and the barrier insulating film 107. In the case of using the same material, the protective insulating film 114, the barrier insulating film 107, and the hard mask film 112 are integrated to improve the adhesion of the interface, and the resistance change element 100 can be strongly protected.

  The interlayer insulating film 115 is an insulating film formed on the protective insulating film 114. For the interlayer insulating film 115, for example, a silicon oxide film, an SiOC film, or the like can be used. The interlayer insulating film 115 may be a stack of a plurality of insulating films. The interlayer insulating film 115 may be made of the same material as the interlayer insulating film 117. In the interlayer insulating film 115, a lower hole for embedding the via A119a and the via B119b is formed, and the via A119a and the via B119b are embedded in the lower hole via the second barrier metal A120a and the second barrier metal B120b. ing.

  The low-k film 116 is an insulating film with a low dielectric constant interposed between the interlayer insulating films 115 and 117 using a low dielectric constant film (for example, a SiOCH film) or the like having a dielectric constant lower than that of a silicon oxide film. In the low-k film 116, a wiring trench for embedding the second wiring A118a and the second wiring B118b is formed, and the second wiring A118a and the second wiring A118a and the second barrier metal B120b are formed in the wiring trench. The second wiring B 118 b is embedded.

  The interlayer insulating film 117 is an insulating film formed on the low-k film 116. As the interlayer insulating film 117, for example, a silicon oxide film, an SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of a silicon oxide film, or the like can be used. The interlayer insulating film 117 may be a stack of a plurality of insulating films. The interlayer insulating film 117 may be made of the same material as the interlayer insulating film 115. In the interlayer insulating film 117, a wiring trench for embedding the second wiring A118a and the second wiring B118b is formed, and the second wiring A118a and the second wiring A118a and the second wiring B120b are interposed in the wiring trench. Two wires B 118 b are embedded.

  The second wiring A 118 a and the second wiring B 118 b are wirings embedded in the wiring grooves formed in the interlayer insulating film 117 and the Low-k film 116 via the second barrier metal A 120 a and the second barrier metal B 120 b. The second wiring A118a and the second wiring B118b are integrated with the via A119a and the via B119b. The via A119a is embedded in the lower hole formed in the interlayer insulating film 115, the protective insulating film 114, and the hard mask film 112 via the second barrier metal A120a. The via B 119 b is embedded in the lower hole formed in the interlayer insulating film 115 and the protective insulating film 114 via the second barrier metal B 120 b.

  The via A119a is electrically connected to the upper second electrode 111 via the second barrier metal A120a. The via B119b is electrically connected to the first wiring C105c via the second barrier metal B120b. For example, copper can be used for the second wiring A 118 a and the second wiring B 118 b and the via A 119 a and the via B 119 b.

  The second barrier metal A120a and the second barrier metal B120b prevent the metal forming the second wiring A118a and the second wiring B118b (including the via A119a and the via B119b) from diffusing into the interlayer insulating films 115 and 117 or the lower layer Do. Therefore, the second barrier metal A 120a and the second barrier metal B 120b are conductive films having a barrier property covering the side surfaces or the bottom surfaces of the second wiring A 118a and the second wiring B 118b, the via A 119a and the via B 119b.

  The second barrier metal A120a and the second barrier metal B120b may be, for example, tantalum or tantalum nitride if the second wiring A118a and the second wiring B118b, the via A119a and the via B119b are made of a metal element whose main component is copper. A refractory metal such as titanium nitride or tungsten carbonitride, or a nitride thereof, or a laminated film thereof can be used. The second barrier metal A 120 a and the second barrier metal B 120 b are preferably made of the same material as the upper second electrode 111. For example, when the second barrier metal A 120 a and the second barrier metal B 120 b have a laminated structure of tantalum nitride (lower layer) / tantalum (upper layer), it is preferable to use tantalum nitride as the lower layer material for the upper second electrode 111. .

  The barrier insulating film 121 is an insulating film formed on the interlayer insulating film 117 including the second wiring A 118 a and the second wiring B 118 b. The barrier insulating film 121 has a role of preventing oxidation of a metal (for example, copper) forming the second wiring A 118 a and the second wiring B 118 b and diffusion of the metal to the upper layer. As the barrier insulating film 121, for example, a silicon carbonitride film, a silicon nitride film, a stacked structure thereof, or the like can be used.

  FIGS. 3 and 4 are diagrams showing switch operation characteristics of the variable resistance element 100. FIG. FIG. 3 shows an off state when the lower second electrode 110 is grounded via the second wiring A 118 a, the via A 119 a and the upper second electrode 111 in the variable resistance element 100 and a positive voltage is applied to the first wiring A 105 a. Fig. 6 shows a distribution of switch voltages representing a transition voltage from to on. 4 shows the distribution of leakage current in the off state (FIG. 4) when the lower second electrode 110 is grounded and a positive voltage is applied to the first wiring A 105a, as in FIG.

  The distributions in FIG. 3 and FIG. 4 are measured using 4096 resistance change element arrays in the same chip. In FIG. 3 and FIG. 4, the difference (linear scale) between the data and the average value is converted into the cumulative probability when the 4096 pieces of data follow the normal distribution with the average value and the dispersion as the average value and the dispersion as they are. On the vertical axis. For example, the cumulative probability 16% corresponds to the difference between the data and the average value to −1 × standard deviation, the cumulative probability 50% corresponds to ± 0 × standard deviation, and the cumulative probability 84% corresponds to + 1 × standard deviation.

  In FIG. 3, an etching gas containing oxygen is used in a dry etching process for opening the barrier insulating film 107 to expose the first wiring A 105 a and the first barrier metal A 106 a and the first wiring B 105 b and the first barrier metal B 106 b. A comparison is made between the case (with oxygen) and the case where oxygen-free etching gas is used (without oxygen). In both cases, zirconium is used for the first ion conductive layer 109a, and becomes zirconium oxide after forming the second ion conductive layer 109b.

  In FIG. 3, the switch voltage is lowered and the switch voltage distribution width (ie, the variation) is reduced in the case where the etching gas with oxygen is used compared to the case where the etching gas without oxygen is used. ing. When the etching gas with oxygen is used, the oxidized portion 108 is formed on the surface of the first barrier metal A 106 a in contact with the first ion conductive layer 109 a. As a result, the electric field is not concentrated on the first barrier metal A 106 a, and the electric field is concentrated on the copper of the first wiring A 105 a. As a result, the switch voltage and the distribution width thereof are considered to be reduced.

  Also, in the distribution width (ie, variation) of the leak current in the off state in FIG. 4, the distribution width of the leak current is smaller when the etching gas with oxygen is used, and when the etching gas without oxygen is used The distribution width of the leak current is larger in the case of. When the oxygen-free etching gas is used, the oxidized portion 108 is not formed in the first barrier metal A 106 a. Therefore, when the upper surface of the first wiring A 105 a and the upper surface of the first barrier metal A 106 a are substantially the same in the vertical direction in the plane, or the first barrier metal A 106 a is higher, the electric field is concentrated on the first barrier metal A 106 a It is considered that the leak current increases or the distribution width of the leak current increases.

  As described above, when the etching gas with oxygen is used, the switch voltage and the variation thereof are reduced, and the variation of the leak current in the off state is reduced. This is because when the etching gas with oxygen is used, the oxidized portion 108 is formed on the surface of the first barrier metal A 106 a, and the electric field is not concentrated on the first barrier metal A 106 a by the oxidized portion 108, and the first wiring A 105 a Corresponds to the concentration of the electric field.

5A to 5L are schematic cross-sectional views showing steps 1 to 12 of manufacturing the semiconductor device 10 of the present embodiment.
(Step 1)
An interlayer insulating film 102 (for example, a silicon oxide film, a film thickness of 500 nm) is deposited over the semiconductor substrate 101 (for example, a silicon substrate on which a semiconductor element is formed). Thereafter, a low dielectric constant film (for example, a SiOCH film, 150 nm thick) having a low relative dielectric constant is deposited on the interlayer insulating film 102 as a Low-k film 103. After that, a silicon oxide film (for example, a silicon oxide film, 100 nm in film thickness) is deposited on the low-k film 103 as an interlayer insulating film 104.

  Thereafter, a wiring trench is formed in the interlayer insulating film 104 and the low-k film 103 by using a lithography method (including photoresist formation, dry etching, and photoresist removal). After that, the first wiring A105a and the first wiring B105b are interposed in the wiring groove via the first barrier metal A106a, the first barrier metal B106b and the first barrier metal C106c (for example, tantalum nitride / tantalum, film thickness 5 nm / 5 nm). And embedding the first wiring C 105 c (for example, copper).

  The interlayer insulating films 102 and 104 can be formed by plasma CVD (Chemical Vapor Deposition). The first barrier metal A 106 a, the first barrier metal B 106 b, and the first barrier metal C 106 c can be formed by PVD (Physical Vapor Deposition). After forming a copper seed by PVD on the first barrier metal A 106 a, the first barrier metal B 106 b, and the first barrier metal C 106 c, the first wiring A 105 a, the first wiring B 105 b, and the first wiring C 105 c are copper by electrolytic plating. Embedded in the wiring trench. Furthermore, after heat treatment at a temperature of 200 ° C. or more, the film can be formed by removing excess copper outside the wiring trench by a CMP (Chemical Mechanical Polishing) method.

A series of formation methods of such copper wiring can use a general method in the art. Here, the CMP method is a method of planarizing the irregularities on the surface of the wafer generated during the process of forming a multilayer wiring by bringing it into contact with a polishing pad which is rotated while flowing a polishing liquid on the surface of the wafer. It is possible to form embedded wiring (damascene wiring) by polishing extra copper embedded in the trench or to planarize by polishing the interlayer insulating film.
(Step 2)
A barrier insulating film 107 (for example, a silicon nitride film or a silicon carbonitride film, a film thickness of 30 nm) is formed over the interlayer insulating film 104 including the first wiring A 105 a, the first wiring B 105 b, and the first wiring C 105 c. Here, the barrier insulating film 107 can be formed by plasma CVD. The film thickness of the barrier insulating film 107 is preferably about 10 nm to 50 nm.
(Step 3)
A hard mask film 107 a (for example, a silicon oxide film, 40 nm in film thickness) is formed on the barrier insulating film 107. At this time, the hard mask film 107a is preferably made of a material different from that of the barrier insulating film 107 from the viewpoint of maintaining a large etching selectivity in dry etching, and may be an insulating film or a conductive film. As the hard mask film 107a, for example, a silicon oxide film, a silicon nitride film, titanium nitride, titanium, tantalum, tantalum nitride or the like can be used, and a laminated film of silicon nitride / silicon oxide film can also be used.
(Step 4)
The shape of the opening is patterned on the hard mask film 107a using a photoresist (not shown), and dry etching is performed using the photoresist as a mask to form an opening pattern. Thereafter, the photoresist is peeled off by oxygen plasma ashing or the like. At this time, the dry etching does not necessarily have to stop on the upper surface of the barrier insulating film 107, and may reach the inside of the barrier insulating film 107.
(Step 5)
The barrier insulating film 107 exposed from the opening of the hard mask film 107 a is etched back (dry etching) using the hard mask film 107 a as a mask. Thus, an opening is formed in the barrier insulating film 107, and the first wiring A 105a and the first wiring B 105b are exposed from the opening of the barrier insulating film 107. At this time, etch back is performed using a mixed gas of fluorocarbon gas, argon, and oxygen. Specifically, fluorocarbon and oxygen are mixed to the same extent, and argon is mixed at a ratio of 10 to 20 times that of fluorocarbon or oxygen. As a result of the etch back, the exposed portions of the copper of the first wiring A 105 a and the first wiring B 105 b and the first barrier metal A 106 a and the first barrier metal B 106 b are oxidized. An oxidized portion 108 is formed in the first barrier metal A 106 a and the first barrier metal B 106 b.

  At this time, by controlling the mixing ratio of oxygen gas used for etch back, the copper of the first wiring A 105 a and the first wiring B 105 b is not oxidized, and only the first barrier metal A 106 a and the first barrier metal B 106 b are oxidized. Also good. Because the standard Gibbs energy of copper formed in the first wiring A 105 a and the first wiring B 105 b is larger than the standard Gibbs energy in which tantalum constituting the first barrier metal A 106 a and the first barrier metal B 106 b is tantalum pentoxide. By setting appropriate conditions, only the first barrier metal A 106 a and the first barrier metal B 106 b can be selectively oxidized.

  Thereafter, by exposure to plasma using a mixed gas of nitrogen and argon, etching by-products and the like generated at the time of etch back are removed. Furthermore, when the oxidation of the barrier metal oxidized portion 108 is insufficient, the plasma may be exposed to plasma of pure oxygen or plasma of a mixed gas of oxygen and nitrogen. The exposure to the plasma may be performed in the chamber subjected to the etch back processing, or may be performed using, for example, an ashing apparatus.

In the etch back of the barrier insulating film 107, the wall surface of the opening of the barrier insulating film 107 can be tapered by using reactive dry etching. In reactive dry etching, a gas containing fluorocarbon can be used as an etching gas. The hard mask film 107a is preferably completely removed during etch back, but may be left as it is if it is an insulating material. In addition, the shape of the opening of the barrier insulating film 107 can be circular, and the diameter of the circle can be 30 nm to 500 nm.
(Step 6)
The ion conductive layer 109 is formed on the barrier insulating film 107 including the first wiring A 105 a and the first wiring B 105 b. First, 1 nm of zirconium is deposited by sputtering. Zirconium is oxidized when forming the second ion conduction layer 109b to form a first ion conduction layer 109a. At this time, when the copper of the first wiring A 105 a and the first wiring B 105 b is oxidized by performing annealing at a temperature of 350 ° C. under a vacuum environment, oxygen on the copper side diffuses into the first ion conductive layer 109 a And oxidized copper is reduced. This is because oxygen is transferred to the zirconium side which is more easily oxidized because the Gibbs energy generated normally of copper oxide is larger than the Gibbs energy generated normally of zirconium oxide. The annealing is preferably about 2 minutes to 10 minutes.

Further, a SiOCH polymer film containing silicon, oxygen, carbon, and hydrogen is formed by plasma CVD as the second ion conductive layer 109b. The raw material cyclic organic siloxane and helium as a carrier gas flow into the reaction chamber, the supply of both is stabilized, and when the pressure in the reaction chamber becomes constant, the application of RF power is started. The supply amount of the raw material is 10 to 200 sccm, and the supply amount of helium is 500 sccm supplied directly to the reaction chamber in a separate line and 500 sccm via the raw material vaporizer. Since moisture and the like are attached to the opening of the barrier insulating film 107 by exposure to the air, heat treatment is performed under reduced pressure at a temperature of about 250 ° C. to 350 ° C. before deposition of the first ion conductive layer 109 a to degas the substrate. It is preferable to keep the
(Step 7)
An alloy of ruthenium and titanium is formed as a lower second electrode 110 by co-sputtering to a film thickness of 10 nm on the ion conductive layer 109. At this time, a ruthenium target and a titanium target exist in the same chamber, and an alloy film is deposited by sputtering simultaneously. At this time, by setting the applied power to the ruthenium target to 150 W and the applied power to the titanium target to 50 W, the ruthenium content in the alloy of ruthenium and titanium is 75 at. And%.

Furthermore, the upper second electrode 111 is formed on the lower second electrode 110. As the upper second electrode 111, titanium nitride is formed to a film thickness of 25 nm by reactive sputtering. At this time, the power applied to the titanium target is 600 W, and nitrogen gas and argon gas are introduced into the chamber for sputtering. At this time, by setting the flow rates of nitrogen and argon to 1: 1, the ratio of titanium in titanium nitride is 70 at. And%.
(Step 8)
A hard mask film 112 (for example, a silicon nitride film or a silicon carbonitride film, a film thickness of 30 nm) and a hard mask film 113 (for example, a silicon oxide film, a film thickness of 80 nm) are stacked in this order on the upper second electrode 111. The hard mask film 112 and the hard mask film 113 can be formed by plasma CVD. The hard mask films 112 and 113 can be formed using a general plasma CVD method in the art. The hard mask film 112 and the hard mask film 113 are preferably different types of films. For example, the hard mask film 112 can be a silicon nitride film and the hard mask film 113 can be a silicon oxide film.

At this time, the hard mask film 112 is preferably made of the same material as the protective insulating film 114 and the barrier insulating film 107 described later. That is, by surrounding the entire periphery of the variable resistance element 100 with the same material, it is possible to integrate the material interface, prevent entry of moisture and the like from the outside, and prevent detachment from the variable resistance element 100 itself. . The hard mask film 112 can be formed by a plasma CVD method. For example, it is preferable to use a high density silicon nitride film or the like by high density plasma of a mixed gas of SiH ₄ / N ₂ .
(Step 9)
A photoresist (not shown) for patterning the resistance change element portion is formed on the hard mask film 113. Thereafter, using the photoresist as a mask, the hard mask film 113 is dry etched until the hard mask film 112 appears. The photoresist is then removed using oxygen plasma ashing and organic stripping.
(Step 10)
The hard mask film 112, the upper second electrode 111, the lower second electrode 110, and the ion conductive layer 109 are continuously dry etched using the hard mask film 113 as a mask. At this time, the hard mask film 113 is preferably completely removed during etch back, but may remain as it is. For example, when the upper second electrode 111 is titanium nitride, it can be processed by RIE (Reactive Ion Etching) based on Cl ₂ , and when the lower second electrode 110 is an alloy of ruthenium and titanium, Cl ₂ / RIE processing can be performed with a mixed gas of O ₂ .

Further, in the etching of the ion conductive layer 109, it is necessary to stop the dry etching on the barrier insulating film 107 on the lower surface. When the ion conductive layer 109 is a SIOCH polymer film containing silicon, oxygen, carbon, and hydrogen, and the barrier insulating film 107 is a silicon nitride film or a silicon carbonitride film, a CF ₄ system, CF ₄ / Cl ₂ system The RIE processing can be performed by adjusting the etching conditions with a mixed gas of CF ₄ / Cl ₂ / Ar system or the like.

By using such a hard mask RIE method, processing can be performed without exposing the resistance change element portion to oxygen plasma ashing for resist removal. In addition, when the oxidation treatment is performed by oxygen plasma after processing, the oxidation plasma treatment can be performed without depending on the peeling time of the resist.
(Step 11)
A protective insulating film 114 (for example, a silicon nitride film or a silicon carbonitride film, 20 nm) is formed on the barrier insulating film 107 including the hard mask film 112, the upper second electrode 111, the lower second electrode 110, and the ion conductive layer 109. accumulate. The protective insulating film 114 can be formed by plasma CVD, but it needs to be maintained under reduced pressure in the reaction chamber before film formation, at which time oxygen is desorbed from the side surface of the ion conductive layer 109 to cause ion conduction. The problem of increased layer leakage current arises. In order to suppress them, it is preferable to set the film formation temperature of the protective insulating film 114 to 300 ° C. or less. Furthermore, since the film formation gas is exposed under reduced pressure before film formation, it is preferable not to use a reducing gas. For example, it is preferable to use a silicon nitride film or the like which is formed at a substrate temperature of 300 ° C. by high density plasma using a mixed gas of SiH ₄ / N ₂ .
(Step 12)
An interlayer insulating film 115 (for example, a silicon oxide film), a low dielectric constant film with a low relative dielectric constant (for example, a SiOCH film, 150 nm film thickness) as the Low-k film 116 on the protective insulating film 114, an interlayer insulating film 117 (for example For example, a silicon oxide film is deposited in this order. Thereafter, wiring trenches for the second wiring A118a and the second wiring B118b, and via holes for the via A119a and the via B119b are formed. Thereafter, using the copper dual damascene wiring process, the second wiring A118a and the second wiring B118b are interposed in the wiring trench and the lower hole via the second barrier metal A120a and the second barrier metal B120b (for example, tantalum nitride / tantalum). At the same time, (for example, copper) and the via A119a and the via B119b (for example, copper) are formed. Thereafter, a barrier insulating film 121 (for example, a silicon nitride film) is deposited on the interlayer insulating film 117 including the second wiring A 118 a and the second wiring B 118 b.

  The formation of the second wiring A 118 a and the second wiring B 118 b can use the same process as the formation of the lower layer wiring. At this time, by using the same material as the second barrier metal A 120 a and the upper second electrode 111, the contact resistance between the second barrier metal A 120 a and the upper second electrode 111 can be reduced, and the device performance can be improved. become.

  The interlayer insulating film 115, the low-k film 116, and the interlayer insulating film 117 can be formed by plasma CVD. In order to eliminate the difference in level formed by the resistance change element 100, the interlayer insulating film 115 may be deposited thick, and the interlayer insulating film 115 may be scraped and planarized by CMP to make the interlayer insulating film 115 a desired thickness. The via A 119 a and the via B 119 b are patterned by exposure with the same photomask, and simultaneously etched and formed.

  FIG. 6 is a schematic cross-sectional view showing the configuration of a modification of the semiconductor device of this embodiment. The semiconductor device 10 ′ is characterized in that the via A 119 a and the via B 119 b have the same depth, and the other configuration is the same as the semiconductor device 10. Therefore, the reference numerals of the respective components of the semiconductor device 10 ′ are the same as the reference numerals of the respective components of the semiconductor device 10.

  The portion sandwiched between the first wiring A 105 a and the first wiring B 105 b of the interlayer insulating film 104 is further lower in the depth direction than the dug portion of the end of the first wiring A 105 a and the first wiring B 105 b surrounding this portion. Being dug down. By doing this, the upper surface of the laminated film formed of the ion conductive layer 109, the lower second electrode 110, and the upper second electrode 111 on the interlayer insulating film 104 can be compared with the first wiring A 105a, the first wiring B 105 b, and the first wiring. It can be made to substantially correspond to the upper surface of C105c. Therefore, when the via A119a is connected to the laminated film on the interlayer insulating film 104, the depths of the via A119a and the via B119b can be made the same. By making the depths of the via A 119 a and the via B 119 b the same, it is possible to make the process time such as dry etching when forming the both substantially the same. As a result, it is possible to suppress plasma damage in the case where the process time is shorter, which is generated when the process times for forming both are different.

  FIG. 7 is a schematic cross-sectional view showing another structure of the semiconductor device of the present embodiment. Another semiconductor device 20 of the present embodiment has a two-terminal variable resistance element 200 formed in a multilayer wiring layer on a semiconductor substrate 201 such as a silicon substrate.

  The semiconductor device 20 is different from the semiconductor device 10 in that the semiconductor device 10 has a three-terminal variable resistance element 100, whereas the semiconductor device 20 has a two-terminal variable resistance element 200. The other structures and materials are the same as those of the semiconductor device 10.

  That is, the semiconductor substrate 201, the interlayer insulating film 202, the low-k film 203, and the interlayer insulating film 204 are the same as the semiconductor substrate 101, the interlayer insulating film 102, the low-k film 103, and the interlayer insulating film 104 of the semiconductor device 10. . The first wiring A 205 a, the first wiring C 205 c, the first barrier metal A 206 a, the first barrier metal C 206 c, the barrier insulating film 207, and the oxidation unit 208 are the first wiring A 105 a, the first wiring C 105 c, and the first wiring of the semiconductor device 10. This is the same as the barrier metal A 106 a, the first barrier metal C 106 c, the barrier insulating film 107, and the oxidized portion 108.

  The first ion conductive layer 209 a, the second ion conductive layer 209 b, the lower second electrode 210, the upper second electrode 211, the hard mask film 212, the hard mask film 213, and the protective insulating film 214 The ion conductive layer 109 a, the second ion conductive layer 109 b, the lower second electrode 110, the upper second electrode 111, the hard mask film 112, the hard mask film 113, and the protective insulating film 114 are the same.

  The interlayer insulating film 215, the low-k film 216, the interlayer insulating film 217, and the barrier insulating film 221 are the same as the interlayer insulating film 115, the low-k film 116, the interlayer insulating film 117, and the barrier insulating film 121 of the semiconductor device 10. It is. Furthermore, the second wiring A218a, the second wiring B218b, the via A219a, the via B219b, the second barrier metal A220a, and the second barrier metal B220b are the second wiring A118a, the second wiring B118b, the via A119a, and the via B119b of the semiconductor device 10. And the same as the second barrier metal A 120a and the second barrier metal B 120b.

  The correspondence between the components of this embodiment and the components of the first embodiment is as follows. That is, the resistance change elements 100 and 200 of the present embodiment correspond to the resistance change element 1 of the first embodiment, the ion conductive layers 109 and 209 correspond to the resistance change film 11, and the first wirings A 105 a and 205 a and the first wirings B 105 b. The first electrodes 12 correspond to each other. The lower second electrodes 110 and 210 and the upper second electrodes 111 and 211 are for the second electrode 13, the first barrier metals A 106 a and 206 a, the first barrier metals B 106 b for the barrier metal 14, and the oxidized portions 108 and 208. The insulators 15 correspond to each other.

  According to the resistance change elements 100 and 200 of the present embodiment, the barrier metal of the first wiring is in contact with the resistance change film via the insulator. Thereby, the electric field concentration in the barrier metal is prevented, and the electric field concentration in the first wiring (first electrode) becomes possible. As a result, it is possible to reduce the voltage required for the switch operation of the variable resistance elements 100 and 200 and the variation thereof.

  As described above, according to the present embodiment, it is possible to provide a semiconductor device having a metal deposition type variable resistance element in which the voltage required for the switch operation and the variation thereof are reduced.

  The present invention is not limited to the above embodiments, and various modifications are possible within the scope of the invention described in the claims, and they are also included in the scope of the present invention.

Moreover, although a part or all of the above-mentioned embodiment may be described as the following additional notes, it is not limited to the following.
(Supplementary Note 1)
Metal deposition type resistance change film,
A first electrode which supplies metal ions to the resistance change film in contact with one surface of the resistance change film;
And a second electrode in contact with the other surface of the resistance change film,
The first electrode has a barrier metal on an outer periphery thereof, and the barrier metal is in contact with the variable resistance film via an insulator.
(Supplementary Note 2)
The variable resistance element according to claim 1, wherein the insulator comprises an oxide of the barrier metal.
(Supplementary Note 3)
The variable resistance element according to claim 1 or 2, wherein the barrier metal comprises tantalum or titanium.
(Supplementary Note 4)
Additional resistance change film having a second resistance change film having a metal on the one side of the resistance change film and having a metal whose absolute value of the standard energy of generated Gibbs energy is larger than the first electrode and smaller than the barrier metal The variable resistance element according to any one of the above.
(Supplementary Note 5)
The variable resistance element according to claim 4, wherein the second variable resistance film contains at least one of zirconium, hafnium, indium, lanthanum, manganese, molybdenum, niobium and tungsten.
(Supplementary Note 6)
The variable resistance element according to any one of Appendices 1 to 5, wherein the first electrode comprises copper.
(Appendix 7)
The variable resistance element according to any one of Appendices 1 to 6, wherein the variable resistance film includes an ion conductor having at least silicon, oxygen, and carbon.
(Supplementary Note 8)
The variable resistance element according to Appendix 7, wherein the variable resistance film has a relative dielectric constant of 2.1 or more and 3.0 or less.
(Appendix 9)
15. A semiconductor device comprising the resistance change element according to any one of appendices 1 to 8 and a copper wiring, wherein the copper wiring doubles as the first electrode.
(Supplementary Note 10)
Forming a wire through a barrier metal in a wire trench provided in an interlayer insulating film formed on a semiconductor substrate;
An insulating barrier film having an opening through which at least the barrier metal and the wiring are exposed is formed on the wiring and the interlayer insulating film.
Forming an insulator on the surface of the barrier metal exposed to the opening;
A method of manufacturing a semiconductor device, wherein a resistance change film and an upper electrode are sequentially formed on at least the surface of the insulator and the wiring through the opening.
(Supplementary Note 11)
The method of manufacturing the semiconductor device according to claim 10, wherein the insulator is formed by oxidizing the barrier metal.
(Supplementary Note 12)
The method of manufacturing a semiconductor device according to claim 10, wherein the barrier metal comprises tantalum or titanium.
(Supplementary Note 13)
The second resistance change film is formed between the wiring and the resistance change film, the second resistance change film having a metal whose absolute value of the standard energy of Gibbs energy generated is larger than the wiring and smaller than the barrier metal. A method of manufacturing a semiconductor device according to item 1.
(Supplementary Note 14)
The method of manufacturing the semiconductor device according to claim 13, wherein the second resistance change film includes at least one of zirconium, hafnium, indium, lanthanum, manganese, molybdenum, niobium, and tungsten.
(Supplementary Note 15)
The method for manufacturing a semiconductor device according to any one of appendices 10 to 14, wherein the wiring contains copper.
(Supplementary Note 16)
The method for manufacturing a semiconductor device according to any one of appendices 10 to 15, wherein the resistance change film includes an ion conductor having at least silicon, oxygen, and carbon.
(Supplementary Note 17)
The method of manufacturing the semiconductor device according to claim 16, wherein the resistance change film has a relative permittivity of the ion conductor of 2.1 or more and 3.0 or less.

1, 100, 200 resistance change elements 10, 10 ', 20 semiconductor devices 101, 201 semiconductor substrates 102, 202 interlayer insulating films 103, 203 low-k films 104, 204 interlayer insulating films 105a, 205a first wiring A
105b First Wiring B
105c, 205c first wiring C
106a, 206a first barrier metal A
106b 1st barrier metal B
106c, 206c first barrier metal C
107, 207 barrier insulating film 107a hard mask film 108, 208 oxidized portion 109, 209 ion conductive layer 109a, 209a first ion conductive layer 109b, 209b second ion conductive layer 110, 210 lower second electrode 111, 211 upper second Electrodes 112, 113, 212, 213 Hard mask film 114, 214 Protective insulating film 115, 215 Interlayer insulating film 116, 216 Low-k film 117, 217 Interlayer insulating film 118a, 218a Second wiring A
118b, 218b second wiring B
119a, 219a Via A
119b, 219b Via B
120a, 220a second barrier metal A
120b, 220b second barrier metal B

Claims (10)

Metal deposition type resistance change film,
A first electrode which supplies metal ions to the resistance change film in contact with one surface of the resistance change film;
And a second electrode in contact with the other surface of the resistance change film,
The first electrode has a barrier metal on an outer periphery thereof, and the barrier metal is in contact with the variable resistance film via an insulator.   The variable resistance element according to claim 1, wherein the insulator comprises an oxide of the barrier metal.   The variable resistance element according to claim 1, wherein the barrier metal contains tantalum or titanium.   4. The second resistance change film according to claim 1, further comprising: a metal on the one surface of the resistance change film having a metal whose absolute value of the standard generated Gibbs energy is larger than the first electrode and smaller than the barrier metal. The variable resistance element according to any one of the above.   5. The variable resistance element according to claim 4, wherein the second variable resistance film contains at least one of zirconium, hafnium, indium, lanthanum, manganese, molybdenum, niobium and tungsten.   The variable resistance element according to any one of claims 1 to 5, wherein the first electrode comprises copper.   The resistance change element according to any one of claims 1 to 6, wherein the resistance change film contains an ion conductor having at least silicon, oxygen, and carbon.   A semiconductor device comprising the resistance change element according to any one of claims 1 to 7 and a copper wiring, wherein the copper wiring doubles as the first electrode. Forming a wire through a barrier metal in a wire trench provided in an interlayer insulating film formed on a semiconductor substrate;
An insulating barrier film having an opening through which at least the barrier metal and the wiring are exposed is formed on the wiring and the interlayer insulating film.
Forming an insulator on the surface of the barrier metal exposed to the opening;
A method of manufacturing a semiconductor device, wherein a resistance change film and an upper electrode are sequentially formed on at least the surface of the insulator and the wiring through the opening.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the insulator is formed by oxidizing the barrier metal.

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