JP2019036622A - Storage circuit and control method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage circuit in which a circuit scale is suppressed. SOLUTION: A plurality of flip-flops connected in series, a first wiring that distributes one of a first clock and a second clock to each of the flip-flops, and a third clock are distributed to each of the flip-flops. Each of the flip-flops is based on a first latch that operates based on either a clock from the first wiring or a third clock, and a clock from the first wiring. A storage circuit having a second latch that operates. The first latch operates based on the first clock in the first operation mode, operates based on the third clock in a second operation mode different from the first operation mode, and the second latch operates based on the third clock. It operates based on the first clock in the first operation mode, and operates based on the second clock in the second operation mode. [Selection diagram] Fig. 1

Description

  The present invention relates to a memory circuit and a method for controlling the memory circuit.

  Conventionally, Mux-D method and LSSD (Level Sensitive Scan Design) are methods for performing a scan operation of a shift register formed by connecting a plurality of flip-flops (hereinafter also referred to as “FF”) in a semiconductor integrated circuit in series. ) Method is known (for example, see Patent Document 1).

  In the Mux-D method, since a clock signal (including a relay buffer; the same applies hereinafter) used during normal operation is also used during scan operation, one type of clock wiring is used. On the other hand, in the LSSD system, in addition to the clock signal used during the normal operation, two types of clock signals used during the scan operation are used, so a total of three types of clock wiring are used.

Japanese Patent Laid-Open No. 11-142477

  However, in the Mux-D method, there is only one type of clock wiring that distributes the clock to each FF in the shift register. Therefore, the phase of the clock input to the N + 1 stage FF may be delayed due to the influence of the wiring length, the number of buffer stages, manufacturing variations, and the like, compared to the phase of the clock input to the N stage FF. There is a possibility that the shift register malfunctions due to racing occurring between them (N represents a natural number). In order to prevent this malfunction, for example, even in a scan chain (scan path) in which a plurality of FFs are connected in series, as in the path used during normal operation (normal path), confirmation and countermeasures are taken to ensure that racing does not occur. Is called.

  In a normal path, since a delay occurs due to the presence of a logic gate for performing a logical operation and a relay buffer for long-distance transfer, racing is unlikely to occur. However, since the scan path is a short-distance transfer, such a logic gate and a relay buffer are not necessarily required, so that racing is more likely to occur than in a normal path. Therefore, in the Mux-D method, it is highly necessary to intentionally add a delay gate on the scan path as a countermeasure against racing, and the number of gates may increase and the circuit scale may increase.

  On the other hand, the LSSD system has an advantage of preventing racing because a scan-dedicated clock signal having a sufficiently shifted phase is supplied to each of the master latch and the slave latch during the scan operation, in addition to the clock signal for system operation. . However, there is a risk that the number of gates and wiring increases and the circuit scale increases because there are a total of three clock wiring lines, one clock signal for system operation and two clock signals dedicated to scanning.

  Therefore, the present disclosure provides a memory circuit in which the circuit scale is suppressed and a method for controlling the memory circuit.

In one aspect of the present disclosure,
A plurality of flip-flops connected in series;
A first wiring that distributes either the first clock or the second clock to each of the flip-flops;
A second wiring for distributing a third clock to each of the flip-flops,
Each of the flip-flops is
A first latch that operates based on either the clock from the first wiring or the third clock;
A memory circuit is provided having a second latch that operates based on a clock from the first wiring.

In one embodiment of the present disclosure,
A control device for controlling a memory circuit, comprising:
The memory circuit includes a plurality of flip-flops connected in series, a first wiring for distributing either the first clock or the second clock to each of the flip-flops, and a third clock to each of the flip-flops. A second wiring to distribute,
Each of the flip-flops has a first latch that operates based on either the clock from the first wiring or the third clock, and a second latch that operates based on the clock from the first wiring. And
The control device selects either the first clock or the second clock as a clock to be supplied to the first wiring, and selects either the clock from the first wiring or the third clock in the first latch. A method for controlling a memory circuit is provided which is selected as a clock to be supplied to the memory circuit.

  According to the present disclosure, it is possible to provide a storage circuit whose circuit scale is suppressed and a method for controlling the storage circuit.

It is a figure which shows an example of a structure of a memory circuit. It is a figure which shows an example of a structure of a clock generation part. It is a figure which shows an example of a structure of a flip-flop. It is a figure which shows an example of a structure of a latch. It is a time chart which shows an example of the clock produced | generated by the clock production | generation part. 3 is a flowchart illustrating an example of a method for controlling a memory circuit. It is a time chart which shows an example of scanning operation. It is a figure which shows the 1st circuit structural example of a flip-flop. It is a figure which shows the 2nd circuit structural example of a flip-flop.

  In the memory circuit according to the present embodiment, the clock line connecting the clock generation unit and each FF is reduced to two by improving the LSSD method that does not require racing measures. Since the circuit scale is suppressed due to the decrease in the clock wiring, the degree of integration of the memory circuit is improved. In addition, the number of clock wiring steps and power consumption can be reduced by reducing the number of clock wiring lines. Next, details of the memory circuit in this embodiment will be described.

  FIG. 1 is a diagram illustrating an example of a configuration of a memory circuit in the present embodiment. The scan circuit 100 is an example of a memory circuit in the present embodiment.

  The scan circuit 100 is used in a scan test, for example. A scan test using a scan circuit is one of testability design methods. A control device 101 such as a tester forms a scan chain by connecting a plurality of FFs (scan FFs) in a semiconductor chip in series in a test mode. The control device 101 sets an input signal value (input value) from the scan-in terminal to the scan chain, and observes an output signal value (output value) output from the scan chain from the scan-out terminal. As a result, the scan FF on the scan chain can be handled equivalently to the external input terminal or the external output terminal of the semiconductor chip, so that each circuit under test (each combinational circuit) between the scan FFs can be used by using a semiconductor tester or the like. It can be tested from outside the semiconductor chip.

  The scan circuit 100 is a semiconductor integrated circuit including a clock generation unit 54, a first wiring 51, a second wiring 52, and a plurality of FFs 53.

  The clock generation unit 54 is a circuit that generates a first clock signal CK and a second clock signal TCK based on the reference clock RCK. The clock generation unit 54 supplies the clock signal CK to the wiring 51 and supplies the clock signal TCK to the wiring 52.

  The wiring 51 is one of clock wirings that distributes the clock signal CK to each of the plurality of FFs 53. The wiring 52 is one of clock wirings that distributes the clock signal TCK to each of the plurality of FFs 53.

  The plurality of FFs 53 are connected in series based on the active test mode signal TM supplied from the control device 101, thereby forming the shift register 50. The shift register 50 has a plurality of FFs 53 connected in series so that the output signal SL of the preceding FF 53 is input to the succeeding FF 53 as the scan signal TDI. The scan signal TDI input to the first stage FF 53 is a signal input from the control device 101 via the scan-in terminal of the semiconductor chip. The output signal SL output from the final stage FF 53 is a signal output to the control device 101 via the scan-out terminal of the semiconductor chip.

  The control device 101 outputs a test mode signal TM whose logic level is active when each FF 53 is scanned (when each FF 53 is operated in a test mode). On the other hand, when operating each FF 53 normally (when operating each FF 53 in the normal mode), the control device 101 outputs a test mode signal TM whose logic level is inactive.

  The clock generator 54 may be mounted inside the semiconductor chip or may be mounted outside the semiconductor chip. Since the clock generator 54 is mounted inside the semiconductor chip, the control device 101 that supplies the reference clock RCK in the test mode can handle the scan circuit 100 as an LSSD scan circuit. That is, the control device 101 can supply the reference clock RCK as in the case of supplying the reference clock RCK to a conventional LSSD scan circuit.

  FIG. 2 is a diagram illustrating an example of the configuration of the clock generation unit. The clock generation unit 54 includes a clock generation unit 55 for normal operation, a clock generation unit 56 for scan operation, and a selector 57.

  Based on the reference clock RCK supplied in the normal mode, the normal operation clock generator 55 generates and outputs a normal clock SCK used in the normal operation performed in the normal mode. The clock generator 56 for scan operation generates and outputs two test clocks TCKA and TCKB used during the scan operation performed in the test mode based on the reference clock RCK supplied during the test mode. The normal clock SCCK is an example of the first clock, the test clock TCKB is an example of the second clock, and the test clock TCKA is an example of the third clock. The normal mode is an example of a first operation mode, and the test mode is an example of a second operation mode that is different from the first operation mode.

  The selector 57 is an example of a first selector. The selector 57 is a circuit that selects one of the normal clock SCK and the test clock TCKB as the clock signal CK supplied to the wiring 51 based on the test mode signal TM. The selector 57 selects the normal clock SCK as the clock signal CK when the test mode signal TM is inactive (TM = 0), and selects the test clock TCKB when the test mode signal TM is active (TM = 1). The clock signal CK is selected. On the other hand, the clock generation unit 56 outputs the test clock TCKA as the clock signal TCK supplied to the wiring 52.

  FIG. 3 is a diagram illustrating an example of the configuration of the FF. Each of the plurality of FFs 53 includes a master latch 61, a slave latch 62, an inverter 58, a selector 59, and a selector 60.

  The master latch 61 is an example of a first latch. The slave latch 62 is an example of a second latch. The master latch 61 and the slave latch 62 are circuits each having an input node D, an output node Q, and a clock node CLK. The output node Q of the master latch 61 is connected to the input node D of the slave latch 62. A specific example of the master latch 61 and the slave latch 62 is a D latch.

  The master latch 61 operates based on any one of the clock signal CK from the wiring 51 and the clock signal TCK (test clock TCKA) from the wiring 52. Specifically, the master latch 61 is connected to the input node D of the master latch 61. Holds input data to be input. On the other hand, the slave latch 62 operates based on the clock signal CK from the wiring 51. Specifically, the slave latch 62 is output from the output node Q of the master latch 61 based on the inverted clock of the clock signal CK from the wiring 51. Holds the output signal.

  FIG. 4 is a diagram illustrating an example of the configuration of the latch. Each of the master latch 61 and the slave latch 62 has a configuration illustrated in FIG. Each latch has inverters 63, 65, 66 and a switch 64. The switch 64 operates according to a clock input from the clock node CLK.

  In the present embodiment, each latch writes data input to the input node D when the level of the clock input to the clock node CLK transitions from a low level to a high level. Each latch writes data input to the input node D while the level of the clock input to the clock node CLK is high, and outputs the data input to the input node D as it is from the output node Q. . On the other hand, when the level of the clock input to the clock node CLK transitions from a high level to a low level, each latch outputs data input to the input node D at the transition time (or output from the output node Q at the transition time). Data). Each latch continuously outputs the held data from the output node Q regardless of the logic level of the data input to the input node D while the level of the clock input to the clock node CLK is low. To do.

  In FIG. 3, the FF 53 has a selector 59 before the clock node CLK of the master latch 61. The selector 59 is an example of a second selector. The selector 59 is a clock that supplies one of the clock signal CK from the wiring 51 and the clock signal TCK (test clock TCKA) from the wiring 52 to the clock node CLK of the master latch 61 based on the test mode signal TM. As a circuit to be selected. The selector 59 supplies the clock signal CK to the master latch 61 when the test mode signal TM is inactive. On the other hand, the selector 59 supplies the clock signal TCK to the master latch 61 when the test mode signal TM is active.

  The FF 53 has an inverter 58 in front of the clock node CLK of the slave latch 62. The inverter 58 outputs a signal (inverted clock) obtained by inverting the clock signal CK.

  The FF 53 has a selector 60 in the preceding stage of the input node D of the master latch 61. The selector 60 is an example of a third selector. The selector 60 is a circuit that selects one of the data signal DI and the scan signal TDI as input data to be supplied to the input node D of the master latch 61 based on the test mode signal TM. The selector 60 supplies the data signal DI to the master latch 61 when the test mode signal TM is inactive. On the other hand, the selector 60 supplies the scan signal TDI to the master latch 61 when the test mode signal TM is active.

  The data signal DI is a signal output in a normal mode from a preceding combination circuit among a plurality of combination circuits (not shown) existing between the FFs 53. The scan signal TDI is an output signal SL output in the test mode from the slave latch 62 of the preceding FF 53 among the plurality of FFs 53.

  FIG. 5 is a time chart illustrating an example of a clock generated by the clock generation unit. During normal operation, the inactive test mode signal TM is a normal mode that is input to the clock generator 54 and each FF 53. In the normal mode, the clock generator 54 outputs the normal clock SCK for normal operation as the clock signal CK. In the normal mode, the master latch 61 and the slave latch 62 in each FF 53 operate based on the clock signal CK (in this case, the normal clock SCK).

  On the other hand, during the scan operation, the active test mode signal TM is a test mode that is input to the clock generator 54 and each FF 53. In the test mode, the clock generation unit 54 outputs the test clock TCKB for scan operation as the clock signal CK, and outputs the test clock TCKA for scan operation as the clock signal TCK. In the test mode, the clock generator 54 outputs two clock signals CK and TCK having the same period and different phases. In the test mode, the master latch 61 in each FF 53 operates based on the clock signal TCK (test clock TCKA), and the slave latch 62 in each FF 53 is based on the clock signal CK (in this case, the test clock TCKB). Works.

  FIG. 6 is a diagram illustrating an example of a method for controlling the memory circuit. FIG. 7 is a diagram illustrating an example of a scan operation in the test mode.

  The control device 101 activates the test mode signal TM to set the operation mode of the scan circuit 100 to the test mode (step S1), and sets the data signal DI from the scan-in terminal (step S2). That is, the control device 101 operates the master latch 61 based on the clock signal TCK (in this case, the test clock TCKA), and operates the slave latch 62 based on the clock signal CK (in this case, the test clock TCKB). .

  Next, the control device 101 deactivates the test mode signal TM to set the operation mode of the scan circuit 100 to the normal mode (step S5), and supplies the one-pulse clock signal CK to each FF 53 (step S4). That is, the control device 101 operates the master latch 61 based on the clock signal CK (in this case, the normal clock SCK), and operates the slave latch 62 based on the clock signal CK (in this case, the normal clock SCK). . As a result, in each FF 53, capture is performed in which the data signal DI output from the preceding combinational circuit is taken into the subsequent FF53.

  Next, the control device 101 activates the test mode signal TM to set the operation mode of the scan circuit 100 to the test mode (step S5), and reads the output signal SL from the scan-out terminal (step S6). That is, the control device 101 operates the master latch 61 based on the clock signal TCK (in this case, the test clock TCKA), and operates the slave latch 62 based on the clock signal CK (in this case, the test clock TCKB). .

  Thus, according to the present embodiment, in the test mode, the generation of racing can be prevented by supplying clocks having different phases to the master latch 61 and the slave latch 62. Further, as compared with the conventional LSSD system, the number of clock wirings is reduced from three to two, so that the clock wiring work can be reduced by one step. Further, compared with the Mux-D method, since the racing gate is not necessary, the delay gate is also unnecessary, and therefore the number of steps for the racing countermeasure can be reduced. As described above, the number of gates and wiring can be reduced as compared with the conventional method, so that the circuit scale can be suppressed. Therefore, effects of improving the degree of integration and reducing power consumption can be obtained.

  FIG. 8 is a diagram illustrating a first circuit configuration example of the FF. p * represents a P-channel MOSFET, and n * represents an N-channel MOSFET (* is a natural number). MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor. In the transistor p * and the transistor n *, an electrode with an arrow is a gate, an electrode on the arrowhead side of the arrow is a source, and an electrode on the arrowhead side of the arrow is a drain. According to the circuit configuration of FIG. 8, the FF 53 shown in FIG. 3 can be realized. Note that the connection relationship between the transistors is clear from the drawing, and thus the description thereof is omitted.

  The FF 53 shown in FIG. 8 has a circuit configuration in which the selector 59 is formed by a NAND-NAND circuit. NAND represents a negative logical product. The selector 59 selects and outputs one of the clock signal CK and the clock signal TCK. The selector 59 is formed by a first NAND circuit formed by transistors p2, p3, n2, and n3, a second NAND circuit formed by transistors p4, p5, n4, and n5, and transistors p6, p7, n6, and n7. And a third NAND circuit. The output of the first NAND circuit and the output of the second NAND circuit are input to the third NAND circuit. The output of the third NAND circuit is input to the master latch 61.

  FIG. 9 is a diagram illustrating a second circuit configuration example of the FF. The FF 53 shown in FIG. 9 has a circuit configuration in which the selector 59 is formed by an AND-NOR composite gate. AND represents a logical product, and NOR represents a negative logical sum. Similarly to the case of FIG. 8, the circuit configuration of FIG. 9 can realize the FF 53 shown in FIG. Further, since the connection relationship between the transistors is clear from the drawing, description thereof is omitted.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
A plurality of flip-flops connected in series;
A first wiring that distributes either the first clock or the second clock to each of the flip-flops;
A second wiring for distributing a third clock to each of the flip-flops,
Each of the flip-flops is
A first latch that operates based on either the clock from the first wiring or the third clock;
And a second latch that operates based on a clock from the first wiring.
(Appendix 2)
The first latch operates based on the first clock in a first operation mode, operates based on the third clock in a second operation mode different from the first operation mode,
The storage circuit according to appendix 1, wherein the second latch operates based on the first clock in the first operation mode and operates based on the second clock in the second operation mode.
(Appendix 3)
The first clock supplied to the first wiring in the first operation mode, the second clock supplied to the first wiring in the second operation mode, and supplied to the second wiring in the second operation mode. The memory circuit according to appendix 2, further comprising a clock generation unit that generates the third clock.
(Appendix 4)
The first latch holds input data based on either the clock from the first wiring or the third clock,
4. The memory circuit according to claim 1, wherein the second latch holds an output signal of the first latch based on an inverted clock of the clock from the first wiring. 5.
(Appendix 5)
A first selector that selects either the first clock or the second clock as a clock to be supplied to the first wiring;
Each of the flip-flops is
A second selector for selecting either the clock from the first wiring or the third clock as a clock to be supplied to the first latch;
The storage circuit according to any one of appendices 1 to 4, further comprising: a third selector that selects any one of a data signal and a scan signal as input data to be supplied to the first latch.
(Appendix 6)
The storage circuit according to appendix 5, wherein the first selector, the second selector, and the third selector operate based on a common select signal.
(Appendix 7)
The storage circuit according to any one of appendices 1 to 6, wherein the second clock and the third clock have different phases.
(Appendix 8)
A control device for controlling a memory circuit, comprising:
The memory circuit includes a plurality of flip-flops connected in series, a first wiring for distributing either the first clock or the second clock to each of the flip-flops, and a third clock to each of the flip-flops. A second wiring to distribute,
Each of the flip-flops has a first latch that operates based on either the clock from the first wiring or the third clock, and a second latch that operates based on the clock from the first wiring. And
The control device selects either the first clock or the second clock as a clock to be supplied to the first wiring, and selects either the clock from the first wiring or the third clock in the first latch. A method for controlling a memory circuit, which is selected as a clock to be supplied to the memory.
(Appendix 9)
The control device operates the first latch based on the first clock in a first operation mode, operates based on the third clock in a second operation mode different from the first operation mode,
The storage circuit according to appendix 8, wherein the control device operates the second latch based on the first clock in the first operation mode and operates based on the second clock in the second operation mode. Control method.
(Appendix 10)
The control device includes: the first clock supplied to the first wiring in the first operation mode; the second clock supplied to the first wiring in the second operation mode; and the second clock supplied to the first wiring in the second operation mode. The method for controlling a memory circuit according to appendix 9, wherein the clock generation unit outputs the third clock supplied to the second wiring.
(Appendix 11)
The control device causes the first latch to hold input data based on either the clock from the first wiring or the third clock,
The storage circuit according to any one of appendices 8 to 10, wherein the control device causes the second latch to hold an output signal of the first latch based on an inverted clock of the clock from the first wiring. Control method.
(Appendix 12)
The control device causes the first selector to select either the first clock or the second clock as a clock to be supplied to the first wiring, and selects either the clock from the first wiring or the third clock. Any one of appendices 8 to 11, wherein the second selector is selected as a clock to be supplied to the first latch, and the third selector is selected as input data to be supplied to the first latch, either a data signal or a scan signal A method for controlling the memory circuit according to the item.
(Appendix 13)
13. The storage circuit control method according to appendix 12, wherein the control device outputs a common select signal for operating the first selector, the second selector, and the third selector.
(Appendix 14)
14. The method for controlling a memory circuit according to any one of appendices 8 to 13, wherein the second clock and the third clock have different phases.

50 shift register 51, 52 wiring 53 flip-flop 54 clock generation unit 57, 59, 60 selector 61 master latch 62 slave latch 100 scan circuit 101 control device

Claims (8)

A plurality of flip-flops connected in series;
A first wiring that distributes either the first clock or the second clock to each of the flip-flops;
A second wiring for distributing a third clock to each of the flip-flops,
Each of the flip-flops is
A first latch that operates based on either the clock from the first wiring or the third clock;
And a second latch that operates based on a clock from the first wiring. The first latch operates based on the first clock in a first operation mode, operates based on the third clock in a second operation mode different from the first operation mode,
2. The memory circuit according to claim 1, wherein the second latch operates based on the first clock in the first operation mode and operates based on the second clock in the second operation mode.   The first clock supplied to the first wiring in the first operation mode, the second clock supplied to the first wiring in the second operation mode, and supplied to the second wiring in the second operation mode. The memory circuit according to claim 2, further comprising a clock generation unit that generates the third clock to be generated. The first latch holds input data based on either the clock from the first wiring or the third clock,
4. The memory circuit according to claim 1, wherein the second latch holds an output signal of the first latch based on an inverted clock of the clock from the first wiring. 5. A first selector that selects either the first clock or the second clock as a clock to be supplied to the first wiring;
Each of the flip-flops is
A second selector for selecting either the clock from the first wiring or the third clock as a clock to be supplied to the first latch;
5. The memory circuit according to claim 1, further comprising: a third selector that selects any one of a data signal and a scan signal as input data to be supplied to the first latch. 6.   The memory circuit according to claim 5, wherein the first selector, the second selector, and the third selector operate based on a common select signal.   The memory circuit according to claim 1, wherein the second clock and the third clock have different phases. A control device for controlling a memory circuit, comprising:
The memory circuit includes a plurality of flip-flops connected in series, a first wiring for distributing either the first clock or the second clock to each of the flip-flops, and a third clock to each of the flip-flops. A second wiring to distribute,
Each of the flip-flops has a first latch that operates based on either the clock from the first wiring or the third clock, and a second latch that operates based on the clock from the first wiring. And
The control device selects either the first clock or the second clock as a clock to be supplied to the first wiring, and selects either the clock from the first wiring or the third clock in the first latch. A method for controlling a memory circuit, which is selected as a clock to be supplied to the memory.

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