JP2019022135A - Timing generator and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly accurate timing generator. A timing generator 100 includes a plurality of phase interpolators PI, and each phase interpolator PI includes a first signal having an edge at a first timing, a second signal having an edge at a second timing, and the like. In response to this, the output signal SOUT having an edge at the timing corresponding to the control data can be generated. The timing generator 100 includes N stages (N ≧ 2), each stage including a first phase interpolator 112 and a second phase interpolator 114. The output node of the first phase interpolator 112 of the i-th (1 ≦ i ≦ N-1) stage is the first input of each of the first phase interpolator 112 and the second phase interpolator 114 of the (i + 1) th stage. Connected to the node. Further, the output node of the second phase interpolator 114 of the i-th stage is connected to the second input node of each of the first phase interpolator 112 and the second phase interpolator 114 of the (i + 1) th stage. [Selection diagram] Fig. 3

Description

  The present invention relates to a timing generator.

  In a semiconductor integrated circuit (hereinafter referred to as IC), there are cases where it is desired to digitally control the timing (phase) of an internal signal with high accuracy. In this specification, a circuit that generates an arbitrary timing (phase) is referred to as a timing generator.

1A to 1C are circuit diagrams of a conventional timing generator. The timing generator 10 in FIG. 1A includes a digital counter 12 and a determiner 14. The counter 12 is set with an initial value INIT corresponding to the target timing. When the counter 12 is activated at the reference timing, the counting operation starts. The determiner 14 changes the output OUT when the count value of the counter 12 reaches a predetermined value. The output OUT is a signal delayed by T _CK × INIT from the reference timing. The time resolution in the timing generator 10 is _TCK and is restricted by the frequency of the clock signal CLK applied to the counter 12.

The timing generator 20 in FIG. 1B includes a plurality of delay elements (buffers) D _{1 to} D _N connected in series, and a selector 22 that selects output taps of the plurality of delay elements. The time resolution in this configuration is limited by the delay time τ _d of the delay element. Since the delay time τ _d varies greatly depending on manufacturing variations, temperature, and power supply voltage conditions, a feedback loop for stabilizing the delay time τ _d is usually constructed.

  The timing generator 30 in FIG. 1C includes a PLL (Phase Locked Loop) circuit. The PLL circuit includes a phase comparator PC, a charge pump CP, a VCO (Voltage Controlled Oscillator) 32 and a frequency divider 34. The VCO 32 includes a ring oscillator, and one clock can be selected by a selector 36 from a plurality of taps provided in the ring oscillator. The timing generator 30 in FIG. 1C has a large circuit area and consumes a large amount of power. Further, since it takes time until the feedback loop is stabilized, there is a problem that the startup time is long.

When the timing generator of FIGS. 1A to 1C is used, the upper limit or minimum delay value of the speed of the application circuit using the timing generator is restricted by the timing generator. Therefore, as another approach, a circuit using a phase interpolator (PI) has been proposed (Non-Patent Document 1). Non-Patent Document 1 discloses a circuit configuration in which two-input, three-output phase interpolators (also referred to as phase blenders) are connected in multiple stages. 2A and 2B are circuit diagrams of a timing generator using a conventional phase interpolator. The timing generator 40 shown in FIG. 2A includes a plurality of phase interpolators 42 arranged in a tournament shape. In the case of this method, in order to obtain an M-bit ( ^2M gradation) resolution, (2 × 2 ^M −1) phase interpolators 42 are required, and the circuit area becomes enormous. The multiplexer 44 is required for selecting one output among different 2 ^M pieces of phase output phi _out timings. Furthermore, since the phase interpolator 42 of the signal path that does not contribute to the final output also operates, useless power consumption occurs.

The timing generator 50 in FIG. 2B is configured as a pipeline type including a plurality of phase interpolators 52 and a multiplexer 54 connected in series. In this system, since (M + 1) number of phase interpolators 52 and M number of multiplexers 54 are required to obtain a resolution of M bits (2 ^M gradations), the timing generator 40 in FIG. Compared with this, the circuit area can be greatly reduced.

JP 2001-273048 A JP 2002-190724 A JP 2003-87113 A JP 2006-319966 A JP 2001-339280 A JP2011-259286A JP 2013-46271 A JP 2012-231894 A International Publication WO2012 / 167239

Aravind Tharayil Narayanan et al., "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of .250 dB", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 7, JULY 2016

  As a result of studying the timing generator 50 of FIG. 2B, the present inventor has come to recognize the following problems. In the timing generator 50 of FIG. 2B, the intermediate signal passes through the multiplexer (analog switch) 54.

  In each multiplexer 54, two signal paths are always selected, but the delay amounts of the two selected signal paths are required to be completely the same. In other words, the linearity (that is, the effective time resolution) of the timing control of the timing generator 50 is restricted by the variation in the delay amount of the multiplexer 54.

  In addition, when the pulse signal passes through the multiplexer, waveform distortion occurs. This waveform distortion is also a factor that degrades the linearity of the timing control of the timing generator 50.

  Further, every time the time resolution is increased by one bit, it is necessary to add one combination of the phase interpolator 52 and the multiplexer 54. This means that the variation of the delay amount increases in exchange for the improvement of 1 bit of the time resolution, and the improvement of the time resolution is greatly restricted by this trade-off relationship.

  The present invention has been made in view of the above problems, and one of exemplary purposes of an aspect thereof is to provide a highly accurate timing generator.

  One embodiment of the present invention relates to a timing generator. The timing generator comprises N (N ≧ 2) stages, each stage including a first phase interpolator and a second phase interpolator. The output node of the first phase interpolator of the i-th (1 ≦ i ≦ N−1) stage is connected to the first input node of each of the first phase interpolator and the second phase interpolator of the (i + 1) -th stage. Is done. The output node of the second phase interpolator of the i-th stage is connected to the second input node of each of the first phase interpolator and the second phase interpolator of the (i + 1) th stage. Each of the first phase interpolator and the second phase interpolator can receive the first signal at the first input node and the second signal at the second input node, and can generate an output signal having an edge at a timing according to the control data. Configured.

  According to this aspect, the resolution K in each stage can be used as a design parameter, and the resolution of the timing generator as a whole can be defined according to the resolution K and the number N of stages. Theoretically, the time resolution is infinitely high without being limited to the frequency of the reference signal. In addition, since a signal having timing information at the edge does not pass through the multiplexer (analog switch), highly accurate timing control is possible. In addition, by adjusting the resolution K of each stage, it is possible to design to suppress the number N of stages, and it is also possible to suppress variations accompanying an increase in the number of stages.

  In the Nth stage, one of the first phase interpolator and the second phase interpolator may be omitted. As a result, the circuit area can be reduced.

  In the i-th (1 ≦ i ≦ N−1) stage, the edges of the output signals of the first phase interpolator and the second phase interpolator may have a time difference corresponding to the time resolution of the stage. For example, in each stage, codes having different values may be supplied to the first phase interpolator and the second phase interpolator. Thereby, the highest time resolution can be obtained.

  In the first stage, a common first reference signal is input to the first input nodes of the first phase interpolator and the second phase interpolator, and the second input of the first phase interpolator and the second phase interpolator. A common second reference signal may be input to the nodes.

  In the first stage, the first reference signal is input to the first input node of the first phase interpolator, and the second input node of the first phase interpolator and the first input node of the second phase interpolator are A common second reference signal may be input, and a third reference signal may be input to the second input node of the second phase interpolator.

  The phase interpolator charges or discharges the capacitor with the amount of current according to the control data after the occurrence of the first timing according to the capacitor and (i) the first signal, and (ii) according to the second signal, A charge / discharge circuit that charges or discharges the capacitor with a constant amount of current after the second timing occurs, and an output circuit that generates an output signal whose level changes when the voltage of the capacitor reaches a threshold value may be included. .

  In one aspect, the phase interpolator includes a first input node that receives a first signal that transitions from a first level to a second level, and a second signal that transitions from the first level to the second level after being delayed from the first signal. Receiving a second input node, a first line to which a first voltage is supplied, a second line to which a second voltage is supplied, an intermediate line, a capacitor having one end connected to the intermediate line, and a first signal And an initialization circuit for initializing the voltage of the capacitor during a period in which both the second signal and the second signal are at the first level, and a plurality of parallel connections between the intermediate line and the second line corresponding to a plurality of bits of the input code And an output circuit that generates an output signal whose level changes when the voltage of the capacitor crosses a predetermined threshold value. Each circuit unit includes a resistor and a first path provided in series between the intermediate line and the second line, and a second path provided in parallel with the first path. The first path is configured to be on when the first signal is at the second level and the corresponding bit of the input code is the first value, and the second path is at the second level of the second signal. And when the corresponding bit of the input code is the second value, it is configured to be turned on.

According to this aspect, when the delay time of the second signal with respect to the first signal is T _P and the number of circuit units is N, the phase of the output signal can be controlled with T _P / N as the unit delay width.

  Since a current source that defines the charging current or discharging current (collectively referred to as charging / discharging current) of the capacitor is not required, in one embodiment, low voltage operation is possible.

  In the configuration using a current source, a bias circuit for biasing the current source is required, and a delay at the start of the operation can be a problem. On the other hand, since this embodiment does not require a bias circuit, in one embodiment, it is possible to perform a phase interpolation operation without waiting for the bias circuit to start when the operation starts.

  Further, in a configuration in which a capacitor is discharged (or charged) only by a MOS (Metal Oxide Semiconductor) transistor without using a resistor or a current source, it is necessary to define a charge / discharge current based on the gate length L of the MOS transistor. In this case, if the gate length L is increased in order to reduce the current, the gate capacity increases and power consumption increases. On the other hand, it is possible to adjust the charge / discharge current based on the channel width W of the MOS transistor. However, reducing the channel width W in order to reduce the current causes an increase in dispersion and a decrease in performance. Will do. In addition, the minimum width of the channel width W has a process manufacturing limit. Therefore, it is difficult to achieve both low power consumption and high performance with the design method of charge / discharge current using only the parameter W / L of the MOSFET. On the other hand, in this aspect, the charge / discharge current can be defined by the resistance. Therefore, in one embodiment, the gate capacitance of the first switch can be reduced, and the power consumption can be reduced.

  Furthermore, since circuit design using both the capacitance of the capacitor and the resistance value of the resistor as parameters is possible, it is possible to design in consideration of the balance of accuracy, circuit area, power consumption, and the like.

  The first route and the second route may include a first switch and a second switch, respectively. The first signal is input to the first switch of the first path, the second signal is input to the first switch of the second path, and the corresponding bit of the input code is input to the second switch of the first path. And the complementary signal of the corresponding bit of the input code may be input to the second switch of the second path.

  The second switch may be provided between the first switch and the resistor. Thereby, DNL (differential nonlinearity error) and INL (integral nonlinearity error) can be improved compared to the reverse case.

Each of the first path and the second path may further include a third switch provided on the opposite side of the second switch across the first switch. A bit corresponding to the input code may be input to the third switch of the first path, and a complementary signal of the corresponding bit of the input code may be input to the third switch of the second path.
Thereby, the influence of clock feedthrough and charge injection on both the resistance side and the intermediate line side can be suppressed, and DNL (differential nonlinearity error) and INL (integral nonlinearity error) can be further reduced.

  One end of the resistor may be connected to the second line, and the first path may be provided between the other end of the resistor and the intermediate line.

  One end of the resistor may be connected to the intermediate line, and the first path may be provided between the other end of the resistor and the second line.

  The initialization circuit may include an initialization transistor provided between the first line and the intermediate line, and a logic gate that turns on the initialization transistor during a period in which both the first signal and the second signal are at the first level. Good.

  The capacitor may be a variable capacitor. The other end of the capacitor may be grounded.

  Another embodiment of the present invention relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay pulse generator. The delay pulse generator may include a set signal generator that generates a set signal and a reset signal generator that generates a reset signal. At least one of the set signal generator and the reset signal generator may include any of the timing generators described above. The delay pulse generator may output a pulse signal that transitions to a first level according to the output signal of the set signal generator and to a second level according to the output signal of the reset signal generator.

  The pulse signal may be a pulse width modulation signal. When modulating the edges on both sides, both the set signal generator and the reset signal generator may be composed of the timing generator described above. When only one edge is modulated, only one of the set signal generator and the reset signal generator may be configured by the timing generator described above, and the other may be configured by a fixed delay circuit.

  The semiconductor integrated circuit may be a class D amplifier controller, a DC / DC converter controller, an LED driver controller, or a motor controller.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  Further, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore a sub-combination of these described features can also be the present invention. .

  According to an aspect of the present invention, a highly accurate timing generator can be provided.

1A to 1C are circuit diagrams of a conventional timing generator. 2A and 2B are circuit diagrams of a timing generator using a conventional phase interpolator. It is a block diagram of the timing generator which concerns on embodiment. It is a figure explaining the basic operation | movement of a phase interpolator. FIG. 4 is an operation waveform diagram of the timing generator of FIG. 3. It is a figure explaining the pipeline operation | movement of the timing generator of FIG. It is a circuit diagram of the timing generator concerning the 1st modification. It is a circuit diagram of a delay pulse generator using a timing generator. It is a block diagram of a digitally controlled switching power supply. It is a block diagram of a motor drive system. FIGS. 11A and 11B are block diagrams of audio circuits. It is a block diagram of a light-emitting device. It is a circuit diagram of the phase interpolator which concerns on 1st Embodiment. It is a circuit diagram of the phase interpolator which concerns on 1st Example. 15A to 15C are circuit diagrams of configuration examples of the output circuit. It is a circuit diagram of another example of composition of an output circuit. It is a circuit diagram of another example of composition of an output circuit. It is a circuit diagram of the example of composition of a capacitor. It is an operation | movement waveform diagram of a phase interpolator. 20A and 20B are equivalent circuit diagrams for explaining the operation of the phase interpolator. It is a figure explaining the dependence of the control code of operation | movement of a phase interpolator. FIG. 3 is a simplified circuit diagram of a phase interpolator according to a first comparison technique. FIG. 6 is a simplified circuit diagram of a phase interpolator according to a second comparison technique. It is a circuit diagram of the phase interpolator which concerns on 1st Example. It is a circuit diagram of the phase interpolator which concerns on 2nd Example. FIGS. 26A to 26C are operation waveform diagrams of the phase interpolators according to the first to third embodiments. FIGS. 27A and 27B are diagrams illustrating the relationship between the input code and the delay amount of each of the phase interpolators according to the first to third embodiments. FIG. 28A is a diagram showing the DNL of each of the phase interpolators according to the first to third embodiments, and FIG. 28B is the INL of each of the phase interpolators according to the first to third embodiments. FIG. It is a circuit diagram of the phase interpolator which concerns on 2nd Embodiment. It is a circuit diagram of the phase interpolator which concerns on 4th Example. It is a circuit diagram of the phase interpolator which concerns on 5th Example. It is a circuit diagram of the phase interpolator which concerns on 3rd Embodiment. It is a circuit diagram of the phase interpolator which concerns on 6th Example. It is an operation | movement waveform diagram of the phase interpolator of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. This includes cases where the connection is indirectly made through other members that do not affect the connection state or inhibit the function.

  Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C, or the member B and the member C are directly connected, This includes cases where the connection is indirectly made through other members that do not affect the connection state or inhibit the function.

  FIG. 3 is a block diagram of the timing generator 100 according to the embodiment. The timing generator 100 is composed of a combination of a plurality of phase interpolators PI.

The phase interpolator PI has two input nodes IN1, IN2 and one output node OUT. The two input nodes IN1, IN2, and the signal _{S 1} having an edge in the first timing phi _A, the signal _{S 2} having the edge is input to the second timing phi _B. The phase interpolator PI generates an output signal having an edge at the timing φ _OUT corresponding to the control data, and outputs it from the output node OUT. Here for ease of understanding, the first timing phi _A, it is assumed that precedes the second timing phi _B.

FIG. 4 is a diagram for explaining the basic operation of the phase interpolator PI. The signal _{S 1} of the edge is generated at the input node IN1 at time _{t 0,} from time _{t 0} to time _{t 1} after a predetermined time ΔT elapses, the signal _{S 2} of the edge of the input node IN2 is generated. If the number of gradations of the phase interpolator PI is K (K ≧ 2), the time resolution Δt is given by ΔT / K. The phase interpolator PI, control data _{D CNT} is given, when the d value of the control data _{D CNT} in decimal, the time _{t 2} generated by the edge of the output signal _{S OUT} (output timing phi _OUT) is Is given by the following equation.
t ₂ = t ₁ + τ + d × Δt
τ is a predetermined offset delay amount, and τ ≧ 0.

  The configuration of the phase interpolator PI is not particularly limited, and a known technique may be used, or a configuration described later may be employed.

  Returning to FIG. The timing generator 100 includes N (N ≧ 2) stages 110_1 to 110_N. Each stage 110 includes a first phase interpolator (hereinafter referred to as a main interpolator) 112 and a second phase interpolator (hereinafter referred to as a sub interpolator) 114.

  The output node OUT of the main interpolator 112 of the i-th (1 ≦ i ≦ N−1) stage 110 — i is the first input of each of the main interpolator 112 and the sub-interpolator 114 of the (i + 1) -th stage 110 — (i + 1). Connected to node IN1. The output node OUT of the sub-interpolator 114 of the i-th stage 110_i is connected to the second input node IN2 of each of the main interpolator 112 and the sub-interpolator 114 of the (i + 1) -th stage 110_ (i + 1).

The two reference signals REF ₁ and REF ₂ may be given to the main interpolator 112 and the sub interpolator 114 of the first stage 110_1, as shown by a one-dot chain line. The edge of one reference signal REF ₂ is delayed by a predetermined time ΔT ₀ from the edge of the other REF ₁ .

Each stage can have a different number of gradations K, and the number of gradations of the i-th stage is represented as K _i (K ≧ 2). Of course, all the stages may have the same number of gradations.

Each stage 110 is given control data _{DCNT [i]} . The main interpolator 112 generates an output signal S _{OUTA [i]} having an edge at timing φ _{OUTA [i]} corresponding to the value d _i of the control data D _{CNT [i]} .

On the other hand, the sub-interpolator 114 generates an output signal S _{OUTB [i]} having an edge at a predetermined delay time ΔT _[i] and a delayed timing φ _{OUTB [i]} from the timing φ _{OUTA [i]} of the main interpolator 112. To do.

The main interpolator 112 and the sub interpolator 114 are supplied with values d _{A [i]} and d _{B [i]} corresponding to the control data D _{CNT [i]} , respectively.

For example, when the configurations of the main interpolator 112 and the sub interpolator 114 are the same, a predetermined difference J _[i] may be given to the codes given to the main interpolator 112 and the sub interpolator 114.
d _{A [i]} = d _i
d _{B [i]} = d _i + J _i
And it is sufficient. J _[i] is a constant, and is preferably 1. However, any other value may be used, and the delay time ΔT _[i] is represented by the following equation.
ΔT _[i] = Δt _[i−1] × J _[i]

In the following, it is assumed that J _[i] = 1, the delay time ΔT _[i] is equal to the time resolution Δt _[i], and the following relational expression holds.
Δt _[i] = Δt _[i−1] / K _i

Alternatively, the circuit configuration of the main interpolator 112 and the sub interpolator 114 is changed so that a predetermined delay time ΔT _[i] is generated when the same value d _i is given to the main interpolator 112 and the sub interpolator 114. May be added.

  In the Nth stage 110_N, one of the main interpolator 112 and the sub interpolator 114 may be omitted. As a result, the circuit area can be reduced.

  The above is the configuration of the timing generator 100. Next, the operation will be described. FIG. 5 is an operation waveform diagram of the timing generator 100 of FIG.

Here, for ease of understanding, it is assumed that N = 2 and K ₁ = K ₂ = 4. Further, the offset delay amount τ of each stage is set to zero. Reference signals REF ₁ and REF ₂ having a time difference ΔT ₀ are input to the _first stage. FIG. 5 shows the operation when d ₁ = 1 and d ₂ = 3.

The edge timing φ _{A [1]} of the output S _{OUTA [1]} of the _first stage main interpolator 112 occurs at time t ₂ .
t ₂ = t ₁ + Δt _[1] × d ₁ = t ₁ + Δt _[1]
The edge timing φ _{B [1]} of the output S _{OUTB [1]} of the sub-interpolator 114 of the first stage occurs at time t ₃ .
t ₃ = t ₂ + ΔT _[1]

The edge timing φ _{A [2]} of the output S _{OUTA [2]} of the second stage main interpolator 112 occurs at time t ₄ .
t ₄ = t ₃ + Δt _[2] × d ₂ = t ₃ + 3 × Δt _[2]
The edge timing φ _{B [2]} of the output S _{OUTB [2]} of the second stage sub-interpolator 114 occurs at time t ₅ .
t ₅ = t ₄ + ΔT _[2]

In this example, the output S _{OUTA [2]} of the second stage main interpolator 112 is taken out as the output of the timing generator 100. The edge φ _{OUTA [2]} of the output S _{OUTA [2]} has a phase corresponding to the two control data _DCNT .

FIG. 6 is a diagram for explaining the pipeline operation of the timing generator of FIG. M _i represents the resolution of the i-th stage, and the relationship K _i = 2 ^Mi holds. Each time the stage advances, the time difference ΔT between the two outputs of the previous stage becomes 1/2 ^Mi times, and the time resolution increases.

The above is the operation of the timing generator 100. According to the timing generator 100, in accordance with increasing the number of stages N of the stage, also in accordance with increasing the resolution K _i of each stage, it is possible to increase the resolution of the phase. When generalized, the number of gray levels of the timing generator 100 is K ₁ × K ₂ ×... × K _N. If the number of stages is N, K ₁ = K ₂ =... = K _N = K, phase control with K ^N gradations is possible, and the time resolution is ΔT ₀ / K ^N. For example, when K = 16 and N = 2, 256 gradations (equivalent to 8 bits) can be controlled.

The timing generator 100 has the following advantages.
First, the timing generator 100 does not necessarily require a high-speed clock in order to obtain fine time resolution. When only a low-speed clock exists and the time difference ΔT ₀ between the _two reference signals REF ₁ and REF ₂ is large, the time resolution can be increased by increasing the number of stages and / or increasing the number of gradations of each stage. Can be high.

  Secondly, the timing generator 100 has the advantages of a small circuit area and low power consumption. Specifically, in comparison with the timing generator 40 in FIG. 2A, the number of phase interpolators PI required to obtain the same time resolution can be greatly reduced. Further, in the comparison including the timing generator 50 of FIG. 2B, the number of stages necessary for obtaining the same time resolution can be reduced by increasing the resolution K for each stage.

  In addition, in the timing generator 100, all the phase interpolators PI contribute to the output, and no wasteful power consumption is generated, which is advantageous from the viewpoint of power consumption.

Further, in relation to the power consumption, the timing generator 100 operates only when the _two reference signals REF ₁ and REF ₂ change, so that no unnecessary power consumption occurs.

Third, the timing generator 100 has the advantage that analog switch (multiplexer) on the signal path is not required, and can adjust the number of stages N by resolution K _i of each stage. As described above, the timing generator 50 in FIG. 2B has a reduced time resolution or is restricted by the multiplexer (switch) 52 on the signal path. Further, in the timing generator 50 of FIG. 2B, the number of stages must be increased according to the required time resolution. When the number of stages increases, the delay amount is greatly varied, the linearity of the timing control is deteriorated, and the effective time resolution is lowered. On the other hand, the timing generator 100 does not need to switch the signal path, does not need a multiplexer, and can increase the number of stages even if the time resolution is improved. Resolution can be realized with high linearity. However, the timing generator 100 may be used for an application that requires a time resolution of several tens of ps to sub-ns.

  Fourth, since the timing generator 100 does not have a feedback loop, there is an advantage that start-up is fast.

  Fifth, when a phase interpolator described with reference to FIG. 13 or later is used as the phase interpolator of the timing generator 100, it is less likely to be affected by process variations, power supply voltage variations, and temperature variations. There is.

  Next, a modified example of the timing generator 100 will be described.

(First modification)
FIG. 7 is a circuit diagram of the timing generator 100 according to the first modification. In the first stage 110_1, the reference signal REF ₁ is common to the first input node N1 of the main interpolator 112, and is common to the second input node N2 of the main interpolator 112 and the first input node N1 of the sub-interpolator 114. reference signal REF ₂ of, the second input node N2 of the secondary interpolator 114, the reference signal REF ₃ is input.

(Second modification)
In the embodiment, the case where the output of the sub interpolator 114 is delayed with the main interpolator 112 as a reference has been described. However, the present invention is not limited to this, and the output of the main interpolator 112 is preceded by the output of the sub interpolator 114 as a reference. You may let them.
d _{A [i]} = d _i −J _[i]
d _{B [i]} = d _i

(Use)
Next, the use of the timing generator 100 will be described. FIG. 8 is a circuit diagram of a delay pulse generator 200 using the timing generator 100. The delay pulse generator 200 includes a set signal generator 210, a reset signal generator 220, an output circuit 230, and a reference signal generator 240. At least one of the set signal generator 210 and the reset signal generator 220 includes the timing generator 100 of FIG.

The reference signal generator 240 generates reference signals REF ₁ and REF ₂ having predetermined frequencies and supplies them to the set signal generator 210 and the reset signal generator 220. The set signal generator 210 generates a set signal S _SET having an edge at timing t ₁ corresponding to the control data D _{CNT_SET} . The reset signal generator 220 generates a reset signal S _RESET having an edge at timing t ₂ corresponding to the control data D _{CNT_RESET} . The output circuit 230 generates a pulse signal S _OUT that transitions to a first level (eg, high) in response to the set signal S _SET and transitions to a second level (eg, low) in response to the reset signal S _RESET . The configuration of the output circuit 230 is not limited, and can be configured by a flip-flop or a latch.

The delayed pulse generator 200 can set the edge of the pulse signal S _OUT at arbitrary timings t ₁ and t ₂ in accordance with the control data D _{CNT_SET} and D _{CNT_RESET} . The delay pulse generator 200 can be used as a digital pulse width modulator (DPMW), for example.

When used as a digital pulse width modulator, since the cycle of the pulse signal S _OUT is constant, one value of the control data D _{CNT_SET} and D _{CNT_RESET} (that is, the positive edge (rising edge, leading edge) of the pulse signal S _OUT ) And the negative edge (one timing of the falling edge and trailing edge) are fixed, and the other is variable, so that the pulse width (the length of the high section or the low section) can be changed.

Alternatively, when the timing of the positive edge of the pulse signal S _OUT is fixed, only the reset signal generator 220 may be configured using the timing generator 100, and the set signal generator 210 may be configured with a delay circuit. When fixing the timing of negative edge of the pulse signal S _OUT Conversely, only the set signal generator 210 is constructed using a timing generator 100, the reset signal generator 220 may be configured with a delay circuit.

  Next, the application of the delay pulse generator 200 will be described. The delay pulse generator 200 can be used in various digital controller ICs (Integrated Circuits).

  FIG. 9 is a block diagram of a digitally controlled switching power supply 300. The switching power supply 300 includes a peripheral circuit 310 in addition to the controller 400. Although FIG. 9 shows a buck converter, the topology of the peripheral circuit 310 is not limited thereto, and various circuit configurations such as a boost converter, a buck-boost converter, a flyback converter, and a forward converter can be taken.

The controller 400 is an IC (Integrated Circuit) integrated on one semiconductor chip. Transistor _M H, _{M L} may be integrated in the controller 400. A feedback signal V _FB corresponding to the output voltage V _OUT is input to the feedback (FB) pin of the controller 400. The A / D converter 410 converts the feedback signal V _FB into a digital signal D _FB . The digital controller 420 feedback-controls the duty ratio command value DUTY so that the digital signal D _FB approaches the target value D _REF . The digital controller 420 includes a PI (proportional / integral) controller or a PID (proportional / integral / differential) controller.

Digital pulse width modulator 430 is configured using the architecture of the delay pulse generator 200 of Figure 8, the high-side pulse S _H having a pulse width corresponding to the duty ratio command value DUTY, therewith complementary low-side pulses S _L is generated. High-side driver 440H, respectively low-side driver 440L is a high-side pulse _{S H,} in accordance with the low-side pulse _{S L,} the transistor _M H of the peripheral circuit 310, drives the _{M L.}

  Although the constant voltage output has been described in this example, the present invention can also be applied to a constant current output.

  FIG. 10 is a block diagram of the motor drive system 500. The motor drive system 500 includes a three-phase motor 502, a three-phase inverter 510, a rotation speed detector 520, and a motor controller 600.

The rotation speed detector 520 generates a rotation speed signal _SDET indicating the rotation speed of the three-phase motor 502. The motor controller 600 controls the three-phase inverter 510 so that the current rotational speed indicated by the rotational speed signal _SDET approaches the target rotational speed.

  The motor controller 600 is an IC (Integrated Circuit) integrated on one semiconductor chip. The motor controller 600 includes a digital controller 610, digital pulse modulators 620U to 620W, and gate drivers 630U to 630W.

Digital controller 610, the current rotational speed indicated by the speed signal _{S DET} is to approach the target rotation speed, generates a duty ratio command value DUTY_U～DUTY_W. The configuration and control method of the digital controller 610 are not particularly limited, and a known technique may be used. Digital pulse modulator 620U~630W generates a pulse signal _{S OUT _U~S} OUT _W having a pulse width corresponding to a corresponding duty ratio command value DUTY_U～DUTY_W. The gate driver 630U~630W, depending on the corresponding pulse signal _{S OUT _U~S} OUT _W, drives the corresponding leg of the three-phase inverter 510.

  In this example, the rotation speed control system has been described. However, the present invention can also be applied to a motor drive system for torque control and position control. Further, the digital pulse modulator 620 and the gate driver 630 may be integrated in one IC.

  FIGS. 11A and 11B are block diagrams of audio circuits. FIG. 11A shows a single end system and FIG. 11B shows a BTL (Bridged Transformerless) system, but the basic configuration is the same. The audio circuit 800 includes an electroacoustic transducer 802, a filter 804, and an audio IC 820. The electroacoustic transducer 802 is a speaker or a headphone, and converts an electrical signal into an acoustic signal. The filter 804 removes a high-frequency component of a PWM (Pulse Width Modulation) signal generated by the audio IC 820 and supplies it to the electroacoustic transducer 802.

The audio IC 820 includes a digital pulse width modulator 822, a gate driver 824, and a class D amplifier 826. The digital pulse width modulator 822 converts the digital audio signal _DIN into a PWM signal _SPWM . The gate driver 824 drives the class D amplifier 826 in accordance with the PWM signal.

  11A and 11B, the digital pulse width modulator 822 can be configured using the architecture of the delay pulse generator 200 described above.

  FIG. 12 is a block diagram of the light emitting device. The light emitting device 900 includes an LED 902, a dimming circuit 904, a DC / DC converter 906, and an LED driver controller 920.

The DC / DC converter 906 supplies the drive voltage V _OUT to the _LED 902 and outputs a current I _LED stabilized to a certain amount. The topology of the DC / DC converter 906 is not limited and may be a synchronous rectification step-down converter. Alternatively, the DC / DC converter 906 may be a boost converter or a flyback converter. The sense resistor R _S is provided in series with the _LED 902 in order to detect the current I _LED flowing through the _LED 902 (or the dimming circuit 910). The dimming circuit 910 switches the current I _LED flowing in the _LED 902 with a duty ratio corresponding to the target luminance. The dimming circuit 910 includes a bypass switch 912 in parallel with the LED 902 and a digital pulse width modulator 914. The digital pulse width modulator 914 generates a PWM signal having a duty ratio corresponding to the target luminance of the LED 902 and drives the bypass switch 912 according to the PWM signal. The digital pulse width modulator 914 can be constructed using the architecture of the delayed pulse generator 200 described above.

The LED driver controller 920 drives the switching element 908 of the DC / DC converter 906 so that the output current I _LED of the DC / DC converter 906 becomes constant. The A / D converter 922 converts one of the current detection signals _VCS into a digital value in an operation region where the current I _LED is somewhat large. The controller 924, the current detection signal _{V CS} so as to approach the target value, and generates a duty ratio command value DUTY (constant current mode). Current _{I LED} is a small operation region, because the detection of the current detection signal _{V CS} is difficult, A / D converter 922 converts the output voltage _{V OUT} to a digital value. The controller 924 generates the duty ratio command value DUTY so that the output voltage _VOUT approaches the target value (constant voltage mode). The digital pulse width modulator 926 generates a PWM signal S _PWM corresponding to the duty ratio command value DUTY. The driver 928 drives the switching element of the DC / DC converter 906 according to the PWM signal S _PWM . The digital pulse width modulator 926 may be configured using the architecture of the delayed pulse generator 200 described above.

(Phase interpolator)
The configuration of the phase interpolator is not particularly limited, and for example, a known phase interpolator as described in Patent Documents 1 to 9 can be used. However, in order to realize the higher linearity of the timing generator 100, a phase interpolator described below can be used.

(First embodiment)
FIG. 13 is a circuit diagram of the phase interpolator 700 according to the first embodiment. The phase interpolator 700 has a first input node IN1, a second input node IN2, and an output node OUT. The two input nodes IN1, IN2, and the signal _{S 1} having an edge in the first timing phi _A, the signal _{S 2} having the edge is input to the second timing phi _B. The phase interpolator 700 generates an output signal S _OUT having an edge at the timing φ _OUT corresponding to the input code D _CNT and outputs it from the output node OUT. Here, for ease of understanding, the first timing phi _A, shall precede the second timing phi _B, to their time difference and T _P. The time difference _{T P} is also referred to as a reference time _{T P.} In this embodiment, the edge defining the timing (phase) is a positive edge (rising edge, leading edge).

Phase interpolator 700 includes a first line 702, second line 704, intermediate line 706, the capacitor _{C 1,} the initialization circuit 710, a plurality of circuit units 720_1～720_N, the output circuit 730 and an input buffer 740. The number N of circuit units 720 corresponds to the number of gradations (time resolution) of the phase interpolator 700, in other words, the number of gradations of the input code _DCNT , and when the input code _DCNT is expressed by a thermometer code. Equal to the number of bits.

A first voltage is supplied to the first line 702, and a second voltage is supplied to the second line 704. In the present embodiment, the first voltage is the power supply voltage V _DD and the second voltage is the ground voltage V _SS (V _GND ). Therefore, the first line 702 is a power supply line and the second line 704 is a ground line.

One end of the capacitor C ₁ is connected to the intermediate line 706, the other end potential thereof is grounded is fixed.

Initialization circuit 710 is provided between the first line 702 and the intermediate line 706, the period first signals _{S 1} and the second signal _{S 2} are both the first level (low level), the capacitor _{C 1} of the voltage ( The capacitor voltage V _C1 is initialized. Here, the initialization voltage is the power supply voltage V _DD of the first line 702.

The plurality of circuit units 720_1 to 720_N are connected in parallel between the intermediate line 706 and the second line 704. A plurality of circuit units 720_1~720_N has a function of discharging the electric charge of the capacitor _{C 1.}

The output circuit 730 generates an output signal S _OUT whose level changes when the capacitor voltage V _C1 crosses a predetermined threshold value V _TH . The timing at which the capacitor voltage V _C1 and the predetermined threshold value V _TH cross is the output timing φ _OUT , and the output signal S _OUT has an edge at the output timing φ _OUT . Although not limited thereto, for example, the output circuit 730 can be configured by voltage comparison means for binarizing the voltage signal, such as a CMOS inverter or buffer, a voltage comparator, a dynamic latch circuit, and a level shift circuit.

The plurality of circuit units 720_1 to 720_N are configured similarly. Each circuit unit 720 includes a resistor R _g , a first path 724, and a second path 726.

One end of the resistor _{R g} is connected to the second line 704. The first path 724 is provided between the resistor _{R g} of the other end and the intermediate line 706. The first path 724, first signal _{S 1} is a second level (high), and the corresponding bit sel input code _{D CNT} is turned on when a first value (here, 1).

The second path 726 between the resistor _{R g} of the other end and the intermediate line 706, is provided in parallel with the first path 724. The second path 726, the signal _{S 2} is a second level (high), and the corresponding bit sel input code _{D CNT} is turned on when the second value (in this case 0 to) a.

The above is the basic configuration of the phase interpolator 700.
Since the phase interpolator 700 has a simple circuit configuration and does not have a current source, the phase interpolator 700 operates at a low voltage. Further, as will be described in detail later, it is not easily affected by process variations, power supply voltage fluctuations, and temperature fluctuations, and can be started at a high speed.

The variation of the resistance R _g is to appear is compressed first signal S ₁ and second signal S ₂ of the edge of the timing phi _A, in relative time difference phi _B, the effect is substantially negligible. This eliminates the need for processing such as trimming the resistor _Rg with high accuracy.

  The present invention is understood as the block diagram and circuit diagram of FIG. 13 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, more specific embodiments and modifications will be described in order not to narrow the scope of the present invention but to help understanding the essence and circuit operation of the invention and to clarify them.

(First embodiment)
FIG. 14 is a circuit diagram of the phase interpolator 700A according to the first embodiment. Initialization circuit 710 includes an initialization transistor _{M P1} is a PMOS transistor, the logic gate 712. The logic gate 712, the signal _{S 1} and a signal corresponding to the logical sum of the second signal _{S 2,} and outputs to the gate of the initialization transistor _{M P1.} The logic gate 712 in this example is an OR gate, the signal _{S 1} and the signal _{S 2} is the period of both the low level, the initialization transistor _{M P1} is turned on, the capacitor voltage _{V C1} is initialized to _{V DD} The

The first path 724 includes a first switch SW _A1 to a third switch SW _A3 connected in series. Similarly, the second path 726 includes a first switch SW _B1 to a third switch SW _B3 connected in series.

The first switches SW _A1 and SW _B1 are NMOS transistors, and the first signals S ₁ and S ₂ are input to the respective gates. The first switch _{SW A1} of the first path 724, the first signal _{S 1} is turned on during the second level (high), the first switch _{SW B1} of the second path 726, the signal _{S 2} is the second Turns on during the level (high) period. The input buffer 740 drives the plurality of first switches SW _A1 and SW _B1 included in the plurality of circuit units 720 according to the first signal S ₁ and the second signal S ₂ . Incidentally, if the output impedance of a circuit for generating a first signal S ₁ and second signal S ₂ is low enough (when the driving capability is high), the input buffer 740 may be omitted.

The pair of the second switch SW _A2 and the third switch SW _A3 in the first path 724 is turned on (off) complementarily with the pair of the second switch SW _B2 and the third switch SW _B3 in the second path 726. The second switch and the third switches SW _A2 , SW _A2 , SW _B2 , and SW _B2 may be transistors that are the same type as the first switches SW _A1 and SW _B1 (that is, NMOS transistors).

The input code D _CNT input to the phase interpolator 700 may be an N-bit thermometer code, and the thermometer code includes N bits sel [0] to sel [N−1]. Each bit sel is supplied to a corresponding one of the plurality of circuit units 720. In each circuit unit 720_i (1 ≦ i ≦ N), the pair of the second switch SW _A2 and the third switch SW _A3 of the first path 724 is controlled according to the corresponding bit sel [i−1], and the second The pair of the second switch SW _B2 and the third switch SW _{B3 in} the path 726 is controlled according to the inverted signal #sel [i−1] of the corresponding bit sel [i−1]. The inversion signal #sel can be generated by the inverter 722.

Regarding the plurality of circuit units 720_1 to 720_N, when the first path 724 (or the second path 726) is in a conductive state, the impedances of the paths are equal and the impedance is R. Impedance R of the first path 724, a resistance value of the resistor _{R g,} the sum of the ON resistance of the plurality of switches _SW A1 _{to SW A3,} the impedance R of the second path 726, a resistance value of the resistor _{R g,} This is the sum of the ON resistances of the plurality of switches SW _{B1 to} SW _B3 .

  FIGS. 15A to 15C are circuit diagrams of configuration examples of the output circuit 730. FIG. The output circuit 730 in FIG. 15A is a CMOS inverter. The output circuit 730 in FIG. 15B is a voltage comparator using a differential amplifier. The output circuit 730 in FIG. 15C is configured using a level shift circuit.

FIG. 16 is a circuit diagram of a configuration example of the output circuit 730. The output circuit 730 in FIG. 16 is configured using a dynamic latch circuit. The capacitor voltage V _C1 is input to the enable terminal (latch terminal, clock input) of the dynamic latch circuit. The output circuit 730 further receives a reset signal RST (inverted logic), and is configured to be initialized before the voltage comparison operation. In the initialized state, the output S _OUT is high. When the capacitor voltage V _C1 crosses the threshold value V _TH , the dynamic latch circuit is activated, voltage comparison between V _DD and V _GND is performed, and the output S _OUT transitions to a low level.

  The output circuit 730 may be formed integrally with a circuit subsequent to the phase interpolator 700. For example, in the case where a differential flip-flop is disposed after the phase interpolator 700, the output circuit 730 can be incorporated in the differential flip-flop. FIG. 17 is a circuit diagram of a differential flip-flop in which the output circuit 730 is incorporated. The configuration of the output circuit 730 in FIG. 17 is the same as that of the dynamic latch circuit in FIG.

Figure 18 is a circuit diagram of a configuration example of the capacitor C _1. Capacitor C ₁ may be constituted by a variable capacitance. The configuration of the variable capacitor is not particularly limited, and a known technique may be used. In addition to the capacitor C _1, or alternatively, the resistance R _g may be variable resistors.

The above is the configuration of the phase interpolator 700A. Next, the operation of the phase interpolator 700A will be described.
FIG. 19 is an operation waveform diagram of the phase interpolator 700A. Here, N = 4 is taken as an example. Prior to time t ₀ , both the first signal S ₁ and the second signal S ₂ are at a low level, and therefore the capacitor voltage V _C1 is initialized to the power supply voltage V _DD which is an initial value. Since the first signal S ₁ and the second signal S ₂ are at the low level, the first switches SW _A1 and SW _B1 are both off, the first path 724 and the second path 726 are in the cut-off state, and the capacitor C ₁ The electric charge is held in

20A and 20B are equivalent circuit diagrams for explaining the operation of the phase interpolator 700. FIG. 20 (a) is representative of the first signal _{S 1} is high level, the signal _{S 2} is at the low level state, i.e., the time _t 0 ~t ₁ in Figure 19. And FIG. 20 (b) represents the first signal _{S 1} and second signal _{S 2} both a high level state, i.e., a time _{t 1} after the Figure 19. When the capacitor voltage V _C1 crosses the threshold voltage V _TH , the output signal S _OUT transitions.

  Of the thermometer code sel [N-1: 0] input to the phase interpolator 700, the number of bits having a value of 1 is K. However, 0 ≦ K ≦ N.

In the state of FIG. 20 (a), the capacitor _{C 1} is discharged by the parallel connection circuit 721a of the K resistors R. The resistance of the parallel connection circuit 721a is R / K, and the time constant is CR / K. Therefore, the capacitor voltage V _C1 (t ₁ ) at time t ₁ in FIG. A is expressed by Expression (1).
V _C1 (t ₁ ) = V _DD · exp (−T _P / (CR / K)) (1)

In the state of FIG. 20 (b), the independent of the value of the control code _{D CNT} (i.e. K), the capacitor _{C 1} is discharged by the parallel connection circuit 721b of all N resistors R. The resistance of the parallel connection circuit 721b is R / N, and the time constant is CR / N.

The time τ required for the voltage V _C1 to drop to the threshold voltage V _TH with the voltage V _C1 (t ₁ ) of the formula (1) as an initial value is expressed by the formula (2).
τ = CR / N ln (V _C1 (t ₁ ) / V _TH ) (2)

Substituting equation (1) into equation (2) yields equation (3).
_{τ = C R / N ln (} V DD · exp (-T P / (C R / K)) / V TH)
= CR / N {ln (V _DD / V _TH ) -T _P / (CR / K))}
_{= C R / N ln (V} DD / V TH) -T P K / N (3)

Therefore, the delay time T _DELAY from time t ₀ to time t ₃ is expressed by equation (4).
_{T DELAY} = T _P + τ
_{= C R / N ln (V} DD / V TH) + T P (N-K) / N (4)

The first term on the right side of equation (4) is a constant (offset delay) that does not depend on the control code. Therefore, according to phase interpolator 700 according to the embodiment, phase φ _OUT of output signal S _OUT can be controlled using reference time T _P / N as time resolution (unit delay width).

When the capacitor is discharged (or charged) with a constant current source, the capacitor voltage changes linearly. On the other hand, when the capacitor is discharged (or charged) with a resistor, the capacitor voltage changes nonlinearly according to an exponential function determined by the CR time constant. Therefore, intuitively, using a resistor seems to degrade accuracy compared to using a constant current source. However, equation (4) mathematically shows that the delay time can be accurately controlled in increments of unit delay width T _P / N, and there is no demerit of using a resistor. The merit of using the resistor will be described later.

This in order to generate a phase accurate phase delayed by interpolator 700, (N-K) = 1 the delay time _{T DELAY} of time is found to be greater than the reference time _{T P.} Then, the reference time T _P can be used in the following ranges.
T _P <CR In (V _DD / V _TH ) / (N−1)

When the initialized capacitor C ₁ is discharged by all N circuit units 720, the capacitor voltage V _C1 crosses the threshold voltage V _TH after the reference time _TP has elapsed from the start of discharge. Further, the impedance R and the capacitor C may be determined. In other words, R and C may be determined so that the following relational expression holds.
T _P = CR / N ln (V _DD / V _TH ) (5)

Substituting equation (5) into equation (4) yields equation (6).
_{T DELAY = T P + T P} / N × (N-K) ... (6)
Get. That is, when K = N, the phase of the output signal S _OUT can be matched with the phase of the second signal S ₂ .

FIG. 21 is a diagram for explaining the dependency of the control code on the operation of the phase interpolator 700. Here, for easy understanding, the voltage change of the capacitor voltage V _C1 is represented by a straight line. Further, it is assumed that the circuit is designed so as to satisfy Expression (5). FIG. 21 shows waveforms of control codes sel [3: 0] = [1111] to [0000]. It should be noted that the control code is a thermometer code, and only the number of 1 is significant, and the bit order has no essential meaning. As is apparent from FIG. 21, the phase φ _OUT of the output signal S _OUT can be controlled according to the control code sel [3: 0].

  The above is the operation of the phase interpolator 700A. Next, advantages of the phase interpolator 700A will be described. The advantages of the phase interpolator 700 become clear by contrast with several comparison techniques.

(First comparative technique)
FIG. 22 is a simplified circuit diagram of the phase interpolator 700R according to the first comparison technique. Note that the comparison technique must not be recognized as a known technique. Circuit unit 720R phase interpolator 700R, instead of the resistor _{R g} of the circuit unit 720, the current source CS is provided. In this phase interpolator 700R, the voltage ΔV across the current source CS must be maintained higher than the saturation voltage V _SAT . As a result, the power supply voltage V _DD cannot be reduced, and the power consumption increases.

On the other hand, in the phase interpolator 700 according to the embodiment, since the current source CS does not exist, the power supply voltage V _DD can be lowered and the power consumption can be reduced. For example, in the process generation of 0.18 μm to 28 nm, the threshold value of the MOS transistor is Vth = 0.25 to 0.7V, and the overdriver voltage is about Vod = 0.15 to 0.2V. Therefore, the phase interpolator 700 according to the embodiment can operate at V _DD = 1 V or less, and the manufactured sample can also operate at 0.6 V or less.

  Further, when the current source CS is used as in the comparative technique, a bias circuit 750 for biasing the current source CS is required, which is advantageous in terms of circuit area. Further, since it is not necessary to consider the influence of noise of the bias voltage, the layout becomes easy.

  Further, in the comparative technique, the phase interpolator 700R can be operated only after the bias circuit 750 is activated after the IC is powered on.

  On the other hand, the phase interpolator 700 according to the embodiment can be operated immediately after the IC is powered on.

(Second comparative technique)
FIG. 23 is a simplified circuit diagram of a phase interpolator 700S according to the second comparison technique. The circuit unit 720S of the phase interpolator 700S has a configuration in which the current source CS is omitted from the phase interpolator 700R of FIG. In this comparative technique, the impedance R of the first path 724 is defined by the sum of the on-resistances of the first switch SW _A1 and the switch SW _A2 , and the impedance R of the second path 726 is the first switch SW _B1 and the switch SW _B2. It is defined by the sum of the on-resistances.

In order to reduce the power consumption of the phase interpolator 700S, it is desirable to increase the impedance R and reduce the discharge current. However, in the phase interpolator 700S, in order to increase the on-resistance of the switches SW _A1 and SW _A2 (SW _B1 and SW _B2 ), the gate length L of the MOS transistor must be increased. As the gate length L increases, the gate capacity of the MOS transistor increases, so that the slew rate of the gate voltage decreases and the switching loss increases. Also, the gate drive current required to turn on or turn off the switch increases. For this reason, the phase interpolator 700S in FIG.

  On the other hand, it is possible to adjust the charge / discharge current based on the channel width W of the MOS transistor. However, reducing the channel width W in order to reduce the current causes an increase in dispersion and a decrease in performance. Will do. In addition, the minimum width of the channel width W has a process manufacturing limit. Therefore, it is difficult to achieve both low power consumption and high performance with the design method of charge / discharge current using only the parameter W / L of the MOSFET.

Phase interpolator 700 contrast (700A or rear out of 700B,, 700C) according to, by increasing the resistance value of the resistor _{R g,} a gate length L of the _{SW A1 ~SW A3, SW B1 ~SW} B3 Since it is not necessary to lengthen the switching loss, the switching loss can be reduced, the gate driving current can be reduced, and the channel width W does not need to be reduced, so that an increase in variation and a accompanying performance deterioration can be suppressed.

(Second embodiment)
FIG. 24 is a circuit diagram of a phase interpolator 700B according to the second embodiment. In this embodiment, the third switches SW _A3 and SW _B3 on the intermediate line 706 side are omitted from the circuit unit 720 of FIG. Other configurations are the same as those of the phase interpolator 700A. Also according to the second embodiment, the output signal S _OUT having a phase corresponding to the control code can be generated. Further, it has the same advantages as described in connection with the first embodiment.

(Third embodiment)
FIG. 25 is a circuit diagram of a phase interpolator 700C according to the third embodiment. In this embodiment, the circuit unit 720 of FIG. 2, the resistance _{R g} side of the second switch _SW A2, _{SW B2} is omitted. Other configurations are the same as those of the phase interpolator 700A. Also according to the third embodiment, the output signal S _OUT having a phase corresponding to the control code can be generated. Further, it has the same advantages as described in connection with the first embodiment.

(Comparison evaluation)
Subsequently, the characteristics of the phase interpolators 700A, 700B, and 700C according to the first to third embodiments are compared.

FIGS. 26A to 26C are operation waveform diagrams of the phase interpolators 700A to 700C according to the first to third embodiments. FIGS. 26A to 26C show simulation results, where V _DD = 1.5 V and N = 16. 26A to 26C, the behavior of the capacitor voltage V _{C1 at} the timing when the first signal S ₁ and the second signal S ₂ transition is different.

  FIGS. 27A and 27B are diagrams illustrating the relationship between the input code and the delay amount of each of the phase interpolators 700A to 700C according to the first to third embodiments. FIG. 27B shows the relative delay time offset so that the delay amount becomes zero when the input code is zero.

  FIG. 28A is a diagram showing the respective DNLs of the phase interpolators 700A to 700C according to the first to third embodiments, and FIG. 28B is a phase interpolator according to the first to third embodiments. It is a figure which shows each INL of 700A-700C.

The simulation result will be described.
First Embodiment In more detail, referring to FIG. 26 (a) related to the first embodiment 700A, it operates with a waveform that is closest to the ideal as shown in FIG. Focusing on the first path 724 side, by the switch _SW A2, _{SW A3} is provided on both sides of the first switch _{SW A1,} due to the clock feed-through and charge injection in the first switch _{SW A1} is suppressed .

That is, since it is possible to turn off the upper and lower switch _SW A2, _{SW A3} of the first switch _{SW A1} of the first signal _{S 1} is input, the clock feedthrough of the first switch _{SW A1,} unnecessary due to charge injection into the intermediate line 706 Alternatively, undesirable charge is suppressed, and unnecessary voltage fluctuation is suppressed.

Further, since the upper and lower switches SW _A2 and SW _A3 can be turned off, unnecessary or undesired charges on the node between SW _A1 and SW _A2 and the node between SW _A1 and SW _A3 are suppressed. Unnecessary effects on the voltage V _C1 have been eliminated. The same applies to the second path 726 side.

  In the first embodiment, as described above, the effects of charge injection and clock feedthrough on both the upper side and the lower side are suppressed. Therefore, as shown in FIGS. 28A and 28B, both INL and DNL It shows very good characteristics close to zero.

Second Embodiment Referring to FIG. 26 (b) related to the second embodiment 700B, since there is no upper switch SW _A3 , the clock feedthrough and charge injection of the first switch SW _A1 are used to connect the intermediate line 706. Unnecessary charge is generated, and the capacitor voltage V _C1 fluctuates (Operation 1).

Further, since there is no upper switch SW _A3 , when the first switch SW _A1 is turned on, an unnecessary or undesirable charge is generated for the node between the SW _A1 and the SW _A2, and an unnecessary discharge is generated from the charge of the intermediate line 706. (Action 2).

  Referring to FIG. 28 (a), the initial DNL code has a large deviation and gradually decreases, approaching the ideal, but does not eventually intersect the ideal, with the middle code (6 to 7) as the boundary. , DNL increases. This is because action 1 and action 2 cancel each other out, but action 1 has a slightly larger effect, and the delay becomes slightly larger, resulting in an increase in DNL. Since DNL is larger than ideal, INL shows a monotonous increase as shown in FIG.

-3rd Example In FIG.26 (c) related to 3rd Example 700C, since upper switch SW _A3 exists, the clock feedthrough and charge injection from 1st switch SW _A1 to the intermediate | middle line 706 are suppressed. ing.

On the other hand, since there is no lower switch SW _A2 , when the first switch SW _A1 is turned on, an extra charge is generated at the node between SW _A1 and SW _A3 . This charge, decreases the voltage of the upper node of the resistors R _g is, the gate-source voltage V _gs of the first switch SW _A1 is increased, the ON resistance is reduced, the discharge of the intermediate line 706 will prematurely.

  Referring to FIG. 28A, in the third embodiment, the DNL deviation increases toward the minus side. This is because, unlike the second embodiment, the influence of discharge is large. Therefore, as shown in FIG. 28 (b), INL also greatly decreases.

  From these comparison results, excellent characteristics are shown in the order of the first, second, and third embodiments. Therefore, when the number of circuit elements may be large, the first embodiment may be adopted. On the other hand, when the characteristics can be compromised, the circuit area can be reduced by adopting the second embodiment. Although there is no reason to actively adopt the third embodiment, the third embodiment is sufficiently useful depending on the required performance.

(Second Embodiment)
FIG. 29 is a circuit diagram of a phase interpolator 700C according to the second embodiment. The phase interpolator 700C is different from the phase interpolator 700 (FIG. 1) according to the first embodiment in the arrangement of the resistors _Rg . That is, in the first embodiment, while the resistance R _g is provided on the second line 704 side of the first path 724, the phase interpolator 700C according to the second embodiment, the resistor R _g is provided closer to the intermediate line 706 than the first path 724. Also by this phase interpolator 700C, the same effect as in the first embodiment can be obtained.

(Fourth embodiment)
Next, a specific configuration example of the phase interpolator 700C according to the second embodiment will be described. FIG. 30 is a circuit diagram of a phase interpolator 700D according to the fourth embodiment. In the phase interpolator 700D, the configurations of the first path 724 and the second path 726 are the same as those in FIG. Thereby, the influence of clock feedthrough and charge injection can be suppressed, and DNL (differential nonlinearity error) and INL (integral nonlinearity error) can be reduced.

(5th Example)
FIG. 31 is a circuit diagram of a phase interpolator 700E according to the fifth embodiment. In the phase interpolator 700E, the switch SW _A2 on the second line 704 side is omitted from the first path 724, and the switch SW _B2 on the second line 704 side is also omitted from the second path 726.

In the fifth embodiment, between the first switch _{SW A1} and the resistor _{R g} is provided a third switch _{SW A3,} between the first switch _{SW B1} and the resistor _{R g,} the third switch _{SW B3} is provided . Therefore, the influence of clock feedthrough and charge injection on the resistance side can be suppressed by the third switches SW _A3 and SW _B3 .

On the other hand, when the second line 704 is a ground line (or power supply line), the impedance thereof is sufficiently low, so that charge injection and clock feedthrough to the source side of the first switch SW _A1 and the first switch SW _B1 occur. However, the fluctuation of the potential of the second line 704 can be ignored. Therefore, even if the second switch SW _A2 and the second switch SW _B2 are omitted, DNL and INL that are comparable to the fourth embodiment can be realized. In the fifth embodiment, since the number of transistors can be reduced, the circuit area can be reduced.

(Third embodiment)
FIG. 32 is a circuit diagram of a phase interpolator 700F according to the third embodiment. In the first and second embodiments, attention is paid to the phase of the positive edge of the first signal S ₁ and the second signal S ₂ , but in the third embodiment, a negative edge (falling edge, trailing edge) is used. Acts as a trigger. The phase interpolator 700F has a configuration in which the phase interpolator 700 of FIG.

(Sixth embodiment)
FIG. 33 is a circuit diagram of a phase interpolator 700G according to the sixth embodiment. In the circuit unit 720, each of the first path 724 and the second path 726 includes three switches SW _{A1 to} SW _A3 and SW _{B1 to} SW _B3 , as in the first embodiment. Each switch is a PMOS transistor.

The initialization circuit 710 includes an initialization transistor _MN1 that is an NMOS transistor, and a logic gate 712. In this embodiment, logic gate 712 is an AND (logical product) gate.

FIG. 34 is an operation waveform diagram of the phase interpolator 700G of FIG. As described with reference to FIGS. 32 to 34, the phase interpolator 700 using a negative edge as a trigger can also be configured. Also, the switches SW _A3 and SW _B3 may be omitted from the phase interpolator 700G of FIG. Alternatively, the switches SW _A2 and SW _B2 may be omitted from the phase interpolator 700G of FIG.

  The phase interpolator has been described based on the embodiment. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  Also regarding the second embodiment (FIGS. 29 to 31), a configuration in which the P channel and the N channel are switched by upside down is also effective as one aspect of the present invention.

The resistor _Rg may be inserted both above and below the first path 724, and the second path 726 may be connected in parallel with the first path 724.

When the control code D _CNT is given as an M-bit binary code, the control code D _CNT may be expanded into a plurality of bits sel [0] to sel [N−1]. For this purpose, a decoder for converting binary code into thermometer code may be used, but the following processing may be simply performed. For example, when M = 3, N = 2 ^M = 8 gradation control is possible. In this case, the binary MSB (Most Significant Bit) is sel [0] to sel [3], the second bit of the binary is sel [4] to sel [5], and the binary LSB (Least Significant Bit) May be sel [6].

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Timing generator, 110 ... Stage, 112 ... Main interpolator, 114 ... Sub interpolator, PI ... Phase interpolator, 200 ... Delay pulse generator, 210 ... Set signal generator, 220 ... Reset signal generator, 230 DESCRIPTION OF SYMBOLS ... Output circuit 300 ... Switching power supply 310 ... Peripheral circuit 400 ... Controller 410 ... A / D converter 420 ... Digital controller 430 ... Digital pulse width modulator 440 ... Driver 500 ... Motor drive system 502 ... Three-phase motor, 510 ... Three-phase inverter, 520 ... Rotational speed detector, 600 ... Motor controller, 610 ... Digital controller, 620 ... Digital pulse modulator, 630 ... Gate driver, 800 ... Audio circuit, 802 ... Electroacoustic transducer 804 ... filter, 820 ... audio IC, DESCRIPTION OF SYMBOLS 22 ... Digital pulse width modulator, 824 ... Gate driver, 826 ... Class D amplifier, 900 ... Light emitting device, 902 ... LED, 906 ... DC / DC converter, 910 ... Dimming circuit, 912 ... Bypass switch, 914 ... Digital pulse Width modulator, 920 ... LED driver controller, 922 ... A / D converter, 924 ... controller, 926 ... digital pulse width modulator, 928 ... driver, S ₁ ... first signal, S ₂ ... second signal, output signal S _OUT , 700 ... phase interpolator, IN 1 ... first input node, IN 2 ... second input node, OUT ... output node, 702 ... first line, 704 ... second line, 706 ... intermediate line, C ₁ ... capacitor, 710 ... Initialization circuit, 712 ... Logic gate, 720 ... Circuit unit, 721 ... Parallel connection circuit, 722 ... In Converter, 724 ... first path, 726 ... second path, 730 ... output circuit, 740 ... input buffer, R g _{... resistors, SW} A1, SW _{B1 ...} first _{switch, SW} A2, SW _B2: second switch, SW _A3 , SW _B3 ... Third switch.

Claims (12)

N stages (N ≧ 2), each stage including a first phase interpolator and a second phase interpolator;
The output node of the first phase interpolator of the i th (1 ≦ i ≦ N−1) stage is the first input of each of the first phase interpolator and the second phase interpolator of the (i + 1) th stage. Connected to the node,
An output node of the second phase interpolator of the i th stage is connected to a second input node of each of the first phase interpolator and the second phase interpolator of the (i + 1) th stage,
Each of the first phase interpolator and the second phase interpolator receives a first signal at the first input node and a second signal at the second input node, and outputs an edge at a timing according to control data. A timing generator configured to generate a signal.   The timing generator of claim 1, wherein one of the first phase interpolator and the second phase interpolator is omitted in the Nth stage.   In an i-th (1 ≦ i ≦ N−1) stage, edges of output signals of the first phase interpolator and the second phase interpolator have a time difference corresponding to the time resolution of the stage. The timing generator according to claim 1 or 2.   In the first stage, a common first reference signal is input to the first input node of the first phase interpolator and the second phase interpolator, and the first phase interpolator and the second phase interpolator are input. 4. The timing generator according to claim 1, wherein a common second reference signal is input to the second input node of the counter. 5.   4. The common signal is input to the second input node of the first phase interpolator and the first input node of the second phase interpolator in the first stage. 5. The timing generator described in 1. Each of the first phase interpolator and the second phase interpolator is
A capacitor;
(I) charging or discharging the capacitor with a current amount according to the control data according to the first signal; (ii) charging or discharging the capacitor with a constant current amount according to the second signal. Charging and discharging circuit,
An output circuit for generating the output signal whose level changes when the voltage of the capacitor reaches a threshold;
The timing generator according to claim 1, comprising: A set signal generator for generating a set signal;
A reset signal generator for generating a reset signal;
With
At least one of the set signal generator and the reset signal generator includes the timing generator according to any one of claims 1 to 6,
A semiconductor integrated circuit that outputs a pulse signal that transitions to a first level according to an output signal of the set signal generator and to a second level according to an output signal of the reset signal generator.   The semiconductor integrated circuit according to claim 7, wherein the pulse signal is a pulse width modulation signal.   9. The semiconductor integrated circuit according to claim 7, which is a controller of a class D amplifier.   9. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is a controller of a DC / DC converter.   9. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is an LED driver controller.   9. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is a motor controller.