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JP2019016743A - Multilayer substrate - Google Patents

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JP2019016743A
JP2019016743A JP2017134811A JP2017134811A JP2019016743A JP 2019016743 A JP2019016743 A JP 2019016743A JP 2017134811 A JP2017134811 A JP 2017134811A JP 2017134811 A JP2017134811 A JP 2017134811A JP 2019016743 A JP2019016743 A JP 2019016743A
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insulating base
region
coil
base material
multilayer substrate
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政明 金尾
Masaaki Kanao
政明 金尾
知大 古村
Tomohiro FURUMURA
知大 古村
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to JP2017134811A priority Critical patent/JP2019016743A/en
Priority to CN201821082321.0U priority patent/CN208490035U/en
Publication of JP2019016743A publication Critical patent/JP2019016743A/en
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Abstract

To achieve a multilayer substrate having a constitution where a stepped part is formed at a boundary between a first region and a second region due to a difference in the number of lamination layers of insulating base material layers to inhibit variation in coil properties, which is caused by positional deviation of coil conductor patterns located near the stepped part.SOLUTION: A multilayer substrate 101 comprises a laminate 10 having a first region F1 and a second region F2, a stepped part SP and a coil 3 formed in the first region F1. The laminate 10 is formed by lamination of resin-based insulating base material layers in which the number of lamination layers is smaller in the second region F2 than in the first region F1. The stepped part SP is formed at a boundary between the first region F1 and the second region F2 due to a difference in the number of lamination layers of the insulating base material layers. The coil 3 is formed to include coil conductor patterns 31, 32, 33 and a first interlayer connection conductor (interlayer connection conductors V11, V12). The first interlayer connection conductor is arranged at a part ADP along and closer to the stepped part SP out of the coil conductor patterns 31, 32, 33 when viewed from a lamination direction (Z-axis direction) of the insulating base material layers.SELECTED DRAWING: Figure 1

Description

本発明は、多層基板に関し、特に樹脂を主材料とする複数の絶縁基材層を積層した積層体と、この積層体に形成されるコイルとを備える多層基板に関する。   The present invention relates to a multilayer substrate, and more particularly to a multilayer substrate including a laminate in which a plurality of insulating base layers made mainly of a resin are laminated, and a coil formed in the laminate.

従来、樹脂を主材料とする複数の絶縁基材層を積層してなる積層体と、積層体に形成されるコイルと、を備える各種多層基板が知られている。   2. Description of the Related Art Conventionally, various multilayer substrates including a laminate formed by laminating a plurality of insulating base layers mainly composed of a resin and a coil formed on the laminate are known.

例えば、特許文献1には、厚肉部(以下、第1領域)および薄肉部(以下、第2領域)を有する積層体と、第1領域に形成されるコイルと、を備えた多層基板が開示されている。上記多層基板では、コイルが、2つ以上の絶縁基材層にそれぞれ形成される複数のコイル導体パターンと、複数のコイル導体パターンを接続する層間接続導体とを含んで構成されている。上記複数のコイル導体パターンは、複数の絶縁基材層の積層方向から視て、互いに重なるように配置されている。   For example, Patent Document 1 discloses a multilayer substrate including a laminated body having a thick portion (hereinafter referred to as a first region) and a thin portion (hereinafter referred to as a second region), and a coil formed in the first region. It is disclosed. In the multilayer substrate, the coil includes a plurality of coil conductor patterns respectively formed on two or more insulating base layers and an interlayer connection conductor that connects the plurality of coil conductor patterns. The plurality of coil conductor patterns are arranged so as to overlap each other when viewed from the stacking direction of the plurality of insulating base layers.

上記多層基板では、第2領域の絶縁基材層の積層数が、第1領域の絶縁基材層の積層数よりも少ないため、第2領域が可撓性を有し、第1領域と第2領域との境界付近に積層数が異なる段差部が存在する。   In the multilayer substrate, since the number of laminated insulating base material layers in the second region is smaller than the number of laminated insulating base material layers in the first region, the second region has flexibility, and the first region and the first region There are stepped portions having different numbers of layers near the boundary between the two regions.

国際公開第2015/083525号International Publication No. 2015/083525

一般的に、特許文献1に示されるような多層基板(積層体)は、段差部の形状に応じた金型を用いて、積層した複数の絶縁基材層を加熱加圧することにより得られる。   Generally, a multilayer substrate (laminated body) as shown in Patent Document 1 is obtained by heating and pressing a plurality of laminated insulating base material layers using a mold corresponding to the shape of the stepped portion.

図6は、段差部を有する多層基板の、製造工程の一部を示す断面図である。図6に示すように、多層基板(積層体)は、積層した複数の絶縁基材層11a,12a,13a,14a,15aを、金型1a,2aを用いて積層方向(Z軸方向)に加熱加圧して得られる。金型2aの表面には、積層体の段差部SP1aの形状に応じた段差部SP2aが形成されている。しかし、金型2aの形状を積層体の段差部SP1aと完全に一致させることは困難であり、加熱加圧時の接合不良を抑制するため、金型2aの段差部SP2aの高さH2を段差部SP1aの高さH1よりも小さく形成することが一般的である。   FIG. 6 is a cross-sectional view showing a part of the manufacturing process of the multilayer substrate having a stepped portion. As shown in FIG. 6, the multilayer substrate (laminated body) includes a plurality of laminated insulating base material layers 11a, 12a, 13a, 14a, and 15a in the laminating direction (Z-axis direction) using molds 1a and 2a. Obtained by heating and pressing. On the surface of the mold 2a, a stepped portion SP2a corresponding to the shape of the stepped portion SP1a of the laminated body is formed. However, it is difficult to completely match the shape of the mold 2a with the stepped portion SP1a of the laminate, and the height H2 of the stepped portion SP2a of the mold 2a is set to be a stepped portion in order to suppress poor bonding during heating and pressing. In general, it is formed smaller than the height H1 of the portion SP1a.

しかし、上述した製造方法では、次のような理由によって、コイルの特性にばらつきが生じる虞がある。   However, in the manufacturing method described above, the characteristics of the coil may vary due to the following reasons.

(a)絶縁基材層の積層数が多い第1領域には、絶縁基材層の積層数が少ない第2領域よりも、加熱加圧時に高い圧力が加わる。そのため、加熱加圧時に、樹脂を主材料とする絶縁基材層が、第1領域から第2領域に向かって流動する。このとき、段差部SP1a近傍における絶縁基材層の流動は特に大きく(図6における矢印を参照)、絶縁基材層の流動に伴って段差部SP1a近傍に位置するコイル導体パターンの位置ずれが生じやすい。 (A) A higher pressure is applied to the first region where the number of insulating base material layers is greater than that of the second region where the number of insulating base material layers is smaller during heating and pressurization. Therefore, at the time of heating and pressurizing, the insulating base material layer containing resin as a main material flows from the first region toward the second region. At this time, the flow of the insulating base material layer in the vicinity of the stepped portion SP1a is particularly large (see the arrow in FIG. 6), and the displacement of the coil conductor pattern located in the vicinity of the stepped portion SP1a occurs with the flow of the insulating base material layer. Cheap.

(b)複数の絶縁基材層の積層方向に、複数のコイル導体パターンが重なるように配置される部分には、加熱加圧時に圧力が集中して加わるため、コイル導体パターンの位置ずれが大きくなりやすい。 (B) Since the pressure is concentrated and applied to the portion where the plurality of coil conductor patterns are overlapped in the stacking direction of the plurality of insulating base layers, the positional deviation of the coil conductor pattern is large. Prone.

(c)また、段差部SP1a近傍は、金型2aに接触する面積が大きいため(例えば、図6における絶縁基材層13a,14a,15aの右端面、および絶縁基材層15aの下面)、加熱加圧時にプレス機による熱の影響を受けやすい。そのため、加熱加圧時に段差部SP1a近傍の絶縁基材層は流動しやすく、段差部SP1a近傍に位置するコイル導体パターンの位置ずれが生じやすい。 (C) Further, the vicinity of the stepped portion SP1a has a large area in contact with the mold 2a (for example, the right end surface of the insulating base layers 13a, 14a, and 15a in FIG. 6 and the bottom surface of the insulating base layer 15a). It is easily affected by heat from the press during heating and pressurization. Therefore, the insulating base material layer in the vicinity of the stepped portion SP1a tends to flow during heating and pressurization, and the coil conductor pattern located in the vicinity of the stepped portion SP1a is likely to be displaced.

本発明の目的は、絶縁基材層の積層数の相違により第1領域と第2領域との境界に段差部が形成される構成において、段差部近傍に位置するコイル導体パターンの位置ずれに伴うコイル特性の変動を抑制した多層基板を提供することにある。   An object of the present invention is due to a displacement of a coil conductor pattern located in the vicinity of a stepped portion in a configuration in which a stepped portion is formed at the boundary between the first region and the second region due to a difference in the number of laminated insulating base layers. An object of the present invention is to provide a multilayer substrate in which fluctuations in coil characteristics are suppressed.

(1)本発明の多層基板は、
樹脂を主材料とする複数の絶縁基材層が積層されて形成され、第1領域、および前記第1領域よりも前記絶縁基材層の積層数が少ない第2領域を有する積層体と、
前記複数の絶縁基材層の積層数の相違により前記第1領域と前記第2領域との境界に形成される段差部と、
前記第1領域に形成されるコイルと、
を備え、
前記コイルは、前記複数の絶縁基材層のうち2以上の絶縁基材層に形成される複数のコイル導体パターンと、前記絶縁基材層に形成され、前記複数のコイル導体パターン同士を接続する第1層間接続導体と、を含んで構成され、
前記複数のコイル導体パターンは、前記複数の絶縁基材層の積層方向から視て、少なくとも一部が互いに重なるように配置され、
前記第1層間接続導体は、前記積層方向から視て、前記複数のコイル導体パターンのうち、前記段差部に沿って近接する部分に配置されることを特徴とする。
(1) The multilayer substrate of the present invention is
A laminate having a plurality of insulating base material layers made of resin as a main material, and having a second region in which the number of the insulating base material layers is less than the first region, and the first region;
A step portion formed at a boundary between the first region and the second region due to a difference in the number of stacked layers of the plurality of insulating base layers;
A coil formed in the first region;
With
The coil is formed on the insulating base layer and a plurality of coil conductor patterns formed on two or more insulating base layers among the plurality of insulating base layers, and connects the plurality of coil conductor patterns to each other. A first interlayer connection conductor, and
The plurality of coil conductor patterns are arranged so that at least some of them overlap each other when viewed from the stacking direction of the plurality of insulating base material layers,
The first interlayer connection conductor is disposed in a portion of the plurality of coil conductor patterns that are close to each other along the step portion when viewed from the stacking direction.

一般に、段差部近傍は、加熱加圧時に高い圧力が加わり、プレス機による熱の影響を受けやすいため、加熱加圧時における絶縁基材層の流動は大きい。一方、上記構成では、コイル導体パターンのうち段差部に沿って近接する部分に、加熱加圧時にコイル導体パターンよりも位置ずれを生じ難い第1層間接続導体が配置されるため、加熱加圧時における段差部近傍の絶縁基材層の流動が、第1層間接続導体によって抑制される。したがって、この構成により、加熱加圧時に、段差部近傍に位置するコイル導体パターンの位置ずれや変形等を抑制でき、コイル導体パターンの位置ずれや変形等に伴うコイルの特性変化を抑制できる。   Generally, in the vicinity of the stepped portion, a high pressure is applied at the time of heating and pressurization, and it is easily affected by heat from the press, so that the flow of the insulating base material layer at the time of heating and pressurization is large. On the other hand, in the above configuration, the first interlayer connection conductor that is less likely to be displaced than the coil conductor pattern at the time of heating and pressurization is disposed in a portion adjacent to the stepped portion of the coil conductor pattern. The flow of the insulating base material layer in the vicinity of the step portion is suppressed by the first interlayer connection conductor. Therefore, with this configuration, it is possible to suppress misalignment or deformation of the coil conductor pattern located in the vicinity of the step portion during heating and pressurization, and it is possible to suppress changes in the coil characteristics due to misalignment or deformation of the coil conductor pattern.

(2)上記(1)において、前記絶縁基材層に形成されるダミー導体パターンを備え、前記ダミー導体パターンは、前記積層方向から視て、前記段差部に近接する位置に配置されることが好ましい。この構成では、段差部とコイルとの間に存在するダミー導体パターンにより、加熱加圧時における段差部近傍の絶縁基材層の流動がさらに抑制される。 (2) In the above (1), a dummy conductor pattern formed on the insulating base layer is provided, and the dummy conductor pattern is disposed at a position close to the stepped portion when viewed from the stacking direction. preferable. In this configuration, the dummy conductor pattern existing between the step portion and the coil further suppresses the flow of the insulating base material layer near the step portion during heating and pressurization.

(3)上記(2)において、前記ダミー導体パターンは、前記積層方向から視て、前記段差部に沿って配置されることが好ましい。この構成により、加熱加圧時における段差部近傍の絶縁基材層の流動が、より効果的に抑制される。 (3) In said (2), it is preferable that the said dummy conductor pattern is arrange | positioned along the said level | step-difference part seeing from the said lamination direction. With this configuration, the flow of the insulating base material layer in the vicinity of the step portion during heating and pressurization is more effectively suppressed.

(4)上記(2)または(3)において、前記ダミー導体パターンは、前記積層方向から視て、前記段差部を跨るように配置されることが好ましい。この構成により、ダミー導体パターンが段差部に跨るように配置されていない場合に比べ、加熱加圧時における段差部近傍の絶縁基材層の流動はさらに抑制される。また、この構成により、積層体を形成した後の、段差部近傍の機械的強度を高めることできる。さらに、この構成により、段差部近傍の第2領域を容易に塑性変形(曲げ加工)可能な多層基板を実現できる。 (4) In said (2) or (3), it is preferable that the said dummy conductor pattern is arrange | positioned so that it may straddle the said level | step-difference part seeing from the said lamination direction. With this configuration, the flow of the insulating base material layer in the vicinity of the step portion during heating and pressurization is further suppressed as compared with the case where the dummy conductor pattern is not disposed so as to straddle the step portion. Further, with this configuration, it is possible to increase the mechanical strength in the vicinity of the stepped portion after the stacked body is formed. Furthermore, with this configuration, it is possible to realize a multilayer substrate that can easily plastically deform (bend) the second region in the vicinity of the stepped portion.

(5)上記(2)から(4)のいずれかにおいて、前記ダミー導体パターンは、前記複数の絶縁基材層のうち2以上の絶縁基材層に形成される複数のダミー導体パターンであり、前記第1領域に形成され、前記複数のダミー導体パターン同士を接続する第2層間接続導体を備え、前記第2層間接続導体は、前記積層方向から視て、前記段差部に近接する位置に配置されることが好ましい。この構成では、コイルと段差部との間に、加熱加圧時にコイル導体パターンよりも位置ずれを生じ難い第2層間接続導体が配置される。そのため、第2層間接続導体によって、加熱加圧時における段差部近傍の絶縁基材層の流動がさらに抑制される。 (5) In any one of the above (2) to (4), the dummy conductor pattern is a plurality of dummy conductor patterns formed on two or more insulating base layers among the plurality of insulating base layers. A second interlayer connection conductor formed in the first region and connecting the plurality of dummy conductor patterns is provided, and the second interlayer connection conductor is disposed at a position close to the step portion when viewed from the stacking direction. It is preferred that In this configuration, the second interlayer connection conductor that is less likely to be displaced than the coil conductor pattern during heating and pressurization is disposed between the coil and the stepped portion. Therefore, the flow of the insulating base material layer in the vicinity of the step portion during heating and pressurization is further suppressed by the second interlayer connection conductor.

(6)上記(1)から(5)のいずれかにおいて、前記複数の絶縁基材層は、熱可塑性樹脂からなることが好ましい。この構成によれば、積層した複数の絶縁基材層を一括プレスすることにより、積層体を容易に形成できるため、多層基板の製造工程が削減され、コストを低く抑えることができる。 (6) In any one of the above (1) to (5), the plurality of insulating base layers are preferably made of a thermoplastic resin. According to this configuration, a laminated body can be easily formed by collectively pressing a plurality of laminated insulating base layers, so that the manufacturing process of the multilayer substrate can be reduced and the cost can be kept low.

本発明によれば、絶縁基材層の積層数の相違により第1領域と第2領域との境界に段差部が形成される構成において、段差部近傍に位置するコイル導体パターンの位置ずれに伴うコイル特性の変動を抑制した多層基板を実現できる。   According to the present invention, in the configuration in which the stepped portion is formed at the boundary between the first region and the second region due to the difference in the number of laminated insulating base material layers, the coil conductor pattern located near the stepped portion is displaced. A multilayer substrate that suppresses fluctuations in coil characteristics can be realized.

図1(A)は第1の実施形態に係る多層基板101の断面図であり、図1(B)は多層基板101の平面図である。FIG. 1A is a cross-sectional view of the multilayer substrate 101 according to the first embodiment, and FIG. 1B is a plan view of the multilayer substrate 101. 図2は、多層基板101の分解平面図である。FIG. 2 is an exploded plan view of the multilayer substrate 101. 図3は、多層基板101を備える通信モジュール201の回路図である。FIG. 3 is a circuit diagram of the communication module 201 including the multilayer substrate 101. 図4(A)は第2の実施形態に係る多層基板102の断面図であり、図4(B)は多層基板102の平面図である。4A is a cross-sectional view of the multilayer substrate 102 according to the second embodiment, and FIG. 4B is a plan view of the multilayer substrate 102. 図5は、多層基板102の分解平面図である。FIG. 5 is an exploded plan view of the multilayer substrate 102. 図6は、段差部を有する多層基板の、製造工程の一部を示す断面図である。FIG. 6 is a cross-sectional view showing a part of the manufacturing process of the multilayer substrate having a stepped portion.

以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明または理解の容易性を考慮して、便宜上実施形態を分けて示すが、異なる実施形態で示した構成の部分的な置換または組み合わせが可能である。第2の実施形態以降では第1の実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。   Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In each figure, the same reference numerals are assigned to the same portions. In consideration of ease of explanation or understanding of the main points, the embodiments are shown separately for convenience, but the components shown in different embodiments can be partially replaced or combined. In the second and subsequent embodiments, description of matters common to the first embodiment is omitted, and only different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.

《第1の実施形態》
図1(A)は第1の実施形態に係る多層基板101の断面図であり、図1(B)は多層基板101の平面図である。図2は、多層基板101の分解平面図である。なお、図2では、構造を分かりやすくするため、コイル導体パターン31,32,33をドットパターンで示している。また、図1において、各部の厚みは誇張して図示している。このことは以降に示す各断面図でも同様である。
<< First Embodiment >>
FIG. 1A is a cross-sectional view of the multilayer substrate 101 according to the first embodiment, and FIG. 1B is a plan view of the multilayer substrate 101. FIG. 2 is an exploded plan view of the multilayer substrate 101. In FIG. 2, the coil conductor patterns 31, 32, and 33 are shown as dot patterns for easy understanding of the structure. In FIG. 1, the thickness of each part is exaggerated. The same applies to the cross-sectional views shown below.

多層基板101は、積層体10、段差部SP、コイル3、外部接続電極P1,P2等を備える。   The multilayer substrate 101 includes a laminated body 10, a stepped portion SP, a coil 3, external connection electrodes P1, P2, and the like.

積層体10は、第1領域F1および第2領域F2を有しており、コイル3は第1領域F1に形成されている。また、積層体10は、第1主面VS1と、第1主面VS1に対向する第2主面VS2A,VS2Bと、を有する。第2主面VS2Aは第1領域F1に位置する面であり、第2主面VS2Bは第2領域F2に位置する面である。外部接続電極P1は、第2領域F2の第2主面VS2Bに形成されており、外部接続電極P2は、第1領域F1の第2主面VS2Aに形成されている。   The laminate 10 has a first region F1 and a second region F2, and the coil 3 is formed in the first region F1. The stacked body 10 includes a first main surface VS1 and second main surfaces VS2A and VS2B facing the first main surface VS1. The second main surface VS2A is a surface located in the first region F1, and the second main surface VS2B is a surface located in the second region F2. The external connection electrode P1 is formed on the second main surface VS2B of the second region F2, and the external connection electrode P2 is formed on the second main surface VS2A of the first region F1.

積層体10は、長手方向がX軸方向に一致する矩形の絶縁体平板である。積層体10は、樹脂(熱可塑性樹脂)を主材料とする複数の絶縁基材層14,13,12,11をこの順に積層して形成される。積層体10の第1領域F1は、絶縁基材層14,13,12,11の順に積層して形成される。第2領域F2は、絶縁基材層12,11の順に積層して形成される。図2等に示すように、絶縁基材層11,12は、第1領域F1と第2領域F2とに亘って形成される絶縁基材層である。絶縁基材層11,12,13,14は、例えばポリイミド(PI)や液晶ポリマー(LCP)等を主材料とする樹脂シートである。   The laminated body 10 is a rectangular insulating flat plate whose longitudinal direction coincides with the X-axis direction. The laminate 10 is formed by laminating a plurality of insulating base material layers 14, 13, 12, and 11 mainly made of a resin (thermoplastic resin) in this order. The first region F1 of the stacked body 10 is formed by stacking the insulating base material layers 14, 13, 12, and 11 in this order. The second region F2 is formed by laminating the insulating base material layers 12 and 11 in this order. As shown in FIG. 2 etc., the insulating base material layers 11 and 12 are insulating base material layers formed over the first region F1 and the second region F2. The insulating base layers 11, 12, 13, and 14 are resin sheets mainly composed of, for example, polyimide (PI), liquid crystal polymer (LCP), or the like.

第2領域F2の絶縁基材層の積層数(2層)は、第1領域F1の絶縁基材層の積層数(4層)よりも少ない。そのため、積層体10の第2領域F2は、第1領域F1よりも曲がり易く、可撓性を有する。第1領域F1は、第2領域F2よりも硬く、第2領域F2よりも曲がり難い。また、複数の絶縁基材層の積層数の相違により、第1領域F1と第2領域F2との境界に段差部SPが形成される。本実施形態に係る段差部SPはYZ平面に平行である。   The number of laminated insulating base material layers in the second region F2 (two layers) is smaller than the number of laminated insulating base material layers in the first region F1 (four layers). Therefore, the second region F2 of the stacked body 10 is easier to bend than the first region F1, and has flexibility. The first region F1 is harder than the second region F2, and is less likely to bend than the second region F2. In addition, a stepped portion SP is formed at the boundary between the first region F1 and the second region F2 due to the difference in the number of stacked insulating base material layers. The step part SP according to the present embodiment is parallel to the YZ plane.

絶縁基材層11,12,13,14は、それぞれ長手方向がX軸方向に一致する矩形の平板である。絶縁基材層11,12のX軸方向の長さは、絶縁基材層13,14のX軸方向の長さよりも長い。絶縁基材層11,12の平面形状は略同じであり、絶縁基材層13,14の平面形状は略同じである。   The insulating base layers 11, 12, 13, and 14 are rectangular flat plates whose longitudinal directions coincide with the X-axis direction. The length of the insulating base material layers 11 and 12 in the X-axis direction is longer than the length of the insulating base material layers 13 and 14 in the X-axis direction. The planar shapes of the insulating base layers 11 and 12 are substantially the same, and the planar shapes of the insulating base layers 13 and 14 are substantially the same.

絶縁基材層11の裏面には、コイル導体パターン31および導体21が形成されている。コイル導体パターン31は、絶縁基材層11の中央より第1辺(図2における絶縁基材層11の左辺)寄りの位置に配置される1ターン弱の矩形ループ状の導体パターンである。導体21は、概略的にX軸方向に延伸するクランク状の導体パターンである。コイル導体パターン31および導体21は、例えばCu箔等の導体パターンである。   A coil conductor pattern 31 and a conductor 21 are formed on the back surface of the insulating base material layer 11. The coil conductor pattern 31 is a rectangular loop-shaped conductor pattern of less than one turn disposed at a position closer to the first side (left side of the insulating base layer 11 in FIG. 2) than the center of the insulating base layer 11. The conductor 21 is a crank-shaped conductor pattern that extends substantially in the X-axis direction. The coil conductor pattern 31 and the conductor 21 are conductor patterns such as a Cu foil, for example.

絶縁基材層12の裏面には、コイル導体パターン32および外部接続電極P1が形成されている。コイル導体パターン32は、絶縁基材層12の中央より第1辺(図2における絶縁基材層12の左辺)寄りの位置に配置される1ターン弱の矩形ループ状の導体パターンである。外部接続電極P1は、絶縁基材層12の第2辺(図2における絶縁基材層12の右辺)中央付近に配置される矩形の導体パターンである。コイル導体パターン32および外部接続電極P1は、例えばCu箔等の導体パターンである。   A coil conductor pattern 32 and an external connection electrode P1 are formed on the back surface of the insulating base layer 12. The coil conductor pattern 32 is a rectangular loop-shaped conductor pattern of less than one turn disposed at a position closer to the first side (the left side of the insulating base layer 12 in FIG. 2) than the center of the insulating base layer 12. The external connection electrode P1 is a rectangular conductor pattern arranged near the center of the second side of the insulating base layer 12 (the right side of the insulating base layer 12 in FIG. 2). The coil conductor pattern 32 and the external connection electrode P1 are conductor patterns such as a Cu foil, for example.

また、絶縁基材層12には、層間接続導体V1,V11が形成されている。本実施形態に係る層間接続導体V11が、本発明における「第1層間接続導体」に相当する。   In addition, interlayer connection conductors V <b> 1 and V <b> 11 are formed on the insulating base material layer 12. The interlayer connection conductor V11 according to the present embodiment corresponds to the “first interlayer connection conductor” in the present invention.

絶縁基材層13の裏面には、コイル導体パターン33が形成されている。コイル導体パターン33は、絶縁基材層13の外形に沿って巻回される1ターン弱の矩形ループ状の導体パターンである。コイル導体パターン33は、例えばCu箔等の導体パターンである。   A coil conductor pattern 33 is formed on the back surface of the insulating base layer 13. The coil conductor pattern 33 is a rectangular loop-shaped conductor pattern of less than one turn that is wound along the outer shape of the insulating base layer 13. The coil conductor pattern 33 is a conductor pattern such as a Cu foil, for example.

また、絶縁基材層13には、層間接続導体V12が形成されている。本実施形態に係る層間接続導体V12が、本発明における「第1層間接続導体」に相当する。   Further, an interlayer connection conductor V12 is formed on the insulating base material layer 13. The interlayer connection conductor V12 according to the present embodiment corresponds to the “first interlayer connection conductor” in the present invention.

絶縁基材層14の裏面には、外部接続電極P2が形成されている。外部接続電極P2は、絶縁基材層14の中央より第3辺(図2における絶縁基材層14の下辺)寄りの位置に配置される矩形の導体パターンである。外部接続電極P2は、例えばCu箔等の導体パターンである。   An external connection electrode P <b> 2 is formed on the back surface of the insulating base material layer 14. The external connection electrode P2 is a rectangular conductor pattern disposed at a position closer to the third side (lower side of the insulating base layer 14 in FIG. 2) than the center of the insulating base layer 14. The external connection electrode P2 is a conductor pattern such as a Cu foil, for example.

また、絶縁基材層14には、層間接続導体V2が形成されている。   In addition, an interlayer connection conductor V <b> 2 is formed on the insulating base material layer 14.

外部接続電極P1は、層間接続導体V1を介して導体21の第1端に接続される。導体21の第2端は、コイル導体パターン31の第1端に接続される。コイル導体パターン31の第2端は、層間接続導体V11を介してコイル導体パターン32の第1端に接続される。コイル導体パターン32の第2端は、層間接続導体V12を介してコイル導体パターン33の第1端に接続される。コイル導体パターン33の第2端は、層間接続導体V2を介して外部接続電極P2に接続される。   The external connection electrode P1 is connected to the first end of the conductor 21 via the interlayer connection conductor V1. The second end of the conductor 21 is connected to the first end of the coil conductor pattern 31. The second end of the coil conductor pattern 31 is connected to the first end of the coil conductor pattern 32 via the interlayer connection conductor V11. The second end of the coil conductor pattern 32 is connected to the first end of the coil conductor pattern 33 via the interlayer connection conductor V12. The second end of the coil conductor pattern 33 is connected to the external connection electrode P2 via the interlayer connection conductor V2.

このように、コイル導体パターン31,32,33および層間接続導体V11,V12によって、Z軸方向に巻回軸AXを有する3ターン弱の矩形ヘリカル状のコイル3が構成される。   In this way, the coil conductor patterns 31, 32, 33 and the interlayer connection conductors V11, V12 constitute a rectangular helical coil 3 of less than 3 turns having the winding axis AX in the Z-axis direction.

図1(A)および図1(B)等に示すように、コイル導体パターン31,32,33は、複数の絶縁基材層の積層方向(Z軸方向)から視て、互いに略重なるように配置されている。また、図1(A)および図1(B)等に示すように、層間接続導体V11,V12(第1層間接続導体)は、Z軸方向から視て、コイル導体パターン31,32,33のうち、段差部SPに沿って近接する部分ADP(図2におけるコイル導体パターン31,32,33のうち、Y軸方向に延伸する右辺部分)に配置される。   As shown in FIGS. 1A and 1B, the coil conductor patterns 31, 32, and 33 are substantially overlapped with each other when viewed from the stacking direction (Z-axis direction) of the plurality of insulating base layers. Has been placed. Further, as shown in FIGS. 1A and 1B, the interlayer connection conductors V11 and V12 (first interlayer connection conductor) have coil conductor patterns 31, 32, and 33 as viewed from the Z-axis direction. Among these, it is arranged in a portion ADP (the right side portion extending in the Y-axis direction among the coil conductor patterns 31, 32, and 33 in FIG. 2) that is close along the stepped portion SP.

ここで、本発明における「段差部に沿って近接する部分」とは、コイル導体パターン31,32,33のうち、段差部SPに沿って延伸する部分で、且つ、他の部分よりも段差部SPに近接して配置されている部分を言う。また、本発明における「段差部に沿った部分」とは、例えば、コイル導体パターンのうち、コイル導体パターンの延伸方向と段差部SPとのなす角度が−30°から+30°の範囲内である部分を言う。   Here, the “part close to the step part” in the present invention is a part extending along the step part SP of the coil conductor patterns 31, 32, 33, and the step part more than the other parts. The part arrange | positioned close to SP is said. In addition, the “part along the stepped portion” in the present invention means, for example, that the angle formed between the extending direction of the coil conductor pattern and the stepped portion SP in the coil conductor pattern is within a range of −30 ° to + 30 °. Say the part.

本実施形態に係る多層基板101によれば、次のような効果を奏する。   The multilayer substrate 101 according to this embodiment has the following effects.

(a)一般に、段差部SP近傍は、加熱加圧時に高い圧力が加わり、プレス機による熱の影響を受けやすいため、加熱加圧時における絶縁基材層の流動は大きい。一方、本実施形態では、段差部SPに沿って近接する部分ADPに、加熱加圧時にコイル導体パターンよりも位置ずれを生じ難い層間接続導体(第1層間接続導体)が配置されるため、加熱加圧時における段差部SP近傍の絶縁基材層の流動が、第1層間接続導体によって抑制される。したがって、この構成により、加熱加圧時に、段差部SP近傍に位置するコイル導体パターンの位置ずれや変形等を抑制でき、コイル導体パターンの位置ずれや変形等に伴うコイルの特性変化を抑制できる。 (A) Generally, in the vicinity of the stepped portion SP, a high pressure is applied at the time of heating and pressurization, and it is easily affected by heat from the press machine, so that the flow of the insulating base layer at the time of heating and pressurization is large. On the other hand, in the present embodiment, an interlayer connection conductor (first interlayer connection conductor) that is less likely to be displaced than the coil conductor pattern at the time of heating and pressurization is disposed in the portion ADP adjacent along the stepped portion SP. The flow of the insulating base material layer in the vicinity of the stepped portion SP at the time of pressurization is suppressed by the first interlayer connection conductor. Therefore, with this configuration, it is possible to suppress the displacement and deformation of the coil conductor pattern located in the vicinity of the stepped portion SP at the time of heating and pressurization, and it is possible to suppress changes in the coil characteristics caused by the displacement and deformation of the coil conductor pattern.

なお、本実施形態では、複数の絶縁基材層11,12,13,14が熱可塑性樹脂からなる。そのため、接合層(例えば、半硬化状態のプリプレグ樹脂シート)を用いて積層体を形成する場合に比べ、加熱加圧時における絶縁基材層の流動が大きくなりやすく、コイル導体パターンの位置ずれや変形等に伴うコイルの特性変化が生じやすい。したがって、上記構成は、接合層を用いずに積層体を形成する場合に特に有効である。   In the present embodiment, the plurality of insulating base material layers 11, 12, 13, and 14 are made of a thermoplastic resin. Therefore, compared to the case where a laminate is formed using a bonding layer (for example, a semi-cured prepreg resin sheet), the flow of the insulating base material layer during heating and pressurization is likely to increase, Coil characteristic changes easily occur due to deformation and the like. Therefore, the above configuration is particularly effective when a laminated body is formed without using a bonding layer.

なお、本実施形態で示したように、第1層間接続導体の数は複数であることが好ましい。複数の第1層間接続導体を、段差部SPに沿って近接する部分ADPに配置することにより、加熱加圧時における段差部SP近傍の絶縁基材層の流動を効果的に抑制できる。   As shown in the present embodiment, the number of first interlayer connection conductors is preferably plural. By disposing the plurality of first interlayer connection conductors in the portion ADP adjacent along the stepped portion SP, the flow of the insulating base layer near the stepped portion SP at the time of heating and pressing can be effectively suppressed.

(b)本実施形態では、複数の絶縁基材層11,12,13,14が熱可塑性樹脂からなる。この構成によれば、後に詳述するように、積層した複数の絶縁基材層11,12,13,14を一括プレスすることにより、積層体10を容易に形成できるため、多層基板101の製造工程が削減され、コストを低く抑えることができる。 (B) In this embodiment, the plurality of insulating base material layers 11, 12, 13, and 14 are made of a thermoplastic resin. According to this configuration, as will be described in detail later, the laminated body 10 can be easily formed by collectively pressing the plurality of laminated insulating base material layers 11, 12, 13, and 14. The number of processes is reduced, and the cost can be kept low.

本実施形態に係る多層基板101は、例えば次に示す製造方法によって製造される。   The multilayer substrate 101 according to the present embodiment is manufactured by, for example, the following manufacturing method.

(1)まず、複数の絶縁基材層11,12,13,14を準備する。その後、複数の絶縁基材層11,12,13,14に、コイル導体パターン31,32,33、導体21および外部接続電極P1,P2を形成する。具体的には、集合基板状態の絶縁基材層11,12,13,14の片側主面(裏面)に金属箔(例えばCu箔)をラミネートし、その金属箔をフォトリソグラフィでパターンニングする。これにより、絶縁基材層11の裏面にコイル導体パターン31および導体21を形成し、絶縁基材層12の裏面にコイル導体パターン32および外部接続電極P1を形成し、絶縁基材層13の裏面にコイル導体パターン33を形成し、絶縁基材層14の裏面に外部接続電極P2を形成する。 (1) First, a plurality of insulating base material layers 11, 12, 13, and 14 are prepared. Thereafter, the coil conductor patterns 31, 32, 33, the conductor 21 and the external connection electrodes P1, P2 are formed on the plurality of insulating base material layers 11, 12, 13, 14. Specifically, a metal foil (for example, Cu foil) is laminated on one main surface (back surface) of the insulating base material layers 11, 12, 13, and 14 in the aggregate substrate state, and the metal foil is patterned by photolithography. Thereby, the coil conductor pattern 31 and the conductor 21 are formed on the back surface of the insulating base material layer 11, the coil conductor pattern 32 and the external connection electrode P1 are formed on the back surface of the insulating base material layer 12, and the back surface of the insulating base material layer 13 is formed. The coil conductor pattern 33 is formed on the insulating substrate layer 14, and the external connection electrode P 2 is formed on the back surface of the insulating base layer 14.

絶縁基材層11,12,13,14は例えばポリイミド(PI)や液晶ポリマー(LCP)等を主材料とする樹脂(熱可塑性樹脂)シートである。   The insulating base layers 11, 12, 13, and 14 are resin (thermoplastic resin) sheets whose main material is, for example, polyimide (PI), liquid crystal polymer (LCP), or the like.

また、複数の絶縁基材層12,13,14には、層間接続導体V1,V2,V11,V12が形成される。層間接続導体V1,V2,V11,V12は、絶縁基材層12,13,14にレーザー等で貫通孔を設けた後、Cu,Sn等のうち1以上もしくはそれらの合金を含む導電性ペーストを配設し、後の加熱加圧で硬化させることによって設けられる。そのため、層間接続導体V1,V2,V11,V12は、後の加熱加圧の温度よりも融点(溶融温度)が低い材料とする。   In addition, interlayer connection conductors V1, V2, V11, and V12 are formed on the plurality of insulating base material layers 12, 13, and 14, respectively. The interlayer connection conductors V1, V2, V11, and V12 are made of conductive paste containing one or more of Cu, Sn, or the like, or an alloy thereof after providing through holes in the insulating base layers 12, 13, and 14 with a laser or the like. It is provided by disposing and curing by subsequent heating and pressing. Therefore, the interlayer connection conductors V1, V2, V11, and V12 are made of materials having a melting point (melting temperature) lower than the temperature of subsequent heating and pressurization.

(2)次に、上部金型および下部金型(図5における金型1a,2aを参照)を用いて、積層方向(Z軸方向)に向かって、積層した複数の絶縁基材層11,12,13,14を加熱加圧する。具体的には、下部金型の上に、複数の絶縁基材層14,13,12,11の順に積層した後、上部金型および下部金型を用いて、積層した複数の絶縁基材層11,12,13,14を加熱加圧して積層体を形成する。 (2) Next, using the upper mold and the lower mold (see molds 1a and 2a in FIG. 5), a plurality of insulating base material layers 11 stacked in the stacking direction (Z-axis direction), 12, 13, and 14 are heated and pressurized. Specifically, a plurality of insulating base material layers 14, 13, 12, 11 are stacked in this order on the lower mold, and then the plurality of insulating base material layers stacked using the upper mold and the lower mold. 11, 12, 13, and 14 are heated and pressed to form a laminate.

(3)その後、上部金型および下部金型から集合基板状態の積層体を取り外し、集合基板状態の積層体を分断することで、個別の多層基板101を得る。 (3) Thereafter, the multilayer substrate 101 is removed from the upper mold and the lower mold, and the multilayer substrate 101 is separated by dividing the multilayer substrate in the aggregate substrate state.

この製造方法によれば、積層した複数の絶縁基材層11,12,13,14を一括プレスすることにより、積層体10を容易に形成できる。そのため、多層基板101の製造工程が削減され、コストを低く抑えることができる。   According to this manufacturing method, the laminated body 10 can be easily formed by collectively pressing the plurality of laminated insulating base material layers 11, 12, 13, and 14. Therefore, the manufacturing process of the multilayer substrate 101 is reduced, and the cost can be kept low.

本実施形態に係る多層基板101は、例えば次のように用いられる。図3は、多層基板101を備える通信モジュール201の回路図である。図3において、多層基板101が備えるコイル3をコイルアンテナANTで表している。   The multilayer substrate 101 according to the present embodiment is used as follows, for example. FIG. 3 is a circuit diagram of the communication module 201 including the multilayer substrate 101. In FIG. 3, the coil 3 included in the multilayer substrate 101 is represented by a coil antenna ANT.

通信モジュール201は、コイルアンテナANT(多層基板101)、キャパシタC1およびIC4を備える。図3に示すように、IC4にコイルアンテナANTが接続され、コイルアンテナANTにキャパシタC1が並列接続されている。IC4、キャパシタC1および多層基板101は、図示しない回路基板に実装され、回路基板に形成される導体パターンにより電気的に接続される。多層基板101は、外部接続電極(図1(A)における外部接続電極P1,P2)を、はんだ等の導電性接合材を介して回路基板に接合することによって、回路基板に接続される。   The communication module 201 includes a coil antenna ANT (multilayer substrate 101), a capacitor C1, and an IC4. As shown in FIG. 3, a coil antenna ANT is connected to the IC 4 and a capacitor C1 is connected in parallel to the coil antenna ANT. IC4, capacitor C1, and multilayer substrate 101 are mounted on a circuit board (not shown) and are electrically connected by a conductor pattern formed on the circuit board. The multilayer substrate 101 is connected to the circuit board by bonding external connection electrodes (external connection electrodes P1 and P2 in FIG. 1A) to the circuit board via a conductive bonding material such as solder.

図3に示すコイルアンテナANTとキャパシタC1とIC4自信が持つ容量成分とで、LC共振回路が構成される。IC4は、例えばパッケージングされたRFICチップ(ベアチップ)である。キャパシタC1は、例えばチップ型キャパシタ等である。   The LC resonance circuit is configured by the coil antenna ANT, the capacitor C1, and the capacitance component possessed by the IC4 itself shown in FIG. The IC 4 is, for example, a packaged RFIC chip (bare chip). The capacitor C1 is, for example, a chip capacitor.

なお、図3では、キャパシタC1が、回路基板に実装されるチップ型キャパシタである例を示したが、これに限定されるものではない。キャパシタC1は、例えば多層基板101に実装されていてもよい。また、キャパシタC1はチップ部品に限定されるものではない。キャパシタC1は、例えば、複数の絶縁基材層に形成される、互いに対向する導体パターン間に形成される層間容量であってもよい。   Although FIG. 3 shows an example in which the capacitor C1 is a chip capacitor mounted on a circuit board, the present invention is not limited to this. The capacitor C1 may be mounted on the multilayer substrate 101, for example. The capacitor C1 is not limited to a chip component. The capacitor C1 may be, for example, an interlayer capacitance formed between conductive patterns facing each other formed on a plurality of insulating base material layers.

《第2の実施形態》
第2の実施形態では、ダミー導体パターンを備える多層基板の例を示す。
<< Second Embodiment >>
In the second embodiment, an example of a multilayer substrate having a dummy conductor pattern is shown.

図4(A)は第2の実施形態に係る多層基板102の断面図であり、図4(B)は多層基板102の平面図である。図5は、多層基板102の分解平面図である。なお、図5では、構造を分かりやすくするため、コイル導体パターン31,32,33をドットパターンで示している。   4A is a cross-sectional view of the multilayer substrate 102 according to the second embodiment, and FIG. 4B is a plan view of the multilayer substrate 102. FIG. 5 is an exploded plan view of the multilayer substrate 102. In FIG. 5, the coil conductor patterns 31, 32, and 33 are shown as dot patterns for easy understanding of the structure.

多層基板102は、ダミー導体パターン41,42および層間接続導体V21,V22を備える点で、第1の実施形態に係る多層基板101と異なる。多層基板102の他の構成については、多層基板101と実質的に同じである。   The multilayer substrate 102 is different from the multilayer substrate 101 according to the first embodiment in that the multilayer substrate 102 includes dummy conductor patterns 41 and 42 and interlayer connection conductors V21 and V22. Other configurations of the multilayer substrate 102 are substantially the same as those of the multilayer substrate 101.

以下、第1の実施形態に係る多層基板101と異なる部分について説明する。   Hereinafter, parts different from the multilayer substrate 101 according to the first embodiment will be described.

ダミー導体パターン41は、絶縁基材層12の中央付近に配置される矩形の導体パターンである。ダミー導体パターン42は、絶縁基材層13の第2辺(図4における絶縁基材層13の右辺)付近に配置される矩形の導体パターンである。   The dummy conductor pattern 41 is a rectangular conductor pattern disposed near the center of the insulating base material layer 12. The dummy conductor pattern 42 is a rectangular conductor pattern disposed near the second side of the insulating base layer 13 (the right side of the insulating base layer 13 in FIG. 4).

また、層間接続導体V21,V22は、絶縁基材層13に形成されている。また、図4(A)および図4(B)に示すように、層間接続導体V21,V22は、積層体10の第1領域F1に形成されている。ダミー導体パターン41,42は、層間接続導体V21,V22を介して接続されている。   The interlayer connection conductors V21 and V22 are formed on the insulating base material layer 13. Further, as shown in FIGS. 4A and 4B, the interlayer connection conductors V21 and V22 are formed in the first region F1 of the multilayer body 10. The dummy conductor patterns 41 and 42 are connected via interlayer connection conductors V21 and V22.

本実施形態に係る層間接続導体V21,V22が、本発明における「第2層間接続導体」に相当する。   The interlayer connection conductors V21 and V22 according to the present embodiment correspond to the “second interlayer connection conductor” in the present invention.

本実施形態では、図4(A)および図4(B)等に示すように、ダミー導体パターン41,42が、Z軸方向から視て、段差部SPに沿って近接する位置に配置されている。本実施形態では、ダミー導体パターン41が、Z軸方向から視て、段差部SPに跨るように配置されている。図4(B)に示すように、ダミー導体パターン41,42は、コイル3の巻回軸AX方向(Z軸方向)から視て、コイル開口OPに重なっていない。   In the present embodiment, as shown in FIGS. 4A and 4B, the dummy conductor patterns 41 and 42 are arranged at positions close to each other along the stepped portion SP as viewed from the Z-axis direction. Yes. In the present embodiment, the dummy conductor pattern 41 is disposed so as to straddle the stepped portion SP as viewed from the Z-axis direction. As shown in FIG. 4B, the dummy conductor patterns 41 and 42 do not overlap the coil opening OP when viewed from the winding axis AX direction (Z-axis direction) of the coil 3.

ここで、「ダミー導体パターンが段差部に近接する位置に配置される」とは、ダミー導体パターンの少なくとも一部が、部分ADPと段差部SPとの間に配置されることを言う。また、「ダミー導体パターンが段差部に沿って配置される」とは、ダミー導体パターンの外縁のうち、段差部SPに沿った部分が段差部SPの全長の1/2以上となるように、ダミー導体パターンが配置されることを言う。   Here, “the dummy conductor pattern is disposed at a position close to the step portion” means that at least a part of the dummy conductor pattern is disposed between the portion ADP and the step portion SP. Further, “the dummy conductor pattern is arranged along the stepped portion” means that the portion along the stepped portion SP of the outer edge of the dummy conductor pattern is ½ or more of the entire length of the stepped portion SP. A dummy conductor pattern is arranged.

また、本実施形態では、層間接続導体V21,V22(第2層間接続導体)が、Z軸方向から視て、段差部SPに近接する位置に配置されている。   In the present embodiment, the interlayer connection conductors V21 and V22 (second interlayer connection conductors) are disposed at positions close to the stepped portion SP when viewed from the Z-axis direction.

ここで、「第2層間接続導体が段差部に近接する位置に配置される」とは、第2層間接続導体が、部分ADPと段差部SPとの間に配置されることを言う。   Here, “the second interlayer connection conductor is disposed at a position close to the step portion” means that the second interlayer connection conductor is disposed between the portion ADP and the step portion SP.

本実施形態に係る多層基板102によれば、第1の実施形態で述べた効果以外に、次のような効果を奏する。   The multilayer substrate 102 according to the present embodiment has the following effects in addition to the effects described in the first embodiment.

(c)本実施形態では、ダミー導体パターン41,42が、Z軸方向から視て、段差部SPに近接して配置されている。この構成では、段差部SPとコイル3との間に存在するダミー導体パターン41,42によって、加熱加圧時における段差部SP近傍の絶縁基材層の流動がさらに抑制される。そのため、この構成により、加熱加圧時に、段差部SP近傍に位置するコイル導体パターンの位置ずれや変形等はさらに抑制され、コイル導体パターン位置ずれや変形等に伴うコイルの特性変化がさらに抑制される。 (C) In the present embodiment, the dummy conductor patterns 41 and 42 are disposed close to the stepped portion SP when viewed from the Z-axis direction. In this configuration, the dummy conductor patterns 41 and 42 existing between the stepped portion SP and the coil 3 further suppress the flow of the insulating base material layer near the stepped portion SP during heating and pressurization. Therefore, this configuration further suppresses displacement and deformation of the coil conductor pattern located in the vicinity of the stepped portion SP during heating and pressurization, and further suppresses changes in coil characteristics due to displacement and deformation of the coil conductor pattern. The

(d)また、本実施形態で示したように、ダミー導体パターン41,42は、Z軸方向から視て、段差部SPに沿って近接する位置に配置されることが好ましい。この構成により、加熱加圧時における段差部SP近傍の絶縁基材層の流動が、より効果的に抑制される。 (D) Further, as shown in the present embodiment, the dummy conductor patterns 41 and 42 are preferably arranged at positions close to each other along the stepped portion SP as viewed from the Z-axis direction. With this configuration, the flow of the insulating base material layer in the vicinity of the stepped portion SP during heating and pressurization is more effectively suppressed.

(e)本実施形態では、層間接続導体V21,V22(第2層間接続導体)が、Z軸方向から視て、段差部SPに沿って近接する位置に配置されている。この構成では、コイル3と段差部SPとの間に、加熱加圧時にコイル導体パターンよりも位置ずれを生じ難い層間接続導体(第2層間接続導体)が配置される。そのため、層間接続導体V21,V22によって、加熱加圧時における段差部SP近傍の絶縁基材層の流動がさらに抑制される。 (E) In the present embodiment, the interlayer connection conductors V21 and V22 (second interlayer connection conductors) are arranged at positions close to each other along the stepped portion SP when viewed from the Z-axis direction. In this configuration, an interlayer connection conductor (second interlayer connection conductor) that is less likely to be displaced than the coil conductor pattern during heating and pressurization is disposed between the coil 3 and the stepped portion SP. Therefore, the interlayer connection conductors V21 and V22 further suppress the flow of the insulating base layer in the vicinity of the stepped portion SP at the time of heating and pressing.

なお、第2層間接続導体の数は複数であることが好ましい。複数の第2層間接続導体を、段差部SPに沿って近接する位置に配置することにより、加熱加圧時における段差部SP近傍の絶縁基材層の流動を効果的に抑制できる。   The number of second interlayer connection conductors is preferably plural. By disposing the plurality of second interlayer connection conductors at positions close to each other along the stepped portion SP, the flow of the insulating base material layer near the stepped portion SP at the time of heating and pressing can be effectively suppressed.

(f)また、本実施形態では、ダミー導体パターン41が、Z軸方向から視て、段差部SPに跨るように配置されている。この構成により、ダミー導体パターンが段差部SPに跨るように配置されていない場合に比べ、加熱加圧時における段差部SP近傍の絶縁基材層の流動(例えば、加熱加圧時に、第1領域F1から第2領域F2に向かって移動する絶縁基材層の流動)がさらに抑制される。また、この構成により、積層体10を形成した後の、段差部SP近傍の機械的強度を高めることできる。さらに、この構成により、段差部SP近傍の第2領域F2を容易に塑性変形(曲げ加工)可能な多層基板を実現できる。 (F) Moreover, in this embodiment, the dummy conductor pattern 41 is arrange | positioned so that it may straddle the level | step-difference part SP seeing from a Z-axis direction. With this configuration, compared to the case where the dummy conductor pattern is not arranged so as to straddle the stepped portion SP, the flow of the insulating base layer near the stepped portion SP at the time of heating and pressing (for example, the first region at the time of heating and pressing). The flow of the insulating base material layer moving from F1 toward the second region F2 is further suppressed. Further, with this configuration, the mechanical strength in the vicinity of the stepped portion SP after the stacked body 10 is formed can be increased. Furthermore, with this configuration, it is possible to realize a multilayer substrate that can easily plastically deform (bend) the second region F2 in the vicinity of the stepped portion SP.

なお、本実施形態で示したように、ダミー導体パターン41,42は、Z軸方向から視て、コイル3のコイル開口OPに重ならないことが好ましい。この構成により、ダミー導体パターンがコイル3による磁界の形成を妨げてしまうことを抑制できる。   As shown in the present embodiment, it is preferable that the dummy conductor patterns 41 and 42 do not overlap the coil opening OP of the coil 3 when viewed from the Z-axis direction. With this configuration, it is possible to suppress the dummy conductor pattern from preventing the coil 3 from forming a magnetic field.

《その他の実施形態》
以上に示した各実施形態では、積層体10が矩形の平板である例を示したが、この構成に限定されるものではない。積層体の平面形状は、本発明の作用効果を奏する範囲において適宜変更可能であり、例えば多角形、円形、楕円形、クランク形、L字形、T字形、Y字形等であってもよい。
<< Other Embodiments >>
In each embodiment shown above, although the laminated body 10 showed the example which is a rectangular flat plate, it is not limited to this structure. The planar shape of the laminate can be appropriately changed within the range where the effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse, a crank shape, an L shape, a T shape, a Y shape, or the like.

また、以上に示した各実施形態では、4つの絶縁基材層11,12,13,14を積層して形成される積層体の例を示したが、この構成に限定されるものではない。積層体を形成する絶縁基材層の積層数は、本発明の作用効果を奏する範囲において適宜変更可能である。積層体を形成する絶縁基材層の積層数は、例えば2つまたは3つでもよく、5つ以上でもよい。さらに、第1領域F1の絶縁基材層の積層数、および第2領域F2の絶縁基材層の積層数についても、本発明の作用効果を奏する範囲において適宜変更可能である。   Moreover, in each embodiment shown above, although the example of the laminated body formed by laminating | stacking the four insulating base material layers 11, 12, 13, and 14 was shown, it is not limited to this structure. The number of laminated insulating base layers forming the laminate can be appropriately changed within the range where the effects of the present invention are exhibited. The number of insulating base material layers forming the laminate may be two or three, for example, or five or more. Furthermore, the number of insulating base material layers in the first region F1 and the number of insulating base material layers in the second region F2 can also be changed as appropriate within the scope of the effects of the present invention.

以上に示した各実施形態では、熱可塑性樹脂からなる複数の絶縁基材層を積層して加熱加圧することにより、積層体を形成する例を示したが、この構成に限定されるものではない。例えば、熱硬化性樹脂からなる複数の絶縁基材層の間に、接合層(例えば、半硬化状態のプリプレグ樹脂)を挟んで積層したものを加熱加圧することにより積層体を形成してもよい。   In each embodiment shown above, although the example which forms a laminated body by laminating | stacking and heat-pressing the several insulating base material layer which consists of thermoplastic resins was shown, it is not limited to this structure. . For example, a laminate may be formed by heating and pressing a laminate in which a bonding layer (for example, a semi-cured prepreg resin) is sandwiched between a plurality of insulating base material layers made of a thermosetting resin. .

また、以上に示した各実施形態では、Z軸方向に巻回軸AXを有する3ターン弱の矩形ヘリカル状のコイル3が構成される例を示したが、コイルの形状、ターン数等はこれに限定されるものではない。コイルの外形、構成およびターン数は、本発明の作用効果を奏する範囲において適宜変更可能である。コイルは、例えばスパイラル状の複数のコイル導体パターンを層間接続導体で接続する構成であってもよい。コイルの外形(巻回軸AX方向(Z軸方向)から視たコイルの外形)は、矩形に限定されるものではなく、例えば円形、楕円形等であってもよい。また、コイルの巻回軸AXはZ軸方向に完全に一致している必要はない。   In each of the embodiments described above, an example in which a rectangular helical coil 3 having a winding axis AX in the Z-axis direction and having a winding axis AX of less than 3 turns is shown. It is not limited to. The outer shape, configuration, and number of turns of the coil can be changed as appropriate within the scope of the effects of the present invention. For example, the coil may be configured to connect a plurality of spiral coil conductor patterns with interlayer connection conductors. The outer shape of the coil (the outer shape of the coil viewed from the winding axis AX direction (Z-axis direction)) is not limited to a rectangle, and may be, for example, a circle or an ellipse. Further, the winding axis AX of the coil does not have to be completely coincident with the Z-axis direction.

以上に示した各実施形態では、全てのコイル導体パターン31,32,33が、Z軸方向から視て、互いに略重なるように配置されている例を示したが、この構成に限定されるものではない。複数のコイル導体パターンは、Z軸方向から視て、少なくとも一部が互いに重なるように配置される構成であってもよい。   In each of the embodiments described above, an example in which all the coil conductor patterns 31, 32, and 33 are arranged so as to substantially overlap each other when viewed from the Z-axis direction has been described. However, the present invention is limited to this configuration. is not. The plurality of coil conductor patterns may be arranged so that at least a part thereof overlaps each other when viewed from the Z-axis direction.

さらに、以上に示した各実施形態では、コイルが、3つの絶縁基材層にそれぞれ形成される3つのコイル導体パターンを含んで構成される例を示したが、この構成に限定されるものではない。コイルは、2以上の絶縁基材層にそれぞれ形成される2以上のコイル導体パターンを含んで構成されていればよい。すなわち、コイルを構成するコイル導体パターンの数は、2以上であればよい。   Furthermore, in each embodiment shown above, although the coil showed the example comprised including three coil conductor patterns each formed in three insulating base material layers, it is not limited to this structure. Absent. The coil should just be comprised including the 2 or more coil conductor pattern formed in 2 or more insulation base material layers, respectively. That is, the number of coil conductor patterns constituting the coil may be two or more.

以上に示した各実施形態では、1つの第1領域F1と1つの第2領域とを有する積層体の例を示したが、この構成に限定されるものではない。第1領域F1および第2領域F2の形状、個数、位置等は、本発明の作用効果を奏する範囲において適宜変更可能である。例えば、第1領域F1の数が複数であってもよく、第2領域F2の数が複数であってもよい。すなわち、段差部SPの数が複数であってもよい。   In each of the embodiments described above, an example of a stacked body having one first region F1 and one second region has been described, but the present invention is not limited to this configuration. The shape, the number, the position, and the like of the first region F1 and the second region F2 can be appropriately changed within the range where the effects of the present invention are exhibited. For example, the number of first regions F1 may be plural, and the number of second regions F2 may be plural. That is, the number of stepped portions SP may be plural.

なお、段差部SPの数が複数である場合には、コイル導体パターンのうち、それぞれの段差部に沿って近接する部分に、第1層間接続導体が配置されることが好ましい。   In addition, when the number of the step portions SP is plural, it is preferable that the first interlayer connection conductor is disposed in a portion of the coil conductor pattern that is close along each step portion.

以上に示した各実施形態では、コイルのみ備える多層基板の例を示したが、多層基板(積層体)に形成される回路構成はこれに限定されるものではない。積層体に形成される回路は、本発明の作用効果を奏する範囲において適宜変更可能である。例えば、導体パターンで形成されたキャパシタや各種伝送線路(ストリップライン、マイクロストリップライン、ミアンダ、コプレーナ等)が、積層体に形成されていてもよい。また、例えば、チップ型インダクタやチップ型キャパシタ等のチップ部品が、積層体に実装されていてもよい。   In each embodiment shown above, the example of the multilayer board | substrate provided only with a coil was shown, However, The circuit structure formed in a multilayer board | substrate (laminated body) is not limited to this. The circuit formed in the laminate can be appropriately changed within the range where the effects of the present invention are exhibited. For example, a capacitor formed with a conductor pattern and various transmission lines (strip line, microstrip line, meander, coplanar, etc.) may be formed in the laminate. Further, for example, chip components such as a chip inductor and a chip capacitor may be mounted on the multilayer body.

また、外部接続電極の個数、配置および形状等は、第1・第2の実施形態で示した構成に限定されるものではない。外部接続電極の個数および配置は、積層体に形成される回路に応じて適宜変更かのうである。また、外部接続電極の平面形状は、矩形に限定されるものではなく、例えば正方形、多角形、円形、楕円形、T字形、L字形等であってもよい。   Further, the number, arrangement, shape, and the like of the external connection electrodes are not limited to the configurations shown in the first and second embodiments. The number and arrangement of the external connection electrodes can be changed as appropriate according to the circuit formed in the laminate. The planar shape of the external connection electrode is not limited to a rectangle, and may be, for example, a square, a polygon, a circle, an ellipse, a T shape, an L shape, or the like.

なお、第1の実施形態では、はんだ等の導電性接合材を介して、多層基板の外部接続電極を回路基板等に接続する例を示したが、この構成に限定されるものではない。多層基板は、例えばコネクタを用いて回路基板等に接続されていてもよい。   In the first embodiment, the example in which the external connection electrode of the multilayer board is connected to the circuit board or the like via a conductive bonding material such as solder has been described. However, the present invention is not limited to this configuration. The multilayer board may be connected to a circuit board or the like using a connector, for example.

最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形および変更が適宜可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲内と均等の範囲内での実施形態からの変更が含まれる。   Finally, the description of the above embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.

ANT…コイルアンテナ
C1…キャパシタ
AX…コイルの巻回軸
F1…第1領域
F2…第2領域
OP…コイル開口
P1,P2…外部接続電極
SP,SP1a,SP2a…段差部
ADP…コイル導体パターンのうち、段差部に沿って近接する部分
V1,V2…層間接続導体
V11,V12…層間接続導体(第1層間接続導体)
V21,V22…層間接続導体(第2層間接続導体)
VS1…積層体の第1主面
VS2A,VS2B…積層体の第2主面
1a,2a…金型
3…コイル
4…IC
10…積層体
11,11a,12,12a,13,13a,14,14a,15a…絶縁基材層
21…導体
31,32,33…コイル導体パターン
41,42…ダミー導体パターン
101,102…多層基板
201…通信モジュール
ANT ... coil antenna C1 ... capacitor AX ... coil winding axis F1 ... first region F2 ... second region OP ... coil openings P1, P2 ... external connection electrodes SP, SP1a, SP2a ... stepped portion ADP ... coil conductor pattern , Portions V1, V2 ... interlayer connection conductors V11, V12 ... interlayer connection conductors (first interlayer connection conductors) adjacent to each other along the stepped portion
V21, V22 ... interlayer connection conductor (second interlayer connection conductor)
VS1 ... 1st main surface VS2A of a laminated body, VS2B ... 2nd main surface 1a, 2a of a laminated body ... Mold 3 ... Coil 4 ... IC
DESCRIPTION OF SYMBOLS 10 ... Laminated body 11, 11a, 12, 12a, 13, 13a, 14, 14a, 15a ... Insulating base material layer 21 ... Conductor 31, 32, 33 ... Coil conductor pattern 41, 42 ... Dummy conductor pattern 101, 102 ... Multilayer Substrate 201 ... communication module

Claims (6)

樹脂を主材料とする複数の絶縁基材層が積層されて形成され、第1領域、および前記第1領域よりも前記絶縁基材層の積層数が少ない第2領域を有する積層体と、
前記複数の絶縁基材層の積層数の相違により前記第1領域と前記第2領域との境界に形成される段差部と、
前記第1領域に形成されるコイルと、
を備え、
前記コイルは、前記複数の絶縁基材層のうち2以上の絶縁基材層に形成される複数のコイル導体パターンと、前記絶縁基材層に形成され、前記複数のコイル導体パターン同士を接続する第1層間接続導体と、を含んで構成され、
前記複数のコイル導体パターンは、前記複数の絶縁基材層の積層方向から視て、少なくとも一部が互いに重なるように配置され、
前記第1層間接続導体は、前記積層方向から視て、前記複数のコイル導体パターンのうち、前記段差部に沿って近接する部分に配置される、多層基板。
A laminate having a plurality of insulating base material layers made of resin as a main material, and having a second region in which the number of the insulating base material layers is less than the first region, and the first region;
A step portion formed at a boundary between the first region and the second region due to a difference in the number of stacked layers of the plurality of insulating base layers;
A coil formed in the first region;
With
The coil is formed on the insulating base layer and a plurality of coil conductor patterns formed on two or more insulating base layers among the plurality of insulating base layers, and connects the plurality of coil conductor patterns to each other. A first interlayer connection conductor, and
The plurality of coil conductor patterns are arranged so that at least some of them overlap each other when viewed from the stacking direction of the plurality of insulating base material layers,
The first interlayer connection conductor is a multilayer substrate that is disposed in a portion of the plurality of coil conductor patterns that are close to each other along the step portion when viewed from the stacking direction.
前記絶縁基材層に形成されるダミー導体パターンを備え、
前記ダミー導体パターンは、前記積層方向から視て、前記段差部に近接する位置に配置される、請求項1に記載の多層基板。
Comprising a dummy conductor pattern formed on the insulating base layer;
The multilayer substrate according to claim 1, wherein the dummy conductor pattern is disposed at a position close to the step portion when viewed from the stacking direction.
前記ダミー導体パターンは、前記積層方向から視て、前記段差部に沿って配置される、請求項2に記載の多層基板。   The multilayer substrate according to claim 2, wherein the dummy conductor pattern is disposed along the step portion when viewed from the stacking direction. 前記ダミー導体パターンは、前記積層方向から視て、前記段差部を跨るように配置される、請求項2または3に記載の多層基板。   The multilayer substrate according to claim 2, wherein the dummy conductor pattern is disposed so as to straddle the stepped portion when viewed from the stacking direction. 前記ダミー導体パターンは、前記複数の絶縁基材層のうち2以上の絶縁基材層に形成される複数のダミー導体パターンであり、
前記第1領域に形成され、前記複数のダミー導体パターン同士を接続する第2層間接続導体を備え、
前記第2層間接続導体は、前記積層方向から視て、前記段差部に近接する位置に配置される、請求項2から4のいずれかに記載の多層基板。
The dummy conductor pattern is a plurality of dummy conductor patterns formed on two or more insulating base layers among the plurality of insulating base layers.
A second interlayer connection conductor formed in the first region and connecting the plurality of dummy conductor patterns;
5. The multilayer substrate according to claim 2, wherein the second interlayer connection conductor is disposed at a position close to the step portion when viewed from the stacking direction.
前記複数の絶縁基材層は、熱可塑性樹脂からなる、請求項1から5のいずれかに記載の多層基板。   The multilayer substrate according to claim 1, wherein the plurality of insulating base layers are made of a thermoplastic resin.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020093047A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093043A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093037A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093056A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093055A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093046A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093058A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093060A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093036A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
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JP2020093059A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015079773A1 (en) * 2013-11-28 2015-06-04 株式会社村田製作所 Electromagnet, camera-lens driving method, and electromagnet manufacturing method
WO2015083525A1 (en) * 2013-12-06 2015-06-11 株式会社村田製作所 Inductor element and electronic device
WO2017051649A1 (en) * 2015-09-25 2017-03-30 株式会社村田製作所 Antenna module and electronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015079773A1 (en) * 2013-11-28 2015-06-04 株式会社村田製作所 Electromagnet, camera-lens driving method, and electromagnet manufacturing method
WO2015083525A1 (en) * 2013-12-06 2015-06-11 株式会社村田製作所 Inductor element and electronic device
WO2017051649A1 (en) * 2015-09-25 2017-03-30 株式会社村田製作所 Antenna module and electronic device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2020093043A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093037A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
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JP2020093046A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093058A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
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JP2020093036A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093044A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093057A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Amusement machine
JP2020093042A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093041A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine
JP2020093059A (en) * 2018-12-12 2020-06-18 株式会社三洋物産 Game machine

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