JP2018207144A - Elastic wave device - Google Patents

Abstract

To improve the heat dissipation of heat generated in an IDT. An acoustic wave device is provided on a support substrate, a piezoelectric substrate bonded to the support substrate, the piezoelectric substrate, a plurality of electrode fingers, and the plurality of electrode fingers. An IDT 20 having a bus bar 26 connected thereto, and a first wiring layer 14 that fills an opening provided in the piezoelectric substrate 10 and has at least a part of an upper surface thereof in contact with at least a part of the bus bar 26 of the IDT. Are provided. [Selection] Figure 1

Description

  The present invention relates to an acoustic wave device, for example, an acoustic wave device provided with a wiring connected to an IDT.

  Elastic wave devices are used in filters for mobile communication. It is known that an IDT (Interdigital Transducer) is provided on a piezoelectric substrate bonded on a support substrate. It is known that wiring connected to the IDT is provided on the upper surface of the support substrate from which the piezoelectric substrate has been removed (for example, Patent Document 1).

Japanese Patent Laid-Open No. 2006-40882

  However, in patent document 1, wiring and IDT are connected on a piezoelectric substrate. With such a structure, the heat generated in the IDT is not sufficiently released.

  This invention is made | formed in view of the said subject, and aims at improving heat dissipation.

  The present invention provides a support substrate, a piezoelectric substrate bonded on the support substrate, an IDT having a plurality of electrode fingers and a bus bar connected to the plurality of electrode fingers, An acoustic wave device comprising: a first wiring layer filled in an opening provided in a piezoelectric substrate and having at least a part of an upper surface thereof in contact with at least a part of the bus bar of the IDT.

  In the above configuration, the opening may penetrate the piezoelectric substrate, and the first wiring layer may be in contact with the support substrate.

  In the above configuration, at least part of the upper surface of the first wiring layer and the upper surface of the piezoelectric substrate may be flat.

  The said structure WHEREIN: The heat conductivity of the said support substrate and the said 1st wiring layer can be set as the structure higher than the heat conductivity of the said piezoelectric substrate.

  In the above configuration, a second wiring layer provided on the first wiring layer may be provided so as to face the first wiring layer with an insulating film or a gap provided in the opening interposed therebetween. it can.

  The said structure WHEREIN: It can be set as the structure which comprises the 3rd wiring layer provided adjacent to the said 1st wiring layer on the said piezoelectric substrate.

  In the above configuration, the first wiring layer is provided between the two IDTs, contacts one bus bar of the two IDTs, and the third wiring layer is provided between the two IDTs. The other IDT may be in contact with the other bus bar and adjacent to the first wiring layer.

  In the above configuration, the annular metal layer surrounding the IDT and embedded in the periphery of the piezoelectric substrate, the substrate mounted on the piezoelectric substrate, and surrounding the substrate in a plan view, and the IDT and the lower surface of the substrate are spaced from each other And a sealing portion for sealing the IDT so as to face each other.

  The said structure WHEREIN: The said 1st wiring layer can be set as the structure provided so that the said IDT may be enclosed in planar view.

  In the above configuration, the upper surface of the support substrate may have a recess, and the first wiring layer may be in contact with the support substrate at least in the recess.

  In the above configuration, a filter including the IDT may be provided.

  In the above configuration, a plurality of series resonators each including the IDT are connected in series between an input terminal and an output terminal, and are connected in parallel between the input terminal and the output terminal. A filter including one or a plurality of parallel resonators including an IDT may be provided, and the first wiring layer may be connected between at least two of the plurality of series resonators.

  In the above configuration, a multiplexer including the filter can be provided.

  According to the present invention, heat dissipation can be improved.

FIG. 1A is a plan view of the acoustic wave resonator according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIG. 2A to FIG. 2D are cross-sectional views (part 1) illustrating the method for manufacturing the acoustic wave resonator according to the first embodiment. FIG. 3A to FIG. 3C are cross-sectional views (part 2) illustrating the method for manufacturing the acoustic wave resonator according to the first embodiment. FIG. 4A to FIG. 4D are cross-sectional views (part 1) illustrating the method for manufacturing the acoustic wave resonator according to the first modification of the first embodiment. 5A and 5B are cross-sectional views (part 2) illustrating the method for manufacturing the acoustic wave resonator according to the first modification of the first embodiment. FIG. 6A to FIG. 6J are cross-sectional views showing the wiring layers in the second and third modifications of the first embodiment. FIG. 7A is a plan view of the filter according to the second embodiment, and FIG. 7B is a cross-sectional view taken along the line AA of FIG. 7A. FIG. 8 is a cross-sectional view of the acoustic wave device according to the third embodiment. FIG. 9 is a plan view of the piezoelectric substrate in the third embodiment. FIG. 10 is a circuit diagram of a duplexer according to the fourth embodiment. FIG. 11A is a plan view of a duplexer according to the fourth embodiment, and FIG. 11B is a cross-sectional view taken along line AA of FIG. FIG. 12A is a plan view of a filter according to the fifth embodiment, and FIG. 12B is a cross-sectional view taken along line AA in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  Example 1 is an example of an acoustic wave resonator as an acoustic wave device. FIG. 1A is a plan view of the acoustic wave resonator according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. As shown in FIGS. 1A and 1B, a piezoelectric substrate 10 is bonded to a support substrate 11. The support substrate 11 is, for example, a sapphire substrate, an alumina substrate, a spinel substrate, or a silicon substrate. The piezoelectric substrate 10 is, for example, a tantalum lithium substrate or a lithium niobate substrate. The support substrate 11 and the piezoelectric substrate 10 are bonded, for example, at room temperature.

  An opening is provided in the piezoelectric substrate 10, and the wiring layer 14 is filled in the opening. The wiring layer 14 is a metal layer such as a copper layer, a gold layer, a silver layer, a tungsten layer, or a molybdenum layer. A metal film 12 is formed on the piezoelectric substrate 10 and the wiring layer 14. The metal film 12 includes, for example, a barrier film 12a and a low resistance film 12b. The barrier film 12 a is a titanium film, for example, and suppresses mutual diffusion between the low resistance film 12 b and the piezoelectric substrate 10. The low resistance film 12b has a lower resistance than the barrier film 12a, for example, an aluminum film or a copper film.

  The 1-port elastic wave resonator 25 includes an IDT 20 and a reflector 22 formed of the metal film 12. The reflectors 22 are provided on both sides of the IDT 20. The IDT 20 has a pair of comb electrodes 27. The comb-shaped electrode 27 includes a plurality of electrode fingers 24 and a bus bar 26 to which the plurality of electrode fingers 24 are connected. One electrode finger 24 and the other electrode finger 24 of the pair of comb-shaped electrodes 27 are provided substantially alternately. A part of the lower surface of the bus bar 26 is in contact with the upper surface of the wiring layer 14. Thereby, the bus bar 26 and the wiring layer 14 are electrically connected. A protective film 16 is provided so as to cover the metal film 12 and the wiring layer 14. The protective film 16 is, for example, a silicon nitride film or a silicon oxide film. The protective film 16 protects the metal film 12 and the wiring layer 14 and suppresses diffusion of metal atoms in the metal film 12 and the wiring layer 14 to the upper layer.

  The electrode fingers 24 of the IDT 20 excite surface acoustic waves on the piezoelectric substrate 10. The excited elastic wave is reflected by the reflector 22. The wavelength λ of the elastic wave substantially corresponds to the pitch of the electrode fingers 24. The propagation direction of the elastic wave is the X direction, and the extending direction of the electrode finger 24 is the Y direction. The X direction and the Y direction may not be the X axis direction and the Y axis direction of the piezoelectric substrate 10. When the piezoelectric substrate 10 is a Y-cut X-propagating lithium tantalate substrate or a Y-cut X-propagating lithium niobate substrate, the X direction is the X-axis orientation. The linear thermal expansion coefficient of the support substrate 11 is smaller than the linear thermal expansion coefficient of the piezoelectric substrate 10. Thereby, the frequency temperature coefficient can be brought close to zero. A temperature compensation film may be provided on the piezoelectric substrate 10 so as to cover the IDT 20. The temperature compensation film is, for example, a silicon oxide film or a silicon oxide film containing fluorine.

  FIG. 2A to FIG. 3C are cross-sectional views illustrating the method for manufacturing the acoustic wave resonator according to the first embodiment. As shown in FIG. 2A, the lower surface of the piezoelectric substrate 10 is bonded to the upper surface of the support substrate 11. For example, the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10 are irradiated with an ion beam of an inert gas, a neutral beam, or plasma. Thereby, an amorphous layer of several nm or less is formed on the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10. Unbonded bonds are generated on the surface of the amorphous layer. Due to the presence of unbonded bonds, the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10 are activated. Unbonded bonds on the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10 are bonded to each other. Thereby, the support substrate 11 and the piezoelectric substrate 10 are joined at normal temperature. The piezoelectric substrate 10 and the support substrate 11 may be joined by an adhesive or the like. The film thickness of the piezoelectric substrate 10 is, for example, 1 μm to 30 μm.

  As shown in FIG. 2B, an opening 30 is formed in the piezoelectric substrate 10. The opening 30 is formed using a dry etching method or a wet etching method. The width of the opening 30 is, for example, 5 μm or more.

  As shown in FIG. 2C, a seed layer 32 is formed on the inner surface of the opening 30 and the upper surface of the piezoelectric substrate 10. The seed layer 32 is, for example, a titanium film and a copper film from the support substrate 11 side. The titanium film functions as an adhesion layer that improves the adhesion between the wiring layer and the support substrate 11 and the piezoelectric substrate 10. The copper film functions as a layer for supplying an electrolytic plating current.

  As shown in FIG. 2D, by supplying a current through the seed layer 32, a copper layer is formed on the seed layer 32 as the wiring layer 14 using an electrolytic plating method. The seed layer 32 and the wiring layer 14 on the piezoelectric substrate 10 are removed by using, for example, a CMP (Chemical Mechanical Polishing) method. Thereby, the seed layer 32 and the wiring layer 14 on the piezoelectric substrate 10 are removed, and the upper surface of the piezoelectric substrate 10 and the upper surface of the wiring layer 14 are planarized. The wiring layer 14 may be formed by using an electroless plating method, a sputtering method, a vapor deposition method, or a CVD (Chemical Vapor Deposition) method. In FIG. 1B, illustration of the seed layer 32 is omitted.

  As shown in FIG. 3A, a metal film 12 having a predetermined pattern is formed on the piezoelectric substrate 10. Electrode fingers 24 and bus bars 26 are formed by the metal film 12. The width at which the bus bar 26 and the wiring layer 14 are in contact is, for example, 1 μm or more. The metal film 12 is formed using, for example, a vapor deposition method and a lift-off method, or a sputtering method and an etching method.

  As shown in FIG. 3B, a protective film 16 is formed on the piezoelectric substrate 10 so as to cover the metal film 12. The protective film 16 is formed using, for example, a CVD method or a sputtering method. The protective film 16 is patterned.

  As shown in FIG. 3C, bump pads 28 are formed on the wiring layer 14. The pad 28 is a metal layer such as a gold layer, for example. The pad 28 is formed using, for example, a plating method, a sputtering method, or a vapor deposition method.

  According to the first embodiment, the wiring layer 14 and the seed layer 32 (first wiring layer) are filled in openings provided in the piezoelectric substrate 10. At least a part of the wiring layer 14 is in contact with at least a part of the bus bar 26 of the IDT 20. As a result, as shown by an arrow 80 in FIG. 1B, the heat generated in the IDT 20 is directly conducted from the metal film 12 to the wiring layer 14 and released from the support substrate 11. Therefore, release of heat generated in the IDT 20 can be promoted.

  Further, the wiring layer 14 and the seed layer 32 may not be in contact with the upper surface of the support substrate 11, but the opening penetrates the piezoelectric substrate 10, and the wiring layer 14 and the seed layer 32 are in contact with the support substrate 11. Is preferred. Thereby, heat is directly conducted from the wiring layer 14 and the seed layer 32 to the support substrate 11. Therefore, the release of heat generated in the IDT 20 can be further promoted.

  Further, at least a part of the upper surface of the wiring layer 14 and the upper surface of the piezoelectric substrate 10 are flat. Thereby, disconnection of the metal film 12 at the boundary between the piezoelectric substrate 10 and the wiring layer 14 can be suppressed.

  The thermal conductivity of the support substrate 11 (for example, sapphire) and the wiring layer 14 (for example, copper) is higher than the thermal conductivity of the piezoelectric substrate 10 (for example, lithium tantalate). Thereby, the heat generated in the IDT 20 can be released to the support substrate 11 through the wiring layer 14 and the seed layer 32. Therefore, the release of heat generated in the IDT 20 can be further promoted.

[Modification 1 of Example 1]
FIG. 4A to FIG. 5B are cross-sectional views illustrating a method for manufacturing the acoustic wave resonator according to the first modification of the first embodiment. As shown in FIG. 4A, the piezoelectric substrate 10 is prepared. As shown in FIG. 4B, the opening 30 is formed in the piezoelectric substrate 10 by using, for example, an etching method. As shown in FIG. 4C, the seed layer 32 and the wiring layer 14 embedded in the opening 30 are formed as in FIGS. 2C and 2D. 4D, as in FIG. 2A, the lower surface of the piezoelectric substrate 10 (upper surface in FIG. 4D) is bonded to the upper surface of the support substrate 11 (lower surface in FIG. 4D). To do.

  As shown in FIG. 5A, the upper surfaces (lower surfaces in FIG. 5A) of the piezoelectric substrate 10 and the wiring layer 14 are planarized using, for example, a CMP method. As shown in FIG. 5B, the metal film 12 is formed on the upper surfaces (lower surfaces in FIG. 5B) of the piezoelectric substrate 10 and the wiring layer 14. Thereafter, a protective film or the like is formed.

  In the first modification of the first embodiment, the side surface of the wiring layer 14 is inclined so that the upper surface of the wiring layer 14 is smaller than the lower surface. Thereby, the upper surface of the piezoelectric substrate 10 can be used effectively. Therefore, the chip size can be reduced.

[Modification 2 of Embodiment 1]
FIG. 6A to FIG. 6H are cross-sectional views showing wiring layers in the second modification of the first embodiment. As shown in FIG. 6A, the side surface of the wiring layer 14 may be inclined so that the upper surface of the wiring layer 14 is larger than the lower surface. As shown in FIG. 6B, a recess may be provided on the upper surface of the wiring layer 14, and a gap 34 may be provided in the recess. As shown in FIG. 6C, the insulating film 33 may be embedded in the recess on the upper surface of the wiring layer 14. The insulating film 33 is, for example, a silicon oxide film or a silicon nitride film. As shown in FIG. 6D, when the upper surfaces of the piezoelectric substrate 10 and the wiring layer 14 are planarized using the CMP method, the upper surface of the wiring layer 14 may be a concave surface 34a by dishing.

  As shown in FIG. 6E, another wiring layer 36 may be provided on the wiring layer 14, and the wiring layers 14 and 36 may be in electrical contact. The wiring layer 36 is a metal layer such as a copper layer or a gold layer. As shown in FIG. 6 (f), a gap 35 may be provided between the wiring layer 14 and the piezoelectric substrate 10.

  As shown in FIG. 6G, even if a wiring layer 36 (second wiring layer) is provided on the wiring layer 14 so as to face the wiring layer 14 with the insulating film 33 provided in the opening interposed therebetween. Good. As shown in FIG. 6H, a wiring layer 36 may be provided on the wiring layer 14 so as to face the wiring layer 14 with a gap 34 provided in the opening interposed therebetween. The wiring layers 14 and 36 are electrically separated by the insulating film 33 or the gap 34 and constitute a cross wiring. The thickness of the insulating film 33 and the gap 34 is, for example, 1 μm.

[Modification 3 of Embodiment 1]
FIG. 6I and FIG. 6J are cross-sectional views showing wiring layers in the third modification of the first embodiment. As shown in FIG. 6I, the upper surface of the support substrate 11 has a recess 31 defined by the opening of the piezoelectric substrate 10. The seed layer 32 is in contact with the upper surface of the support substrate 11 in the recess 31. In FIG. 6 (i), the first wiring layer including the wiring layer 14 and the seed layer 32 contacts the recess 31. Thereby, the area where the seed layer 32 contacts the support substrate 11 is increased. Therefore, the adhesion strength between the seed layer 32 and the support substrate 11 is improved. In addition, heat dissipation from the wiring layer 14 to the support substrate 11 is improved. In FIG. 2B, after the opening is formed in the piezoelectric substrate 10, a dry process such as ion milling or dry etching, or mechanical processing such as blasting or processing using a dicing blade is performed. Thereby, the recessed part 31 can be formed. Other configurations are the same as those in FIG.

  As shown in FIG. 6 (j), the upper surface of the recess 31 is a curved surface protruding upward. Thereby, the contact area of the seed layer 32 and the support substrate 11 becomes large from FIG.6 (i). Therefore, adhesion strength and heat dissipation can be further improved. By performing a dry process such as ion milling or dry etching for forming the recess 31, the recess 31 tends to be a curved surface. Other configurations are the same as those in FIG.

  As shown in FIGS. 6 (i) and 6 (j), the upper surface of the support substrate 11 has a recess 31, and the wiring layer 14 and the seed layer 32 (first wiring layer) are in contact with the support substrate 11 at least in the recess 31. To do. Thereby, the adhesion strength between the first wiring layer and the seed layer 32 and the heat dissipation from the wiring layer to the support substrate 31 can be improved.

  Example 2 is an example of a filter as an elastic wave device. FIG. 7A is a plan view of the filter according to the second embodiment, and FIG. 7B is a cross-sectional view taken along the line AA of FIG. 7A. As shown in FIG. 7A, the acoustic wave resonator 25, the wiring layers 14 and 18, and the pad 28 are provided on the piezoelectric substrate 10 and the support substrate 11. The acoustic wave resonator 25 includes an IDT 20 and a reflector 22. As shown in FIG. 7B, the wiring layer 14 is embedded in the opening formed in the piezoelectric substrate 10. The wiring layer 18 is provided on the piezoelectric substrate 10. At least a part of the lower surface of one bus bar 26 is in contact with the upper surface of the wiring layer 14, and at least a part of the upper surface of the other bus bar 26 is in contact with the lower surface of the wiring layer 18. The wiring layer 18 is a metal layer such as a copper layer or a gold layer.

  As shown in FIG. 7A, the plurality of acoustic wave resonators 25 correspond to the series resonators S1 to S4 and the parallel resonators P1 to P3. The pad 28 corresponds to the input terminal Tin, the output terminal Tout, and the ground terminal Tgnd. Bumps (not shown) are formed on the pad 28. The series resonators S1 to S4 are connected in series via the wiring layer 14 and / or 18 between the input terminal Tin and the output terminal Tout. The parallel resonators P1 to P3 are connected in parallel via the wiring layers 14 and / or 18 between the input terminal Tin and the output terminal Tout.

  The wiring layers 14 and 18 are provided along the bus bar 26 in order to reduce the resistance between the electrode fingers 24. For this reason, wiring layers having different potentials are extended oppositely between adjacent parallel resonators. This causes a short circuit between the wiring layers and / or increases the parasitic capacitance between the wiring layers. In addition, it is difficult to miniaturize the wiring layer.

  Therefore, a wiring layer connected to the parallel resonator P1 between the parallel resonators P1 and P2 is a wiring layer 14, and a wiring layer connected to the parallel resonator P2 is a wiring layer 18. Among the parallel resonators P2 and P3, a wiring layer connected to the parallel resonator P2 is a wiring layer 14, and a wiring layer connected to the parallel resonator P3 is a wiring layer 18. As a result, as shown in FIG. 7B, one wiring layer 14 is embedded in the piezoelectric substrate 10, and the other wiring layer 1 is provided on the piezoelectric substrate 10. For this reason, the short circuit with the wiring layers 14 and 18 can be suppressed. Further, the parasitic capacitance between the wiring layers 14 and 18 can be suppressed. Furthermore, the wiring layer can be miniaturized.

  According to the second embodiment, the wiring layer 18 (third wiring layer) is provided adjacent to the wiring layer 14 (first wiring layer) on the piezoelectric substrate 10. Thereby, the short circuit between the wiring layers 14 and 18 can be suppressed, and the parasitic capacitance between the wiring layers 14 and 18 can be suppressed. Further, the wiring layers 14 and 18 can be miniaturized.

  As shown in FIG. 7B, the wiring layer 14 is provided between the two IDTs 20, contacts one bus bar 26 of the IDT 20, and the wiring layer 18 contacts the other bus bar 26. Thereby, a short circuit and parasitic capacitance between the wiring layers 14 and 18 respectively connected between two adjacent IDTs 20 can be suppressed.

  In the ladder type filter, since high frequency power is mainly applied to the series resonator, the series resonator becomes high temperature. Therefore, as shown in FIG. 7A, a wiring layer connected between at least two of the plurality of series resonators S1 to S4 is referred to as a wiring layer. Thereby, the heat generated in the series resonator can be efficiently released.

  The series resonator (eg, S2 and S3) sandwiched between the series resonators has a limited heat release path. Therefore, the wiring layer connected to the series resonators S2 and S3 is preferably the wiring layer 14.

  FIG. 8 is a cross-sectional view of the acoustic wave device according to the third embodiment. As shown in FIG. 8, terminals 40 are provided on the lower surface of the support substrate 11. The terminal 40 is a foot pad for connecting the acoustic wave resonator 25 to the outside. An acoustic wave resonator 25 is provided on the upper surface of the piezoelectric substrate 10. A wiring layer 14 and an annular metal layer 68 penetrating the piezoelectric substrate 10 are provided. An acoustic wave resonator 25 is electrically connected to the wiring layer 14. A pad 28 is provided on the wiring layer 14.

  The annular metal layer 68 is provided on the periphery of the piezoelectric substrate 10 so as to surround the acoustic wave resonator 25. The wiring layer 14 and the annular metal layer 68 are metal layers made of the same material. A through electrode 42 penetrating the support substrate 11 is provided. The through electrode 42 electrically connects the wiring layer 14 and the terminal 40. The through electrode 42 is a metal layer such as a copper layer or a gold layer. An annular electrode 62 is provided on the annular metal layer 68. The annular electrode 62 is a metal layer such as a nickel layer, a tungsten layer, a copper layer, an aluminum layer, or a gold layer. If the solder wettability of the upper surface of the annular metal layer 68 is good, the annular electrode 62 may not be provided.

  An elastic wave resonator 52 and a wiring layer 54 are provided on the lower surface of the substrate 50. The elastic wave resonator 52 is, for example, a piezoelectric thin film resonator. The substrate 50 is, for example, a silicon substrate, a sapphire substrate, a spinel substrate, or an alumina substrate. The wiring layer 54 is a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 50 is flip-chip mounted (face-down mounted) on the piezoelectric substrate 10 via the bumps 44. The bump 44 is, for example, a gold bump, a solder bump, or a copper bump. The bump 44 joins the pad 28 and the wiring layer 54.

  A sealing portion 60 is provided on the piezoelectric substrate 10 so as to surround the substrate 50. The sealing part 60 is a metal material such as solder. The sealing part 60 is joined to the annular electrode 62. A flat lid 64 is provided on the upper surface of the substrate 50 and the upper surface of the sealing portion 60. The lid 64 is, for example, a metal plate or an insulating plate. A protective film 66 is provided so as to cover the lid 64 and the sealing portion 60. The protective film 66 is a metal film or an insulating film.

  The acoustic wave resonators 25 and 52 are opposed to each other with a gap 65 interposed therebetween. The gap 65 is sealed by the sealing portion 60, the piezoelectric substrate 10, the substrate 50, and the lid 64. The elastic wave resonators 25 and 52 are surrounded by the gap 65 so that vibration is not restricted.

  FIG. 9 is a plan view of the piezoelectric substrate in the third embodiment. As shown in FIG. 9, an acoustic wave resonator 25 is provided on the piezoelectric substrate 10. A wiring layer 14 is provided in the piezoelectric substrate 10. An annular metal layer 68 is provided in the piezoelectric substrate 10 at the periphery of the support substrate 11. Bumps 44 are provided on the pads 28. The plurality of acoustic wave resonators 25 correspond to the series resonators S1 to S3 and the parallel resonators P1 and P2. The plurality of bumps 44 correspond to the input terminal Tin, the output terminal Tout, and the ground terminal Tgnd. Between the input terminal Tin and the output terminal Tout, series resonators S1 to S3 are connected in series, and parallel resonators P1 and P2 are connected in parallel.

  According to the third embodiment, the annular metal layer 68 surrounds the IDT 20 and is embedded in the periphery of the piezoelectric substrate 10. The substrate 50 is mounted on the piezoelectric substrate 10. The sealing unit 60 seals the IDT 20 so as to surround the substrate 50 in plan view and the IDT 20 and the lower surface of the substrate 50 face each other with the gap 65 interposed therebetween. Thereby, as shown by the arrow 82 in FIG. 8, the heat generated in the acoustic wave resonator 25 is radiated from the terminal 40 through the wiring layer 14 and the support substrate 11. Further, as indicated by an arrow 84, the heat generated in the acoustic wave resonator 25 is released through the wiring layer 14, the support substrate 11, the annular metal layer 68, the annular electrode 62, and the sealing portion 60. Therefore, the heat generated in the acoustic wave resonator 25 can be released efficiently.

  The thermal conductivity of the annular metal layer 68, the annular electrode 62, and the sealing portion 60 is preferably larger than the thermal conductivity of the piezoelectric substrate 10. Thereby, heat can be released more efficiently. Although the example in which the ladder type filter is formed on the piezoelectric substrate 10 has been described, the piezoelectric substrate 10 may be provided with a multimode filter. Although the example in which the piezoelectric thin film resonator is provided as the acoustic wave resonator 52 on the lower surface of the substrate 50 has been described, a surface acoustic wave resonator, a passive element, or an active element may be provided on the lower surface of the substrate 50. . Electronic elements may not be provided on the lower surface of the substrate 50.

  Example 4 is an example of a duplexer as an elastic wave device. FIG. 10 is a circuit diagram of a duplexer according to the fourth embodiment. As shown in FIG. 10, a transmission filter 90 is connected between the common terminal Ant and the transmission terminal Tx. A reception filter 92 is connected between the common terminal Ant and the reception terminal Rx. The transmission filter 90 passes a signal in the transmission band of the high-frequency signal input from the transmission terminal Tx as a transmission signal to the common terminal Ant, and suppresses signals of other frequencies. The reception filter 92 passes a signal in the reception band among the high frequency signals input from the common terminal Ant to the reception terminal Rx as a reception signal, and suppresses signals of other frequencies.

  FIG. 11A is a plan view of a duplexer according to the fourth embodiment, and FIG. 11B is a cross-sectional view taken along line AA of FIG. As shown in FIGS. 11A and 11B, a transmission filter 90 and a reception filter 92 are provided on the piezoelectric substrate 10. The transmission filter 90 and the reception filter 92 each include an acoustic wave resonator 25, a wiring layer 14, and a pad 28. The transmission filter 90 and the reception filter 92 are ladder type filters each having series resonators S1 to S3 and parallel resonators P1 and P2. A wiring layer 14 a embedded in the piezoelectric substrate 10 is provided between the transmission filter 90 and the reception filter 92. For example, a ground potential is supplied to the wiring layer 14a.

  According to the fourth embodiment, the isolation between the transmission filter 90 and the reception filter 92 can be improved by the wiring layer 14a. Although a duplexer transmission filter and reception filter have been described as examples of filters for improving isolation, other filters may be used. It is preferable that the filters that improve isolation do not have overlapping pass bands. Although a ladder filter has been described as an example of the transmission filter 90 and the reception filter 92, a multimode filter may be used. Although the duplexer has been described as an example, a multiplexer such as a triplexer or a quadplexer may be used.

  FIG. 12A is a plan view of a filter according to the fifth embodiment, and FIG. 12B is a cross-sectional view taken along line AA in FIG. As shown in FIGS. 12A and 12B, the acoustic wave resonator 25, the wiring layer 14, and the pad 28 are provided on the piezoelectric substrate 10. A wiring layer 14 b is embedded in the piezoelectric substrate 10 so as to surround the acoustic wave resonator 25. For example, a ground potential is supplied to the wiring layer 14b.

  According to the fifth embodiment, the wiring layer 14b is provided so as to surround the IDT 20 in a plan view. Thereby, the isolation between IDT20 can be improved.

  As in the second to fifth embodiments, when the filter includes the IDT and the wiring layer 14 in the first embodiment and the modifications thereof, the heat dissipation of the filter can be improved. The number of series resonators and parallel resonators in the ladder filter can be arbitrarily set. In the second embodiment, the ladder type filter is described as an example of the filter using the wiring layer 14, but a multimode filter may be used.

  As in the fourth embodiment, when the multiplexer includes the filters of the second, fourth, and fifth embodiments, the heat dissipation of the multiplexer can be improved.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Piezoelectric substrate 11 Support substrate 12 Metal film 14, 14a, 14b, 18, 36 Wiring layer 16 Protective film 20 IDT
DESCRIPTION OF SYMBOLS 22 Reflector 24 Electrode finger 25 Elastic wave resonator 26 Bus bar 27 Comb electrode 30 Opening 34, 35 Air gap 33 Insulating film 44 Bump 50 Substrate 52 Elastic wave resonator 60 Sealing part 65 Air gap 68 Annular metal layer

Claims (13)

A support substrate;
A piezoelectric substrate bonded on the support substrate;
An IDT provided on the piezoelectric substrate and having a plurality of electrode fingers and a bus bar to which the plurality of electrode fingers are connected;
A first wiring layer filled in an opening provided in the piezoelectric substrate, wherein at least a part of the upper surface is in contact with at least part of the bus bar of the IDT;
An elastic wave device comprising:   The acoustic wave device according to claim 1, wherein the opening penetrates the piezoelectric substrate, and the first wiring layer is in contact with the support substrate.   3. The acoustic wave device according to claim 1, wherein at least a part of the upper surface of the first wiring layer and the upper surface of the piezoelectric substrate are flat.   4. The acoustic wave device according to claim 1, wherein thermal conductivity of the support substrate and the first wiring layer is higher than thermal conductivity of the piezoelectric substrate. 5.   5. The semiconductor device according to claim 1, further comprising a second wiring layer provided on the first wiring layer so as to face the first wiring layer with an insulating film or a gap provided in the opening interposed therebetween. The acoustic wave device according to item.   6. The acoustic wave device according to claim 1, further comprising a third wiring layer provided adjacent to the first wiring layer on the piezoelectric substrate. The first wiring layer is provided between the two IDTs and contacts one bus bar of the two IDTs.
The acoustic wave device according to claim 6, wherein the third wiring layer is provided between the two IDTs, contacts the other bus bar of the two IDTs, and is adjacent to the first wiring layer. An annular metal layer surrounding the IDT and embedded in the periphery of the piezoelectric substrate;
A substrate mounted on the piezoelectric substrate;
A sealing portion that seals the IDT so as to surround the substrate in a plan view and the IDT and the lower surface of the substrate face each other with a gap therebetween;
The elastic wave device according to claim 1, further comprising:   The elastic wave device according to any one of claims 1 to 8, wherein the first wiring layer is provided so as to surround the IDT in a plan view.   The elastic wave device according to claim 2, wherein an upper surface of the support substrate has a recess, and the first wiring layer is in contact with the support substrate at least in the recess.   The acoustic wave device according to any one of claims 1 to 10, further comprising a filter including the IDT. A plurality of series resonators connected in series between the input terminal and the output terminal, each including the IDT, and connected in parallel between the input terminal and the output terminal, each including the IDT 1 Or a filter including a plurality of parallel resonators,
The acoustic wave device according to claim 6, wherein the first wiring layer is connected between at least two of the plurality of series resonators. The acoustic wave device according to claim 11, further comprising a multiplexer including the filter.

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