JP2018148676A - Switching power supply control semiconductor device - Google Patents

Abstract

A switching power supply control semiconductor device capable of notifying an external load device when a decrease in input voltage is detected is provided.
A switching power supply control semiconductor device 11 has a direct current from a voltage input terminal VH to which an input voltage is inputted from an external power supply, and an auxiliary winding of a transformer to which the voltage of the external power supply is applied to a primary main winding. When the DC power supply terminal VCC to which the voltage is input and the detection voltage of the input voltage is detected to be lower than the first threshold voltage, and the detection voltage of the DC voltage is detected to be higher than the second threshold voltage And a power good signal generator 34 for outputting a power good signal to an external device.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device for switching power supply control that notifies an abnormal state of a power supply device to the outside by a power good signal.

  The output voltage is input as a feedback voltage, and the feedback voltage is supplied to the first comparator to which the first threshold voltage is input to obtain a short protection signal, and the feedback voltage is input to the second threshold voltage. 2 Supply an overvoltage protection signal to the comparator, supply the short protection signal and overvoltage protection signal to the OR gate to generate an abnormality detection signal, and input the abnormality detection signal to the switch element to detect the abnormality. There has been proposed a power supply device that outputs a power good signal to a microcomputer or the like that becomes a high level when not detected and becomes a low level when an abnormality is detected (see Patent Document 1).

  However, in the prior art described in Patent Document 1, when the short protection signal or the overvoltage protection signal changes from low level to high level, a power good signal that changes from high level to low level is output. Can be notified to the outside, but it cannot be notified to the outside that the switching operation has stopped due to a decrease in the input voltage.

  For example, in a flyback type switching power supply, when a rectified voltage obtained by rectifying an AC power supply with a diode is input to the VH terminal at the time of startup, the rectified voltage is supplied to an external capacitor by the startup circuit, and the capacitor is charged to generate a DC voltage. Vcc is formed, and when the DC voltage Vcc becomes equal to or higher than the threshold voltage, the switching operation is started and the operation of the starting circuit is stopped. Thereafter, the DC voltage Vcc is maintained by the voltage generated in the auxiliary winding of the flyback transformer by the switching operation. In this state, when the input voltage from the AC power supply is cut off and the rectified voltage input to the VH terminal is lowered, the switching operation is stopped by the brownout circuit, and when the DC voltage Vcc is lowered thereby, the starting circuit is started. The At this time, since the rectified voltage is not input to the starting circuit, the capacitor cannot be charged, and the power supply circuit is reset when the DC voltage Vcc continues to decrease and becomes lower than the threshold voltage of the low voltage prevention function. Even if the input voltage is supplied from a DC power source such as a battery, the same operation is performed if the battery energy is exhausted and the voltage input to the VH terminal is reduced.

  In order to notify the outside whether or not this low voltage prevention function has been exhibited, the power good signal generation circuit described in Patent Document 1 described above is used. As shown in FIG. Can be configured.

  That is, the voltage Vin1 obtained by dividing the voltage Vr input to the VH terminal by the voltage dividing circuit 102 is supplied to the first comparator 101, and the voltage Vin2 obtained by dividing the DC voltage Vcc by the voltage dividing circuit 104 is supplied to the second comparator 103. And outputs the outputs of the first comparator 101 and the second comparator 103 to the NAND circuit 105. By supplying the output of the NAND circuit 105 to a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 106, a constant current source 107 is connected to the source of the P-channel MOSFET 106, and the drain is connected to the terminal PGS. A power good signal Spg for notifying the outside whether or not the low voltage prevention function is exhibited can be obtained from the terminal PGS.

By supplying the power good signal Spg to the photodiode 109a constituting the photocoupler 109 via the current limiting resistor 108, the power good signal Spg is notified from the phototransistor 109b constituting the photocoupler to an external microcomputer or the like. be able to.
The operation of the configuration of FIG. 6 will be described with reference to FIG. When the voltage Vr input to the VH terminal starts to be input at the time t21 as shown by the voltage Vin1 in FIG. 7A, which is the divided voltage, an external capacitor is charged by an activation circuit (not shown). Charging is started as indicated by the voltage Vin2 in FIG. 7B, which is the divided voltage of the DC voltage Vcc.

  When the divided voltage Vin2 of the DC voltage Vcc exceeds the switching operation start threshold voltage Vth2a at time t22, the switching power supply enters an operating state, and the switching operation is started as shown in FIG. At this time, the outputs of the first comparator 101 and the second comparator 103 become high level, and the output of the NAND circuit 105 becomes low level, whereby the P-channel MOSFET 106 is turned on and the constant current of the constant current source 107 is changed to PGS. As shown in FIG. 7C, a power good signal Spg is output to the terminal.

The power good signal Spg is supplied to the photodiode 109a constituting the photocoupler 109, whereby the photodiode 109a emits light and the phototransistor 109b is turned on.
After that, when the input voltage from the AC power source or the battery is cut off at time t23 and the rectified voltage Vr input to the VH terminal decreases, the output of the first comparator 101 becomes low level and the output of the NAND circuit 105 becomes high level. As a result, the P-channel MOSFET 106 is turned off, the output of the power good signal Spg is stopped as shown in FIG. 7C, and the current supplied to the photocoupler 109 as shown in FIG. 7D. Is cut off.

  On the other hand, the switching operation is continued until time t24. During this period, energy stored in the input capacitor connected to the external input voltage is transferred to the auxiliary winding by the switching operation, and thereby the DC voltage Vcc is maintained. When the switching operation is stopped at time t24, the DC voltage Vcc gradually decreases as shown in FIG. 7B. Therefore, the external device to which the power good signal Spg is supplied can execute the off sequence process between the time points t23 and t24.

JP 2014-3814 A

  In the power good signal generation circuit of FIG. 6 described above, the switching power supply performs the switching operation, and the power good signal Spg is always output to the photocoupler 109 in a state where the rectified voltage Vr is supplied. . The current supplied to the photodiode 109a of the photocoupler 109 must be determined in consideration of the conversion efficiency of the photocoupler 109 and its variation, and this current is usually 10 times the base current of the transistor. More than about is required.

This is a particular problem when it is essential to realize low standby power as a power supply specification. For example, when the device or system is in a dormant state, but the minimum power consumption is reduced for the next start-up, a minimum circuit such as a microcomputer is operating. It is.
In this case, the switching power supply uses a special switching operation such as intermittent switching operation or a low power consumption operation, and the power circuit cannot waste power consumption. Current is subject to reduction.

Therefore, it is conceivable to configure the external circuit as shown in FIG. 8 in order to suppress the current flowing through the photocoupler 109 during the normal operation of the switching power supply.
That is, the cathode of the photodiode 109a of the photocoupler 109 and the collector of the first transistor 111 are connected, and the emitter of the first transistor 111 is grounded. Then, the base of the first transistor is connected to the DC voltage Vcc through the current limiting resistor 112 and is connected to the collector of the second transistor 113 whose emitter is grounded. The anode of the photodiode 109a is connected to the DC voltage Vcc via the resistor 108. The power good signal Spg is supplied to the base of the second transistor 113 via the base resistor 114.

  In the circuit configuration of FIG. 8, as shown in FIG. 9C, the second transistor 113 is turned on in the section where the power good signal Spg is at a high level, so that the first transistor 111 is turned off. The energization of the photo-coupler 109 to the photodiode 109a is cut off. On the other hand, when the power good signal Spg is at the low level, the second transistor 113 is turned off and the first transistor 111 is turned on, so that a time t21 is obtained as shown in FIG. The current of the photocoupler 109 flows between the time t22 and the current of the photocoupler 109 flows between the time t23 and the time t24 when the off-sequence processing is executed, and then the current flowing through the photocoupler 109 decreases.

  At this time, since the switching power supply is not activated between the time t21 and the time t22, there is no output voltage on the secondary side of the flyback transformer, and the apparatus and the system are not activated. Can not be executed, so there is no problem. Thereafter, when the normal operation state after time t22 is entered, the power good signal Spg becomes high level, but the current of the photocoupler 109 does not flow, and the off sequence process is not executed.

  However, the circuit configuration of FIG. 8 can reduce the current supplied to the photocoupler 109 during normal operation, but causes a problem when the switching power supply is turned on. When an input voltage is input to the switching power supply at the time of start-up, an external capacitor that generates the DC voltage Vcc is charged by the starting circuit connected to the input voltage, and the DC voltage Vcc starts to rise. In the circuit configuration of FIG. 8, a forward current flows through the photodiode 109a of the photocoupler 109 until the divided voltage Vin2 of the DC voltage Vcc reaches the switching operation start threshold voltage Vth2a. The current for charging decreases, and the startup time becomes longer. Also, when the input voltage is low or when the forward current of the photodiode of the photocoupler is set to a large value, the charging current of the startup circuit must cover the current consumption before startup in the switching power supply and the current consumption in the external circuit. In the worst case, the divided voltage Vin2 of the DC voltage Vcc may not reach the switching operation start threshold voltage Vth2a, resulting in a start-up failure.

  Therefore, the present invention has been made by paying attention to the above-mentioned problems of the prior art, and switching that can output a power good signal only at the time of off-sequence processing without affecting the charging of the DC voltage at startup. An object of the present invention is to provide a power supply control semiconductor device.

  In order to achieve the above object, an aspect of a semiconductor device for controlling a switching power supply according to the present invention includes a voltage input terminal to which an input voltage is input from an external power supply, and a voltage of the external power supply input to the voltage input terminal. DC power supply terminal to which DC voltage is input from the auxiliary winding of the transformer applied to the primary side main winding, and detection that the detection voltage of the input voltage is lower than the first threshold voltage, and detection of DC voltage And a power good signal generation unit that outputs a power good signal to an external device when it is detected that the voltage is equal to or higher than the second threshold voltage.

  According to one aspect of the present invention, the input voltage and the control voltage are individually monitored, and when the input voltage drops below the first threshold voltage and the control voltage is above the second threshold voltage, the power good signal Can be output to an external device. Therefore, it is possible to output a power good signal only when off sequence processing is necessary while suppressing current consumption at startup.

1 is a circuit diagram of an overall configuration showing an embodiment of a switching power supply to which a switching power supply control semiconductor device according to the present invention is applied. It is a block diagram which shows the specific structure of the semiconductor device for switching power supply control which concerns on this invention. It is a block diagram which shows a power good signal generation circuit. 4 is a timing chart for explaining the operation of the power good signal generation circuit of FIG. 3. It is a block diagram which shows the modification of a power good signal generation circuit. It is a circuit diagram which shows the conventional power good signal generation circuit. 7 is a timing chart for explaining the operation of the power good signal generation circuit of FIG. 6. It is a circuit diagram which shows the other example of the conventional power good signal generation circuit. FIG. 9 is a timing chart for explaining the operation of the power good signal generation circuit of FIG. 8. FIG.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

A switching power supply control device according to an embodiment of the present invention will be described below with reference to the drawings.
As shown in FIG. 1, the entire configuration of the switching power supply apparatus has an AC input terminal 2 connected to an external AC power supply 1, and the AC input terminal 2 is connected to a rectifier circuit 3. A smoothing capacitor 4 is connected between the positive output terminal and the negative output terminal of the rectifier circuit 3. The positive electrode side of the smoothing capacitor 4 is connected to one end of the primary main winding L11 of the flyback transformer 5. The other end of the primary main winding L11 is connected to the drain of the switching element 6 formed of, for example, an N-channel MOSFET. The source of the switching element 6 is connected to the first ground potential GND 1 via the resistor 7.

The gate of the switching element 6 is connected to the OUT terminal of the switching power supply control semiconductor device 11 serving as a control circuit. Therefore, the switching element 6 performs a switching operation by the pulse width modulation signal Spwm output from the OUT terminal of the switching power supply control semiconductor device 11.
The switching power supply control semiconductor device 11 includes an integrated circuit. In addition to the OUT terminal, the VH terminal, the overheat latch protection LAT terminal, the feedback control FB terminal, the current detection CS terminal, the GND terminal, and the switching power supply A VCC terminal for power generation of the control semiconductor device 11 is provided.

  The VH terminal of the switching power supply control semiconductor device 11 is connected to a connection line between the power supply terminal 2 and the rectifier circuit 3 via rectifier diodes 12 and 13 and a current limiting resistor 14. The LAT terminal of the switching power supply control semiconductor device 11 is connected to one end of the thermistor 15, and the other end of the thermistor 15 is connected to the first ground potential GND1. The FB terminal of the semiconductor device 11 for switching power supply control is connected to the first ground potential GND1 through the phototransistor 16a constituting the photocoupler 16. The CS terminal of the switching power supply control semiconductor device 11 is connected to a common connection point of the capacitor 17 and the resistor 18, the other end of the capacitor 17 is connected to the first ground potential GND 1, and the other end of the resistor 18 is current detection. The resistor 7 and the switching element 6 are connected. The capacitor 17 and the resistor 18 constitute a noise filter for the signal detected by the current detection resistor 7.

  The VCC terminal of the switching power supply control semiconductor device 11 is connected to the positive terminal of the capacitor 19 and the cathode terminal of the diode 20, and the negative terminal of the capacitor 19 is connected to the first ground potential GND1. The anode terminal of the diode 20 is connected to one end of the primary side auxiliary winding L12 of the transformer 5, and the other end of the primary side auxiliary winding L12 is connected to the first ground potential GND1. The capacitor 19, the diode 20, and the primary side auxiliary winding L12 constitute a circuit that converts the AC voltage generated in the primary side auxiliary winding L12 into a DC power supply voltage, and constitute a power supply circuit of the semiconductor device 11 for switching power supply control doing.

  The transformer 5 has a secondary main winding L <b> 21, and one end thereof is connected to the anode terminal of the diode 21. The cathode terminal of the diode 21 is connected to the positive terminal of the capacitor 22, and the negative terminal of the capacitor 22 is connected to the other end of the secondary winding L21 and is connected to the second ground potential GND2. The secondary winding L21, the diode 21 and the capacitor 22 constitute a circuit for converting the AC voltage generated in the secondary winding L21 into a DC voltage, and constitute an output circuit of the switching power supply device. 22 positive terminals are connected to the load 23.

The positive terminal of the capacitor 22 is connected to the anode terminal of the photodiode 16 b that constitutes the photocoupler 16, and the cathode terminal of the photodiode 16 b is connected to the cathode terminal of the shunt regulator 25 that constitutes the shunt regulator circuit 24. The anode terminal of the shunt regulator 25 is connected to the second ground potential GND2.
The shunt regulator 25 is connected to a connection point of voltage dividing resistors 26 and 27 constituting a shunt regulator circuit 24 connected in series between the positive terminal and the negative terminal of the capacitor 22. The shunt regulator circuit 24 detects a voltage supplied to the load 23, and a voltage corresponding to the detection result is supplied as a feedback voltage Vfb to the FB terminal of the switching power supply control semiconductor device 11 via the photocoupler 16. .

This feedback voltage Vfb is also a signal indicating the magnitude of the load. The heavier the load (the larger the current flowing through the load 23), the larger the value of the feedback voltage Vfb, and the lighter the load (the current flowing through the load 23). The smaller the value), the smaller the value of the feedback voltage Vfb.
Here, the AC power supply 1, the rectifier circuit 3, the smoothing capacitor 4, the flyback transformer 5, the MOSFET 6, the diode 21, and the capacitor 22 constitute a switching power supply operating unit.

  Next, a specific configuration of the switching power supply control semiconductor device 11 will be described with reference to FIG. Hereinafter, the ground (GND) potential shown for the specific configuration of the switching power supply control semiconductor device 11 is the first ground potential GND1. The switching power supply control semiconductor device 11 is connected between a startup circuit 31 connected between the VH terminal and the VCC terminal and supplying current from the VH terminal to the VCC terminal at startup, and between the startup circuit 31 and the VCC terminal. A low voltage detection circuit 32 having hysteresis for operating the starter circuit 31 when the DC voltage Vcc at the VCC terminal is low, and an internal power supply circuit 33 for forming an internal power supply of 5 V, for example, connected to the VCC terminal. .

The VH terminal is for supplying a current to the power supply terminal VCC at the time of startup, and the main power supply terminal of the switching power supply control semiconductor device 11 itself is the VCC terminal.
The low voltage detection circuit 32 activates the activation circuit 31 when the DC voltage Vcc is less than the threshold voltage Vth0b, and stops the activation circuit 31 when the DC voltage Vcc becomes equal to or higher than the threshold voltage Vth0a. Note that the low voltage detection circuit 32 has hysteresis means that the threshold voltage Vth0 input to the inverting input terminal of the low voltage detection circuit 32 is actually composed of two threshold voltages, ie, the threshold voltage. Vth0a represents a higher threshold voltage, and threshold voltage Vth0b represents a lower threshold voltage (hereinafter, the notation method for other threshold voltages is also the same).

The internal power supply circuit 33 supplies the internal power supply voltage of 5 V to each circuit in the switching power supply control semiconductor device 11 as an operation power supply when the power supply voltage of the VCC terminal is within the normal range, and also the DC voltage of the VCC terminal. When Vcc drops below the set voltage, a reset signal for resetting each circuit in the switching power supply control semiconductor device 11 is output.
The switching power supply control semiconductor device 11 monitors the input voltage Vin input from the VH terminal and the DC voltage Vcc input from the VCC terminal, and outputs a power good signal to the external load 23. A generation unit 34 is provided.

  As shown in FIG. 3, the power good signal generator 34 includes a first comparator 34a and a determination timer 34b as an input voltage detector that monitors the voltage Vin1 divided by the voltage dividing circuit VD1 of the input voltage Vin. A second comparator 34c as a DC voltage detection unit that monitors the voltage Vin2 divided by the voltage dividing circuit VD2 of the DC voltage Vcc, a power good signal output unit 34d, a delay time timer 34i, and a delay circuit 34j are provided. ing.

  In the first comparator 34a, the input voltage Vr input to the VH terminal is input to the non-inverting input terminal via the voltage dividing circuit VD1, and the first threshold voltage Vth1 is input to the inverting input terminal. Since this first comparator 34a has a hysteresis characteristic, the first threshold voltage Vth1 has two values Vth1a and Vth1b (Vth1a> Vth1b). When the divided voltage Vin1 of the input voltage Vr increases, the first comparison signal Sc1 that is the output of the first comparator 34a is at a low level when the initial divided voltage Vin1 is equal to or lower than the switching operation stop threshold voltage Vth1b. . Then, when the divided voltage Vin1 of the input voltage Vr exceeds the switching operation start threshold voltage Vth1a, the high-level first comparison signal Sc1 is output to the determination timer 34b. On the other hand, when the divided voltage Vin1 of the input voltage Vr falls from a state higher than the switching operation start threshold voltage Vth1a, the low level first voltage V11 falls below the switching operation stop threshold voltage Vth1b lower than the switching operation start threshold voltage Vth1a. 1 comparison signal Sc1 is output to determination timer 34b.

  The determination timer 34b starts counting when the first comparison signal Sc1 at the low level is input, and changes the determination signal Sd from the high level to the low level when counting to a predetermined delay time. When the high-level first comparison signal Sc1 is input to the determination timer 34b, the determination timer 34b is reset and the determination signal Sd becomes high level. Here, if the prescribed delay time is set to be equal to or longer than a half cycle of the AC input from the AC power supply 1 (when the rectification by the rectifier circuit is full-wave rectification), even if the determination timer 34b starts counting, the count is not increased. Since the first comparison signal Sc1 having the high level is always input before the end, the counting of the determination timer 34b does not end and the determination signal Sd does not become the low level. That is, if the AC input is normally input from the AC power supply 1 (if the peak value of the divided voltage Vin1 of the input voltage Vr exceeding the switching operation start threshold voltage Vth1 is continuously input to the first comparator 34a. ) The determination signal Sd is kept at a high level in principle. On the contrary, if the state where the peak of the AC input from the AC power supply 1 does not reach the predetermined value continues, the count of the determination timer 34b ends and the determination signal Sd becomes low level.

  Accordingly, if the determination signal Sd is at a high level, it indicates that the input voltage Vr is normal (a state in which a switch operation is possible), and if it is at a low level, it indicates that it is abnormal. It should be noted that the prescribed delay time is set to a length corresponding to several cycles of the AC power supply 1 so that the determination signal Sd does not become low level due to erroneous detection due to noise or the like or a short-time instantaneous voltage drop at a level that does not cause a problem. Set to.

  In the second comparator 34c, the divided voltage Vin2 of the DC voltage Vcc input to the VCC terminal is input to the non-inverting input terminal, and the second threshold voltage Vth2 is input to the inverting input terminal. Since the second comparator 34c has hysteresis characteristics, the second threshold voltage Vth2 has two values Vth2a and Vth2b (Vth2a> Vth2b). When the divided voltage Vin2 of the DC voltage Vcc increases, the second comparison signal Sc2 that is the output of the second comparator 34c is at a low level when the initial divided voltage Vin2 is equal to or lower than the switching operation start threshold voltage Vth2a. . Then, when the DC voltage Vcc exceeds the switching operation start threshold voltage Vth2a, the high-level second comparison signal Sc2 is output. Conversely, when the divided voltage Vin2 of the DC voltage Vcc falls from a state higher than the switching operation start threshold voltage Vth2a, when the switching operation stop threshold voltage Vth2b as the first threshold voltage lower than the switching operation start threshold voltage Vth2a is reached In addition, a low-level second comparison signal Sc2 is output.

  The second comparison signal Sc2 is input to the power good signal output unit 34d and the delay circuit 34j. The output of the delay circuit 34j is input to the second reset terminal of the determination timer 34b. Accordingly, the determination timer 34b is reset by the output of the delay circuit 34j at the moment when the divided voltage Vin2 of the DC voltage Vcc exceeds the switching operation start threshold voltage Vth2a.

The power good signal output unit 34d includes a logic inverting circuit 34e, a logic circuit (NAND gate) 34f, a P-channel MOSFET 34g, and a constant current circuit 34h.
The logic inversion circuit 34e inverts the logic level of the determination signal Sd output from the determination timer 34b. The logic inversion circuit 34e outputs the determination signal Sd ′ that has been logically inverted and inputs it to the NAND gate 34f.

The NAND gate 34f receives a determination signal Sd ′ obtained by logically inverting the determination signal Sd output from the logic inverting circuit 34e and a second comparison signal Sc2 output from the second comparator 34c, and outputs the logical output of the P-channel MOSFET 34g. Enter the gate.
The P-channel MOSFET 34g has an open drain configuration in which the source is connected to the internal power supply output from the internal power supply circuit 33 via the constant current circuit 34h, and the drain is connected to the PGS terminal.

The delay time timer 34i has an inverting input terminal to which the determination signal Sd of the determination timer 34b is input. When the determination signal Sd becomes a low level, a delay time for performing a preset off sequence process is set. The switching stop signal SStp is output to the driver circuit 35 after the delay time has elapsed.
Further, the determination signal Sd of the determination timer 34b is output to the driver circuit 35 as the switching enable signal Ssab.

  Further, the anode of a photodiode 36a constituting the photocoupler 36 is connected to the PGS terminal via a current limiting resistor R1, and the cathode of the photodiode 36a is connected to the ground potential. The phototransistor 36b constituting the photocoupler 36 is connected to the load 23, and when the power good signal Spg is at a high level, the load 23 executes an off sequence process.

  The driver circuit 35 outputs a pulse width modulation (PWM) signal having a frequency corresponding to the feedback voltage Vfb from the load 23 to the switching element 6 from the OUT terminal. The driver circuit 35 outputs a pulse width modulation signal to the OUT terminal when the switching enable signal Ssab output from the power good signal generation unit 34 is at a high level, and a switching stop signal input from the delay time timer 34i. When Sstp becomes high level, the output of the pulse width modulation signal to the OUT terminal is stopped.

Further, the driver circuit 35 performs overcurrent suppression control based on the current detection value Vi input from the CS terminal, and performs overheat suppression control based on the temperature detection value Vt input from the LAT terminal.
Next, the operation of the above embodiment will be described with reference to FIG.
First, at the time t1 shown in FIG. 4A, the capacitor 19 is discharged, and the supply of the rectified voltage obtained by rectifying the AC signal from the AC power source 1 input to the VH terminal with the diodes 12 and 13 is stopped. It is assumed that it is in the state that has been done.

  In this state, since the input voltage Vr input to the VH terminal is zero and the DC voltage Vcc input to the VCC terminal is also zero, the internal power supply is not output from the internal power supply circuit 33. The semiconductor device 11 for switching power supply control is in an operation stop state. In this state, the switching element 6 also stops the switching operation, the power good signal generation unit 34 is also in the operation stop state, the power good signal Spg is not output from the PGS terminal, and the photodiode 36a of the photocoupler 36 It remains off without being energized.

An AC voltage is output from the AC power source 1 at time t2 from this operation stop state, and this AC voltage is rectified by the diodes 12 and 13 and input to the VH terminal as an input voltage Vr in a pulsating state.
When the input voltage Vr is input, the starter circuit 31 enters an operating state, and a starter current is supplied from the starter circuit 31 to the capacitor 19 through the VCC terminal, and charging of the capacitor 19 is started. For this reason, the divided voltage Vin2 of the DC voltage Vcc at the VCC terminal gradually increases as shown in FIG. 4B, and the divided voltage Vin2 of the DC voltage Vcc becomes the set voltage (threshold voltage Vth2a) of the internal power supply circuit 33. If it exceeds, an internal voltage is output from the internal power supply circuit 33, and the internal power is supplied to each circuit of the semiconductor device 11 for switching power supply control so that each circuit is in an operating state.

  At this time, the determination timer 34b also starts to operate, but the determination signal Sd is at a high level as shown in FIG. 4A by the output of the delay circuit 34j. After that, every time the vicinity of the peak value of the divided voltage Vin1 of the input voltage Vr exceeding the first threshold voltage Vth1 (switching operation start threshold voltage Vth1a) arrives, the first comparison signal Sc1 of the first comparator 34a becomes high level. Thus, the determination timer 34b is reset. This high level determination signal Sd is logically inverted by the logic inversion circuit 34e, and is input to the NAND gate 34f at a low level. Therefore, the output signal of the NAND gate 34f maintains a high level, the P-channel MOSFET 34g maintains an off state, the power good signal Spg is not output to the PGS terminal, and the photodiode 36a of the photocoupler 36 is in a non-energized state. Keep the light off.

On the other hand, in the second comparator 34c, the second comparison signal Sc2 output from the second comparator 34c remains low until the divided voltage Vin2 of the DC voltage Vcc reaches the switching operation start threshold voltage Vth2a of the second comparator 34c. maintain. For this reason, the output signal of the NAND gate 34f maintains a high level.
Further, when the determination signal Sd of the determination timer 34b becomes high level, the switching enable signal Ssab is output to the driver circuit 35.

When the divided voltage Vin2 of the DC voltage Vcc exceeds the switching operation start threshold voltage Vth2a at time t3, the pulse width modulation signal Spwm is output from the driver circuit 35 to the output terminal OUT, and this is supplied to the gate of the switching element 6. The switching element 6 starts a switching operation.
For this reason, an AC induced voltage is generated in the secondary main winding L 21 of the flyback transformer 5, this AC induced voltage is rectified by the diode 21, smoothed by the capacitor 22, and supplied to the load 23. A current corresponding to the load current supplied to the load 23 flows through the shunt regulator 25 through the photodiode 16 b of the photocoupler 16. Therefore, the feedback voltage Vfb is input to the FB terminal through the photocoupler 16, and the frequency of the pulse width modulation signal of the driver circuit 35 is controlled.

  At this time t3, the divided voltage Vin2 of the DC voltage Vcc exceeds the switching operation start threshold voltage Vth2a, and the second comparator 34c outputs the second comparison signal Sc2 having a high level, but the divided voltage Vin1 of the input voltage Vr. The output signal of the NAND gate 34f is maintained at a low level, the P-channel MOSFET 34g is maintained in an OFF state, and the power good signal is maintained as long as the peak value of the NAND gate 34f repeatedly exceeds the first threshold voltage Vth1 (switching operation start threshold voltage Vth1a). Spg maintains a low level.

  During this time, when the control voltage Vcc exceeds the threshold voltage Vth0 of the low voltage detection circuit 32 having hysteresis, the activation circuit 31 is deactivated. Further, when the switching element 6 performs the switching operation, the alternating current output from the primary side auxiliary winding L12 of the flyback transformer 5 is rectified by the diode 20, smoothed by the capacitor 19, and supplied to the VCC terminal. The switching power supply control semiconductor device 11 is in a normal operation state.

When the AC power supply 1 is stopped from the normal operation state and the divided voltage Vin1 of the input voltage Vr to the VH terminal becomes equal to or lower than the threshold voltage Vth1 (switching operation stop threshold voltage Vth1b), the first comparison signal Sc1 of the first comparator 34a. Is maintained at the low level, the determination timer 34b finishes counting at time t4, and the determination signal Sd becomes the low level.
Since this determination signal Sd is supplied to the delay time timer 34i, the delay time timer 34i starts measuring the delay time.

  At the same time, the determination signal Sd is logically inverted by the logic inversion circuit 34e to become a high level determination signal Sd '. At this time, since the divided voltage Vin2 of the DC voltage Vcc exceeds the switching operation start threshold voltage Vth2a of the second comparator 34c as shown in FIG. 4B, the second comparison output from the second comparator 34c. The signal Sc2 is maintained at a high level.

  Therefore, at time t4, the output signal of the NAND gate 34f is inverted from the low level to the high level, the P-channel MOSFET 34g is turned on, and the current supplied from the constant current circuit 34h is power good as shown in FIG. The signal Spg is supplied to the photodiode 36a of the photocoupler 36 through the PGS terminal. Therefore, the power good signal Spg can be notified to the load 23 through the photocoupler 36. Therefore, the load 23 determines that the load current supplied from the secondary main winding L21 of the flyback transformer 5 is stopped, performs necessary data saving, etc., and turns off the load 23. Perform off-sequence processing.

In this state, the driver circuit 35 continues to operate, and as shown in FIG. 4E, the output of the pulse width modulation signal Spwm is continued, so that the current required by the load 23 is the pulse width modulation signal. This is ensured by controlling the frequency. The energy source at this time is the smoothing capacitor 4.
After that, when the delay time of the delay time timer 34i elapses at time t5, the switching stop signal SStp is output from the delay time timer 34i to the driver circuit 35, whereby the pulse width modulation signal Spwm from the driver circuit 35 is output. Output is stopped. As a result, the switching operation of the switching element 6 is stopped, and the current supply from the secondary main winding L21 of the flyback transformer 5 to the load 23 is stopped. The driver circuit 35 executes the switching operation if at least one of the switching enable signal Ssab and the switching stop signal SStp is at a high level, and stops the switching operation when both of them are at a low level. To do.

  The delay time of the delay time timer 34i is set to a time sufficient for executing the off sequence process. Note that the switching operation is stopped at time t5 by the delay time timer 34i. If the switching operation is continued further, the voltage drop of the smoothing capacitor 4 proceeds, and the driver circuit 35 outputs a predetermined energy against this. This is because the on-time of the switching element 6 is lengthened to increase the input current to be sent to the side (secondary side), and thus the current flowing through the switching element 6 may exceed the allowable range.

  As the switching operation of the switching element 6 stops, the divided voltage Vin2 of the DC voltage Vcc supplied to the VCC terminal also gradually decreases as shown in FIG. 4B. When the divided voltage Vin2 of the control voltage Vcc falls below the switching operation stop threshold voltage Vth2b of the second comparator 34c at time t6, the comparison signal Sc2 of the second comparator 34c is inverted from the high level to the low level. Therefore, the output signal of the NAND gate 34f is inverted from the low level to the high level, the P-channel MOSFET 34g is turned off, and the output of the power good signal Spg from the PGS terminal is stopped.

  Even when the delay time timer 34i is timed up and the determination signal Sd becomes a low level at time t4, the peak value of the divided voltage Vin1 of the input voltage Vr is thereafter the first threshold voltage Vth1 (switching operation start threshold voltage Vth1a). ) When returning to the above, the first comparison signal Sc1 of the first comparator 34a returns to high level and the determination signal Sd of the determination timer 34b returns to high level, thereby stopping the output of the power good signal Spg. The delay time timer 34i is reset and the normal operation state is continued.

  Thus, according to the above embodiment, the output of the power good signal Spg is such that the divided voltage Vin1 of the input voltage Vr is equal to or lower than the switching operation stop threshold voltage Vth1b, the determination signal Sd becomes low level, and the DC voltage Vcc is divided. This is performed only when the voltage Vin2 continues the switching operation stop threshold voltage Vth2b or higher. For this reason, the power good signal Spg is not output when the capacitor 19 is charged by the starting current in the starting circuit 31 at the time of starting the supply of the rectified voltage Vr to the VH terminal. Therefore, it is possible to prevent the charging current to the capacitor 19 from being consumed for generating the power good signal Spg, and to reliably prevent the start-up time from being delayed or the start-up failure from occurring. it can.

  Even when the input voltage Vr input to the VH terminal at the time of startup is lower and the peak value of the divided voltage Vin1 of the input voltage Vr is equal to or lower than the first threshold voltage Vth1 of the first comparator 34a, the starter circuit 31 operates. When the capacitor 19 is charged and the divided voltage Vin2 of the DC voltage Vcc reaches the switching operation start threshold voltage Vth2a of the second comparator 34c and the internal power supply circuit 33 is activated, the power good signal Spg is output. Will be. However, at this time, since both the switching enabling signal Ssab and the switching stop signal Sstp are at the low level, the switching operation of the switching element 6 is not actually started, and the secondary main winding L21 of the flyback transformer 5 is not started. In this state, no AC induced voltage is generated, and the off-sequence process is not executed.

  Switching in which the divided voltage Vin1 of the input voltage Vr is equal to or higher than the first threshold voltage Vth1 (switching operation start threshold voltage Vth1a) of the first comparator 34a, and the divided voltage Vin2 of the DC voltage Vcc becomes the second threshold voltage of the second comparator 34c. When the voltage exceeds the operation stop threshold voltage Vth2 (Vth2a) or more, the internal power supply circuit 33 operates to activate the driver circuit 35. The driver circuit 35 supplies the pulse width modulation signal Spwm to the switching element 6 to enter the switching operation state. Become. However, since the power good signal Spg is not output at this time as well, no current consumption occurs in the photocoupler 36, and an increase in low standby power when the load 23 is in a light load state can be prevented. it can.

From this state, when the AC power supply is cut off and the divided voltage Vin1 of the input voltage Vr drops below the first threshold voltage Vth1 (Vth1b) of the first comparator 34a, the power good signal Spg is output for the first time. Then, the photodiode 36a of the photocoupler 36 is turned on, and the off sequence process is executed by the load 23.
Thus, according to the present embodiment, the input voltage Vr is monitored by the first comparator 34a and the determination timer 34b, and the DC voltage Vcc is monitored by the second comparator 34c, whereby the divided voltage Vin1 of the input voltage Vr is switched. The power good signal Spg is generated only when the stop threshold voltage Vth1b or lower and the divided voltage Vin2 of the DC voltage Vcc is maintained at the switching operation stop threshold voltage Vth2b or higher that is the second threshold voltage. It is possible to notify the load 23 via For this reason, the off sequence process with the load 23 can be performed effectively. In addition, the power good signal generator 34 for this purpose can have a simple configuration in which only two comparators 34a and 34c, a determination timer 34b, a power good signal output unit 34d, and a photocoupler 36 are provided.

  In the above embodiment, the case where the photodiode 36a of the photocoupler 36 is directly connected to the PGS terminal via the current limiting resistor R1 has been described. However, the present invention is not limited to this, as shown in FIG. The PGS terminal is connected to the base of the transistor 40, the collector of this transistor is connected to the cathode of the photodiode 36a of the photocoupler 36 to which the control voltage Vcc is supplied to the anode via the current limiting resistor R1, and the emitter is connected. It may be grounded.

  In the above embodiment, the case where the output voltage on the secondary side of the flyback transformer 5 is detected by the shunt regulator 25 and the detection result is transmitted as the feedback voltage via the photocoupler 16 has been described. However, the present invention is not limited to this. Instead, the output voltage on the secondary side can be indirectly detected by the output voltage of the primary side auxiliary winding L12 of the transformer 5, and this can be used as the feedback voltage.

Moreover, although the case where the present invention is applied to a flyback type switching power supply has been described in the above embodiment, the present invention is not limited to this, and the present invention can also be applied to an LLC current resonance type switching power supply. it can.
Further, although the input voltage to the switching power supply device is a voltage obtained by rectifying the AC input from the external AC power supply 1 by the rectifier circuit 3, it may be a DC voltage such as a battery. In that case, the rectifier circuit 3, the diodes 12, 13 and the delay circuit 34j in FIG. 1 are unnecessary, and the output voltage of the battery is connected to the voltage input terminal VH via the resistor 14. Even if the input voltage is a DC voltage, the first comparator 34a is operated by the voltage, so it is clear that the present invention can be applied.

  Further, although the voltage dividing circuits VD1 and VD2 are applied to the detection of the voltages Vr and Vcc, it goes without saying that a detection voltage of the voltages Vr and Vcc may be obtained by applying a level shift circuit instead of the voltage dividing circuit. That is.

  DESCRIPTION OF SYMBOLS 1 ... AC power source, 3 ... Rectifier circuit, 4 ... Smoothing capacitor, 5 ... Flyback transformer, L11 ... Primary side main winding, L21 ... Secondary side main winding, L12 ... Primary side auxiliary winding, 6 ... Switching Elements 11, semiconductor device for switching power supply control 16, photocoupler 23, load 24, shunt regulator circuit 31, startup circuit 32, low voltage detection circuit 33, internal power supply circuit 34, power good signal generation Part 34a ... first comparator 34b ... determination timer 34c ... second comparator 34d ... power good signal output part 34e ... logic inversion circuit 34f ... logic circuit (Nand gate) 34g ... P-channel MOSFET 34h ... constant Current circuit 34i ... Delay time timer 34j ... Delay circuit 35 ... Driver circuit 36 ... Photocoupler

Claims (8)

A voltage input terminal to which an input voltage is input from an external power supply;
A DC power supply terminal to which a DC voltage is input from an auxiliary winding of a transformer in which the voltage of the external power supply input to the voltage input terminal is applied to the primary main winding;
A power good signal is output to an external device when it is detected that the detected voltage of the input voltage is less than or equal to the first threshold voltage and the detected voltage of the DC voltage is greater than or equal to the second threshold voltage A switching power supply control semiconductor device, comprising: a power good signal generation unit that performs a switching operation.   The power good signal generation unit includes: an input voltage detection unit configured to detect whether or not a detection voltage of the input voltage input to the voltage input terminal is equal to or lower than a first threshold voltage; A direct-current voltage detector that detects whether or not the threshold voltage is greater than or equal to a threshold voltage; the input voltage detector detects that the detected voltage of the input voltage is less than or equal to a first threshold voltage; and the direct-current voltage detector detects the The power good signal output part which outputs a power good signal to an external device when it detects that the detection voltage of DC voltage is more than the said 2nd threshold voltage is provided. Switching power supply control semiconductor device.   The input voltage detection unit includes a comparator to which the input voltage detection voltage and the first threshold voltage are input, and the DC voltage detection unit receives the DC voltage detection voltage and the second threshold voltage. The power good signal output unit is configured to receive an output signal of the input voltage detection unit, a logic circuit to which an output of the DC voltage detection unit is input, a constant current, and a control terminal 3. The switching power supply control semiconductor device according to claim 2, further comprising: a switching element to which an output of the logic circuit is input as a control signal, and outputting a power good signal from the switching element.   4. The apparatus according to claim 1, further comprising: a charging unit externally attached to the DC power supply terminal; and a starting circuit that charges the charging unit with a starting current supplied from the voltage input terminal. The semiconductor device for switching power supply control according to one item.   4. The switching according to claim 3, wherein the power good signal output unit outputs a switching enable signal when a detection voltage of the input voltage exceeds a first threshold voltage in the input voltage detection unit. 5. Semiconductor device for power control.   The power good signal output unit outputs a switching stop signal when a predetermined delay time elapses after the detection voltage of the input voltage is equal to or lower than a first threshold voltage in the input voltage detection unit. Item 6. A semiconductor device for controlling a switching power supply according to Item 3 or 5. The input voltage from the external power source is a rectified voltage of the AC voltage of the AC power source,
The switching power supply according to claim 2, wherein the input voltage detection unit detects whether or not a peak voltage of a detection voltage of the rectified voltage input to the voltage input terminal is equal to or lower than a first threshold voltage. Control semiconductor device. The input voltage detection unit includes a comparator to which a voltage obtained by dividing or level-shifting the input voltage and the first threshold voltage are input, and a determination timer to which an output of the comparator is input, and the comparator is the input When the voltage obtained by dividing or level-shifting the voltage exceeds the first threshold voltage, the discrimination timer is reset, and when the period when the discrimination timer is not reset exceeds the discrimination period, the peak voltage of the detected value of the rectified input voltage becomes the first voltage. Outputs a signal indicating that the threshold voltage is 1 or less,
8. The semiconductor device for controlling a switching power supply according to claim 7, wherein the DC voltage detector includes a comparator to which a voltage obtained by dividing or level-shifting the DC voltage and the second threshold voltage are input.

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