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JP2018148016A - Light emitting diode chip manufacturing method and light emitting diode chip - Google Patents

Light emitting diode chip manufacturing method and light emitting diode chip Download PDF

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JP2018148016A
JP2018148016A JP2017041315A JP2017041315A JP2018148016A JP 2018148016 A JP2018148016 A JP 2018148016A JP 2017041315 A JP2017041315 A JP 2017041315A JP 2017041315 A JP2017041315 A JP 2017041315A JP 2018148016 A JP2018148016 A JP 2018148016A
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transparent substrate
transparent
emitting diode
wafer
light emitting
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卓 岡村
Taku Okamura
卓 岡村
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Disco Corp
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Disco Abrasive Systems Ltd
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Priority to JP2017041315A priority Critical patent/JP2018148016A/en
Priority to TW107104141A priority patent/TWI789375B/en
Priority to KR1020180023657A priority patent/KR102315305B1/en
Priority to CN201810171673.1A priority patent/CN108538995A/en
Publication of JP2018148016A publication Critical patent/JP2018148016A/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/855Optical field-shaping means, e.g. lenses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/819Bodies characterised by their shape, e.g. curved or truncated substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/8506Containers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/036Manufacture or treatment of packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/036Manufacture or treatment of packages
    • H10H20/0363Manufacture or treatment of packages of optical field-shaping means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Dicing (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Laser Beam Processing (AREA)

Abstract

【課題】十分な輝度が得られる発光ダイオードチップの製造方法及び発光ダイオードチップを提供する。【解決手段】結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路19が形成されたウエーハを準備するウエーハ準備工程と、内部に複数の気泡が形成された第1又は第2の透明基板の少なくともどちらか一方の表面又は裏面にLED回路に対応して複数の溝23Bを形成する透明基板加工工程と、第1の透明基板の表面をウエーハの裏面に貼着すると共に第2の透明基板の表面を第1の透明基板の裏面に貼着して一体化ウエーハを形成する透明基板貼着工程と、ウエーハを分割予定ラインに沿って第1及び第2の透明基板と共に切断して一体化ウエーハを個々の発光ダイオードチップ31に分割する分割工程と、を備える製造方法。【選択図】図9Provided are a method of manufacturing a light emitting diode chip and a light emitting diode chip capable of obtaining sufficient luminance. A stacked layer includes a plurality of semiconductor layers including a light emitting layer formed on a transparent substrate for crystal growth. Each of the plurality of semiconductor layers is divided by a plurality of planned dividing lines intersecting each other on a surface of the stacked layer. A wafer preparation step of preparing a wafer in each of which a LED circuit 19 is formed in a region, and a corresponding LED circuit on at least one of the front and back surfaces of the first or second transparent substrate having a plurality of bubbles formed therein. A transparent substrate processing step of forming a plurality of grooves 23B, and attaching the front surface of the first transparent substrate to the back surface of the wafer and attaching the front surface of the second transparent substrate to the back surface of the first transparent substrate. A step of attaching a transparent substrate to form an integrated wafer by dividing the integrated wafer into individual light emitting diode chips 31 by cutting the wafer along with the first and second transparent substrates along a line to be divided. The manufacturing method comprising the steps, a. [Selection diagram] FIG.

Description

本発明は、発光ダイオードチップの製造方法及び発光ダイオードチップに関する。   The present invention relates to a light emitting diode chip manufacturing method and a light emitting diode chip.

サファイア基板、GaN基板、SiC基板等の結晶成長用基板の表面にn型半導体層、発光層、p型半導体層が複数積層された積層体層が形成され、この積層体層に交差する複数の分割予定ラインによって区画された領域に複数のLED(Light Emitting Diode)等の発光デバイスが形成されたウエーハは、分割予定ラインに沿って切断されて個々の発光デバイスチップに分割され、分割された発光デバイスチップは携帯電話、パソコン、照明機器等の各種電気機器に広く利用されている。   A stacked body layer in which a plurality of n-type semiconductor layers, light-emitting layers, and p-type semiconductor layers are stacked is formed on the surface of a crystal growth substrate such as a sapphire substrate, a GaN substrate, or a SiC substrate. A wafer in which a plurality of light emitting devices such as LEDs (Light Emitting Diodes) are formed in a region partitioned by the planned division line is cut along the planned division line and divided into individual light emitting device chips, and the divided light emission Device chips are widely used in various electric devices such as mobile phones, personal computers, and lighting devices.

発光デバイスチップの発光層から出射される光は等方性を有しているため、結晶成長用基板の内部にも照射されて基板の裏面及び側面からも光が出射する。然し、基板の内部に照射された光のうち空気層との界面での入射角が臨界角以上の光は界面で全反射されて基板内部に閉じ込められ、基板から外部に出射されることがないから発光デバイスチップの輝度の低下を招くという問題がある。   Since the light emitted from the light emitting layer of the light emitting device chip is isotropic, the light is emitted also to the inside of the crystal growth substrate, and the light is also emitted from the back and side surfaces of the substrate. However, of the light irradiated to the inside of the substrate, light whose incident angle at the interface with the air layer is greater than the critical angle is totally reflected at the interface and confined inside the substrate, and is not emitted outside from the substrate. Therefore, there is a problem that the luminance of the light emitting device chip is lowered.

この問題を解決するために、発光層から出射された光が基板の内部に閉じ込められるのを抑制するために、基板の裏面に透明部材を貼着して輝度の向上を図るようにした発光ダイオード(LED)が特開2014−175354号公報に記載されている。   In order to solve this problem, a light emitting diode in which a transparent member is attached to the back surface of the substrate to improve the luminance in order to prevent light emitted from the light emitting layer from being confined inside the substrate. (LED) is described in Japanese Patent Application Laid-Open No. 2014-175354.

特開2014−175354号公報JP 2014-175354 A

然し、特許文献1に開示された発光ダイオードでは、基板の裏面に透明部材を貼着することにより輝度が僅かに向上したものの十分な輝度が得られないという問題がある。   However, the light emitting diode disclosed in Patent Document 1 has a problem that sufficient luminance cannot be obtained although the luminance is slightly improved by sticking a transparent member to the back surface of the substrate.

本発明はこのような点に鑑みてなされたものであり、その目的とするところは、十分な輝度が得られる発光ダイオードチップの製造方法及び発光ダイオードチップを提供することである。   The present invention has been made in view of these points, and an object of the present invention is to provide a method of manufacturing a light-emitting diode chip and a light-emitting diode chip that can obtain sufficient luminance.

請求項1記載の発明によると、発光ダイオードチップの製造方法であって、結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路が形成されたウエーハを準備するウエーハ準備工程と、内部に複数の気泡が形成された第1の透明基板又は内部に複数の気泡が形成された第2の透明基板の少なくともどちらか一方の表面又は裏面にLED回路に対応して複数の溝を形成する透明基板加工工程と、該透明基板加工工程を実施した後、該第1の透明基板の表面をウエーハの裏面に貼着すると共に該第2の透明基板の表面を該第1の透明基板の裏面に貼着して一体化ウエーハを形成する透明基板貼着工程と、該透明基板貼着工程を実施した後、該ウエーハを該分割予定ラインに沿って該第1及び第2の透明基板と共に切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、を備えたことを特徴とする発光ダイオードチップの製造方法が提供される。   According to invention of Claim 1, it is a manufacturing method of a light emitting diode chip | tip, Comprising: It has a laminated body layer in which the several semiconductor layer containing a light emitting layer was formed on the transparent substrate for crystal growth, This laminated body layer A wafer preparation step of preparing a wafer in which LED circuits are formed in each region partitioned by a plurality of division lines intersecting each other on the surface of the substrate, and a first transparent substrate having a plurality of bubbles formed therein or the inside A transparent substrate processing step of forming a plurality of grooves corresponding to the LED circuits on the front surface or the back surface of at least one of the second transparent substrates in which a plurality of bubbles are formed, and after performing the transparent substrate processing step Affixing the surface of the first transparent substrate to the back surface of the wafer and attaching the surface of the second transparent substrate to the back surface of the first transparent substrate to form an integrated wafer Steps, and A division step of dividing the integrated wafer into individual light emitting diode chips by cutting the wafer together with the first and second transparent substrates along the division line after performing the bright substrate attaching step; A method for manufacturing a light-emitting diode chip is provided.

好ましくは、透明基板加工工程において形成される溝の断面形状は、三角形状、四角形状、又は半円形状の何れかである。好ましくは、透明基板加工工程において形成される溝は、切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成される。   Preferably, the cross-sectional shape of the groove formed in the transparent substrate processing step is any one of a triangular shape, a quadrangular shape, and a semicircular shape. Preferably, the groove formed in the transparent substrate processing step is formed by any one of a cutting blade, etching, sand blasting, and laser.

該第1及び第2の透明基板は、透明セラミックス、光学ガラス、サファイア、透明樹脂の何れかで形成され、該透明基板貼着工程において、該第1の透明基板は透明接着剤でウエーハに接着され、該第2の透明基板は透明接着剤で該第1の透明基板に接着される。   The first and second transparent substrates are formed of any one of transparent ceramics, optical glass, sapphire, and transparent resin, and the first transparent substrate is bonded to the wafer with a transparent adhesive in the transparent substrate attaching step. Then, the second transparent substrate is bonded to the first transparent substrate with a transparent adhesive.

請求項5記載の発明によると、発光ダイオードチップであって、表面にLED回路が形成された発光ダイオードと、該発光ダイオードの裏面に貼着された内部に複数の気泡が形成された第1の透明部材と、該第1の透明部材の裏面に貼着された内部に複数の気泡が形成された第2の透明部材と、を備え、該第1の透明部材又は該第2の透明部材の少なくともどちらか一方の表面又は裏面に溝が形成されている発光ダイオードチップが提供される。   According to invention of Claim 5, it is a light emitting diode chip | tip, Comprising: The light emitting diode by which the LED circuit was formed in the surface, and several bubble was formed in the inside stuck on the back surface of this light emitting diode. A transparent member, and a second transparent member having a plurality of bubbles formed inside attached to the back surface of the first transparent member, the first transparent member or the second transparent member There is provided a light-emitting diode chip in which a groove is formed on at least one of the front surface and the back surface.

本発明の発光ダイオードチップは、少なくとも2層の透明部材に形成された複数の気泡と溝とによって光が複雑に屈折して第1及び第2の透明部材内に閉じ込められる光が減少し、第1及び第2の透明部材から出射される光の量が増大して発光ダイオードチップの輝度が向上する。   In the light emitting diode chip of the present invention, light is refracted in a complicated manner by a plurality of bubbles and grooves formed in at least two layers of transparent members, and the light confined in the first and second transparent members is reduced. The amount of light emitted from the first and second transparent members is increased, and the luminance of the light emitting diode chip is improved.

光デバイスウエーハの表面側斜視図である。It is a surface side perspective view of an optical device wafer. 図2(A)は透明基板加工工程を示す斜視図、図2(B)〜図2(D)は形成された溝形状を示す断面図である。FIG. 2A is a perspective view showing a transparent substrate processing step, and FIGS. 2B to 2D are cross-sectional views showing the formed groove shape. 図3(A)は表面に第1の方向に伸長する複数の溝を有する第1の透明基板をウエーハの裏面に貼着して第1一体化ウエーハを形成する透明基板貼着工程を示す斜視図、図3(B)は第1一体化ウエーハの斜視図である。FIG. 3A is a perspective view showing a transparent substrate adhering process in which a first transparent substrate having a plurality of grooves extending in the first direction on the surface is adhered to the back surface of the wafer to form a first integrated wafer. FIG. 3 and FIG. 3B are perspective views of the first integrated wafer. 第1の方向及び第1の方向に直交する第2の方向に伸長する複数の溝を表面に有する第1の透明基板をウエーハの裏面に貼着して一体化する透明基板貼着工程を示す斜視図である。The transparent substrate sticking process which sticks and integrates the 1st transparent substrate which has a plurality of slots prolonged on the surface in the 1st direction and the 2nd direction orthogonal to the 1st direction on the back of a wafer is shown. It is a perspective view. 図5(A)は第1一体化ウエーハの裏面に第2の透明基板の表面を貼着して第2一体化ウエーハを形成する様子を示す斜視図、図5(B)は第2一体化ウエーハの斜視図である。FIG. 5A is a perspective view showing a state in which the surface of the second transparent substrate is adhered to the back surface of the first integrated wafer to form the second integrated wafer, and FIG. 5B is the second integrated wafer. It is a perspective view of a wafer. 第2一体化ウエーハをダイシングテープを介して環状フレームで支持する支持工程を示す斜視図である。It is a perspective view which shows the support process which supports a 2nd integrated wafer with an annular frame via a dicing tape. 第2一体化ウエーハを発光ダイオードチップに分割する分割工程を示す斜視図である。It is a perspective view which shows the division | segmentation process which divides | segments a 2nd integrated wafer into a light emitting diode chip. 分割工程終了後の第2一体化ウエーハの斜視図である。It is a perspective view of the 2nd integrated wafer after the end of a division process. 図9(A)〜図9(D)は本発明実施形態に係る発光ダイオードチップの斜視図である。FIG. 9A to FIG. 9D are perspective views of light emitting diode chips according to an embodiment of the present invention.

以下、本発明の実施形態を図面を参照して詳細に説明する。図1を参照すると、光デバイスウエーハ(以下、単にウエーハと略称することがある)11の表面側斜視図が示されている。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a front side perspective view of an optical device wafer 11 (hereinafter sometimes simply referred to as a wafer) 11.

光デバイスウエーハ11は、サファイア基板13上に窒化ガリウム(GaN)等のエピタキシャル層(積層体層)15が積層されて構成されている。光デバイスウエーハ11は、エピタキシャル層15が積層された表面11aと、サファイア基板13が露出した裏面11bとを有している。   The optical device wafer 11 is configured by laminating an epitaxial layer (laminated body layer) 15 such as gallium nitride (GaN) on a sapphire substrate 13. The optical device wafer 11 has a front surface 11a on which an epitaxial layer 15 is stacked and a back surface 11b on which the sapphire substrate 13 is exposed.

ここで、本実施形態の光デバイスウエーハ11では、結晶成長用基板としてサファイア基板13を採用しているが、サファイア基板13に替えGaN基板又はSiC基板等を採用するようにしてもよい。   Here, in the optical device wafer 11 of the present embodiment, the sapphire substrate 13 is employed as the crystal growth substrate. However, a GaN substrate or a SiC substrate may be employed instead of the sapphire substrate 13.

積層体層(エピタキシャル層)15は、電子が多数キャリアとなるn型半導体層(例えば、n型GaN層)、発光層となる半導体層(例えば、InGaN層)、正孔が多数キャリアとなるp型半導体層(例えば、p型GaN層)を順にエピタキシャル成長させることにより形成される。   The stacked body layer (epitaxial layer) 15 includes an n-type semiconductor layer (for example, an n-type GaN layer) in which electrons are majority carriers, a semiconductor layer (for example, an InGaN layer) that is a light emitting layer, and a p in which holes are majority carriers. It is formed by epitaxially growing a type semiconductor layer (for example, a p-type GaN layer) in this order.

サファイア基板13は例えば100μmの厚みを有しており、積層体層15は例えば5μmの厚みを有している。積層体層15に複数のLED回路19が格子状に形成された複数の分割予定ライン17によって区画されて形成されている。ウエーハ11は、LED回路19が形成された表面11aと、サファイア基板13が露出した裏面11bとを有している。   The sapphire substrate 13 has a thickness of 100 μm, for example, and the laminate layer 15 has a thickness of 5 μm, for example. A plurality of LED circuits 19 are defined on the laminate layer 15 by a plurality of division lines 17 formed in a lattice pattern. The wafer 11 has a front surface 11a on which the LED circuit 19 is formed and a back surface 11b on which the sapphire substrate 13 is exposed.

本発明実施形態の発光ダイオードチップの製造方法によると、まず図1に示すような光デバイスウエーハ11を準備するウエーハ準備工程を実施する。また、図2(A)及び図5に示すような内部に複数の気泡が形成された第1の透明基板21と内部に複数の気泡29Aが形成された第2の透明基板21Aとを準備する透明基板準備工程を実施する。   According to the light emitting diode chip manufacturing method of the embodiment of the present invention, first, a wafer preparation step for preparing an optical device wafer 11 as shown in FIG. 1 is performed. Also, a first transparent substrate 21 having a plurality of bubbles formed therein and a second transparent substrate 21A having a plurality of bubbles 29A formed therein are prepared as shown in FIGS. A transparent substrate preparation step is performed.

ウエーハ及び透明基板準備工程を実施した後、ウエーハ11の裏面11bに貼着する第1の透明基板21の表面又は裏面、或いは第1の透明基板21の裏面に貼着する第2の透明基板21Aの表面又は裏面にLED回路19に対応して複数の溝を形成する透明基板加工工程を実施する。この透明基板加工工程は、例えば、よく知られた切削装置を用いて実施する。   After performing the wafer and transparent substrate preparation step, the second transparent substrate 21 </ b> A that is adhered to the front surface or the rear surface of the first transparent substrate 21 that is adhered to the rear surface 11 b of the wafer 11 or the rear surface of the first transparent substrate 21. A transparent substrate processing step for forming a plurality of grooves corresponding to the LED circuit 19 on the front surface or the back surface of the substrate is performed. This transparent substrate processing step is performed using, for example, a well-known cutting device.

図2(A)に示すように、切削装置の切削ユニット10は、スピンドルハウジング12と、スピンドルハウジング12中に回転可能に挿入された図示しないスピンドルと、スピンドルの先端に装着された切削ブレード14とを含んでいる。   As shown in FIG. 2A, the cutting unit 10 of the cutting apparatus includes a spindle housing 12, a spindle (not shown) rotatably inserted into the spindle housing 12, and a cutting blade 14 attached to the tip of the spindle. Is included.

切削ブレード14の切り刃は、例えば、ダイヤモンド砥粒をニッケルメッキで固定した電鋳砥石で形成されており、その先端形状は三角形状、四角形状、又は半円形状をしている。   The cutting blade of the cutting blade 14 is formed of, for example, an electroforming grindstone in which diamond abrasive grains are fixed by nickel plating, and the tip shape thereof is triangular, quadrangular, or semicircular.

切削ブレード14の概略上半分はブレードカバー(ホイールカバー)16で覆われており、ブレードカバー16には切削ブレード14の奥側及び手前側に水平に伸長する一対の(1本のみ図示)クーラーノズル18が配設されている。   The upper half of the cutting blade 14 is covered with a blade cover (wheel cover) 16, and the blade cover 16 is a pair of cooler nozzles (only one is shown) extending horizontally toward the back side and the near side of the cutting blade 14. 18 is arranged.

第1の透明基板21の表面21aに複数の溝23を形成する透明基板加工工程では、第1の透明基板21を図示しない切削装置のチャックテーブルで吸引保持する。そして、切削ブレード14を矢印R方向に高速回転させながら第1の透明基板21の表面21aに所定深さ切り込み、図示しないチャックテーブルに保持された第1の透明基板21を矢印X1方向に加工送りすることにより、第1の方向に伸長する溝23を切削により形成する。   In the transparent substrate processing step of forming the plurality of grooves 23 on the surface 21a of the first transparent substrate 21, the first transparent substrate 21 is sucked and held by a chuck table of a cutting device (not shown). Then, a predetermined depth is cut into the surface 21a of the first transparent substrate 21 while rotating the cutting blade 14 at a high speed in the direction of arrow R, and the first transparent substrate 21 held on a chuck table (not shown) is processed and fed in the direction of arrow X1. Thus, the groove 23 extending in the first direction is formed by cutting.

第1の透明基板21を矢印X1方向に直交する方向にウエーハ11の分割予定ライン17のピッチずつ割り出し送りしながら、第1の透明基板21の表面21aを切削して、図3に示すように、第1の方向に伸長する複数の溝23を次々と形成する。   As shown in FIG. 3, the surface 21a of the first transparent substrate 21 is cut while the first transparent substrate 21 is indexed and fed in the direction orthogonal to the arrow X1 direction by the pitch of the division lines 17 of the wafer 11. A plurality of grooves 23 extending in the first direction are formed one after another.

図3(A)に示すように、第1の透明基板21の表面21aに形成する複数の溝23は一方向にのみ伸長する形態であってもよいし、或いは、図4に示すように、第1の方向及び該第1の方向に直交する第2の方向に伸長する複数の溝23を第1の透明基板21の表面21aに形成するようにしてもよい。   As shown in FIG. 3A, the plurality of grooves 23 formed on the surface 21a of the first transparent substrate 21 may be extended only in one direction, or as shown in FIG. A plurality of grooves 23 extending in the first direction and the second direction orthogonal to the first direction may be formed on the surface 21 a of the first transparent substrate 21.

第1の透明基板21の表面21aに形成する溝は、図2(B)に示すような断面三角形状の溝23、又は図2(C)に示すような断面四角形状の溝23A、又は図2(D)に示すような断面半円形状の溝23Bの何れであってもよい。   The groove formed on the surface 21a of the first transparent substrate 21 is a groove 23 having a triangular cross section as shown in FIG. 2B, or a groove 23A having a square cross section as shown in FIG. Any of the grooves 23B having a semicircular cross section as shown in FIG.

第1の透明基板21及び第2の透明基板21Aは、透明樹脂、光学ガラス、サファイア、透明セラミックスの何れかから形成される。本実施形態では、光学ガラスに比べて耐久性のあるポリカーボネイト、アクリル等の透明樹脂から第1の透明基板21及び第2の透明基板21Aを形成した。尚、溝を形成する方法として、サンドブラスト、エッチング、レーザーを用いてもよい。   The first transparent substrate 21 and the second transparent substrate 21A are formed of any one of transparent resin, optical glass, sapphire, and transparent ceramics. In the present embodiment, the first transparent substrate 21 and the second transparent substrate 21A are formed from a transparent resin such as polycarbonate and acrylic that are more durable than optical glass. As a method for forming the groove, sand blasting, etching, or laser may be used.

上述した実施形態では、第1の透明基板21の表面21aに複数の溝23,23A,23Bを形成しているが、この実施形態に替えて、第1の透明基板21の裏面21bに複数の溝23,23A,23Bを形成するようにしてもよい。   In the embodiment described above, a plurality of grooves 23, 23 </ b> A, 23 </ b> B are formed on the front surface 21 a of the first transparent substrate 21. Instead of this embodiment, a plurality of grooves are formed on the back surface 21 b of the first transparent substrate 21. The grooves 23, 23A, and 23B may be formed.

或いは、第1の透明基板21の表面及び裏面には何ら加工を施すことなく、第2の透明基板21Aの表面21a又は裏面21bにウエーハ11の各LED回路19に対応して複数の溝23,23A,23Bを形成するようにしてもよい。   Alternatively, a plurality of grooves 23 corresponding to each LED circuit 19 of the wafer 11 are formed on the front surface 21a or the back surface 21b of the second transparent substrate 21A without performing any processing on the front surface and the back surface of the first transparent substrate 21. 23A and 23B may be formed.

透明基板加工工程を実施した後、ウエーハ11の裏面11bに第1の透明基板21の表面21aを貼着すると共に第1の透明基板21の裏面21bに第2の透明基板21Aの表面21aを貼着する透明基板貼着工程を実施する。   After performing the transparent substrate processing step, the front surface 21a of the first transparent substrate 21 is adhered to the rear surface 11b of the wafer 11, and the front surface 21a of the second transparent substrate 21A is adhered to the rear surface 21b of the first transparent substrate 21. The transparent substrate sticking process to wear is implemented.

この透明基板貼着工程では、図3(A)に示すように、表面21aに第1の方向に伸長する複数の溝23が形成された第1の透明基板21の表面に、ウエーハ11の裏面11bを透明接着剤により接着して、図3(B)に示すように、ウエーハ11と第1の透明基板21とを一体化して第1一体化ウエーハ25を形成する。   In this transparent substrate attaching step, as shown in FIG. 3A, the back surface of the wafer 11 is formed on the surface of the first transparent substrate 21 in which a plurality of grooves 23 extending in the first direction are formed on the surface 21a. 11b is bonded with a transparent adhesive, and as shown in FIG. 3B, the wafer 11 and the first transparent substrate 21 are integrated to form a first integrated wafer 25.

代替実施形態として、図4に示すように、第1の透明基板21の表面21aに第1の方向及びこの第1の方向に直交する第2の方向に伸長する複数の溝23を有する第1の透明基板21の表面21aに、ウエーハ11の裏面11bを透明接着剤により接着して、ウエーハ11と第1の透明基板21とを一体化するようにしてもよい。ここで、第1の透明基板21の表面21aに形成した溝23のピッチはウエーハ11の分割予定ライン17のピッチに対応する。   As an alternative embodiment, as shown in FIG. 4, the first surface 21 a of the first transparent substrate 21 has a plurality of grooves 23 extending in a first direction and a second direction orthogonal to the first direction. The wafer 11 and the first transparent substrate 21 may be integrated by bonding the back surface 11b of the wafer 11 to the front surface 21a of the transparent substrate 21 with a transparent adhesive. Here, the pitch of the grooves 23 formed on the surface 21 a of the first transparent substrate 21 corresponds to the pitch of the division lines 17 of the wafer 11.

次いで、図5(A)に示すように、第1一体化ウエーハ25の第1の透明基板21の裏面21bに内部に複数の気泡29Aが形成された第2の透明基板21Aの表面21aを貼着して、図5(B)に示すような第2一体化ウエーハ25Aを形成する。   Next, as shown in FIG. 5A, the surface 21a of the second transparent substrate 21A in which a plurality of bubbles 29A are formed is pasted on the back surface 21b of the first transparent substrate 21 of the first integrated wafer 25. The second integrated wafer 25A as shown in FIG. 5B is formed.

この透明基板貼着工程は、上述した順序に限定されるものではなく、第1の透明基板21の裏面21bに第2の透明基板21Aの表面21aを貼着した後、第1の透明基板21の表面21aをウエーハ11の裏面11bに貼着して第2一体化ウエーハ25Aを形成するようにしてもよい。   This transparent substrate sticking process is not limited to the order mentioned above, but after sticking the surface 21a of the 2nd transparent substrate 21A to the back 21b of the 1st transparent substrate 21, the 1st transparent substrate 21 The front surface 21a may be adhered to the back surface 11b of the wafer 11 to form the second integrated wafer 25A.

透明基板貼着工程を実施した後、図6に示すように、第2一体化ウエーハ25Aの第2の透明基板21Aを外周部が環状フレームFに貼着されたダイシングテープTに貼着してフレームユニットを形成し、第2一体化ウエーハ25AをダイシングテープTを介して環状フレームFで支持する支持工程を実施する。   After carrying out the transparent substrate attaching step, as shown in FIG. 6, the second transparent substrate 21A of the second integrated wafer 25A is attached to a dicing tape T whose outer peripheral portion is attached to the annular frame F. A frame unit is formed, and a supporting step of supporting the second integrated wafer 25A with the annular frame F via the dicing tape T is performed.

支持工程を実施した後、フレームユニットを切削装置に投入し、切削装置で一体化ウエーハ25を切削して個々の発光ダイオードチップに分割する分割工程を実施する。この分割工程について、図7を参照して説明する。   After carrying out the supporting step, the frame unit is put into a cutting device, and the dividing step of cutting the integrated wafer 25 with the cutting device and dividing it into individual light emitting diode chips is carried out. This dividing step will be described with reference to FIG.

分割工程では、第2一体化ウエーハ25AをフレームユニットのダイシングテープTを介して切削装置のチャックテーブル20で吸引保持し、環状フレームFは図示しないクランプでクランプして固定する。   In the dividing step, the second integrated wafer 25A is sucked and held by the chuck table 20 of the cutting device via the dicing tape T of the frame unit, and the annular frame F is clamped and fixed by a clamp (not shown).

そして、切削ブレード14を矢印R方向に高速回転させながら切削ブレード14の先端がダイシングテープTに届くまでウエーハ11の分割予定ライン17に切り込み、クーラーノズル18から切削ブレード14及びウエーハ11の加工点に向かって切削液を供給しつつ、第2一体化ウエーハ25Aを矢印X1方向に加工送りすることにより、ウエーハ11の分割予定ライン17に沿ってウエーハ11及び第1、第2の透明基板21,21Aを切断する切断溝27を形成する。   Then, while rotating the cutting blade 14 in the direction of arrow R at high speed, the cutting blade 14 is cut into the division line 17 of the wafer 11 until the tip of the cutting blade 14 reaches the dicing tape T. From the cooler nozzle 18 to the processing point of the cutting blade 14 and the wafer 11. The second integrated wafer 25A is processed and fed in the direction of the arrow X1 while supplying the cutting fluid toward the wafer 11, and the wafer 11 and the first and second transparent substrates 21 and 21A along the scheduled division line 17 of the wafer 11. A cutting groove 27 for cutting is formed.

切削ユニット10をY軸方向に割り出し送りしながら、第1の方向に伸長する分割予定ライン17に沿って同様な切断溝27を次々と形成する。次いで、チャックテーブル20を90°回転してから、第1の方向に直交する第2の方向に伸長する全ての分割予定ライン17に沿って同様な切断溝27を形成して、図8に示す状態にすることで、第2一体化ウエーハ25Aを図9に示すような発光ダイオードチップ31に分割する。   While indexing and feeding the cutting unit 10 in the Y-axis direction, similar cutting grooves 27 are formed one after another along the planned dividing line 17 extending in the first direction. Next, after the chuck table 20 is rotated by 90 °, similar cutting grooves 27 are formed along all the planned dividing lines 17 extending in the second direction orthogonal to the first direction, as shown in FIG. By setting the state, the second integrated wafer 25A is divided into light-emitting diode chips 31 as shown in FIG.

上述した実施形態では、第2一体化ウエーハ25Aを個々の発光ダイオードチップ31に分割するのに切削装置を使用しているが、ウエーハ11及び透明基板21,21Aに対して透過性を有する波長のレーザービームを分割予定ライン13に沿ってウエーハ11に照射して、ウエーハ11及び透明基板21,21Aの内部に厚み方向に複数層の改質層を形成し、次いで、第2一体化ウエーハ25Aに外力を付与して、改質層を分割起点に第2一体化ウエーハ25Aを個々の発光ダイオードチップ31に分割するようにしてもよい。   In the embodiment described above, the cutting device is used to divide the second integrated wafer 25A into the individual light emitting diode chips 31, but the wavelength of the wavelength having transparency to the wafer 11 and the transparent substrates 21 and 21A. The wafer 11 is irradiated with a laser beam along the division line 13 to form a plurality of modified layers in the thickness direction inside the wafer 11 and the transparent substrates 21 and 21A, and then the second integrated wafer 25A. An external force may be applied to divide the second integrated wafer 25A into the individual light emitting diode chips 31 using the modified layer as a division starting point.

図9(A)に示された発光ダイオードチップ31は、表面にLED回路19を有するLED13Aの裏面に内部に複数の気泡29が形成された第1の透明部材21´が貼着されている。また、第1の透明部材21´の表面に溝23Bが形成されている。更に、第1の透明部材21´の裏面に内部に複数の気泡が形成された第2の透明部材21A´が貼着されている。   The light emitting diode chip 31 shown in FIG. 9A has a first transparent member 21 ′ in which a plurality of bubbles 29 are formed inside attached to the back surface of the LED 13 </ b> A having the LED circuit 19 on the front surface. A groove 23B is formed on the surface of the first transparent member 21 '. Further, a second transparent member 21A ′ having a plurality of bubbles formed therein is adhered to the back surface of the first transparent member 21 ′.

図9(B)に示す発光ダイオードチップ31Aは、表面にLED回路19を有するLED13Aの裏面に内部に複数の気泡が形成された第1の透明部材21´が貼着されている。また、第1の透明部材21´の裏面に溝23Bが形成されている。更に、第1の透明部材21´の裏面に第2の透明部材21A´の表面が貼着されている。   In the light emitting diode chip 31A shown in FIG. 9B, a first transparent member 21 ′ having a plurality of bubbles formed therein is attached to the back surface of the LED 13A having the LED circuit 19 on the front surface. A groove 23B is formed on the back surface of the first transparent member 21 '. Furthermore, the surface of the second transparent member 21A ′ is adhered to the back surface of the first transparent member 21 ′.

図9(C)に示す発光ダイオードチップ31Bは、表面にLED回路19を有するLED13Aの裏面に内部に複数の気泡が形成された第1の透明部材21´が貼着されている。更に、第1の透明部材21´の裏面に第2の透明部材21A´が貼着されている。また、第2の透明部材21A´の表面に溝23Bが形成されている。   In the light emitting diode chip 31B shown in FIG. 9C, a first transparent member 21 ′ having a plurality of bubbles formed therein is attached to the back surface of the LED 13A having the LED circuit 19 on the front surface. Further, a second transparent member 21A ′ is adhered to the back surface of the first transparent member 21 ′. A groove 23B is formed on the surface of the second transparent member 21A ′.

図9(D)に示す発光ダイオードチップ31Cは、表面にLED回路19を有するLED13Aの裏面に内部に複数の気泡が形成された第1の透明部材21´が貼着されている。更に、第1の透明部材21´の裏面に第2の透明部材21A´の表面が貼着されている。また、第2の透明部材21A´の裏面に溝23Bが形成されている。   In a light emitting diode chip 31C shown in FIG. 9D, a first transparent member 21 ′ having a plurality of bubbles formed therein is attached to the back surface of an LED 13A having an LED circuit 19 on the front surface. Furthermore, the surface of the second transparent member 21A ′ is adhered to the back surface of the first transparent member 21 ′. A groove 23B is formed on the back surface of the second transparent member 21A ′.

従って、図9(A)に示す発光ダイオードチップ31では、第1の透明部材21´の表面に溝23Bが形成されているため、第1の透明部材21´の表面積が増大する。更に、発光ダイオードチップ31のLED回路19から出射され第1の透明部材21´に入射する光の一部は溝23B部分で屈折されてから第1の透明部材21´内に進入する。   Therefore, in the light emitting diode chip 31 shown in FIG. 9A, the groove 23B is formed on the surface of the first transparent member 21 ′, so that the surface area of the first transparent member 21 ′ increases. Furthermore, a part of the light emitted from the LED circuit 19 of the light emitting diode chip 31 and incident on the first transparent member 21 ′ is refracted by the groove 23 B portion and then enters the first transparent member 21 ′.

よって、第1の透明部材21´及び第2の透明部材21A´から外部に屈折して光が出射する際、第1及び第2の透明部材21´,21A´と空気層との界面での入射角が臨界角以上となる光の割合が減少し、第1、第2の透明部材21´,21A´から出射される光の量が増大し、発光ダイオードチップ31の輝度が向上する。   Therefore, when light is refracted to the outside from the first transparent member 21 ′ and the second transparent member 21A ′, the light is emitted at the interface between the first and second transparent members 21 ′ and 21A ′ and the air layer. The proportion of light whose incident angle is greater than or equal to the critical angle is reduced, the amount of light emitted from the first and second transparent members 21 ′ and 21 A ′ is increased, and the luminance of the light emitting diode chip 31 is improved.

図9(B)〜図9(D)に示す発光ダイオードチップ31A,31B,31Cについても、図9(A)に示す発光ダイオードチップ31と同様な作用効果を奏する。   The light emitting diode chips 31A, 31B, and 31C shown in FIGS. 9B to 9D also have the same effects as the light emitting diode chip 31 shown in FIG.

10 切削ユニット
11 光デバイスウエーハ(ウエーハ)
13 サファイア基板
14 切削ブレード
15 積層体層
17 分割予定ライン
19 LED回路
21 第1の透明基板
21´ 第1の透明部材
21A 第2の透明基板
21A´ 第2の透明部材
23,23A,23B 溝
25 第1一体化ウエーハ
25A 第2一体化ウエーハ
27 切断溝
29 気泡
31,31A,31B,31C 発光ダイオードチップ
10 Cutting unit 11 Optical device wafer (wafer)
13 Sapphire substrate 14 Cutting blade 15 Laminate layer 17 Scheduled division line 19 LED circuit 21 1st transparent substrate 21 ′ 1st transparent member 21A 2nd transparent substrate 21A ′ 2nd transparent members 23, 23A, 23B Groove 25 First integrated wafer 25A Second integrated wafer 27 Cutting groove 29 Air bubbles 31, 31A, 31B, 31C Light emitting diode chip

Claims (5)

発光ダイオードチップの製造方法であって、
結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路が形成されたウエーハを準備するウエーハ準備工程と、
内部に複数の気泡が形成された第1の透明基板又は内部に複数の気泡が形成された第2の透明基板の少なくともどちらか一方の表面又は裏面にLED回路に対応して複数の溝を形成する透明基板加工工程と、
該透明基板加工工程を実施した後、該第1の透明基板の表面をウエーハの裏面に貼着すると共に該第2の透明基板の表面を該第1の透明基板の裏面に貼着して一体化ウエーハを形成する透明基板貼着工程と、
該透明基板貼着工程を実施した後、該ウエーハを該分割予定ラインに沿って該第1及び第2の透明基板と共に切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、
を備えたことを特徴とする発光ダイオードチップの製造方法。
A method of manufacturing a light emitting diode chip,
Each of the regions has a laminate layer in which a plurality of semiconductor layers including a light emitting layer are formed on a transparent substrate for crystal growth, and is divided into a plurality of division lines intersecting each other on the surface of the laminate layer. A wafer preparation step of preparing a wafer on which an LED circuit is formed;
A plurality of grooves corresponding to the LED circuit are formed on the front surface or the back surface of at least one of the first transparent substrate having a plurality of bubbles formed therein or the second transparent substrate having a plurality of bubbles formed therein. Transparent substrate processing step to
After carrying out the transparent substrate processing step, the surface of the first transparent substrate is adhered to the back surface of the wafer and the surface of the second transparent substrate is adhered to the back surface of the first transparent substrate. A transparent substrate pasting process for forming a modified wafer;
A dividing step of dividing the integrated wafer into individual light-emitting diode chips by cutting the wafer together with the first and second transparent substrates along the division line after the transparent substrate attaching step; ,
A method for producing a light-emitting diode chip, comprising:
該透明基板加工工程で形成される前記溝の断面形状は三角形状、四角形状、半円形状の何れかである請求項1記載の発光ダイオードチップの製造方法。   2. The method of manufacturing a light-emitting diode chip according to claim 1, wherein a cross-sectional shape of the groove formed in the transparent substrate processing step is any one of a triangular shape, a square shape, and a semicircular shape. 該透明基板加工工程において、前記溝は切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成される請求項1記載の発光ダイオードチップの製造方法。   2. The method of manufacturing a light-emitting diode chip according to claim 1, wherein in the transparent substrate processing step, the groove is formed by any one of a cutting blade, etching, sand blast, and laser. 該第1及び第2の透明基板は、透明セラミックス、光学ガラス、サファイア、透明樹脂の何れかで形成され、該透明基板貼着工程において該第1の透明基板は透明接着剤を使用してウエーハに接着され、該第2の透明基板は透明接着剤を使用して該第1の透明基板に貼着される請求項1記載の発光ダイオードチップの製造方法。   The first and second transparent substrates are formed of any one of transparent ceramics, optical glass, sapphire, and transparent resin, and in the transparent substrate pasting process, the first transparent substrate is a wafer using a transparent adhesive. The method for manufacturing a light-emitting diode chip according to claim 1, wherein the second transparent substrate is bonded to the first transparent substrate using a transparent adhesive. 発光ダイオードチップであって、
表面にLED回路が形成された発光ダイオードと、
該発光ダイオードの裏面に貼着された内部に複数の気泡が形成された第1の透明部材と、
該第1の透明部材の裏面に貼着された内部に複数の気泡が形成された第2の透明部材と、
を備え、
該第1の透明部材又は該第2の透明部材の少なくともどちらか一方の表面又は裏面に溝が形成されている発光ダイオードチップ。
A light emitting diode chip,
A light emitting diode having an LED circuit formed on the surface;
A first transparent member in which a plurality of bubbles are formed in the inside attached to the back surface of the light emitting diode;
A second transparent member in which a plurality of bubbles are formed in the inside attached to the back surface of the first transparent member;
With
A light emitting diode chip in which a groove is formed on the front surface or the back surface of at least one of the first transparent member and the second transparent member.
JP2017041315A 2017-03-06 2017-03-06 Light emitting diode chip manufacturing method and light emitting diode chip Pending JP2018148016A (en)

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