JP2018145871A - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly measure an edge time of an input pulse.SOLUTION: An electronic control device 1 includes a timer processor 9 notifying interruption request according to input of an input pulse, a main processor 8 executing interruption processing when the interruption request is notified by the timer processor 9, and a shared storage portion 10 to which the main processor 8 and the timer processor 9 can access. A TPU 9 divides an edge time of the input pulse into an on-edge time and an off-edge time, and stores the same in a SDM 10.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic control device.

  In order to improve exhaust gas regulations and fuel efficiency in recent years, for example, in diesel engines, there is an increasing demand for multistage injection that performs many injections in a short period of time. In order to precisely control multi-stage injection, an electronic control device microcomputer (hereinafter referred to as a microcomputer) that controls fuel injection feeds back an injection pulse as an input pulse, captures the edge time of the injection pulse, and interrupts it. Process. As the number of injections per unit period increases, the intervals between the edges of the injection pulses become shorter, so the interval between interrupt processing becomes shorter and the processing load increases with a single processor. Under such circumstances, a configuration using a microcomputer in which a processor for arithmetic processing and a processor for event processing are separately provided is provided (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 4-121442

  Recently, there is an increasing demand for multi-stage injection in which more injections are performed in a shorter period. For example, in a conventional configuration using a solenoid injector, an on-time and an off-time both require an injection pulse of 100 [μs] or more, whereas in a recent configuration using, for example, a piezo injector, an on-time of 70 [Μs], and an injection pulse having an off time of 100 [μs] is requested. Further, in the next generation configuration, it is assumed that an injection pulse having an on time of 70 [μs] and an off time of 50 [μs] is required.

  In a configuration that executes interrupt processing, interrupt processing does not necessarily start at the timing when an edge occurs, but interrupt processing starts after the timing at which an edge occurs due to other interrupt factors or interrupt prohibition processing. In some cases, an interrupt delay may occur. Therefore, in the configuration in which the edge of the input pulse with a short edge interval is captured and interrupt processing is performed, if the interrupt delay time becomes longer than the on-time of the input pulse, an off-edge occurs before the on-edge interrupt processing starts. become. As a result, the edge time is rewritten due to the occurrence of the off-edge, the edge time cannot be accurately measured, and a defect occurs due to the inability to accurately measure the edge time. Such a problem is not limited to the electronic control device that inputs the injection pulse as described above, but may occur if the electronic control device inputs an input pulse with a short edge interval.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to accurately measure the edge time of the input pulse, and to prevent occurrence of problems caused by the inability to accurately measure the edge time. It is another object of the present invention to provide an electronic control device that can be avoided.

  According to the first aspect of the present invention, the timer processor (9) notifies the interrupt request in response to the input pulse being input. When the interrupt request is notified from the timer processor, the main processor (8) executes interrupt processing. The shared storage unit (10) can be accessed by the main processor and the timer processor. The timer processor classifies the edge time of the input pulse into an on-edge time and an off-edge time and stores them in the shared storage unit.

  If the interrupt delay time becomes longer than the on-time of the input pulse and an off-edge occurs before the on-edge interrupt processing is started, the edge time is rewritten due to the occurrence of the off-edge. In response to such rewriting of the edge time, the edge time of the input pulse is divided into an on-edge time and an off-edge time and stored in the shared storage unit. By referring to the on-edge time and off-edge time stored separately, it is possible to accurately measure the edge time of the input pulse, and to prevent the occurrence of problems caused by the inability to accurately measure the edge time. It can be avoided.

Functional block diagram showing an embodiment Timing chart (1) Timing chart (2) Timing chart (part 3) flowchart Timing chart (4) Timing chart (part 5)

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The electronic control device 1 is a device that controls fuel injection from an injector 3 to an engine 2 (corresponding to an internal combustion engine) of a vehicle. The electronic control unit 1 is electrically connected to various sensors (not shown), and appropriately controls various types of information included in various sensor signals input from the various sensors to control fuel injection. The engine 2 is, for example, a diesel engine, a gasoline engine, or a gas engine having a plurality of cylinders.

  The electronic control device 1 includes a microcomputer 4, an output circuit 5 (corresponding to an output unit), an input circuit 6, and an injection IC 7. The microcomputer 4 is a microcomputer in which a processor for arithmetic processing and a processor for event processing are provided separately, and the fuel processor controls the fuel injection by calculating the fuel injection timing, the injection amount, and the like. When an output command is input from the microcomputer 4, the output circuit 5 outputs an injection pulse (corresponding to an input pulse) for controlling fuel injection to the injection IC 7. The injection pulse output from the output circuit 5 is input to the injection IC 7 and also input to the microcomputer 4 via the input circuit 6. That is, the microcomputer 4 feeds back the injection pulse output from the output circuit 5. The injection IC 7 supplies an injector current to the injector 3 when an injection pulse is input from the output circuit 5. When an injector current is supplied from the injection IC 7, the injector 3 opens an injection valve by an actuator (not shown) and injects fuel into the engine 2. The injection IC 7 switches the amount of fuel injected from the injector 3 to the engine 2 by switching the current value of the injector current supplied to the injector 3.

  A method for measuring the edge time of the injection pulse in the configuration in which the injection pulse is fed back in this way will be described. In the configuration in which the processor for arithmetic processing executes interrupt processing at the timing when the edge of the injection pulse occurs, the interrupt processing does not necessarily start at the timing when the edge occurs, but it balances with other interrupt factors and interrupt prohibition processing, etc. As a result, the interrupt process may be delayed from the timing when the edge occurs, and an interrupt delay may occur.

  Here, if the number of injections per unit period is relatively small, that is, the on-time of the injection pulse is designed to be relatively long, and the interrupt delay time is shorter than the on-time of the injection pulse, there is no concern about any problems. . That is, as shown in FIG. 2, if the on time and the off time of the injection pulse are both 100 [μs] or more and the maximum interrupt delay time which is the maximum value of the interrupt delay time is 100 [μs], the port level And edge time can be obtained by interrupt processing, so that the edge time can be accurately measured. Note that the maximum interrupt delay time is a time that is defined so that no interrupt delay occurs even in the maximum high load state. Also, the on-edge interrupt processing can be performed by the processor for arithmetic processing so that an on-event can be notified from the driver to the application. The arithmetic processing processor can execute internal processing by executing off-edge interrupt processing. It is possible to notify the off event from the driver to the application.

  However, there are relatively many requests for the number of injections per unit period, that is, the on-time of the injection pulse is designed to be relatively short, and when the interrupt delay time becomes longer than the on-time of the injection pulse, on-edge interrupt processing is started. An off-edge occurs before the failure, and there are concerns about the following problems. That is, as shown in FIG. 3, if the on time of the injection pulse is 70 [μs], the off time is 100 [μs], and the maximum interrupt delay time is 100 [μs], the port is generated due to the occurrence of an off edge. Since the level is reversed and the edge time is rewritten, the edge time cannot be measured accurately. In addition, although the on-edge interrupt processing can be performed by the processor for arithmetic processing, the on-event notification can be performed, but the processor for arithmetic processing does not execute the off-edge interrupt processing, and omission of the off-edge interrupt processing occurs. Therefore, off event notification cannot be performed.

  Considering this point, the microcomputer 4 separately manages the on-edge time and the off-edge time of the injection pulse. That is, the microcomputer 4 includes a CPU 8 (corresponding to a main processor) as the above-described arithmetic processing processor, a TPU 9 (corresponding to a timer processor) as the above-described event processing processor, and an SDM 10 (in the shared storage unit). And I / O 10, which are interconnected via an internal bus 11. The TPU 9 is a processor having higher responsiveness than the CPU 8 and operates asynchronously with the CPU 8.

  The TPU 9 has a register 13 that can hold only one edge time. When the injection pulse output from the output circuit 5 is fed back via the input circuit 6 and the occurrence of an edge of the input injection pulse is detected, The time when the occurrence of the edge is detected is written in the register 13 as the edge time. That is, when the TPU 9 detects the occurrence of the on-edge of the injection pulse, the time is written in the register 13 as the on-edge time, and when the occurrence of the off-edge of the injection pulse is detected, the TPU 9 writes the time in the register 13 as the off-edge time. In this case, since the register 13 can hold only one edge time, the TPU 9 rewrites the edge time of the register 13 every time it detects the occurrence of an injection pulse edge.

  The CPU 8 is a processor for arithmetic processing as described above, and executes interrupt processing when an interrupt request is notified from the TPU 9. The CPU 8 executes an interrupt process to notify an event from the driver to the application. Further, the CPU 8 can access a first RAM 14 that can hold the number of edges described later and a second RAM 15 that can hold the edge direction. The SDM 10 is accessible by both the CPU 8 and the TPU 9 and stores various types of edge information. That is, the SDM 10 includes an on-edge time storage area 16a for storing on-edge time, an off-edge time storage area 16b for storing off-edge time, and an edge count storage area 16c for storing the number of edges.

  When the TPU 9 detects the occurrence of the edge of the injection pulse as described above, the TPU 9 operates as follows in addition to writing the time at which the occurrence of the edge is detected as the edge time in the register 13. As shown in FIG. 4, the TPU 9 executes a timer processor process every time it detects the occurrence of an on edge or an off edge of an injection pulse (t1 to t4). The execution time of the timer processor process is sufficiently shorter than the on time of the injection pulse. When the TPU 9 detects the occurrence of an on-edge of the injection pulse (t1), it starts timer processor processing, refers to the edge time held in the register 13 during execution of the timer processor processing, and determines the referenced edge time. Write to the on-edge time storage area 16a, increment the number of edges held in the edge number storage area 16c, and end the timer processor process (t11). When the TPU 9 detects the occurrence of an on-edge of the injection pulse, the TPU 9 notifies the CPU 8 of an on-edge interruption request. When an on-edge interrupt request is notified from the TPU 9, the CPU 8 executes on-edge interrupt processing, and internally notifies the application of an on event from the driver.

  Subsequently, when the TPU 9 detects the occurrence of the off-edge of the injection pulse (t2), it starts the timer processor process, and refers to the edge time held in the register 13 during the timer processor process. The edge time is written in the off-edge time storage area 16b, the number of edges held in the edge number storage area 16c is incremented, and the timer processor process is terminated (t12). When the TPU 9 detects the occurrence of an off edge of the injection pulse, the TPU 9 notifies the CPU 8 of an off edge interrupt request. When an off-edge interrupt request is notified from the TPU 9, the CPU 8 executes an off-edge interrupt process, and notifies an off event from the driver to the application. Each time the TPU 9 detects the occurrence of an on edge or an off edge of the injection pulse, the TPU 9 repeats the above processing (t3, t13, t4, t14,...).

Next, the operation of the above configuration will be described with reference to FIGS.
When an interrupt request is notified from the TPU 9, the CPU 8 starts interrupt processing and acquires edge information stored in the SDM 10 (S1). In this case, the edge information acquired by the CPU 8 from the SDM 10 is stored in the on-edge time stored in the on-edge time storage area 16a, the off-edge time stored in the off-edge time storage area 16b, and the edge count storage area 16c. And the number of edges. The CPU 8 reads the number of edges held in the first RAM 14, calculates the difference between the number of read edges and the number of edges acquired from the SDM 10, and is generated in the period from the previous interrupt process to the current interrupt process The difference in the number of edges obtained is calculated (S2). Further, the CPU 8 holds the number of edges acquired from the SDM 10 in the first RAM 14 as the number of edges in the current interrupt process (S3).

  Here, if the interrupt delay time is shorter than the on-time of the injection pulse and the off-edge has not yet occurred when the on-edge interrupt processing is started, the edge that occurred during the period from the previous interrupt processing to the current interrupt processing The difference in the number of times is “1”. On the other hand, if the interrupt delay time is longer than the on-time of the injection pulse and an off-edge has already occurred when the on-edge interrupt processing is started, the edge that occurred during the period from the previous interrupt processing to the current interrupt processing The difference in the number of times is “2”.

  The CPU 8 determines whether or not the calculated difference is “1”, and determines whether or not interruption processing is lost (S4). If the CPU 8 determines that the calculated difference is “1” and determines that no interruption in interrupt processing occurs (S4: YES), the CPU 8 reads the edge direction held in the second RAM 15 and reads the read edge. Event notification to the processor for event processing is performed according to the direction (S5). That is, the CPU 8 issues an on event notification if the edge direction read from the second RAM 15 is the on direction, and performs an off event notification if the edge direction read from the second RAM 15 is the off direction. The CPU 8 reverses the edge direction held in the second RAM 15 and prepares so that event notification in the direction opposite to that of the current interrupt process can be performed in the next interrupt process (S6), and ends the interrupt process.

  As described above, when the CPU 8 determines that the calculated difference is “1” and determines that no interruption of interruption processing occurs, the CPU 8 performs event notification only once and ends the interruption processing. That is, as shown in FIG. 6, the on time of the injection pulse is 70 [μs], the off time is 100 [μs], the interrupt delay time is 70 [μs] or less, and the interrupt delay time is the injection pulse. If it is shorter than the on-time, the CPU 8 starts the on-edge interrupt process before the injection pulse off-edge occurs (t21), so it is determined that no interruption of the interrupt process occurs, and an event notification is sent in the interrupt process. Do it only once.

  On the other hand, when the CPU 8 determines that the calculated difference is not “1” and determines that the interruption process is lost (S4: NO), the CPU 8 determines whether or not the calculated difference is “2”. It is determined whether or not the omission occurs only once (S7). If the CPU 8 determines that the calculated difference is “2” and determines that the interruption process is missed only once (S7: YES), the CPU 8 reads the edge direction held in the second RAM 15 and reads it. Event notification is performed according to the edge direction (S8). Subsequently, the CPU 8 performs event notification according to the edge direction opposite to the read edge direction (S9), and ends the interrupt process.

  As described above, when the CPU 8 determines that the calculated difference is “2” and determines that the interruption of the interruption process occurs only once, the CPU 8 performs the event notification twice and ends the interruption process. In this case, since the CPU 8 performs event notification in two different directions in this case, it is not necessary to reverse the edge direction held in the second RAM 15. That is, as shown in FIG. 7, the CPU 8 has an injection pulse ON time of 70 [μs], an OFF time of 100 [μs], an interrupt delay time of 100 [μs], and an interrupt delay time of If it is longer than the on-time of the injection pulse, the CPU 8 starts the on-edge interrupt processing after the off-edge of the injection pulse occurs (t31), so it is determined that the interruption processing is interrupted only once. Event notification is performed twice in succession. By performing the event notification twice in succession, there is no concern about a problem even if the interruption process is missed only once. If the CPU 8 determines that the calculated difference is not “2” (S7: NO), the CPU 8 determines that there is an influence of noise, and immediately ends the interrupt process.

As described above, according to the present embodiment, the following effects can be obtained.
In the electronic control unit 1, the injection pulse edge time is divided into an on-edge time and an off-edge time and stored in the SDM 10. If the interrupt delay time becomes longer than the on-time of the injection pulse and an off-edge occurs before the on-edge interrupt processing starts, the edge time is rewritten, but the on-edge time and the off-edge time are divided and stored in the SDM 10. Therefore, the on-edge time and off-edge time can be accurately measured by referring to the on-edge time and off-edge time stored separately.

  Further, in the electronic control unit 1, the TPU 9 determines the edge direction of the injection pulse and notifies the CPU 8 of an on-edge or off-edge interrupt request. For example, it can be avoided that the TPU 9 notifies the CPU 8 of an unnecessary interrupt request due to noise or the like, and the processing load on the CPU 8 can be reduced.

  Further, in the electronic control unit 1, when an interrupt request is notified from the TPU 9 to the CPU 8, the CPU 8 acquires the number of edges stored in the SDM 10 and performs event notification based on the on-edge time or the off-edge time. Even if interrupt processing is lost, it is possible to avoid occurrence of problems due to interruption of interrupt processing in advance by dealing with the occurrence of interruption in interrupt processing. Can be done.

  Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

  In this embodiment, although applied to the electronic control apparatus 1 which controls fuel injection, the structure applied to the electronic control apparatus which controls another operation | movement may be sufficient. Further, the configuration is not limited to the configuration applied to the in-vehicle use, but may be the configuration applied to the use other than the in-vehicle usage.

  In the present embodiment, the configuration in which the injection pulse for controlling the fuel injection is feedback-inputted as the input pulse is exemplified. However, for example, the configuration may be such that the pulse output from the sensor is input as the input pulse. In this case, the input circuit 6 that inputs the injection pulse by feedback and the input circuit that inputs the pulse output from the sensor may be the same or different. Further, the pulse output from the sensor may be input via the in-vehicle network or may be input directly without using the in-vehicle network. In addition, the TPU 9 is not limited to the configuration in which the injection pulse or the pulse output from the sensor is input as an input pulse, but may be a configuration in which a pulse generated inside the electronic control device 1 is input as an input pulse, that is, the input circuit is omitted. The configuration that was used may be used.

  In the drawings, 1 is an electronic control unit, 2 is an engine (internal combustion engine), 3 is an injector, 5 is an output circuit (output unit), 6 is an input circuit, 8 is a CPU (main processor), and 9 is a TPU (timer processor). Reference numeral 10 denotes an SDM (shared storage unit).

Claims (5)

A timer processor (9) for notifying an interrupt request in response to an input pulse being input;
When an interrupt request is notified from the timer processor, a main processor (8) that executes interrupt processing;
A shared storage unit (10) accessible by the main processor and the timer processor,
The timer processor is an electronic control device that divides an edge time of an input pulse into an on-edge time and an off-edge time and stores them in the shared storage unit.   The electronic control device according to claim 1, wherein the timer processor determines an edge direction of an input pulse and notifies the main processor of an on-edge or off-edge interrupt request. The timer processor stores the number of edges indicating the number of times the edge of the input pulse has occurred in the shared storage unit,
The main processor, when an on-edge or off-edge interrupt request is notified from the timer processor, acquires the number of edges stored in the shared storage unit, and performs event notification according to the on-edge time or off-edge time. The electronic control device described. An output unit (5) for outputting an injection pulse for controlling fuel injection from the injector (3) to the internal combustion engine (2);
The electronic control device according to any one of claims 1 to 3, wherein the timer processor notifies an interrupt request in response to a feedback input of the injection pulse output from the output unit.   The electronic control device according to any one of claims 1 to 3, wherein the timer processor notifies an interrupt request in response to a pulse output from the sensor being input as an input pulse.

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