JP2018139264A - Optical semiconductor element and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical semiconductor element having a high-mesa embedded structure and a method for manufacturing the optical semiconductor element, which is arranged so that even if layers different in etching rate are present in mesa stripes in embedding pre-processing, removal of damage by side etching suitable for each layer is performed.SOLUTION: A method for manufacturing an optical semiconductor element comprises the steps of: applying a positive type photoresist to a whole wafer surface with high-mesa stripes formed therein; re-exposing the wafer to light with a photomask used in forming the mesa stripes, performing development thereof, and disposing a resist 107 on a side etched portion of an InGaAs contact layer 105 under an insulating film mask 106; and side etching an active layer 102 using an etchant larger, in etching rate, than an etchant used for side etching of the InGaAs contact layer 105. The side wall of the InGaAs contact layer 105 is protected by the resist 107 and as such, the active layer 102 can be side-etched while preventing the erosion to the InGaAs contact layer 105.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a laser optical semiconductor device having a semi-insulating InP buried structure and a method for manufacturing the same.

  A semi-insulating InP embedded laser having a high-mesa ridge stripe processed into a mesa shape by dry etching at least up to the active layer, and having a current blocking structure by growing a semi-insulating InP embedded layer on the side. SIBH-LD) is excellent in terms of low threshold current operation and high efficiency, and is used as a light source for 1.55 μm band optical communication.

  FIG. 9A shows a cross section of the mesa stripe before being embedded and processed by dry etching. The semi-insulating InP buried laser having a mesa stripe cross section shown in FIG. 9A has an active layer 502, an InP clad layer 503 on the InP substrate 501, and a band gap energy between the clad layer material and the contact layer material. An intermediate layer 504, a contact layer 505, and an insulating film mask 506 are stacked. Thereafter, the insulating film mask 506 is processed into a stripe-shaped dry etching mask, and a mesa stripe as shown in FIG. 9A is formed by dry etching. Thereafter, in order to remove the damaged layer due to dry etching, light etching (pre-embedding treatment) of the active layer 502 is performed. This is indispensable in terms of laser characteristics and reliability. As an embedding pretreatment, a 1.55 μm band LD in which light etching using a sulfuric acid-based etching solution (piranha), which is an aqueous solution in which sulfuric acid and hydrogen peroxide water are mixed, oscillates in a 1.55 μm band is common.

Japanese Patent Laid-Open No. 5-82891

  On the other hand, in the 1.3 μm band LD, when InGaAs having the same low contact resistivity as that of the 1.55 μm band is used as the contact layer, the contact layer in contact with the insulating film mask 506 when piranha etching for pre-filling processing is performed. The InGaAs etching rate of 505 is much faster than that of the 1.3 μm band active layer 502, and the InGaAs in the contact layer 505 disappears during the etching of the active layer 502.

  As a method for avoiding this, bromine (Br), which is an etching solution in which an InGaAsP layer having a 1.3 μm band composition is used as a contact layer to deposit a metal to form an alloy electrode and the etching rate does not depend on the type of the semiconductor layer. There is a method of pre-embedding treatment using a system etching solution.

  In the former case, the contact resistance to the 1.3 μm band composition InGaAsP layer is larger than that to the InGaAs layer, resulting in an increase in series resistance. In addition, since a non-alloy electrode cannot be applied, there is a concern that diffusion of alloy electrode metal to the active layer, local stress due to alloy spikes, etc. on the active layer may be adversely affected.

  On the other hand, in the latter case, in the bromine (Br) -based etching solution, the progress of etching is determined by the supply rate of the solution, and the supply amount of the upper part of the mesa is higher than that of the lower part of the mesa. It is etched more. When etching the active layer 502 having a sufficient thickness, the cladding layer 503, the intermediate layer 504, and the contact layer 505 in the upper part of the mesa are etched more than the active layer 502 in the lower part of the mesa as shown in FIG. 9B. As a result, the width of the cladding layer 503, the intermediate layer 504, and the contact layer 505 is significantly narrower than that of the active layer, the resistance of the cladding layer 503 and the contact resistance are increased, the laser series resistance is increased, and the laser characteristics are deteriorated. Problem arises.

  The present invention has been made in view of such problems, and an object of the present invention is a 1.3 μm-band optical semiconductor device having a high-mesa buried structure and a method for manufacturing the same, which are etched during pre-embedding processing. An object of the present invention is to provide an optical semiconductor element in which damage removal by appropriate side etching is performed on each layer even when layers having different rates exist in the mesa stripe, and a manufacturing method thereof.

  In order to solve the above-described problems, the present invention provides a method for manufacturing an optical semiconductor device, wherein a first layered structure in which at least an active layer, a cladding layer, an intermediate layer, and a contact layer are sequentially stacked on a substrate is formed. A second step of forming a mesa stripe by performing dry etching on the laminated structure; and a third step of performing side etching on the contact layer by exposing a side surface of the mesa stripe to a first etching solution. A fourth step of protecting the side-etched portion, and a fifth step of side-etching the active layer and the intermediate layer by exposing a side surface of the mesa stripe to a second etching solution. A step and a sixth step of forming a semi-insulating InP buried layer on the side surface of the mesa stripe are sequentially performed.

  The invention according to claim 2 is a method of manufacturing an optical semiconductor device, wherein the first step of forming a laminated structure in which at least an active layer, a cladding layer, an intermediate layer, and a contact layer are sequentially laminated on a substrate; A second step of forming a stripe pattern of the contact layer; a third step of forming a mask for mesa stripe processing on the exposed surface of the contact layer and the intermediate layer around the contact layer; After the step, a fourth step of forming a mesa stripe wider than the stripe pattern by dry etching, a fifth step of performing side etching by exposing the side surface of the mesa stripe to an etching solution, A sixth step of forming a semi-insulating InP buried layer on the side surface of the mesa stripe is sequentially performed.

  According to a third aspect of the present invention, in the method for manufacturing an optical semiconductor device according to the first or second aspect, the first step of forming the stacked structure includes the length of the mesa stripe as the active layer. And a seventh step of forming an active layer of a 1.3 μm band laser of InGaAsP composition and an active layer of an EA modulator of InAlGaAs composition butt-jointed in a column in the direction.

  The invention according to claim 4 is an optical semiconductor element having a mesa stripe in which an active layer, an InP clad layer, an InGaAsP intermediate layer, and an InGaAs contact layer are sequentially stacked on an InP substrate, wherein the active layer Is narrower than the width of the InP cladding layer, the InP cladding layer is wider than the InGaAsP intermediate layer, and the InGaAsP intermediate layer is wider than the InGaAs contact layer.

  According to a fifth aspect of the present invention, in the optical semiconductor device according to the fourth aspect, the active layer has an InGaAsP composition, or an active layer having an InGaAsP composition and an active layer having an InAlGaAs composition are formed in the same stripe. It is characterized by being.

  The present invention provides a light source with a modulator in which a 1.3 μm band semiconductor laser having an InGaAsP composition and an EA absorption layer having a 1.3 μm band wavelength having an InAlGaAs composition are integrated, and a non-alloy electrode can be used as a contact layer. Therefore, an optical semiconductor element with low resistance and high reliability can be obtained.

(A)-(f) is a figure which shows the manufacturing process of the optical semiconductor element which concerns on Embodiment 1 of this invention. (A)-(g) is a figure which shows the manufacturing process of the optical semiconductor element which concerns on Embodiment 2 of this invention. (A)-(f) is sectional drawing perpendicular | vertical to the stripe direction of LD part which shows the manufacturing process of the optical semiconductor element which concerns on Embodiment 3 of this invention. (A)-(f) is sectional drawing perpendicular | vertical to the stripe direction of the EA part which shows the manufacturing process of the optical semiconductor element which concerns on Embodiment 3 of this invention. It is a figure which shows the structure of the mesa stripe of the optical semiconductor element which concerns on Embodiment 3 of this invention. (A)-(f) is sectional drawing perpendicular | vertical to the stripe direction of LD part which shows the manufacturing process of the optical semiconductor element which concerns on Embodiment 4 of this invention. (A)-(f) is sectional drawing perpendicular | vertical to the stripe direction of the EA part which shows the manufacturing process of the optical semiconductor element which concerns on Embodiment 4 of this invention. It is a figure which shows the structure of the mesa stripe of the optical semiconductor element which concerns on Embodiment 4 of this invention. (A)-(b) is a figure which shows the manufacturing process of the conventional optical semiconductor element.

  Hereinafter, embodiments of the present invention will be described in detail.

(Embodiment 1)
1A to 1F show a manufacturing process of an optical semiconductor element according to Embodiment 1 of the present invention. First, as shown in FIG. 1A, an InGaAsP having a wavelength of 1.3 μm band on an InP substrate 101.
An active layer 102, an InP cladding layer 103, an InGaAsP intermediate layer 104 having a 1.3 μm band composition, and an InGaAs contact layer 105 are grown. An insulating film mask 106 for etching SiO ₂ is laminated thereon, and mesa stripes are formed by dry etching using a chlorine-based gas. The InGaAsP intermediate layer 104 is a band gap discontinuous relaxation layer whose band gap energy is in the middle of the InP cladding layer 103 and the InGaAs contact layer 105.

  Next, the mesa stripe is exposed to a first sulfuric acid-based etching solution composed of a mixed solution of sulfuric acid, hydrogen peroxide solution, and water. As a result, side etching is performed on both sides of the InGaAs contact layer 105 as shown in FIG. As the first sulfuric acid-based etching solution, a solution having a much slower etching rate for the active layer 102 than the sulfuric acid-based etching solution used in the pre-filling growth treatment of the active layer 102 is used. Therefore, the active layer 102 is hardly etched. Of course, the InP cladding layer 103 is not etched either. The etching rate of the first sulfuric acid-based etching solution is adjusted by the ratio of water in the mixed solution of sulfuric acid, hydrogen peroxide solution, and water. As the proportion of water increases, the etching rate decreases.

  Next, as shown in FIG. 1C, a positive photoresist is applied to the entire surface of the wafer, exposed again and developed with the photomask used for forming the mesa stripe, and the InGaAs contact under the insulating film mask 106 is obtained. Photoresist 107 is disposed in the side etching portion of layer 105. Photoresist 107 is in contact with InGaAs contact layer 105 and is formed on the side etched portions on both sides.

  Next, as shown in FIG. 1 (d), a second sulfuric acid-based etchant having a higher etching rate for the active layer 102 than the first sulfuric acid-based etchant used for the side etching of the InGaAs contact layer 105 is used. Then, side etching of the active layer 102 is performed. Since the side wall of the InGaAs contact layer 105 is protected by the photoresist 107, side etching can be performed on the side wall of the active layer 102 while preventing the erosion of the InGaAs contact layer 105, and the damaged layer by dry etching is removed. it can. In the case of this embodiment, the side etching thickness for completely removing the dry etching damage is 0.2 μm on one side. If the active layer width is 1.7 μm in order to obtain a single mode, the mesa width is 2.1 μm. At this time, since the InGaAsP intermediate layer 104 has the same 1.3 μm composition as the active layer 102, the side etching amount of the InGaAsP intermediate layer 104 is equal to that of the active layer 102. In order to prevent side etching of the InGaAsP intermediate layer 104 from reaching the InGaAs contact layer 105, the side etching amount of the InGaAs contact layer 105 was set to 0.5 μm on one side. At this time, it is essential that the side etching of the InGaAsP intermediate layer 104 does not reach the side wall of the InGaAs contact layer 105 side-etched with the first sulfuric acid-based etching solution. Fine adjustment is possible.

  Through a series of etching steps, the side surface of the mesa tribe becomes a stepped shape, and the mesa width relationship between adjacent layers is as follows: InP substrate 101> InGaAsP active layer 102 <InP clad layer 103> InGaAsP intermediate layer 104> InGaAs contact layer 105 It becomes.

  Thereafter, the photoresist 107 is further removed, and a surface treatment with sulfuric acid is performed to grow a semi-insulating InP buried layer 108 on the side surface of the stripe (FIG. 1 (e)). At this time, in order to suppress the plane orientation in which the ridge portion of the insulating film mask 106 formed by side etching of the InGaAs contact layer 105 grows on the insulating film mask 106, the insulating film mask 106 on the semi-insulating InP buried layer 108 is Abnormal growth is prevented.

  Next, the insulating film mask 106 is removed, an interlayer insulating film 109 is formed on the entire surface of the wafer, an insulating film window is opened above the mesa stripe, and a p-side electrode 110 is formed on the InGaAs contact layer 105. The p-side electrode 110 is a non-alloy electrode in which the InGaAs contact layer 105 is heavily doped and the electrode material is TiPtAu. Next, the back surface of the InP substrate 101 is polished to form an n-side electrode 111 of AuGeNi / Au, thereby completing the light emitting element. Even when buried in the semi-insulating InP buried layer 108, the side shape of the stepped shape of the mesa tribe is maintained, and the size relationship between the mesa widths of adjacent layers is InP substrate 101> InGaAsP active layer 102 <InP clad layer 103> InGaAsP Intermediate layer 104> InGaAs contact layer 105. The cross section of the LD portion at this time is shown in FIG.

  In FIGS. 1A to 1F, as an example of this embodiment, the InGaAs contact layer 104 is etched by 0.5 μm on the side of a 2.1 μm wide mesa stripe, and the active layer 102 is etched by 0.2 μm. An example is shown.

  When the InGaAsP intermediate layer 104 is side-etched, the side etching of the InGaAsP intermediate layer 104 is performed so as not to reach the side wall of the InGaAs contact layer 105 so that the InGaAs contact layer 105 is not etched. The side etching of the InGaAsP intermediate layer 104 is performed simultaneously with the side etching of the active layer 102, and the active layer 102 is etched by about several microns to remove the damage of the dry etching, so that the InGaAsP intermediate layer having the same composition as the active layer 102 is etched. 104 is also etched by several microns. Therefore, the InGaAs contact layer 105 needs to be etched deeper than at least a few microns so that it is not exposed in the process of side etching the InGaAsP intermediate layer 104. In actuality, in consideration of etching accuracy and the like, the etching is controlled so that the side wall of the InGaAs contact layer 105 and the side wall of the InGaAsP intermediate layer 104 have a difference in etching depth of about 0.2 μm to 0.5 μm. For example, when the InGaAsP intermediate layer 104 is etched by 0.1 μm to 0.3 μm, the InGaAs contact layer 105 is subjected to side etching by about 0.3 μm to 0.8 μm.

  The optical semiconductor device manufactured in this way can avoid the reduction of the width of the InP clad layer 103 at the top of the mesa, which was observed when the active layer 102 was etched using a bromo (Br) based etchant, and the device resistance. It is possible to avoid a phenomenon in which the resistance of the clad layer occupying most of the resistance increases. Therefore, even if the mesa stripe has the InGaAs contact layer 105 having a much higher etching rate than the active layer 102 of the 1.3 μm band laser, it is possible to obtain good characteristics as a semi-insulating InP buried laser. . Further, in the InGaAs contact layer 105, by increasing the p-type concentration, a non-alloy electrode configuration is possible, which is effective for high reliability. That is, since a small series resistance is obtained, the light output is high, the damaged layer beside the active layer 102 is sufficiently removed, and a non-alloy electrode is possible, so that high reliability is obtained. Further, since the difference in etching depth between the side wall of the InGaAs contact layer 105 and the side wall of the InGaAsP intermediate layer 104 is about 0.2 μm to 0.5 μm, when the InGaAsP intermediate layer 104 is etched, the contact layer 105 is etched. Therefore, even if a slight deviation occurs in the manufacturing process, the characteristics are not deteriorated and the yield is improved.

  The present invention suppresses the side etching amount of the contact layer when the contact layer etching rate is increased because a high concentration doping is applied to the contact layer in order to form a non-alloy electrode even in a 1.55 μm band laser. It is effective because it can. Further, in order to further reduce the resistance, when the width of the InP clad layer is increased to increase the side etching amount of the active layer, it is effective because the reduction of the width of the contact layer can be suppressed.

(Embodiment 2)
2A to 2G show manufacturing steps of the optical semiconductor device according to the second embodiment of the present invention. In the first embodiment, the contact layer is side-etched after the high mesa structure is formed by dry etching. In this embodiment, however, the stripe pattern of the contact layer narrower than the mesa width is formed by etching before the high mesa structure is formed. An insulating film stripe pattern for mesa processing is formed on the intermediate layer below the intermediate layer.

  First, as shown in FIG. 2A, an active layer 202 having a wavelength of 1.3 μm, an InP clad layer 203, an InGaAsP intermediate layer 204 having a 1.3 μm band composition, and an InGaAs contact layer 205 are stacked on an InP substrate 201. . The InGaAsP intermediate layer 204 is a band gap discontinuous relaxation layer having a band gap energy in the middle of the InP cladding layer 203 and the InGaAs contact layer 205.

  Thereafter, a photoresist 206 having a stripe pattern narrower than the cladding width is formed, and a portion of the InGaAs contact layer 205 not covered with the photoresist 206 is removed by wet etching. A mesa cross-sectional view at this point is shown in FIG. Of course, side etching may be used using a wide mask as in the first embodiment.

Next, as shown in FIG. 2C, the photoresist 206 is removed, and insulation for etching SiO ₂ for high-mesa etching so as to cover all of the InGaAs contact layer 205 and a part of the InGaAsP intermediate layer 204 is performed. A film mask 207 is formed. Then, as shown in FIG. 2D, mesa stripes are formed by dry etching. Next, as shown in FIG. 2E, side etching is performed on the active layer 202 using a second sulfuric acid-based etchant in the same manner as in the first embodiment in order to remove the damaged layer. At this time, the InGaAsP layer intermediate layer 204 is also side-etched. On the other hand, since the InGaAs contact layer 205 is protected by the insulating film mask 207, the InGaAs contact layer 205 can be prevented from being eroded. The side etching amount of the InGaAsP intermediate layer 204 can be adjusted by the composition of InGaAsP so as not to reach the InGaAs contact layer 205. As in the first embodiment, the side etching portion of the InGaAsP intermediate layer 204 has a function of suppressing the mode of growth on the insulating film mask 207 in the subsequent semi-insulating InP burying growth, and the semi-insulating InP burying layer 208. It has a role to prevent abnormal growth.

  Through a series of etching steps, the side surface of the mesa tribe becomes a stepped shape, and the mesa width relationship between adjacent layers is as follows: InP substrate 201> InGaAsP active layer 202 <InP clad layer 203> InGaAsP intermediate layer 204> InGaAs contact layer 205 It becomes.

  Thereafter, a semi-insulating InP buried layer 208 is grown on the stripe side surface. Thereafter, the insulating film mask 207 is removed, an interlayer insulating film 209 is formed on the entire surface of the wafer, an insulating film window is opened above the mesa stripe, and a p-side electrode 210 is formed on the InGaAs contact layer 105. The InGaAs contact layer 205 is highly doped and is a non-alloy electrode in which the electrode material is TiPtAu. Next, the back surface of the InP substrate 201 is polished to form the AuGeNi / Au n-side electrode 211, thereby completing the light emitting element. Even at this stage, the mesa width relationship between adjacent layers is InP substrate 201> InGaAsP active layer 202 <InP clad layer 203> InGaAsP intermediate layer 204> InGaAs contact layer 205. Is retained. The cross section of the LD portion at this time is shown in FIG.

  2A to 2G, as an example of this embodiment, the thickness of the InGaAsP intermediate layer 204 is 0.2 μm, and the amount of side etching of the active layer 202 is set to completely remove dry etching damage. An example is shown in which one side is 0.2 μm, the active layer width is 1.7 μm to obtain a single mode, and the mesa stripe width is 2.1 μm. Also in this embodiment, as in the first embodiment, the widths of the InGaAsP intermediate layer 204 and the InGaAs contact layer 205 before filling are formed so as to have a difference of about 0.2 μm to 0.5 μm on one side of the mesa. Also in this embodiment, an optical semiconductor element having good characteristics as a semi-insulating InP buried laser can be manufactured as in the first embodiment. Further, the yield can be improved.

(Embodiment 3)
In the present invention, a 1.3 μm band laser (LD part) whose active layer is made of InGaA _S P-based material and an EA modulator (EA part) whose active layer is made of InGaAlAs-based material are directly or via a waveguide layer. It is also possible to apply to a light source in which joints are integrated and both contact layers are made of InGaAs. This embodiment shows a manufacturing method using the method of Embodiment 1 for an element in which an LD part active layer and an EA part active layer are connected via a waveguide layer by butt joint integration.

FIGS. 3A to 3F and FIGS. 4A to 4F show a process for manufacturing an optical semiconductor device according to the third embodiment of the present invention. 3A to 3F are cross sections perpendicular to the stripe direction of the LD portion, and FIGS. 4A to 4F are cross sections perpendicular to the stripe direction of the EA portion. This laminated structure can be formed by the following procedure. First, an active layer 302 of the LD of the InGaAs _S P-based material on an InP substrate 301 to form the LD island by dry etching and wet etching. Next, the active layer 303 of the InGaAlAs-based material EA part is grown in the region where the active layer 302 on the InP substrate 301 is removed, and LD islands and EA islands are formed by dry etching and wet etching. Next, the waveguide core layer 313 is grown by butt joint in the region where the active layers 302 and 303 on the InP substrate 301 are removed. After forming the active layers 302 and 303 and the waveguide core layer 313 on the InP substrate 301, a clad layer, an intermediate layer, and a contact layer are laminated thereon. A stripe mask is formed on this laminated structure, and dry etching is performed in the same manner as the optical semiconductor element of Embodiment 1 to form a mesa stripe having the structure shown in FIG. In the mesa stripe of the present embodiment, an active layer 302 of InGaA _S P-based material, an active layer 303 of InGaAlAs-based material, and a waveguide core layer 313 connecting them are arranged.

The cross-sectional structure of the LD part and the EA part is a laminated structure as shown in FIGS. 3A and 4A, and an active layer 302 made of InGaA _S P-based material is formed on the LD part on the InP substrate 301, EA. An active layer 303 made of an InGaAlAs-based material, an InP clad layer 304, an InGaAsP intermediate layer 305 having a 1.3 μm band composition, and an InGaAs contact layer 306 are laminated on this portion, and an insulating film mask 307 is formed. The mesa width is a difference in side etching amount, which will be described later, and the side etching amount of the EA portion is larger than that of the LD portion.

  Thereafter, the substrate is exposed to the same first sulfuric acid etching solution as in the first embodiment. Since the etching rates of the InGaAs contact layer 306 and the active layer 303 in the EA portion are approximately the same, both side walls of the InGaAs contact layer 306 and the active layer 303 in the EA portion are subjected to the same side etching. At this time, as shown in FIGS. 3B and 4B, the active layer 302 in the LD portion has a slower etching rate than the InGaAs contact layer 306 and the active layer 303 in the EA portion, and the first etching is performed. The side walls are hardly etched with the liquid.

  Thereafter, a photoresist is applied to the entire surface of the wafer, exposed again and developed with the photomask used for forming the mesa stripe, and the side etching portion of the InGaAs contact layer 306 under the insulating film mask 307 and the active layer 303 of the EA portion are formed. Photoresist 308 is disposed on the side etched portions on both side walls. Photoresist 308 is formed in the side etching portion on both sides in contact with InGaAs contact layer 105 and active layer 303 in the EA portion. The cross sections of the LD part and the EA part at this time are shown in FIGS.

  Next, in this state, the mesa stripe is exposed to a sulfuric acid-based second etching solution having a higher etching rate with respect to the active layer 302 than the first sulfuric acid-based etching solution. Side etching is applied to 305. Cross sections of the LD part and the EA part at this time are shown in FIGS. 3 (d) and 4 (d). As in the first and second embodiments, stepped irregularities are formed on the side surfaces of the mesa stripe by a series of etching processes, as in the first and second embodiments.

  Next, the photoresist 308 is removed, and a surface treatment with sulfuric acid is performed to grow a semi-insulating InP buried layer 309 on the side surface of the stripe. The cross sections of the LD part and the EA part at this time are shown in FIGS. 3 (e) and 4 (e). Thereafter, as in the first and second embodiments, the interlayer insulating film 310, the p-side electrode 311, and the n-side electrode 312 are formed to complete the element. Even at this stage, the mesa widths of adjacent layers are as follows: InP substrate 301> InGaAsP active layer 302, InGaAlAs 303 <InP clad layer 304> InGaAsP intermediate layer 305> InGaAs contact layer 306. The side shape is retained. The cross sections of the LD part and the EA part at this time are shown in FIG. 3 (f) and FIG. 4 (f).

  3 and 4, as an example of the present embodiment, for the LD portion, the InGaAs contact layer 306 is etched by 0.5 μm side with respect to a mesa stripe having a width of 2.1 μm, and the active layer 302 is etched by 0.2 μm side. As for the EA portion, an example in which the InGaAs contact layer 306 and the active layer 303 are side-etched by 0.5 μm with respect to a mesa stripe having a width of 2.5 μm is shown. Also in this embodiment, similarly to Embodiments 1 and 2, the widths of the InGaAsP intermediate layer 305 and the InGaAs contact layer 306 before filling are formed so that there is a difference of about 0.2 μm to 0.5 μm on one side of the mesa. . For this reason, even if some deviation occurs in the manufacturing process, the characteristics are not deteriorated and the yield is improved.

  By this method, even if the active layer of the LD part and the EA part are composed of different material systems and the etching rates of the active layers are different, the damaged layer of the active layer can be sufficiently removed and the light source has a good characteristic and high reliability. An element can be realized. In addition, since the contact layer can be made of InGaAs, a non-alloyed electrode configuration can also contribute to high reliability.

(Embodiment 4)
In the present invention, a 1.3 μm band laser (LD part) whose active layer is made of InGaA _S P-based material and an EA modulator (EA part) whose active layer is made of InGaAlAs-based material are directly or via a waveguide layer. It is also possible to apply to a light source in which joints are integrated and both contact layers are made of InGaAs. This embodiment shows a manufacturing method using the method of Embodiment 2 for an element in which an LD part active layer and an EA part active layer are connected through a waveguide layer by butt joint integration.

FIGS. 6A to 6F and FIGS. 7A to 7F show a manufacturing process of the optical semiconductor device according to the fourth embodiment of the present invention. 6A to 6F are cross sections perpendicular to the stripe direction of the LD portion, and FIGS. 7A to 7F are cross sections perpendicular to the stripe direction of the EA portion. A stacked structure is formed in the same manner as in the third embodiment, a stripe mask is formed on the stacked structure, and dry etching is performed to form a mesa stripe having the structure shown in FIG. In the mesa stripe of the present embodiment, an active layer 402 of InGaA _S P-based material, an active layer 403 of InGaAlAs-based material, and a waveguide core layer 413 connecting them are arranged.

By dry etching like the optical semiconductor device of embodiment 2, a laminated structure as shown in FIG. 2 (a), at least the active layer is disposed and a region of the region and InGaAlAs-based material InGaAs _S P based material Mesa stripes are formed. The cross sections of the LD part and the EA part at this time are shown in FIGS. Active layer 403, the InP clad layer 404,1.3μm band composition InGaAsP intermediate layer 405 made of InGaAlAs-based material in the active layer 402, EA unit consisting or InGaAs _S P-based material to the LD unit on an InP substrate 401, InGaAs contact layer 406 is laminated, and an insulating film mask 407 is formed.

  Thereafter, the entire stripe is exposed to a citric acid-based first etching solution composed of a mixed solution of citric acid, hydrogen peroxide solution, and water. Thus, both side etching of the active layer 403 in the EA portion is performed. At this time, the active layer 402 in the LD portion has an etching rate slower than that of the active layer 403 in the EA portion, and the side wall is hardly etched by the first etching solution. The cross sections of the LD portion and the EA portion at this time are shown in FIGS. 6B and 7B. Instead of the citric acid-based first etching solution, a sulfuric acid-based first etching solution may be used.

  Thereafter, a photoresist is applied to the entire surface of the wafer, and the entire surface of the wafer is exposed to dispose the photoresist 408 in the side etching portion of the active layer in the EA portion. The cross sections of the LD part and the EA part at this time are shown in FIGS.

  Next, in this state, the mesa stripe is exposed to a sulfuric acid-based second etching solution whose etching rate with respect to the active layer 402 is faster than that of the citric acid-based first etching solution. 405 is subjected to side etching. Thereafter, the photoresist 408 is removed. The cross sections of the LD portion and the EA portion at this time are shown in 5 (d) and (d). The side surface of the mesa stripe at this stage is stepped, and the same unevenness as in the first, second, and third embodiments is formed. Also in this embodiment, as in the other embodiments, the widths of the InGaAsP intermediate layer 405 and the InGaAs contact layer 406 before filling are formed so as to have a difference of about 0.2 μm to 0.5 μm on one side of the mesa. For this reason, even if some deviation occurs in the manufacturing process, the characteristics are not deteriorated and the yield is improved.

  Next, a surface treatment with concentrated sulfuric acid is performed to grow a semi-insulating InP buried layer 409 on the stripe side surface. The cross sections of the LD portion and the EA portion at this time are shown in FIGS. 6 (e) and 7 (e). Thereafter, similarly to the first to third embodiments, the interlayer insulating film 410, the p-side electrode 411, and the n-side electrode 412 are formed to complete the element. Even at this stage, the mesa width relationship between adjacent layers is InP substrate 401> InGaAsP active layer 402, InGaAlAs active layer 403 <InP clad layer 404> InGaAsP intermediate layer 405> InGaAs contact layer 406, The stepped side shape is retained. The cross sections of the LD part and the EA part at this time are shown in FIGS. 6 (f) and 7 (f).

  By this method, even if the active layer of the LD part and the EA part are composed of different material systems and the etching rates of the active layers are different, the damaged layer of the active layer can be sufficiently removed and the light source has a good characteristic and high reliability. An element can be realized. In addition, since the contact layer can be made of InGaAs, a non-alloyed electrode configuration can also contribute to high reliability.

DESCRIPTION OF SYMBOLS 101 InP substrate 102 Active layer 103 InP clad layer 104 InGaAsP intermediate layer 105 InGaAs contact layer 106 Insulating film mask 107 Photoresist 108 Semi-insulating InP buried layer 109 Interlayer insulating film 110 P-side electrode 111 N-side electrode 201 InP substrate 202 Active layer 203 InP cladding layer 204 InGaAsP intermediate layer 205 InGaAs contact layer 206 photoresist 207 insulator mask 208 semi-insulating InP buried layer 209 interlayer insulating film 210 p-side electrode 211 n-side electrode 301 InP substrate 302 InGaAs _S P based material or become active Layer 303 Active layer made of InGaAlAs-based material 304 InP cladding layer 305 InGaAsP intermediate layer 306 InGaAs contact layer 307 Insulating film mask 308 photoresist 309 semi-insulating InP buried layer 310 interlayer insulating film 311 p-side electrode 312 n-side electrode 313 waveguide core layer 401 active layer 404 InP consisting of InP substrate 402 InGaAs _S P based material or made active layer 403 InGaAlAs-based materials Cladding layer 405 InGaAsP intermediate layer 406 InGaAs contact layer 407 Insulating film mask 408 Photoresist 409 Semi-insulating InP buried layer 410 Interlayer insulating film 411 p-side electrode 412 n-side electrode 413 Waveguide core layer 501 InP substrate 502 active layer 503 InP cladding Layer 504 Intermediate layer 505 Contact layer 506 Insulating film mask

Claims (5)

A first step of forming a laminated structure in which at least an active layer, a clad layer, an intermediate layer, and a contact layer are sequentially laminated on a substrate;
A second step of forming a mesa stripe by performing dry etching on the laminated structure;
A third step of performing side etching on the contact layer by exposing a side surface of the mesa stripe to a first etching solution;
A fourth step of protecting the side-etched portion;
A fifth step of performing side etching on the active layer and the intermediate layer by exposing a side surface of the mesa stripe to a second etching solution;
A method of manufacturing an optical semiconductor element, comprising sequentially performing a sixth step of forming a semi-insulating InP buried layer on a side surface of the mesa stripe. A first step of forming a laminated structure in which at least an active layer, a clad layer, an intermediate layer, and a contact layer are sequentially laminated on a substrate;
A second step of forming a stripe pattern of the contact layer;
A third step of forming a mask for mesa stripe processing on the exposed surface of the contact layer and the intermediate layer around the contact layer;
A fourth step of forming a mesa stripe wider than the width of the stripe pattern by dry etching after the third step;
A fifth step of performing side etching by exposing a side surface of the mesa stripe to an etching solution;
A method of manufacturing an optical semiconductor element, comprising sequentially performing a sixth step of forming a semi-insulating InP buried layer on a side surface of the mesa stripe.   In the first step of forming the laminated structure, as the active layer, an active layer of a 1.3 μm band laser of InGaAsP composition butt-jointed in a column in the longitudinal direction of the mesa stripe and an EA modulator of InAlGaAs composition are used. The method for manufacturing an optical semiconductor element according to claim 1, further comprising a seventh step of forming an active layer. An optical semiconductor element having a mesa stripe in which an active layer, an InP clad layer, an InGaAsP intermediate layer, and an InGaAs contact layer are sequentially stacked on an InP substrate,
The active layer is narrower than the InP cladding layer, the InP cladding layer is wider than the InGaAsP intermediate layer, and the InGaAsP intermediate layer is wider than the InGaAs contact layer. Semiconductor element.   5. The optical semiconductor device according to claim 4, wherein the active layer has an InGaAsP composition, or an active layer having an InGaAsP composition and an active layer having an InAlGaAs composition are formed in the same stripe.

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