JP2018137747A - Signal output device - Google Patents

Abstract

The present invention reduces spurious frequencies in the vicinity of the frequency of an output signal. A signal output device includes a first direct digital synthesizer that generates and outputs a first digital signal corresponding to a predetermined frequency, and a first analog signal that is converted from the first digital signal. A second direct digital synthesizer 42 that generates and outputs a second digital signal corresponding to a reduced signal that reduces spurious at one frequency; an adder 43 that adds the first digital signal and the second digital signal; And a DA converter 5 that converts the digital signal added by the adder 43 into an analog signal and outputs the analog signal. [Selection] Figure 2

Description

  The present invention relates to a signal output device.

  2. Description of the Related Art Conventionally, a direct digital synthesizer (DDS: Direct Digital Synthesizer) that can change an output frequency to an arbitrary frequency and an arbitrary phase is known (see, for example, Patent Document 1).

JP 2011-77910 A

  The output signal of DDS includes spurious due to harmonics of the frequency of the output signal. Spurious may appear near the frequency of the output signal of the DDS due to aliasing. In particular, when spurious is included in the vicinity of the frequency of the output signal of the DDS, there is a risk of causing performance deterioration of a device that operates based on the output signal.

  Accordingly, the present invention has been made in view of these points, and an object thereof is to provide a signal output device capable of reducing spurious frequencies in the vicinity of the frequency of the output signal.

  The signal output device according to the first aspect of the present invention includes a first direct digital synthesizer that generates and outputs a first digital signal corresponding to a predetermined frequency, and a first analog signal converted from the first digital signal. A second direct digital synthesizer that generates and outputs a second digital signal corresponding to a reduced signal that reduces spurious at at least one frequency included, and adds the first digital signal and the second digital signal. An adder; and a DA converter that converts the added digital signal added by the adder into an analog signal and outputs the analog signal.

  The second direct digital synthesizer may generate and output the second digital signal corresponding to the reduced signal having the same frequency as the spurious and a phase different from the spurious.

  The second direct digital synthesizer may generate and output the second digital signal corresponding to the reduced signal having a predetermined proportion of the amplitude of the spurious.

  A plurality of second direct digital synthesizers that generate and output the second digital signal corresponding to each of a plurality of spurious included in the first analog signal; and the adder includes the first digital signal; A plurality of the second digital signals may be added.

  The apparatus further includes a specifying unit that specifies a frequency and an amplitude of the spurious included in the first analog signal, and the second direct digital synthesizer corresponds to the reduced signal based on the frequency and the amplitude specified by the specifying unit. The second digital signal may be generated and output.

  The signal output device further includes a bit width conversion unit that reduces a bit width of the added digital signal added by the addition unit, and the DA conversion unit has a bit width reduced by the bit width conversion unit. Then, the rounded and added digital signal may be converted into the analog signal.

  The signal output device further includes a level conversion unit that increases the value of the second digital signal, and a display control unit that displays the second digital signal after the level conversion unit increases on the display unit. May be.

  According to the present invention, it is possible to reduce spurious at frequencies near the frequency of the output signal.

It is a figure which shows the outline | summary of the signal output device which concerns on this embodiment. It is a figure which shows the structure of the signal output device which concerns on this embodiment. It is a figure which shows the example of the bit width of data. It is a figure which shows the structure which performed the simulation for confirming the influence of a rounding error. It is a figure which shows the result of having simulated by the structure shown in FIG. It is a figure which shows the spectrum of the signal after a 1st digital signal, a 2nd digital signal, and addition. It is a figure which shows the structure in the case of enlarging the value of a 2nd digital signal by a level conversion part. It is a figure which shows the structure which performed the simulation corresponding to the structure shown in FIG. It is a figure which shows the result simulated by the structure shown in FIG. It is a figure which shows the spectrum in the case of canceling the aliasing noise which has generate | occur | produced in the 1st digital signal using the 2nd digital signal. It is a figure which shows the measurement data of the spurious level of the frequency vicinity of the 2nd harmonic contained in a 1st digital signal. It is a figure which shows the measured data of the spurious level near the frequency of the 5th harmonic contained in a 1st digital signal. It is a figure which shows the structure of the signal output device provided with the specific | specification part which concerns on this embodiment.

[Outline of Signal Output Device 1]
FIG. 1 is a diagram illustrating an outline of a signal output device 1 according to the present embodiment. The signal output device 1 includes a first direct digital synthesizer 41 (hereinafter referred to as a first DDS 41), a second direct digital synthesizer 42 (hereinafter referred to as a second DDS 42), an adder 43, and a DA converter 5 as a conversion unit. With.

  The first DDS 41 generates and outputs a first digital signal corresponding to the first analog signal that is an analog signal having a predetermined frequency. As shown in FIG. 1, the first analog signal converted from the first digital signal includes spurious due to the harmonics of the signal of the predetermined frequency in addition to the signal of the predetermined frequency.

  The second DDS 42 generates and outputs a second digital signal corresponding to a reduced signal that reduces spurious at one frequency included in the first analog signal. Here, the reduction target spurious is referred to as a reduction target spurious.

  The adder 43 adds the first digital signal output from the first DDS 41 and the second digital signal output from the second DDS 42 and outputs the result to the DA converter 5. The DA converter 5 converts the digital signal output from the adder 43 into an analog signal and outputs the analog signal.

The digital signal generated by adding the first digital signal and the second digital signal is a digital signal in which the signal component corresponding to the reduction target spurious and the signal component corresponding to the reduction signal are offset. Thereby, the reduction target spurious is reduced in the analog signal output from the DA converter 5. Therefore, by outputting the second digital signal corresponding to the reduction signal of the frequency near the predetermined frequency from the second DDS 42, the signal output device 1 can reduce the spurious of the frequency near the predetermined frequency.
Next, the configuration of the signal output device 1 will be described.

[Configuration of Signal Output Device 1]
FIG. 2 is a diagram illustrating a configuration of the signal output device 1 according to the present embodiment. As shown in FIG. 2, the signal output device 1 includes a distributor 2, a storage unit 3, a digital signal processing circuit 4, a DA converter 5, and a low-pass filter 6.

  The distributor 2 distributes a reference signal used for sampling a signal input from the outside to the digital signal processing circuit 4 and the DA converter 5. In the present embodiment, the distributor 2 outputs the distributed reference signal to the digital signal processing circuit 4 and the DA converter 5. Here, the frequency of the reference signal is called a sampling frequency.

  The storage unit 3 is, for example, a PROM (Programmable Read Only Memory). The storage unit 3 stores various set values that the digital signal processing circuit 4 refers to. In addition, the storage unit 3 stores a waveform table indicating waveform values for one cycle. The waveform table is a table in which an address corresponding to each phase of the waveform for one period is associated with a waveform value in each phase. Here, it is assumed that the addresses corresponding to the phases are continuous. The number of bits of the address corresponding to each phase is a predetermined number of bits.

  The digital signal processing circuit 4 is, for example, an FPGA (Field-Programmable Gate Array). The digital signal processing circuit 4 includes an external interface (I / F) 40, a first DDS 41, a second DDS 42, and an adder 43.

  The external interface 40 receives input of various information from the outside. The external interface 40 receives input of information indicating a predetermined frequency that is a frequency of an output signal to be output from the signal output device 1 and information indicating a frequency of a reduction signal that reduces the reduction target spurious. The external interface 40 outputs information indicating the predetermined frequency to the first DDS 41 and outputs information indicating the frequency of the reduced signal to the second DDS 42. Hereinafter, the frequency of the reduced signal is referred to as a second frequency.

  The first DDS 41 generates and outputs a first digital signal corresponding to a predetermined frequency. As shown in FIG. 2, the first DDS 41 includes a phase accumulator 411, an adder 412, a waveform signal generation unit 413, and a multiplier 414.

  The phase accumulator 411 sequentially outputs phase information indicating an output signal phase having a predetermined frequency in synchronization with the sampling frequency. The information indicating the phase is information indicating an address in the waveform table stored in the storage unit 3. The phase accumulator 411 updates the phase information by adding a predetermined value to the immediately preceding phase information every time a unit time that is the reciprocal of the sampling frequency elapses.

  The adder 412 adds the address indicated by the phase information output from the phase accumulator 411 and the address corresponding to the phase offset amount of the output signal of the predetermined frequency and outputs the result. Here, the offset amount is stored as parameter information in the storage unit 3, for example. The digital signal processing circuit 4 inputs the phase offset amount of the output signal having a predetermined frequency to the adder 412 based on the parameter information.

The adder 412 discards a value overflowing from a predetermined number of bits as a result of adding two addresses. As a result, the adder 412 outputs an address corresponding to the current phase of the output signal whose phase is shifted by the offset amount.
The waveform signal generation unit 413 refers to the waveform table stored in the storage unit 3 and outputs a waveform value corresponding to the address output from the adder 412.

  The multiplier 414 multiplies the waveform value output from the waveform signal generation unit 413 and the amplitude setting value indicating the amplitude increase / decrease rate. The multiplier 414 outputs the multiplication result to the adder 43 as the first digital signal corresponding to the output signal. Here, the amplitude setting value corresponding to the output signal of the predetermined frequency is stored as parameter information in the storage unit 3, for example. Based on the parameter information, the digital signal processing circuit 4 inputs an amplitude setting value corresponding to an output signal having a predetermined frequency to the multiplier 414.

  The second DDS 42 generates and outputs a second digital signal corresponding to a reduction signal that reduces the reduction target spurious included in the first analog signal converted from the first digital signal. Specifically, the second DDS 42 generates and outputs a second digital signal corresponding to a reduced signal having the same frequency as the reduction target spurious and a phase different from that of the reduction target spurious. The second DDS 42 generates and outputs a second digital signal having an amplitude of a predetermined ratio of the amplitude of the reduction target spurious. As shown in FIG. 2, the second DDS 42 includes a phase accumulator 421, an adder 422, a waveform signal generation unit 423, and a multiplier 424.

  The phase accumulator 421 outputs the address of the waveform table as phase information indicating the phase of the reduced signal of the second frequency in synchronization with the sampling frequency.

The adder 422 adds the address output from the phase accumulator 421 and the address corresponding to the phase offset amount of the reduced signal and outputs the result. Here, the offset amount of the phase of the reduced signal is stored as parameter information in the storage unit 3, for example. It is assumed that the amount of offset of the phase of the reduction signal is set to be opposite to the phase of the reduction target spurious, for example. The digital signal processing circuit 4 inputs the phase offset amount of the reduced signal to the adder 422 based on the parameter information.
The waveform signal generation unit 423 refers to the waveform table stored in the storage unit 3 and outputs a waveform value corresponding to the address output from the adder 422.

  The multiplier 424 multiplies the waveform value output from the waveform signal generation unit 423 by the amplitude setting value indicating the increase / decrease ratio of the amplitude of the reduced signal. The multiplier 424 outputs the multiplication result to the adder 43 as the second digital signal corresponding to the reduced signal. Here, the amplitude setting value corresponding to the reduced signal is stored as parameter information in the storage unit 3, for example. The amplitude setting value is set so that the amplitude of the reduced signal corresponding to the second digital signal output from the multiplier 424 is equal to the amplitude of the reduction target spurious.

  The adder 43 adds the first digital signal output from the first DDS 41 and the second digital signal output from the second DDS 42 and outputs the result to the DA converter 5.

  The DA converter 5 converts the digital signal output from the adder 43 into an analog signal based on the sampling frequency. The DA converter 5 outputs an analog signal to the low-pass filter 6.

  The low pass filter 6 removes the low frequency component of the analog signal output from the DA converter 5. As a result, an output signal having a predetermined frequency is generated. The low-pass filter 6 outputs an analog signal from which low frequency components have been removed to the outside as an output signal.

[Measurement results]
Next, an actual measurement result when spurious is suppressed using the signal output device 1 according to the present embodiment will be shown. When the frequency of the output signal of the signal output device 1 is 42 MHz and the sampling frequency is 200 MHz, the output signal includes a 74 MHz spurious signal as a return of the third harmonic of the output signal. The amplitude of this spurious was −71.63 dBc.

  On the other hand, the spurious was set as a reduction target spurious, and a reduction signal was generated in the second DDS 42. As a result of the measurement, the 74 MHz spurious amplitude was −93.28 dBc, which was improved by 21.65 dBc.

  Further, when the frequency of the output signal of the signal output device 1 is 42 MHz and the sampling frequency is 200 MHz, the output signal includes a spurious of 84 MHz that is a second harmonic and a spurious of 10 MHz as a return of the fifth harmonic. Is included. The amplitude of the 84 MHz spurious was −62.50 dBc, and the amplitude of the 10 MHz spurious was −82.56 dBc. On the other hand, as a result of generating a reduction signal in the second DDS 42 using the spurious at 84 MHz as the reduction target spurious, the amplitude of the spurious at 84 MHz was −92.55 dBc. In addition, as a result of generating a reduction signal in the second DDS 42 using the 10 MHz spurious as the reduction target spurious, the amplitude of the 10 MHz spurious became −103.27 dBc. Therefore, the spurious at 84 MHz and the spurious at 10 MHz were successfully reduced.

[Influence of rounding error]
In the above description, the rounding error caused by the rounding process, which is a process for reducing the data bit width, has not been taken into account. However, if the data bit width is reduced in order to increase the processing speed, the effect of the rounding error causes a spurious response. May not be sufficiently reduced. Hereinafter, a rounding method for sufficiently reducing spurious will be described.

  FIG. 3 is a diagram illustrating an example of the bit width of data in each unit from the waveform signal generation units 413 and 423 to the DA converter 5. In FIG. 3A, a rounding processing unit 415 is provided between the waveform signal generation unit 413 and the multiplier 414, and 23-bit data is converted into 16-bit data. Further, a rounding processing unit 425 is provided between the waveform signal generation unit 423 and the multiplier 424, and 23-bit width data is converted into 16-bit width data. Then, the adder 43 adds 16-bit data. The rounding processing unit 425 functions as a bit width conversion unit that reduces the bit width of the added digital signal added by the adder 43.

  In FIG. 3B, the 23-bit width data output from the waveform signal generation units 413 and 423 is input to the adder 43 via the multipliers 414 and 424. Then, the adder 43 adds the 23-bit data.

  Comparing the configuration of FIG. 3 (a) with the configuration of FIG. 3 (b), in the configuration of FIG. 3 (a), the adder 43 adds 16-bit width data, and therefore is affected by a rounding error. Cheap. On the other hand, in the configuration of FIG. 3B, the adder 43 adds 23-bit width data, so that it is not easily affected by rounding errors and has a sufficient spurious compared to the configuration of FIG. There is a high probability that it can be reduced.

  FIG. 4 is a diagram illustrating a configuration in which a simulation for confirming the influence of a rounding error is performed. FIG. 5 is a diagram showing a result of simulation by the configuration shown in FIG.

  FIG. 4A corresponds to the configuration of FIG. 3A, and shows a configuration in which the adder 43 adds 16-bit width data. “Display A” corresponds to FIG. 5A and is a spectrum display of the first digital signal output by the first DDS 41. “Display B” corresponds to FIG. 5B, and is a spectrum display of the second digital signal (reduced signal for reducing the harmonic component of the first digital signal) output from the second DDS 42. “Display C” is a spectrum display of a signal obtained by adding the first digital signal having a 16-bit width and the second digital signal having a 16-bit width.

  As shown in FIG. 5A, the first digital signal includes a frequency component of 40 MHz, which is a second harmonic, together with a frequency component of 20 MHz. The second digital signal shown in FIG. 5B includes a frequency component for canceling the 40 MHz harmonic component shown in FIG. However, in FIG. 5C, a frequency component of 40 MHz remains. The reason why the frequency component of 40 MHz remains in FIG. 5C is that the adder 43 is affected by a rounding error due to the addition of 16-bit width data.

  FIG. 4B corresponds to the configuration of FIG. 3B and shows a configuration in which the adder 43 adds 23-bit width data. “Display D” corresponds to FIG. 5D, and is a spectrum display of a signal obtained by adding the first digital signal having a 23-bit width and the second digital signal having a 23-bit width. In this case, it can be seen that the 40 MHz harmonic component shown in FIG.

[Support for low-level signals]
When the level of the harmonic component to be removed from the first digital signal is small, there may be a problem that the second digital signal shown in FIG. 5B cannot be observed. FIG. 6 is a diagram illustrating a spectrum of the first digital signal, the second digital signal, and the signal after addition.

  As shown in FIG. 6A, since the level of the harmonic component of the first digital signal is as low as about −93 dBc, the level of the second digital signal for canceling out this harmonic component is also small. In 6 (b), the second digital signal cannot be observed. In order to make it possible to observe the low-level second digital signal in this way, the signal output device 1 includes a level conversion unit that increases the value of the second digital signal, and a second digital signal after the level conversion unit is increased. You may further have a display control part which displays a signal on a display part.

FIG. 7 is a diagram showing a configuration when the level conversion unit 426 increases the value of the second digital signal. Level conversion unit 426, by multiplying the 2 ⁷ to the second digital signal, increasing the value of the second digital signal. In the example illustrated in FIG. 7, a selector 44 is provided in the preceding stage of the rounding processing unit 416. The selector 44 receives a signal output from the multiplier 414, a signal output from the adder 43, and a signal output from the level conversion unit 426.

  The selector 44 switches a signal to be output to the DA converter 5 based on the input 2-bit control data (00, 01, 10, 11). For example, when the control data is 00, the selector 44 outputs the signal input from the adder 43, and when the control data is 01, the selector 44 outputs the signal input from the level conversion unit 426. When the control data is 11, the first digital signal output from the multiplier 414 is output. Since the signal output device 1 is provided with the selector 44 in this way, it becomes easy to observe signals of each part.

FIG. 8 is a diagram illustrating a configuration in which a simulation corresponding to the configuration illustrated in FIG. 7 is performed. FIG. 9 is a diagram showing a result of simulation by the configuration shown in FIG. “Display A” corresponds to FIG. 9A and is a spectrum display of the first digital signal output by the first DDS 41. "Display B" corresponds to FIG. 9 (b), the a spectrum display after converting the level by multiplying the 2 ⁷ to the second digital signal the 2DDS42 outputs. “Display C” is a spectrum display of a signal obtained by adding the first digital signal shown in FIG. 9A and the second digital signal shown in FIG. 9B. Thus, by converting the level of the second digital signal, the second digital signal can be observed even when the level of the second digital signal is low.

  FIG. 10 is a diagram illustrating a spectrum in the case of canceling aliasing noise generated in the first digital signal using the second digital signal with the configuration illustrated in FIG. 8. By adding the first digital signal shown in FIG. 10 (a) and the second digital signal shown in FIG. 10 (b), it can be seen that aliasing noise is removed as shown in FIG. 10 (c).

  FIG. 11 is a diagram illustrating measured data of spurious levels near the frequency of the second harmonic included in the first digital signal. FIG. 11A shows a spurious level when the adder 43 adds the first digital signal having a 16-bit width and the second digital signal having a 16-bit width. FIG. 11B shows a spurious level when the adder 43 adds the first digital signal having a 23-bit width and the second digital signal having a 23-bit width.

  Comparing FIG. 11 (a) with FIG. 11 (b), in FIG. 11 (a), the spurious level of −65 dBc is reduced to an average of about −90 dBc, whereas FIG. In the case, the average is reduced to about -100 dBc. From this, it can be seen that the reduction amount of the spurious level in the case of FIG. 11B added with a 23-bit width is larger.

  FIG. 12 is a diagram showing measured data of spurious levels near the frequency of the fifth harmonic included in the first digital signal. FIG. 12A shows a spurious level when the adder 43 adds the first digital signal having a 16-bit width and the second digital signal having a 16-bit width. FIG. 12B shows a spurious level when the adder 43 adds the first digital signal having a 23-bit width and the second digital signal having a 23-bit width.

  Comparing FIG. 12A and FIG. 12B, in FIG. 12A, the spurious level of −82 dBc decreases to an average of about −95 dBc, whereas FIG. In the case, the average is reduced to about -100 dBc. From this, it can be seen that the reduction amount of the spurious level in the case of FIG. 12B added with a 23-bit width is larger.

[Modification]
In the above description, the example in which the signal output device 1 includes one second DDS 42 corresponding to one reduction target spurious has been described, but the present invention is not limited thereto. The signal output device 1 includes a second DDS that generates and outputs a second digital signal corresponding to a reduced signal included in the first analog signal converted from the first digital signal to reduce spurious at a plurality of frequencies. Also good.

  Further, the signal output device 1 corresponds to each of the plurality of spurious included in the first analog signal as the second DDS that generates and outputs the second digital signal corresponding to the reduced signal that reduces the spurious of the plurality of frequencies. You may make it provide several 2nd DDS42 which produces | generates and outputs a 2nd digital signal. The adder 43 adds the first digital signal output from the first DDS 41 and the plurality of second digital signals output from the plurality of second DDSs 42, thereby reducing spurious at a plurality of frequencies of the output signal. A plurality of digital signals to be generated may be generated. In this way, the signal output device 1 can output an output signal with reduced spurious at an arbitrary frequency.

  Further, the signal output device 1 stores in advance the phase offset amount and the amplitude setting value corresponding to the reduced signal in the storage unit 3 as parameter information, and generates the reduced signal based on the parameter information. However, it is not limited to this.

  For example, the signal output device 1 may include the specifying unit 7 that specifies the frequency and amplitude of spurious included in the output signal output from the low-pass filter 6 in a state where the second DDS 42 is not operated. FIG. 13 is a diagram illustrating a configuration of the signal output device 1 including the specifying unit 7 according to the present embodiment. The specifying unit 7 includes, for example, a CPU. Here, the output signal output from the low-pass filter 6 in a state where the second DDS 42 is not operated is the first analog signal converted from the first digital signal output from the first DDS 41. The second DDS 42 may generate and output a second digital signal corresponding to the reduced signal based on the frequency and amplitude specified by the specifying unit 7.

  By doing so, the signal output device 1 generates the second digital signal based on the frequency and amplitude specified by the specifying unit 7 even when the parameter information is not stored in the storage unit 3 in advance. can do.

  The specifying unit 7 may specify a spurious signal having a frequency that is equal to or lower than the sampling frequency and having a relatively large amplitude among a plurality of spurious signals having a frequency within a predetermined range from the frequency of the output signal. Then, the specifying unit 7 may output, for each of the plurality of second DDSs 42, the second digital signal corresponding to the frequency of the spurious in order from the spurious having the relatively large amplitude. For example, when the specifying unit 7 specifies five spurs and there are only two second DDSs 42, the specifying unit 7 selects the second spurious corresponding to each of two spurs having a relatively large amplitude out of the five spurs. A digital signal may be output from the two second DDSs 42. By doing in this way, the signal output device 1 can preferentially reduce spurious that has a large influence on the output signal.

[Effect of this embodiment]
As described above, according to the present embodiment, the signal output device 1 is included in the first DDS 41 that generates and outputs the first digital signal corresponding to the predetermined frequency, and the first analog signal converted from the first digital signal. A second DDS 42 that generates and outputs a second digital signal corresponding to a reduced signal that reduces spurious at least one frequency, an adder 43 that adds the first digital signal and the second digital signal, and an adder 43 And a DA converter 5 that converts the digital signal added by the above to an analog signal and outputs the analog signal.

  The digital signal generated by adding the first digital signal and the second digital signal by outputting the second digital signal corresponding to the reduced signal of the frequency near the predetermined frequency from the second DDS 42 corresponds to the nearby frequency. This signal corresponds to an analog signal with reduced spurious. Therefore, the signal output device 1 can reduce the spurious of the frequency near the frequency of the output signal.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Signal output device 2 Divider 3 Memory | storage part 4 Digital signal processing circuit 5 DA converter 6 Low pass filter 7 Specific | specification part 40 External interface 41 1st DDS
42 Second DDS
43 Adder 44 Selector 411 Phase Accumulator 412 Adder 413 Waveform Signal Generation Unit 413, 423 Waveform Signal Generation Unit 414 Multiplier 414, 424 Multiplier 415, 416, 425 Rounding Processing Unit 421 Phase Accumulator 422 Adder 423 Waveform Signal Generation Unit 426 Level converter

Claims (7)

A first direct digital synthesizer that generates and outputs a first digital signal corresponding to a predetermined frequency;
A second direct digital synthesizer that generates and outputs a second digital signal corresponding to a reduced signal that reduces spurious at least one frequency included in the first analog signal converted from the first digital signal;
An adder for adding the first digital signal and the second digital signal;
A DA converter that converts the added digital signal added by the adder into an analog signal and outputs the analog signal;
A signal output device comprising: The second direct digital synthesizer generates and outputs the second digital signal corresponding to the reduced signal having the same frequency as the spurious and a phase different from the spurious.
The signal output device according to claim 1. The second direct digital synthesizer generates and outputs the second digital signal corresponding to the reduced signal having a predetermined proportion of the amplitude of the spurious;
The signal output device according to claim 1 or 2. A plurality of second direct digital synthesizers that generate and output the second digital signal corresponding to each of a plurality of spurious included in the first analog signal;
The adding unit adds the first digital signal and the plurality of second digital signals;
The signal output device according to any one of claims 1 to 3. A specifying unit that specifies a frequency and an amplitude of the spurious included in the first analog signal;
The second direct digital synthesizer generates and outputs the second digital signal corresponding to the reduced signal based on the frequency and amplitude specified by the specifying unit.
The signal output device according to claim 1. A bit width converter that reduces the bit width of the added digital signal added by the adder;
The DA conversion unit converts the rounded addition digital signal after the bit width is reduced by the bit width conversion unit into the analog signal.
The signal output device according to any one of claims 1 to 5. A level converter for increasing the value of the second digital signal;
A display control unit for displaying the second digital signal on the display unit after the level conversion unit is enlarged;
Further having
The signal output device according to any one of claims 1 to 6.