JP2018101870A - Digital filter, reciprocal count rate creation circuit, and physical quantity sensor - Google Patents

Abstract

A digital filter, a reciprocal count value generation circuit, and a physical quantity sensor capable of reducing a circuit scale and reducing power consumption are provided. A digital filter for processing a frequency delta-sigma modulated delta-sigma modulated signal, comprising a plurality of filters including at least one moving average filter, and outputting from a predetermined one of the plurality of filters The digital filter is configured such that the bit width of the first signal is smaller than the bit width of the second signal processed by the predetermined filter by reducing the bits including the least significant bit. . Further, it is preferable that a signal output from at least one of the plurality of filters is down-sampled. [Selection] Figure 1

Description

  The present invention relates to a digital filter, a reciprocal count value generation circuit, and a physical quantity sensor.

  There is known a frequency delta-sigma modulation signal output device that generates a delta-sigma modulation signal that is a signal corresponding to a ratio between a frequency of a reference signal (reference clock) and a frequency of a signal under measurement.

  The frequency delta sigma modulation signal output device has a frequency delta sigma modulation unit (hereinafter referred to as “FDSM (Frequency Delta Sigma Modulator)”), and the signal under measurement is frequency delta sigma modulated using the reference signal by the FDSM. Then, a delta-sigma modulated signal is generated and output.

  Patent Document 1 discloses a frequency measurement device including an FDSM and a low-pass filter unit. In this device, the configuration of the low-pass filter unit is simplified to reduce power consumption.

JP 2011-80836 A

  In the device described in Patent Document 1, no consideration is given to the bit width of the signal, and there is room for improvement in terms of circuit scale and power consumption.

  An object of the present invention is to provide a digital filter, a reciprocal count value generation circuit, and a physical quantity sensor that can reduce the circuit scale and power consumption.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

The digital filter of the present invention is a digital filter for processing a frequency delta-sigma modulated delta-sigma modulated signal,
Comprising a plurality of filters including at least one moving average filter;
The bit width of the first signal output from the predetermined filter of the plurality of filters is the bit width of the second signal processed by the predetermined filter by reducing bits including the least significant bit. It is characterized by being configured smaller than.

  In the present invention, a necessary and sufficient bit width output can be obtained with a simple and small-scale configuration so as not to impair the first-order noise shaping function which is one of the characteristics of the frequency delta-sigma modulator. In addition, power consumption can be reduced. In addition, since the primary noise shaping function is exhibited, the noise can be effectively shifted to the high frequency side, whereby the noise component can be reduced by the digital filter and the accuracy can be improved. it can.

In the digital filter of the present invention, it is preferable that a signal output from at least one of the plurality of filters is down-sampled.
Thereby, power consumption can be reduced by lowering the operating speed.

In the digital filter of the present invention, the plurality of filters are electrically connected in series,
It is preferable that a bit width of a signal input to the first-stage filter among the plurality of filters is smaller than a bit width necessary for expressing an absolute value of a signal input to the first-stage filter.

  As a result, the required bit width can be reduced while maintaining the primary noise shaping effect.

In the digital filter of the present invention, it is preferable that a correction unit that corrects a signal output from the predetermined filter among the plurality of filters by a correction value is provided.
As a result, the dynamic range can be increased.

  In the digital filter of the present invention, it is preferable that all of the plurality of filters are moving average filters.

  As a result, a digital filter capable of obtaining an output having a necessary and sufficient bit width can be realized with a simple configuration so as not to impair the primary noise shaping function.

  In the digital filter of the present invention, the bit width of the first signal is preferably a multiple of four.

  As a result, a digital filter capable of obtaining an output having a necessary and sufficient bit width can be realized with a simple configuration so as not to impair the primary noise shaping function.

A reciprocal count value generation circuit of the present invention is a reciprocal count value generation circuit that counts a reference clock at a timing defined by a signal under measurement.
A reciprocal count value generation unit for generating a reciprocal count value;
And a digital filter according to the present invention.

  In the present invention, a necessary and sufficient bit width output can be obtained with a simple and small-scale configuration so as not to impair the first-order noise shaping function which is one of the characteristics of the frequency delta-sigma modulator. In addition, power consumption can be reduced. In addition, since the primary noise shaping function is exhibited, the noise can be effectively shifted to the high frequency side, whereby the noise component can be reduced by the digital filter and the accuracy can be improved. it can.

The physical quantity sensor of the present invention includes a detection unit that detects a physical quantity,
And a reciprocal count value generation circuit of the present invention to which the signal under measurement output from the detection unit is input.

  In the present invention, a necessary and sufficient bit width output can be obtained with a simple and small-scale configuration so as not to impair the first-order noise shaping function which is one of the characteristics of the frequency delta-sigma modulator. In addition, power consumption can be reduced. In addition, since the primary noise shaping function is exhibited, the noise can be effectively shifted to the high frequency side, whereby the noise component can be reduced by the digital filter and the accuracy can be improved. it can.

In the physical quantity sensor of the present invention, the physical quantity is preferably a physical quantity related to vibration.
Thereby, a physical quantity related to vibration can be detected with high accuracy.

1 is a block diagram showing a first embodiment of a reciprocal count value generation circuit of the present invention. FIG. It is a block diagram which shows the digital filter of the reciprocal count value generation circuit shown in FIG. 3 is a timing chart for explaining the operation of the reciprocal count value generation circuit shown in FIG. 1. It is a block diagram which shows 2nd Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows 3rd Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows 4th Embodiment of the reciprocal count value generation circuit of this invention. FIG. 7 is a block diagram showing a delay circuit of the reciprocal count value generation circuit shown in FIG. 6. FIG. 7 is a block diagram showing a sampling rate conversion circuit of the reciprocal count value generation circuit shown in FIG. 6. It is a figure for demonstrating operation | movement of the sampling rate conversion circuit of the reciprocal count value generation circuit shown in FIG. It is a figure for demonstrating operation | movement of the sampling rate conversion circuit of the reciprocal count value generation circuit shown in FIG. It is a figure which shows the internal structure of the detection part in embodiment of the acceleration sensor which is an example of the physical quantity sensor of this invention. It is sectional drawing in the AA line in FIG.

  Hereinafter, a digital filter, a reciprocal count value generation circuit, and a physical quantity sensor of the present invention will be described in detail based on embodiments shown in the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of a reciprocal count value generation circuit according to the present invention. FIG. 2 is a block diagram showing a digital filter of the reciprocal count value generation circuit shown in FIG. FIG. 3 is a timing chart for explaining the operation of the reciprocal count value generation circuit shown in FIG. In FIG. 1, buses in the circuit are indicated by bold lines (the same applies to other drawings).

  In the drawings, the signal under measurement is described as “Fx” and the reference clock (reference signal) is described as “Fs” (the same applies to the drawings of other embodiments).

  In the drawings, subscripts (0, 1,..., 31) are added to “Fx” in order to distinguish the signals under measurement having different phases (the same applies to the drawings of other embodiments).

  In the drawing, a signal output from each latch 31 is described as “S”, and a subscript (0, 1,..., 31) is added to distinguish each signal (another implementation). The same applies to the drawings in the form)

In the following description, a signal obtained by changing the phase of the signal under measurement is also referred to as a “signal under measurement”.
Further, the case where the signal level is “Low” is also referred to as “0”, and the case where the signal level is “High” is also referred to as “1”.

  Also, inversion of the signal, only the rising edge of the signal, that is, the case where the signal changes from “0” to “1”, and the falling edge of the signal, that is, the signal changes from “1” to “0”. Only the case, and both the rising and falling edges of the signal, that is, the case where the signal changes from “0” to “1” and the case where the signal changes from “1” to “0”. included.

  The signal inversion edge is a part representing the inversion of the signal level. As described above, the signal inversion edge represents only the rising edge of the signal and only the falling edge of the signal. , Representing both the rising and falling edges (both edges) of the signal.

  However, in the following description, each of the reference clock (reference signal) and the signal under measurement will be described by taking one of them as an example. In this embodiment, for each of the reference clock and the signal under measurement, the inversion of the signal is both the rise and fall of the signal.

  That is, in the present embodiment, the counter 3 (first counter) detects the inversion edge using the rising edge and falling edge of the reference clock (Fs), and the counter 11 (second counter) The reference clock (Fs) is counted using the rising edge and falling edge of the reference clock (Fs).

  This effectively counts twice the frequency and improves the S / N ratio.

  More specifically, the reciprocal count value generation circuit 1 of the present embodiment detects the rising and falling edges of the reference clock (Fs), and outputs a pulse signal (P) synchronized with the rising and falling edges of the reference clock (Fs). An edge detection unit 9 which is an example of a detection circuit to be generated is provided. The counter 3 (first counter) detects the inverted edge using the pulse signal (P) generated by the edge detection unit 9, and the counter 11 (second counter) detects the edge detection unit 9 The reference clock (Fs) is counted using the pulse signal (P) generated in step (1).

  As a result, the double frequency is effectively counted with a simple configuration, and the SN ratio can be improved. This will be specifically described below.

  The reciprocal count value generation circuit 1 (reciprocal count value generation device) shown in FIG. 1 has a value corresponding to the ratio between the frequency of the reference clock (reference signal) Fs whose frequency is known and the frequency of the signal to be measured Fx (or the above-mentioned It is a circuit (apparatus) that generates a reciprocal count value (a signal indicating a reciprocal count value), which is a value used to generate a value. The reciprocal count value generation circuit 1 employs a reciprocal count method, uses a signal under measurement as an operation clock, and the frequency of the signal under measurement is lower than the frequency of the reference clock.

  First, an outline of the reciprocal count value generation circuit 1 will be briefly described in accordance with the scope of claims, and then described in detail.

  The reciprocal count value generation circuit 1 is a circuit (reciprocal count value generation circuit) that counts the reference clock (Fs) at a timing defined by the signal under measurement (Fx), and a reciprocal count value generation unit that generates a reciprocal count value. 10 and a digital filter 6. According to the reciprocal count value generation circuit 1, a digital filter 6 to be described later can be obtained with a simple configuration so as to obtain an output having a necessary and sufficient bit width so as not to impair the primary noise shaping function. The effect described in the description of can be obtained.

  In this embodiment, the reciprocal count value generation circuit 1 is a circuit that counts the reference clock (Fs) at a timing defined by the signal under measurement (Fx). The reciprocal count value generation circuit 1 is electrically connected in parallel, and a plurality of signals under measurement (Fx) having different phases are respectively input thereto, and a plurality of signals under measurement (Fx) using a reference clock (Fs). A plurality of counters 3 as an example of a plurality of first counters for detecting an inversion edge representing inversion of a level of the counter, a counter 11 as an example of a second counter for counting a reference clock (Fs), and a counter And a reciprocal count value generation unit 10 that generates a reciprocal count value based on 11 count values and the like. Hereinafter, “electrically connected” is also simply referred to as “connection”.

  As an example of the reciprocal count value generation unit 10, for example, the number of inversion edges detected in the signal under measurement (Fx) at the timing specified by the reference clock (Fs), the count value of the counter 11 at the timing, Are integrated in the section defined by the signal under measurement (Fx) to generate a reciprocal count value.

  According to the reciprocal count value generation circuit 1, since the phases of the plurality of signals under measurement are made different, the power consumption can be reduced compared to the case where the phases of the plurality of reference clocks having high frequencies are made different. Further, by inputting signals under measurement having different phases to each counter 3, it is possible to suppress quantization noise caused by idle tones, thereby improving accuracy.

  Moreover, it is possible to count without leaking without a dead period, a primary noise shaping effect is obtained, and noise can be effectively shifted to the high frequency side. Thereby, the noise component can be reduced by the digital filter 6 provided on the output side, and the accuracy can be improved. In addition, the configuration and processing of the digital filter 6 can be simplified.

  The number of inversion edges detected in the signal under measurement is the total value of the number of rising edges and the number of falling edges of the signals under measurement. Thereby, since the effective input frequency of the signal under measurement is doubled, the SN ratio can be improved by the oversampling effect.

  The number of inversion edges detected in the signal under measurement is not limited to the total value, but may be the number of rising edges or the number of falling edges of signals in a plurality of signals under measurement. Thereby, the circuit configuration can be simplified. This will be specifically described below.

  The reciprocal count value generation circuit 1 includes an edge detector 9, a counter 11 as an example of a second counter, at least one delay element 12, and a plurality of counters 3 as an example of a plurality of first counters. A plurality of latches 13, a plurality of latches 14, an adder 4, and a digital filter 6. Each counter 3 is electrically connected in parallel. The number of delay elements 12 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is 32, and the number of delay elements 12 is 31. The number of latches 13 and 14 is equal to the number of counters 3 and is 32. The number of the counters 3 is not particularly limited as long as it is plural, but the upper limit can be set to about 1000, for example.

  The edge detector 9, the counter 11, the latches 14, the adder 4, and the digital filter 6 are connected in this order from the input side to the output side.

  In the present embodiment, the counter 3 includes a frequency delta sigma modulator (hereinafter referred to as “FDSM (Frequency Delta Sigma Modulator)”).

  That is, the counter 3 latches the signal under test Fx in synchronization with the rising edge and the falling edge of the reference clock (reference signal) Fs and outputs the first data, and the reference clock A latch 32 (second latch) that latches the first data and outputs the second data in synchronization with the rising edge and the falling edge, and calculates an exclusive OR of the first data and the second data. And an exclusive OR circuit 33 for generating output data. For example, a D latch or the like can be used as each of the latch 31 and the latch 32, and the latch 31 and the latch 32 include, for example, a D flip-flop circuit.

  The edge detection unit 9 includes a delay element 91 and an exclusive OR circuit 92. The output terminal of the delay element 91 is connected to one input terminal of the exclusive OR circuit 92. As the delay element 91, a buffer is used in the present embodiment.

  The output terminal of the edge detector 9 is connected to the input terminal of the counter 11, and the output terminal of the counter 11 is connected to the input terminal of each latch 14. The output terminal of the latch 14 is connected to the input terminal of the adder 4. As the counter 11, for example, an up counter can be used.

  The output terminals of the edge detector 9 are connected to the clock input terminals of the latches 31 and the latches 32 of the counters 3 and the clock input terminals of the latches 13, respectively. The output terminal of each latch 13 is connected to the clock input terminal of each latch 14.

  The output terminal of each counter 3 is connected to the input terminal of the latch 13 corresponding to the counter 3. The output terminal of each latch 13 is connected to the clock input terminal of the latch 14 corresponding to the latch 13. In addition, as the latch 13 and the latch 14, for example, a D latch or the like can be used.

  The delay element 12 has a function of delaying the signal under measurement, and is connected between the two counters 3 on the input side of the two adjacent counters 3. Therefore, the signal under measurement is input to the latch 31 of the predetermined counter 3, and the signal under measurement is delayed by the delay element 12 and input to the latch 31 of another counter 3. The signal is further delayed by the delay element 12 and input to the latch 31 of another counter 3. In the present embodiment, a buffer is used as the delay element 12.

Next, the digital filter 6 will be described.
First, an outline of the digital filter 6 will be briefly described in accordance with the scope of claims, and then described in detail.

  The digital filter 6 is a digital filter that processes a delta-sigma modulated signal subjected to frequency delta-sigma modulation. The digital filter 6 includes a plurality of filters including at least one moving average filter, and in this embodiment, moving average filters 61, 62, 63, 64, and 65 (see FIG. 2). In addition, in the present embodiment, the bit width (filter output bit width) of the first signal output from the moving average filter 65 (the signal output from the subtractor 653) is a predetermined filter among the plurality of filters. By reducing the bits including the least significant bit, the bit width (filtering bit width) of the second signal (the signal output from the adder 651) processed by the moving average filter 65 (predetermined filter) is reduced. Composed.

  This makes it possible to obtain a necessary and sufficient bit width output with a simple and small-scale configuration so as not to impair the first-order noise shaping function which is one of the features of the frequency delta-sigma modulator. , Power consumption can be reduced. In addition, since the primary noise shaping function is exhibited, it is possible to effectively shift noise to the high frequency side, thereby reducing noise components by the digital filter 6 and improving accuracy. Can do.

  Further, in the digital filter 6, a signal output from at least one moving average filter (filter) among the moving average filter 61 to the moving average filter 65 (a plurality of filters) is down-sampled (divided). In the present embodiment, the signals output from the moving average filters 62 and 64 are downsampled. Thereby, power consumption can be reduced by lowering the operating speed.

  In the digital filter 6, the moving average filter 61 to the moving average filter 65 (a plurality of filters) are electrically connected in series. That is, the moving average filters 61, 62, 63, 64, 65 are connected in order from the output side of the adder 4. The bit width of the signal input to the first-stage moving average filter 61 (filter) of the moving average filter 61 to the moving average filter 65 (multiple filters) is input to the first-stage moving average filter 61 (filter). Smaller than the bit width necessary for expressing the absolute value of the signal (the absolute value of the input signal). As a result, the required bit width can be reduced while maintaining the primary noise shaping effect.

  In addition, the digital filter 6 is an addition that is an example of a correction unit that performs correction using a correction value for a predetermined filter among a plurality of filters, in this embodiment, signals output from the moving average filters 61 and 65. A device 66 and an adder 67 are provided. As a result, the dynamic range can be increased.

  All of the plurality of filters (moving average filter 61 to moving average filter 65) included in the digital filter 6 are moving average filters. Thereby, it is possible to realize the digital filter 6 capable of obtaining an output having a necessary and sufficient bit width without impairing the primary noise shaping function with a simple configuration.

  In the digital filter 6, the bit width of the first signal is a multiple of four. Thereby, it is possible to realize the digital filter 6 capable of obtaining an output having a necessary and sufficient bit width without impairing the primary noise shaping function with a simple configuration. This will be specifically described below.

  As shown in FIG. 2, the digital filter 6 includes a plurality of, in this embodiment, five (five stages) moving average filters 61, 62, 63, 64 and 65, and a plurality of, in this embodiment, two additions. Instruments 66 and 67. Each of the moving average filters 61 to 65 is an example of a filter.

  Further, the moving average filter 61, the adder 66, the moving average filter 62, the moving average filter 63, the moving average filter 64, the moving average filter 65, and the adder 67 are arranged on the input side (of the adder 4). They are connected in series in this order from the output side to the output side.

  The number of filters included in the digital filter 6 is five in the present embodiment, but is not limited thereto, and may be two, three, four, or six or more.

  In the present embodiment, all of the plurality of filters included in the digital filter 6 are moving average filters. However, the present invention is not limited to this, and at least one of the plurality of filters included in the digital filter 6 may be a moving average filter. That's fine. In this case, as a filter that is not a moving average filter among the plurality of filters, for example, another low-pass filter or the like can be used.

  First, the first-stage (first-stage) moving average filter 61 includes a shift register 611 and a subtractor 612. The shift register 611 has a function of storing and outputting 48 previous data. The “48” is an example, and may be set to other numbers.

  The output terminal of the adder 4 is connected to the input terminal of the shift register 611 of the moving average filter 61 and the input terminal on the plus side of the subtractor 612, respectively.

  The output terminal of the shift register 611 is connected to the negative input terminal of the subtractor 612.

  The subtracter 612 subtracts the previous 48 data from the current data. Each piece of data is the total sum of the accumulated reciprocal count values indicated by the signal output from the adder 4. As a result, the subtracter 612 obtains data obtained by adding 48 pieces of data indicating the sum of the reciprocal count values. The reason will be described below.

  First, assuming that 48 pieces of data indicating the sum of the reciprocal count values are Yi (i is an integer of 1 to 48), the Yi is represented by “(Di−1) − (Di)”. D0 is data indicating the sum of the current accumulated reciprocal count values, D1 is data indicating the sum of the previous accumulated reciprocal count values,..., D48 is accumulated 48 times earlier. It is data which shows the sum total of a reciprocal count value.

  Data obtained by adding 48 data indicating the sum of the reciprocal count values is “[(D0) − (D1)] + [(D1) − (D2)] +... + [(D47) − (D48]. When it is calculated, it becomes “(D0) − (D48).” This is the sum of the 48 accumulated previous reciprocal count values from the data indicating the sum of the current accumulated reciprocal count values. This is data obtained by subtracting the data indicating.

  The output terminal of the subtractor 612 is connected to one input terminal of the adder 66, and the output terminal of the adder 66 is connected to one input terminal of an adder 621 of the moving average filter 62 described later. . A predetermined correction value (correction data) is input to the other input terminal of the adder 66. The adder 66 is an example of a correction unit, and the adder 66 performs rough correction, that is, coarse adjustment. In this embodiment, since the signal under measurement and a signal obtained by dividing the signal under measurement are used as the operation clock, the frequency of the operation clock varies. For this reason, this correction can prevent an unnecessary carry of the signal accompanying fluctuations in the frequency of the operation clock. In this correction, for example, the correction value is set so that the center of the bit width of the signal output from the adder 66 becomes the center of the dynamic range.

  The second stage moving average filter 62 includes an adder 621, a shift register 622, and a subtractor 623. The shift register 622 has a function of storing and outputting 48 previous data. The “48” is an example, and may be set to other numbers. In the present embodiment, the adder 621 is a component of the moving average filter 62, but may be excluded from the components.

  The output terminal of the adder 621 is connected to the input terminal of the shift register 622, the positive input terminal of the subtractor 623, and the other input terminal of the adder 621, respectively.

  The adder 621 adds 48 pieces of data. The data is data indicated by a signal output from the adder 66. Thereby, data obtained by adding 48 pieces of data is obtained.

  The output terminal of the shift register 622 is connected to the negative input terminal of the subtractor 623. Since the subtractor 623 is the same as the subtractor 612, the description thereof is omitted.

  The output terminal of the subtracter 623 is connected to one input terminal of an adder 631 of the moving average filter 63 described later.

  The third stage moving average filter 63 includes an adder 631, a shift register 632, and a subtractor 633. The shift register 632 has a function of storing and outputting 48 previous data. The “48” is an example, and may be set to other numbers. In the present embodiment, the adder 631 is a component of the moving average filter 63, but may be excluded from the components.

  The output terminal of the adder 631 is connected to the input terminal of the shift register 632, the positive input terminal of the subtractor 633, and the other input terminal of the adder 631. Since the adder 631 is the same as the adder 621, the description thereof is omitted.

  The output terminal of the shift register 632 is connected to the negative input terminal of the subtractor 633. Since the subtractor 633 is the same as the subtractor 612, the description thereof is omitted.

  The output terminal of the subtractor 633 is connected to one input terminal of an adder 641 of the moving average filter 64 described later.

  The moving average filter 64 at the fourth stage includes an adder 641, a shift register 642, and a subtractor 643. The shift register 642 has a function of storing and outputting 48 previous data. The “48” is an example, and may be set to other numbers. In the present embodiment, the adder 641 is a component of the moving average filter 64, but may be excluded from the components.

  The output terminal of the adder 641 is connected to the input terminal of the shift register 642, the positive input terminal of the subtractor 643, and the other input terminal of the adder 641. Since the adder 641 is the same as the adder 621, the description thereof is omitted.

  The output terminal of the shift register 642 is connected to the negative input terminal of the subtractor 643. Since the subtractor 643 is the same as the subtractor 612, description thereof is omitted.

  The output terminal of the subtractor 643 is connected to one input terminal of an adder 651 of the moving average filter 65 described later.

  The fifth-stage (final stage) moving average filter 65 includes an adder 651, a shift register 652, and a subtractor 653. The shift register 652 has a function of storing and outputting the previous four pieces of data. In addition, the number (in the present embodiment, “4”) of the number of previous samplings of data output from the shift register 652 is the number of shift registers 611, 622, 632, 642 (this embodiment). Then, it is smaller than “48”). Note that “4” is an example, and other numbers may be set. In the present embodiment, the adder 651 is a component of the moving average filter 65, but may be excluded from the components.

  The output terminal of the adder 651 is connected to the input terminal of the shift register 652, the positive input terminal of the subtractor 653, and the other input terminal of the adder 651. Since the adder 651 is the same as the adder 621, the description thereof is omitted.

  The output terminal of the shift register 652 is connected to the negative input terminal of the subtractor 653. Since the subtractor 653 is the same as the subtractor 612, description thereof is omitted.

  The output terminal of the subtracter 653 is connected to one input terminal of the adder 67. A predetermined correction value (correction data) is input to the other input terminal of the adder 67. The adder 67 is an example of a correction unit, and the adder 67 performs fine correction, that is, fine adjustment. By this correction, it is possible to prevent unnecessary carry of the signal accompanying fluctuations in the frequency of the operation clock. In this correction, for example, the correction value is set so that the center of the bit width of the signal output from the adder 67 becomes the center of the dynamic range. As a specific example, for example, when applied to an acceleration sensor, the respective corrections input to the adder 66 and the adder 67 so that the output when no acceleration is applied is as low as possible. Value is set.

  Each latch 14 and the adder 4 constitute a main part of the reciprocal count value generation unit 10. Further, the digital filter 6 may be included in the constituent elements of the reciprocal count value generation unit 10.

  The signal under measurement is input to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first delay element 12 among the plurality of delay elements 12. Yes.

  Further, the reference clock is supplied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. Have been entered.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
In the following description, for ease of understanding, an example is shown as the bit width (number of bits) and speed (frequency) of a predetermined signal, but the present invention is not limited to that example.

  As shown in FIG. 1, the signal under measurement is supplied to the input terminal of the latch 31 of the predetermined counter 3 of the plurality of counters 3 and the input terminal of the first delay element 12 of the plurality of delay elements 12. Each is entered.

  Further, the reference clock is supplied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. Is entered.

  The signal under measurement is delayed by the delay element 12 and input to the input terminal of the latch 31 of another counter 3. As a result, signals under measurement having the same frequency and different phases are input to the input terminals of the latches 31 of the counters 3 (see FIG. 3).

  The edge detector 9 detects the rising edge and the falling edge of the reference clock (Fs). That is, the edge detector 9 outputs a pulse signal (P) having a pulse synchronized with the rising edge of the reference clock (Fs) and a pulse synchronized with the falling edge of the reference clock (Fs).

  The pulse signal (P) output from the edge detection unit 9 is input to the counter 11, and the counter 11 counts the pulses of the pulse signal (P) output from the edge detection unit 9, and counts the pulses. Output the value.

  The pulse signal (P) is input to the clock input terminal of the latch 31 and the clock input terminal of the latch 32 of each counter 3 and the clock input terminal of the latch 13, respectively.

  In each counter 3, the latch 31 latches the signal under measurement (Fx0 to Fx31) in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detector 9). The first data is output, the latch 32 latches the first data in synchronization with the rising edge of the reference clock and outputs the second data, and the exclusive OR circuit 33 outputs the first data and the first data. The exclusive OR of the second data is calculated to generate output data and output it. In each counter 3, the latch 31 latches the signal under measurement in synchronization with the falling edge of the reference clock and outputs the first data, and the latch 32 synchronizes with the falling edge of the reference clock. The first data is latched to output the second data, and the exclusive OR circuit 33 calculates the exclusive OR of the first data and the second data to generate and output the output data. . That is, each counter 3 outputs “1” corresponding to the rise and fall of the signal under measurement, and “0” for the others.

  The signals output from the counters 3 are latched and output by the latch 13 in synchronization with the rising edge and falling edge of the reference clock.

  The count value output from the counter 11 is input to each latch 14. Each latch 14 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

  In the example shown in FIG. 3, the count value output from the latch 14 of a predetermined counter 3 among the counters 3 is “6” at the rising edge of the signal under measurement, and “34” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “6” and “34”, and the reciprocal count value is 28 (= 34−6).

  The count value output from the latch 14 of the other counter 3 is “7” at the rising edge of the signal under measurement, and “34” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “7” and “34”, and the reciprocal count value is 27 (= 34−7).

  The count value output from the latch 14 of the other counter 3 is “7” at the rising edge of the signal under measurement, and “35” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “7” and “35”, and the reciprocal count value is 28 (= 35−7).

  The count value output from the latch 14 of the other counter 3 is “10” at the rising edge of the signal under measurement and “37” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “10” and “37”, and the reciprocal count value is 27 (= 37−10).

  Next, the adder 4 adds the count value output from each latch 14 and outputs the result. This output is the sum of the accumulated reciprocal count values.

  Here, the reciprocal count value in this embodiment is a value corresponding to the output of one of the plurality of counters 3, and the rising edge of the reference clock included between the rising edge and the falling edge of the signal under measurement. Is the number of

  The sum of the reciprocal count values is a value obtained by summing up the reciprocal count values obtained from the outputs of all the counters 3.

  In addition, the reciprocal count value in the present invention is not limited to the reciprocal count value in the narrow sense in the present embodiment, but includes a sum of reciprocal count values, an integrated reciprocal count value, an integrated sum of reciprocal count values, and the like.

  Next, the signal output from the adder 4 is input to the digital filter 6. That is, as shown in FIG. 2, the signal output from the adder 4 is input to the input terminal of the shift register 611 of the moving average filter 61 and the input terminal on the plus side of the subtractor 612. The bit width (minimum unit) of the signal input to the moving average filter 61, the signal processed by the moving average filter 61, and the signal output from the moving average filter 61 are the same. The bit width is smaller than the bit width necessary for expressing the absolute value of the received signal (input signal absolute value). In this case, by expressing the change in the frequency of the signal input to the moving average filter 61, the bit width necessary for expressing the absolute value of the input signal can be reduced. That is, the bit width can be reduced so as not to impair the first-order noise shaping function, whereby the digital filter 6 can be reduced in size, and thus power consumption can be reduced.

  Here, the bit width (minimum unit) of the signal input to the moving average filter 61, the signal processed by the moving average filter 61, and the signal output from the moving average filter 61 is, for example, 20 bits (20 bits is 1). Example). The bit width necessary for expressing the absolute value of the input signal is, for example, 24 bits (24 bits are an example).

  The operation clock used in the circuit from the moving average filter 61 to the adder 631 of the moving average filter 63 is a signal synchronized with the rising edge and the falling edge of the signal under measurement (Fx), for example, 192 ksps (sample / S) The circuit is operated before and after.

  The operation clock used in the circuit from the circuit on the output side of the adder 631 of the moving average filter 63 to the adder 651 of the moving average filter 65 is synchronized with the rising edge and falling edge of the signal under measurement (Fx). This signal is obtained by dividing the signal and has a frequency lower than that of the operation clock used in the circuit from the moving average filter 61 to the adder 631 of the moving average filter 63. In other words, the signal output from the moving average filter 62 is downsampled. As a result, the operating speed can be reduced and the power consumption can be reduced. The operation clock used for the circuit from the circuit on the output side of the adder 631 of the moving average filter 63 to the adder 651 of the moving average filter 65 operates the circuit at around 96 ksps, for example.

  The operation clock used for the shift register 652 and the subtractor 653 of the moving average filter 65 further divides the signal obtained by dividing the signal synchronized with the rising edge and falling edge of the signal under measurement (Fx). The frequency is lower than the operation clock used for the circuit from the circuit on the output side of the adder 631 of the moving average filter 63 to the adder 651 of the moving average filter 65. In other words, the signal output from the moving average filter 64 is downsampled. As a result, the operating speed can be reduced and the power consumption can be reduced. The operation clock used for the shift register 652 and the subtracter 653 of the moving average filter 65 operates the circuit at around 3.2 ksps, for example. The 192 ksps, 96 ksps, and 3.2 ksps are each an example, and are appropriately set according to various conditions. Moreover, the place of a down sample is not limited to the said place, It sets suitably according to various conditions.

  Forty-eight previous data is output from the shift register 611, and the subtracter 612 subtracts the previous 48 data from the current data, thereby moving 48 data by averaging the 48 data. An average value (a value not divided by 48) is obtained, and the moving average value is output to the adder 66. In this way, the high frequency component is blocked or reduced by the moving average filter 61.

  In the adder 66, the data output from the subtracter 612 and the correction value (correction data) are added, that is, correction is performed and the addition value is output.

  Next, the signal output from the adder 66 is input to one input terminal of the adder 621 of the moving average filter 62, and the signal output from the adder 621 is the other input terminal of the adder 621. The adder 621 adds the data indicated by both signals. Then, the adder 621 finally adds 48 pieces of data and inputs them to the input terminal of the shift register 622 and the input terminal on the plus side of the subtractor 623, respectively. The bit width of the signal processed by the moving average filter 62 and the signal output from the moving average filter 62 are the same, and the bit of the signal processed by the moving average filter 61 and the signal output from the moving average filter 61 are the same. It is larger than the width, for example, 26 bits (26 bits is an example).

  Forty-eight previous data is output from the shift register 622, and the subtracter 623 subtracts the previous 48 data from the current data, thereby moving 48 data obtained by averaging the 48 data. An average value (value not divided by 48) is obtained, and the moving average value is output to the adder 631 of the moving average filter 63. In this way, the high frequency component is blocked or reduced by the moving average filter 62.

  Next, the signal output from the subtractor 623 is input to one input terminal of the adder 631 of the moving average filter 63, and the signal output from the adder 631 is input to the other input terminal of the adder 631. The adder 631 adds the data indicated by both signals. The adder 631 finally adds 48 pieces of data and inputs them to the input terminal of the shift register 632 and the input terminal on the plus side of the subtractor 633, respectively. The bit width of the signal processed by the moving average filter 63 and the signal output from the moving average filter 63 are the same, and the bit of the signal processed by the moving average filter 62 and the signal output from the moving average filter 62 are the same. It is larger than the width, for example, 32 bits (32 bits is an example).

  Forty-eight previous data is output from the shift register 632, and the subtracter 633 subtracts the previous 48 data from the current data, thereby moving 48 data obtained by averaging the 48 data. An average value (value not divided by 48) is obtained, and the moving average value is output to the adder 641 of the moving average filter 64. In this way, the high frequency component is blocked or reduced by the moving average filter 63.

  Next, the signal output from the subtracter 633 is input to one input terminal of the adder 641 of the moving average filter 64, and the signal output from the adder 641 is input to the other input terminal of the adder 641. The adder 641 adds the data indicated by both signals. Then, the adder 641 finally adds 48 pieces of data and inputs them to the input terminal of the shift register 642 and the input terminal on the plus side of the subtractor 643, respectively. The bit width of the signal processed by the moving average filter 64 and the signal output from the moving average filter 64 are the same, and the bit of the signal processed by the moving average filter 63 and the signal output from the moving average filter 63 are the same. It is larger than the width, for example, 38 bits (38 bits is an example).

  Forty-eight previous data is output from the shift register 642, and the subtractor 643 subtracts the previous 48 data from the current data, thereby moving the 48 data obtained by averaging the 48 data. An average value (value not divided by 48) is obtained, and the moving average value is output to the adder 651 of the moving average filter 65. In this way, the high frequency component is blocked or reduced by the moving average filter 64.

  Next, the signal output from the subtractor 643 is input to one input terminal of the adder 651 of the moving average filter 65, and the signal output from the adder 651 is the other input terminal of the adder 651. The adder 651 adds the data indicated by both signals. The adder 651 finally adds 48 pieces of data and inputs them to the input terminal of the shift register 652 and the positive input terminal of the subtractor 653, respectively. The bit width of the signal (first signal) output from the moving average filter 65 is smaller than the bit width of the signal (second signal) processed by the moving average filter 65. In this case, the bit width is reduced by reducing the bits including the least significant bit of the signal processed by the moving average filter 65. As a result, the bit width can be reduced so as not to impair the primary noise shaping function, whereby the digital filter 6 can be reduced in size, thereby reducing power consumption. .

  In this embodiment, in the moving average filter 65 at the final stage, the bit width of the output signal is smaller than the bit width of the signal to be processed. Not only the average filter 65 but also other moving average filters may be used. A plurality of moving average filters among the moving average filters 61 to 65 may have the above relationship.

  The bit width of the signal processed by the moving average filter 65 is larger than the bit width of the signal processed by the moving average filter 64 and the signal output from the moving average filter 64.

  The bit width of the signal processed by the moving average filter 65 is, for example, 45 bits (45 bits is an example).

  The bit width of the signal output from the moving average filter 65 is, for example, a part of the 45 bits, that is, the upper n bits (n is a plurality of 2 or more). As a specific example, the upper 32 bits of the 45 bits (32 bits are an example). Furthermore, it is possible to reduce the upper bits of the 45 bits.

  The bit width of the signal (first signal) output from the moving average filter 65 is preferably a multiple of 4. Thereby, it is possible to realize the digital filter 6 capable of obtaining an output having a necessary and sufficient bit width without impairing the primary noise shaping function with a simple configuration.

  The shift register 652 outputs the previous 4 data, and the subtracter 653 subtracts the previous 4 data from the current data, thereby moving 4 data averaged. An average value (a value not divided by 4) is obtained, and the moving average value is output to the adder 67. In this way, the high frequency component is blocked or reduced by the moving average filter 65.

  In the adder 67, the data output from the subtracter 653 and the correction value (correction data) are added, that is, correction is performed and the addition value is output. This output is the sum of reciprocal count values (moving average value).

  As described above, according to the reciprocal count value generation circuit 1, since the phases of the plurality of signals under measurement are made different, the power consumption is reduced compared to the case where the phases of the plurality of reference clocks having high frequencies are made different. be able to.

  Further, by inputting signals under measurement having different phases to each counter 3, quantization noise caused by idle tones can be suppressed. Thereby, accuracy can be improved.

  Moreover, it is possible to count without leaking without a dead period, and a primary noise shaping effect is obtained. Thereby, noise can be effectively shifted to the high frequency side. Thus, the digital filter 6 can reduce noise components and improve accuracy. In addition, the configuration and processing of the digital filter 6 can be simplified.

  In addition, while the digital filter 6 has a simple and small-scale configuration, the digital filter 6 can obtain an output with a necessary and sufficient bit width so as not to impair the primary noise shaping function. Electric power can be reduced.

Further, modifications will be described below.
(1) The counter 3 and the counter 11 are not limited to the above-described configurations, and counters having other configurations can be used. Examples of other counters include a ripple counter and a free-run counter.
(2) The frequency of the signal under measurement may be higher than the frequency of the reference clock.

Second Embodiment
FIG. 4 is a block diagram showing a second embodiment of the reciprocal count value generation circuit of the present invention.

  Hereinafter, the second embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  In the second embodiment, for each of the reference clock and the signal under measurement, the inversion of the signal is both the rise and fall of the signal.

  As shown in FIG. 4, the reciprocal count value generation circuit 1 of the second embodiment includes an edge detector 9, a counter 11 as an example of a second counter, a latch 18, and at least one delay element (see FIG. Not shown), a counter 30 (one shown) as an example of a plurality of first counters, a plurality of latches 17 (one shown), a counting unit 19, a multiplier 25, and a counter 20 A latch 24, a latch 26, an adder 27, and a digital filter 6.

  In the present embodiment, the counter 30 is the same as the counter 3 for 32 in the first embodiment, and one counter indicates the counter 3 for 32 (having the function of the counter 3 for 32). doing). That is, the counter 30 includes 32 latches (not shown) corresponding to the 32 latches 31 of the first embodiment, 32 latches 32 (only one is shown in the figure), and the first embodiment. 32 exclusive OR circuits 330 (only one is shown in the figure) corresponding to the 32 exclusive OR circuits 33 of the embodiment. Similarly, the latches 17 are the same as the 32 latches 14 of the first embodiment, and one latch 32 indicates the latches 14 (having the function of the 32 latches 14). ) Therefore, the description of the counter 30 and the latch 17 is omitted.

  The counter 30, the latch 17, the counting unit 19, the multiplier 25, and the adder 27 are connected in this order from the input side to the output side. The counting unit 19 has a function of counting “1” bits.

  The edge detection unit 9, the counter 11, the latch 18, and the multiplier 25 are connected in this order from the input side to the output side.

  The counter 20 and the latch 24 are connected in this order from the input side to the output side.

  Although not shown, a plurality of (31 in this embodiment) delay elements are connected to the input side of the counter 30 as in the first embodiment.

  The counter 20 includes a latch 21, a latch 22, and an exclusive OR circuit 23, and is configured in the same manner as the counter 3 of the first embodiment. The signal under measurement is input to the input terminal of the latch 21 of the counter 20.

  Further, as the latch 17, the latch 18, the latch 21, the latch 22, and the latch 26, for example, a D latch or the like can be used.

  Further, the output terminals of the edge detector 9 are clock input terminals of latches not shown and clock inputs of the latches 32 corresponding to the latches 31 of the counter 30 of the second embodiment, input terminals of the counter 11, and A clock input terminal of the latch 18, a clock input terminal of the latch 26, a clock input terminal of each latch 17, a clock input terminal of the latch 21 of the counter 20 and a clock input terminal of the latch 22, and a clock input terminal of the latch 24 Are connected to each other.

  The output terminal of the counter 11 is connected to the input terminal of the latch 18. The output terminal of the latch 18 is connected to one input terminal of the multiplier 25. Further, the output terminal of the counting unit 19 is connected to the other input terminal of the multiplier 25.

  The output terminal of the multiplier 25 is connected to one input terminal of the adder 27. The output terminal of the adder 27 is connected to the input terminal of the latch 26, and the output terminal of the latch 26 is connected to the other input terminal of the adder 27. The output terminal of the latch 24 is connected to the reset terminal of the adder 27.

  The output terminal of the adder 27 is connected to the input terminal of the shift register 611 of the moving average filter 61 of the digital filter 6 and the input terminal on the plus side of the subtractor 612 (FIG. 2, FIG. 2). 4). Since the digital filter 6 is the same as that of the first embodiment, the description thereof is omitted.

  Further, the reference clock is supplied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. Have been entered.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 4, the process is the same as in the second embodiment until halfway, and “1” is output from the exclusive OR circuit 330 of the counter 30 corresponding to the rise and fall of the signal under measurement. Otherwise, “0” is output.

  The pulse signal output from the edge detection unit 9 and having a pulse synchronized with the rising edge of the reference clock and a pulse synchronized with the falling edge of the reference clock is supplied to the counter 11, the clock input terminal of the latch 18, and the latch 26. Are input to a clock input terminal of the latch 17, a clock input terminal of the latch 17, a clock input terminal of the latch 21 of the counter 20, a clock input terminal of the latch 22, and a clock input terminal of the latch 24, respectively.

  The signals output from the counter 30 are latched and output by the latch 17 in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detector 9).

  Next, the counting unit 19 counts “1” bits of the signal output from the counter 30. That is, the number of “1” s of the signal output from the counter 30 at each count value of the counter 11 is counted.

  The count value output from the counter 11 is input to the latch 18. The latch 18 latches and outputs the count value in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9).

  Next, the multiplier 25 multiplies the numerical value output from the counting unit 19 and the count value of the counter 11 output from the latch 18 and outputs the multiplied value. This multiplication value is input to one input terminal of the adder 27.

  In the counter 20, the latch 21 latches the signal under measurement in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9) and outputs the first data, The latch 22 latches the first data in synchronization with the rising edge and falling edge of the reference clock and outputs the second data, and the exclusive OR circuit 23 outputs the first data and the second data. An exclusive OR is calculated and output data is generated and output. That is, the counter 20 outputs “1” corresponding to the rise and fall of the signal under measurement, and outputs “0” for the others.

  The signal output from the counter 20 is latched by the latch 24 in synchronization with the rising edge and falling edge of the reference clock, output, and input to the reset terminal of the adder 27.

  The multiplication value output from the multiplier 25 is input to one input terminal of the adder 27. The output of the adder 27 is latched and output by the latch 26 in synchronization with the rising edge and falling edge of the reference clock, and input to the other input terminal of the adder 27.

  The adder 27 adds the current multiplication value and the previous multiplication value latched in the latch 26 and outputs the result. This output is the sum of the accumulated reciprocal count values.

  Next, the signal output from the adder 27 is input to the digital filter 6. In the digital filter 6, the processing described in the first embodiment is performed, and a signal indicating the sum of reciprocal count values (moving average value) is output from the digital filter 6.

  According to the second embodiment as described above, the same effect as that of the above-described embodiment can be exhibited.

<Third Embodiment>
FIG. 5 is a block diagram showing a third embodiment of the reciprocal count value generation circuit of the present invention.

  Hereinafter, the third embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  In the third embodiment, for each of the reference clock and the signal under measurement, signal inversion is both rising and falling of the signal.

  A reciprocal count value generation circuit 1 according to the third embodiment detects a rising edge and a falling edge of a reference clock (Fs) and generates a pulse signal (P) synchronized with the rising edge and the falling edge of the reference clock (Fs). An edge detection unit 9 is provided as an example. The counter 110, which is an example of the second counter, includes a first count unit 111 that counts the rising edge of the reference clock (Fs) and a second counting unit 112 that counts the falling edge of the reference clock (Fs). And. The counter 3 (first counter) detects the inverted edge using the pulse signal (P) detected by the edge detection unit 9, and the counter 110 (second counter) detects the reference clock (Fs). ), The first count unit 111 counts the rising edge of the reference clock (Fs), and the second counting unit 112 counts the falling edge of the reference clock (Fs).

  As a result, the double frequency is effectively counted with a simple configuration, and the SN ratio can be improved. This will be specifically described below.

  As shown in FIG. 5, the reciprocal count value generation circuit 1 according to the third embodiment includes an edge detection unit 9, a counter 110 that is an example of a second counter, at least one delay element 12, and a plurality of first count elements. 1 includes a plurality of counters 3, a plurality of latches 13, a plurality of latches 141, a plurality of latches 142, an adder 4, and a digital filter 6. Each counter 3 is electrically connected in parallel. The number of delay elements 12 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is 32, and the number of delay elements 12 is 31. The number of latches 13, latch 141, and latch 142 is 32, which is equal to the number of counters 3, respectively.

  Note that the edge detector 9, each delay element 12, and each counter 3 are the same as those in the first embodiment, and a description thereof will be omitted.

  The counter 110 includes a first count unit 111, a second count unit 112, and an inverter 113 (phase inversion circuit). The second count unit 112 is connected to the output side of the inverter 113. And the series circuit comprised by the inverter 113 and the 2nd count part 112 and the 1st count part 111 are connected in parallel. The output terminal of the first count unit 111 is connected to the input terminal of each latch 141, and the output terminal of the second count unit 112 is connected to the input terminal of each latch 142. The output terminal of each latch 141 and the output terminal of each latch 142 are connected to the input terminal of the adder 4, respectively. Further, as the first count unit 111 and the second count unit 112, for example, an up counter can be used, for example.

  The output terminals of the edge detector 9 are connected to the clock input terminals of the latches 31 and the latches 32 of the counters 3 and the clock input terminals of the latches 13, respectively.

  The output terminal of each counter 3 is connected to the input terminal of the latch 13 corresponding to the counter 3. The output terminal of each latch 13 is connected to the clock input terminal of the latch 141 corresponding to the latch 13 and the clock input terminal of the latch 142, respectively. Further, as the latch 13, the latch 141, and the latch 142, for example, a D latch or the like can be used.

  The output terminal of the adder 4 is connected to the input terminal of the shift register 611 of the moving average filter 61 of the digital filter 6 and the input terminal on the plus side of the subtractor 612 (FIGS. 2 and 2). 4). Since the digital filter 6 is the same as that of the first embodiment, the description thereof is omitted.

  The signal under measurement is input to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first delay element 12 among the plurality of delay elements 12. Yes.

  The reference clock includes an input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9, the other input terminal of the exclusive OR circuit 92, and a counter 110. Are input to the input terminal of the first count unit 111 and the input terminal of the inverter 113, respectively.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 5, the process is the same as in the second embodiment until halfway, and each counter 3 outputs “1” corresponding to the rise and fall of the signal under measurement, and the others are “0”. Is output.

  On the other hand, the reference clock is input to the counter 110. The first count unit 111 counts the rising edge of the reference clock and outputs the count value of the rising edge of the reference clock.

  The phase of the reference clock is inverted by the inverter 113 and input to the second count unit 112. The second count unit 112 counts the rising edge of the inverted reference clock obtained by inverting the phase of the reference clock, that is, the falling edge of the reference clock, and outputs the count value of the falling edge of the reference clock.

  The signals output from each counter 3 are latched and output by the latch 13 in synchronization with the rising edge and falling edge of the reference clock.

  Further, the count value output from the first count unit 111 is input to each latch 141. Each latch 141 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

  Similarly, the count value output from the second count unit 112 is input to each latch 142. Each latch 142 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

  Next, the adder 4 adds the count value output from each latch 141 and each latch 142, and outputs it. This output is the sum of the accumulated reciprocal count values.

  Next, the signal output from the adder 4 is input to the digital filter 6. In the digital filter 6, the processing described in the first embodiment is performed, and a signal indicating the sum of reciprocal count values (moving average value) is output from the digital filter 6.

  According to the third embodiment as described above, the same effects as those of the above-described embodiment can be exhibited.

<Fourth embodiment>
FIG. 6 is a block diagram showing a fourth embodiment of the reciprocal count value generation circuit of the present invention. FIG. 7 is a block diagram showing a delay circuit of the reciprocal count value generation circuit shown in FIG. FIG. 8 is a block diagram showing a sampling rate conversion circuit of the reciprocal count value generation circuit shown in FIG. 9 and 10 are diagrams for explaining the operation of the sampling rate conversion circuit of the reciprocal count value generation circuit shown in FIG.

  In the drawing, the signal under measurement output from the AND circuit 57 (the signal under measurement immediately before being input to the latch 31) is described as “D”, and the signal output from the latch 31 is referred to as “S”. Describe. A plurality of Ds and a plurality of Ss are distinguished from each other by adding a suffix.

  A pulse signal having a pulse synchronized with the rising edge of the reference clock and a pulse synchronized with the falling edge of the reference clock is described as “P”.

  Hereinafter, the fourth embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  In the fourth embodiment, for each of the reference clock and the signal under measurement, signal inversion is both rising and falling of the signal.

  As shown in FIG. 6, the reciprocal count value generation circuit 1 of the fourth embodiment includes an edge detection unit 9, a counter 110 which is an example of a second counter, a delay circuit 50, and a plurality of first counters. Are a plurality of counters 3, a plurality of latches 13, a plurality of latches 141, a plurality of latches 142, an adder 4, a digital filter 6, and a sampling rate conversion circuit 500. Each counter 3 is electrically connected in parallel.

  That is, the reciprocal count value generation circuit 1 according to the present embodiment is the same as the reciprocal count value generation circuit 1 according to the third embodiment except that the plurality of delay elements 12 are replaced with the delay circuits 50 and the sampling rate conversion circuit 500 is provided. is there. The sampling rate conversion circuit 500 is connected to the output side of the digital filter 6. Therefore, in the fourth embodiment, the description of the same parts as those in the third embodiment will be omitted, and the delay circuit 50 and the sampling rate conversion circuit 500 will be mainly described.

First, the delay circuit 50 will be described.
As shown in FIG. 7, the delay circuit 50 generates a third signal based on the first signal generated based on the detected signal (Fx), which is an example of the trigger signal, and the second signal. The generated loop number control circuit 59 and the plurality of delay elements 51 are electrically connected in series, and a loop is formed by feeding back any one of the outputs of the plurality of delay elements 51 to form a third loop. Is provided with a loop circuit 58 for inputting the first signal to the first delay element 51, and a latch circuit 310 for latching output values of the plurality of delay elements 51 with a pulse signal (P) which is an example of a latch signal. The second signal is one of the outputs of the plurality of delay elements 51, that is, an input signal to the inverter 53 (or an output signal of the inverter 53). The loop circuit 58 stops the feedback when the number of loops of the loop circuit 58 reaches the specified number of loops. With such a configuration, the circuit scale can be reduced. That is, by repeating the loop of the loop circuit 58 a plurality of times, a function that is double the number of cycles can be exhibited without increasing the circuit scale. The signal output from the exclusive OR circuit 56 is an example of a first signal, and the signal output from the AND circuit 57 is an example of a third signal.

  In addition, the cycle number control circuit 59 includes a counter 54 (binary counter), a multiplexer 55, an exclusive OR circuit 56, and an AND circuit 57. As a result, the number of powers of 2 can be easily realized.

  The delay circuit 50 includes a selection unit 520 that selects a predetermined output (hereinafter, also referred to as “delay output”) from among the outputs of the plurality of delay elements 51, and the loop circuit 58 is controlled by the selection unit 520. The selected output is fed back. Thereby, the delay amount can be finely adjusted.

  Further, the time required for one loop of the loop circuit 58 is longer than the latch interval of the latch circuit 310. As a result, the phase at the time of latching of the latch circuit 310 does not advance by 360 ° or more, whereby the subsequent processing can be simplified. This will be specifically described below.

  The delay circuit 50 includes a plurality of delay elements 51, a latch circuit 310 having a plurality of latches 31, a plurality of switches 52, an inverter 53, a counter 54, a multiplexer 55, an exclusive OR circuit 56, And an AND circuit 57 (AND circuit). The counter 54, the multiplexer 55, the exclusive OR circuit 56, the AND circuit 57, each delay element 51, each switch 52, and the inverter 53 constitute the main part of the loop circuit 58. The The counter 54, the multiplexer 55, the exclusive OR circuit 56, and the AND circuit 57 constitute the main part of the cycle number control circuit 59.

  Each delay element 51 is electrically connected in series and has a function of delaying the signal under measurement. Accordingly, the signal under measurement is sequentially delayed by each delay element 51. As the delay element 51, a buffer is used in this embodiment.

  Further, the number of delay elements 51 is one less than the number of latches 31 (counter 3). In the present embodiment, the number of delay elements 51 is 31 and the number of latches 31, that is, the number of counters 3 is 32. Each latch 31 belongs to the delay circuit 50 and each counter 3.

  Each switch 52 is electrically connected in parallel. The number of switches 52 is the same as the number of latches 31 (counter 3). In the present embodiment, the number of switches 52 is 32. The 32 switches 52 constitute a main part of the selection unit 520.

  Further, the counter 54 is not particularly limited, and for example, a binary counter or the like can be used. The output terminal of the counter 54 is connected to the input terminal of the multiplexer 55. The multiplexer 55 is set with the number of delay circuit repetitions. The number of repetitions of the delay circuit is the number of times that the loop in the delay circuit 50 is cycled. In this embodiment, the count value input from the counter 54 to the multiplexer 55 is represented by an 8-bit signal, and the multiplexer 55 has a predetermined bit of the 8-bit signal input from the counter 54. Output the value. The predetermined bit output from the multiplexer 55 is set by a signal input to the selector (Sel) of the multiplexer 55. In the present embodiment, as an example, the predetermined bit set by the selector is 2 bits. In this case, the number of repetitions of the delay circuit is 4, and high and low are output twice with the inversion of the signal under measurement as a trigger.

  Further, the signal under measurement is input to one input terminal of the exclusive OR circuit 56, and the output terminal of the multiplexer 55 is connected to the other input terminal of the exclusive OR circuit 56.

  The output terminal of the exclusive OR circuit 56 is connected to one input terminal of the AND circuit 57, and the output terminal of the inverter 53 is connected to the input terminal of the counter 54 and the other input terminal of the AND circuit 57. Are connected to each other.

  The output terminal of the AND circuit 57 is connected to the input terminal of the first-stage delay element 51 among the plurality of delay elements 51, the input terminal of the corresponding latch 31, and the corresponding switch 52, respectively. Yes.

  The output terminals of the delay elements 51 are connected to the input terminals of the corresponding latches 31 and the corresponding switches 52, respectively.

  In addition, the pulse signal (P) is input to the clock input terminal of the latch 31 and the clock input terminal of the latch 32 of each counter 3 and the clock input terminal of the latch 113, respectively.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
In this embodiment, as an example, a case where the number of delay circuit repetitions is “4” will be described. The sampling rate conversion circuit 500 will be described in detail after this operation description.

  As shown in FIGS. 6 and 7, the signal under measurement (trigger signal) is input to the delay circuit 50. The reference clock includes an input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9, the other input terminal of the exclusive OR circuit 92, and a counter 110. Are input to the input terminal of the first count unit 111 and the input terminal of the inverter 113, respectively. A pulse signal (P) that is an example of a latch signal is input to the delay circuit 50. The pulse signal (P) is input to the clock input terminal of the latch 31 of each counter 3, the clock input terminal of the latch 32, and the clock input terminal of the latch 31.

First, the operation of the delay circuit 50 will be described.
As shown in FIG. 7, the signal under measurement is input to one input terminal of the exclusive OR circuit 56. In the initial state, for example, the count value output of the counter 54 is “0”, and the signal input from the multiplexer 55 to the other input terminal of the exclusive OR circuit 56 is the value of the lower second bit. A certain “0” is assumed.

  First, when the signal under measurement is “1”, the signal “1” is output from the exclusive OR circuit 56, and the signal “1” is input to one input terminal of the AND circuit 57. The signal output from the exclusive OR circuit 56 is an example of the first signal.

  In the initial state, for example, the signal input to the other input terminal of the AND circuit 57 is “1”. In this case, the signal “1” is output from the AND circuit 57. The signal output from the AND circuit 57 is an example of a third signal.

  One of the plurality of switches 52 is turned on (closed), and the other is turned off (open). Selection of ON / OFF of the switch 52 (which switch is to be turned ON) can be performed by operating an operation unit (not shown). By selecting whether the switch 52 is on or off, it is possible to set the time required for one loop of the loop circuit 58. That is, by selecting the switch 52 to be turned on, a predetermined signal under measurement (delayed output) is selected from among a plurality of signals under measurement (a plurality of delayed outputs) having different phases and fed back.

  It should be noted that the time required for one loop of the loop circuit 58 is preferably set longer than the latch interval of the latch circuit 310. As a result, the phase of the latch circuit 310 at the time of latching is prevented from being advanced by 360 ° or more, whereby the subsequent processing can be simplified.

  Next, the signal “1” output from the AND circuit 57 is inverted by the inverter 53 via the switch 52 that is turned on among the plurality of switches 52, and becomes “0”, and is input to the counter 54. Is done. The signal output from the AND circuit 57 and input to the inverter 53 is delayed by the delay element 51 disposed between the AND circuit 57 and the inverter 53, and the delay amount of the delay element 51 is The value depends on the number. The signal inverted by the inverter 53 is an example of the second signal.

  Next, the counter 54 counts and outputs the count value to the multiplexer 55 as an 8-bit signal. Since the signal input to the counter 54 is “0”, the count value is “0”. It is.

  Since the multiplexer 55 outputs the value of the lower-order second bit of the input signal, the signal “0” is output to the other input terminal of the exclusive OR circuit 56 here. As a result, the signal “1” is output from the exclusive OR circuit 56 and input to one input terminal of the AND circuit 57.

  The signal “0” output from the inverter 53 is input to the other input terminal of the AND circuit 57. As a result, a signal “0” is output from the AND circuit 57.

  Next, the signal “0” output from the AND circuit 57 is inverted by the inverter 53 via the switch 52 that is turned on among the plurality of switches 52 to become “1”, and is input to the counter 54. Is done. The counter 54 counts and outputs the count value “1” to the multiplexer 55 as an 8-bit signal.

  The multiplexer 55 outputs a lower second bit value of the input signal, that is, a signal “0”. As a result, the signal “1” is output from the exclusive OR circuit 56 and input to one input terminal of the AND circuit 57.

  The signal “1” output from the inverter 53 is input to the other input terminal of the AND circuit 57. As a result, a signal “1” is output from the AND circuit 57.

  Next, the signal “1” output from the AND circuit 57 is inverted by the inverter 53 via the switch 52 that is turned on among the plurality of switches 52, and becomes “0”, and is input to the counter 54. Is done. The counter 54 counts, but since the signal input to the counter 54 is “0”, the count value remains “1”. That is, the counter 54 outputs the count value “1” to the multiplexer 55 as an 8-bit signal.

  The multiplexer 55 outputs a lower second bit value of the input signal, that is, a signal “0”. As a result, the signal “1” is output from the exclusive OR circuit 56 and input to one input terminal of the AND circuit 57.

  The signal “0” output from the inverter 53 is input to the other input terminal of the AND circuit 57. As a result, a signal “0” is output from the AND circuit 57.

  Next, the signal “0” output from the AND circuit 57 is inverted by the inverter 53 via the switch 52 that is turned on among the plurality of switches 52 to become “1”, and is input to the counter 54. Is done. The counter 54 counts and outputs the count value “2” to the multiplexer 55 as an 8-bit signal.

  The multiplexer 55 outputs the value of the lower second bit of the input signal, that is, the signal “1”. As a result, the signal “0” is output from the exclusive OR circuit 56. As described above, the loop number of the loop of the loop circuit 58 becomes “4”, which is the prescribed number of times, the feedback of the signal under measurement (delayed output) is stopped, and the operation ends.

  In the present embodiment, the delay circuit 50 is configured such that the number of repetitions of the delay circuit can be set to any value of a power of 2, but is not limited thereto, and can be set to any value. May be.

  On the other hand, while the circuit of the loop circuit 58 is circulated, the signal under measurement output from the AND circuit 57 is inputted to the input terminal of the latch 31 of the predetermined (first stage) counter 3 among the plurality of counters 3. Each of the plurality of delay elements 51 is input to the input terminal of the first-stage delay element 51. Further, the signal under measurement is delayed by each delay element 51 as described above, and input to the input terminal of the latch 31 of each other counter 3.

  As a result, signals under measurement (D0 to D31) having the same frequency and different phases are input to the input terminals of the latches 31 of the counters 3. By circulating the loop of the loop circuit 58 once, 32 signals under measurement having the same frequency and different phases can be obtained. Further, in the present embodiment, by looping the loop of the loop circuit 58 four times, 128 signals under measurement having the same frequency and different phases (the number when one half cycle is one) are obtained. Note that the number of repetitions of the delay circuit can be arbitrarily set as described above. By repeating the loop of the loop circuit 58 N times (N is an integer of 1 or more), the frequency is the same and the phase is the same. (32 × N) different signals under measurement are obtained.

  The description of the subsequent operation is omitted, but the signal output from the adder 4 is input to the digital filter 6.

  Next, in the digital filter 6, the process described in the first embodiment is performed, and a signal indicating the sum of reciprocal count values (moving average value) is output from the digital filter 6.

  Next, the signal output from the digital filter 6 is processed by the sampling rate conversion circuit 500 to convert the sampling rate (frequency) and output from the sampling rate conversion circuit 500.

  In the above description, the case where the delay circuit repeat count of the delay circuit 50 is set to “4” has been described. However, the accuracy can be improved by increasing the delay circuit repeat count. That is, the accuracy can be increased as compared with a circuit having an equivalent circuit scale.

Next, the sampling rate conversion circuit 500 will be described.
As shown in FIG. 8, the sampling rate conversion circuit 500 has a sampling rate (sampling frequency) of a filter output value (signal output from the digital filter 6) obtained by filtering a delta-sigma modulated signal subjected to frequency delta-sigma modulation. ). The sampling rate conversion circuit 500 includes a weighting coefficient generation unit 501 for obtaining a weighting coefficient based on an output timing of the filter output value and a sampling timing, and a sampling value of the filter output value weighted using the weighting coefficient. And a sampling unit 502 that outputs as follows. Further, the sampling unit 502 outputs, as the sampling value, a value weighted by the ratio of the filter output value to the section defined by the sampling timing without a dead period.

  As a result, the effect of counting without leaking without dead time is prevented from being destroyed, the primary noise shaping effect can be maintained, and the noise can be effectively shifted to the high frequency side. Thus, the digital filter 6 can reduce noise components and improve accuracy. This will be specifically described below.

  The sampling rate conversion circuit 500 has a function of converting the sampling rate (sampling frequency) of the filter output value output from the digital filter 6.

  That is, the sampling rate conversion circuit 500 obtains the filter output value corresponding to the section immediately before the output timing at the output timing of the filter output value. Then, at the sampling timing, the sum of the filter output values weighted by the occupation time in the section immediately before the sampling timing is obtained as the sampling value.

  Hereinafter, the process of converting the sampling rate performed by the sampling rate conversion circuit 500 will be described with a specific example.

  When the frequency of the output timing of the filter output value (hereinafter also referred to as “filter output frequency (filter output rate)”) is fa and the sampling frequency (sampling rate) based on the sampling timing is fb, when fa> fb, A description will be given separately for the case of fa <fb.

(When fa> fb)
First, a case where “the output timing frequency of the filter output value is higher than the sampling frequency based on the sampling timing” will be described.

  As an advantage of fa> fb, the magnitude relationship between the filter output frequency and the sampling frequency is fixed as “the filter output frequency is higher”, so that each case is simplified.

As shown in FIG. 9, two adjacent sampling timings are t0 and t1 (where t0 <t1), and there is one output timing between the t0 and the t1, and the one output timing. Is ta, the filter output value at ta is Ya, the filter output value at the output timing next to ta is Yb, and the sampling value at t1 is s1, the s1 is the following (1) It is expressed by a formula.
s1 = (ta−t0) Ya + (t1−ta) Yb (1)
Thereby, the sampling rate of the filter output value can be accurately converted.

Two adjacent sampling timings are t2 and t3 (where t2 <t3), and there are two output timings between t2 and t3, and the two output timings are tc and td ( Where tc <td), the filter output value at tc is Yc, the filter output value at td is Yd, the filter output value at the output timing next to td is Ye, and the sampling value at t3 S3 is represented by the following formula (2).
s3 = (tc−t2) Yc + (td−tc) Yd + (t3−td) Ye (2)
Thereby, the sampling rate of the filter output value can be accurately converted.

This will be specifically described below.
As shown in FIG. 9, first, the output timings of the filter output values are sequentially set to ta, tb, tc, td, te, and tf.

The filter output values are sequentially set to Ya, Yb, Yc, Yd, Ye, and Yf.
Further, the sampling timing is sequentially set to t0, t1, t2, t3, and t4.
The sampling values are sequentially set to s0, s1, s2, s3, and s4.

  In such a case, there is one output timing between t0 and t1, between t1 and t2, and between t3 and t4. Therefore, for s1, s2, and s4, 1) The formula is applied.

  Since there are two output timings between t2 and t3, the above equation (2) is applied to s3.

  That is, each sampling value s1, s2, s3, s4 is represented as follows.

s1 = (ta−t0) Ya + (t1−ta) Yb
s2 = (tb−t1) Yb + (t2−tb) Yc
s3 = (tc−t2) Yc + (td−tc) Yd + (t3−td) Ye
s4 = (te−t3) Ye + (t4−te) Yf

  Here, (ta-t0), (t1-ta), (tb-t1), (t2-tb), (tc-t2), (td-tc), (t3-td), (te-t3) , (T4-te) is a weighting coefficient, and this weighting coefficient is obtained by the weighting coefficient generation unit 501. And the sampling part 502 calculates | requires and outputs the said sampling values s1-s4. That is, the sampling unit 502 outputs, as the sampling values s <b> 1 to s <b> 4, values that are weighted by the ratio of the filter output value to the section defined by the sampling timing without a dead period.

  Here, the “dead period” of “without dead period” refers to a period during which no counting is performed. Further, “absent” means substantially not, and if there is no count omission, for example, there may be a dead period of about 1%.

(When fa <fb)
Next, a case where “the output timing frequency of the filter output value is lower than the sampling frequency based on the sampling timing” will be described.

  As an advantage of fa <fb, the magnitude relationship between the filter output frequency and the sampling frequency is fixed as “the filter output frequency is lower”, so that each case is simplified.

As shown in FIG. 10, two adjacent sampling timings are t0 and t1 (where t0 <t1), and there is one output timing between the t0 and the t1, and the one output timing. Is ta, the filter output value at ta is Ya, the filter output value at the output timing next to ta is Yb, and the sampling value at t1 is s1, the s1 is the following (3) It is expressed by a formula.
s1 = (ta−t0) Ya + (t1−ta) Yb (3)
Thereby, the sampling rate of the filter output value can be accurately converted.

The two adjacent sampling timings are t2 and t3 (where t2 <t3), and there is no output timing between t2 and t3, and the filter at the output timing after t3. When the output value is Yc and the sampling value at t3 is s3, s3 is expressed by the following equation (4).
s3 = (t3-t2) Yc (4)
Thereby, the sampling rate of the filter output value can be accurately converted.

This will be specifically described below.
As shown in FIG. 10, first, the output timing of the filter output value is sequentially set to ta, tb, tc, and td.

The filter output values are sequentially set to Ya, Yb, Yc, and Yd.
Further, the sampling timing is sequentially set to t0, t1, t2, t3, and t4.
The sampling values are sequentially set to s0, s1, s2, s3, and s4.

  In such a case, there is one output timing between t0 and t1, between t1 and t2, and between t3 and t4. Therefore, for s1, s2, and s4, 3) The formula is applied.

  Since there is no output timing between t2 and t3, the above equation (4) is applied to s3.

  That is, each sampling value s1, s2, s3, s4 is represented as follows.

s1 = (ta−t0) Ya + (t1−ta) Yb
s2 = (tb−t1) Yb + (t2−tb) Yc
s3 = (t3-t2) Yc
s4 = (tc−t3) Yc + (t4−tc) Yd

  Here, (ta-t0), (t1-ta), (tb-t1), (t2-tb), (t3-t2), (tc-t3), (t4-tc) are weighting coefficients, The weighting coefficient is obtained by the weighting coefficient generation unit 501. And the sampling part 502 calculates | requires and outputs the said sampling values s1-s4. That is, the sampling unit 502 outputs, as the sampling values s <b> 1 to s <b> 4, values that are weighted by the ratio of the filter output value to the section defined by the sampling timing without a dead period.

  In the case of fa = fb, the processing can be included in either case of fa> fb or the case of fa <fb.

  According to the fourth embodiment as described above, the same effect as that of the above-described embodiment can be exhibited.

  In addition, by providing the delay circuit 50, the circuit scale can be reduced when achieving the same accuracy. That is, by repeating the loop of the loop circuit 58 a plurality of times, a function that is double the number of cycles can be exhibited without increasing the circuit scale.

  In addition, the sampling rate conversion circuit 500 can keep the effect of counting without leaking without dead time, and can maintain the primary noise shaping effect. Thereby, noise can be effectively shifted to the high frequency side. Thus, the digital filter 6 can reduce noise components and improve accuracy.

  The reason why the sampling rate conversion circuit 500 can improve the accuracy will be described below.

  First, a signal output from a frequency delta-sigma modulator (hereinafter referred to as a “DSM signal (Delta Sigma Modulation signal)”) is obtained when repeated counting (sampling) is performed without a dead period at a predetermined gate time. This corresponds to a count value column (data column). The noise included in the count value obtained in this case moves to the high frequency band due to the noise shaping effect. For this reason, by removing high frequency from the DSM signal, it is possible to accurately extract the signal component under measurement. A counter including such a frequency delta-sigma modulator has characteristics such that the resolution is improved as the sampling rate (sampling frequency) is increased.

  Here, in order to obtain the noise shaping effect, it is necessary that the count has no dead period. That is, when the count omission occurs, the noise shaping effect cannot be obtained. This count leak is observed as a disturbance.

  Therefore, when the sampling rate is converted, the data string before conversion and the data string after conversion need to be proportional (linear). That is, it is necessary to prevent unnecessary data from being mixed due to count leakage, double counting, and the like. The sampling rate conversion circuit 500 satisfies the above requirements, and therefore the above-described effects can be obtained.

<Embodiment of physical quantity sensor>
FIG. 11 is a diagram illustrating an internal structure of a detection unit in an embodiment of an acceleration sensor which is an example of the physical quantity sensor of the present invention. 12 is a cross-sectional view taken along line AA in FIG.

  Hereinafter, an embodiment of an acceleration sensor, which is an example of a physical quantity sensor, will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  As shown in FIGS. 11 and 12, the acceleration sensor 100 (physical quantity sensor) of the present embodiment includes a detection unit 200 that detects acceleration, which is an example of a physical quantity related to vibration, and a signal under measurement output from the detection unit 200. Is input to the reciprocal count value generation circuit 1 (see FIG. 1 and the like for the reciprocal count value generation circuit 1). The detection unit 200 and the reciprocal count value generation circuit 1 are electrically connected. Since the reciprocal count value generation circuit 1 has already been described, the description thereof is omitted.

  The detection unit 200 includes a flat base portion 210, a substantially rectangular flat plate-shaped movable portion 212 connected to the base portion 210 via a joint portion 211, and a physical quantity spanned between the base portion 210 and the movable portion 212. An acceleration detection element 213 that is an example of the detection element, and a package 220 that houses at least each of the above-described components are provided.

  The detection unit 200 is driven by a drive signal applied to the excitation electrode of the acceleration detection element 213 via the external terminals 227 and 228, the internal terminals 224 and 225, the external connection terminals 214e and 214f, the connection terminals 210b and 210c, and the like. The vibrating beams 213a and 213b of the acceleration detecting element 213 oscillate (resonate) at a predetermined frequency. And the detection part 200 outputs the resonance frequency of the acceleration detection element 213 which changes according to the applied acceleration as a to-be-measured signal (detection signal).

  This signal under measurement is input to the reciprocal count value generation circuit 1, and the reciprocal count value generation circuit 1 operates as described in the above embodiment.

  Moreover, although the number of the detection parts 200 is one in this embodiment, it is not restricted to this, For example, two or three may be sufficient. By providing three detection units 200 and making the detection axes of each detection unit 200 orthogonal (cross) each other, it is possible to detect the acceleration in the axial direction of each of the three detection axes orthogonal to each other.

  Even with the acceleration sensor 100 as described above, the reciprocal count value generation circuit 1 included in the acceleration sensor 100 can exhibit the same effects as those of the above-described embodiment. Thereby, the acceleration sensor 100 can detect the acceleration with high accuracy.

  The digital filter, the reciprocal count value generation circuit, and the physical quantity sensor of the present invention have been described based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each part has the same function. It can be replaced with one having any structure. Moreover, other arbitrary components may be added.

  Further, the present invention may be a combination of any two or more configurations (features) of the above embodiments.

  In the above embodiment, the acceleration sensor is described as an example of the physical quantity sensor. However, in the present invention, if the physical quantity sensor can detect a change in physical quantity as a frequency change, In addition, for example, a mass sensor, an ultrasonic sensor, an angular acceleration sensor, a capacitance sensor, and the like can be given.

  The physical quantity sensor of the present invention includes, for example, various electronic devices such as an inclinometer, a seismometer, a navigation device, an attitude control device, a game controller, a mobile phone, a smartphone, a digital still camera, and various moving bodies such as an automobile. It is possible to apply to. That is, according to the present invention, it is possible to provide an electronic device including the physical quantity sensor of the present invention, a moving object including the physical quantity sensor of the present invention, and the like.

  DESCRIPTION OF SYMBOLS 1 ... Reciprocal count value generation circuit, 3 ... Counter, 4 ... Adder, 9 ... Edge detection part, 10 ... Reciprocal count value generation part, 11 ... Counter, 12 ... Delay element, 13 ... Latch, 14 ... Latch, 17 ... Latch, 18 ... Latch, 19 ... Counter, 20 ... Counter, 21 ... Latch, 22 ... Latch, 23 ... Exclusive OR circuit, 24 ... Latch, 25 ... Multiplier, 26 ... Latch, 27 ... Adder, 30 ... Counter, 31 ... Latch, 310 ... Latch circuit, 32 ... Latch, 33 ... Exclusive OR circuit, 50 ... Delay circuit, 51 ... Delay element, 52 ... Switch, 520 ... Selection unit, 53 ... Inverter, 54 ... Counter 55 ... Multiplexer, 56 ... Exclusive OR circuit, 57 ... Logical product circuit, 58 ... Loop circuit, 59 ... Circuit control circuit, 500 ... Sample Great conversion circuit, 501... Weighting coefficient generation unit, 502... Sampling unit, 6... Digital filter, 61... Moving average filter, 611 ... shift register, 612 ... subtractor, 62 ... moving average filter, 621 ... adder, 622. Shift register, 623 ... subtractor, 63 ... moving average filter, 631 ... adder, 632 ... shift register, 633 ... subtractor, 64 ... moving average filter, 641 ... adder, 642 ... shift register, 643 ... subtractor, 65 ... Moving average filter, 651 ... Adder, 652 ... Shift register, 653 ... Subtractor, 66 ... Adder, 67 ... Adder, 91 ... Delay element, 92 ... Exclusive OR circuit, 100 ... Accelerometer, 110 ... counter, 111 ... first count unit, 112 ... second count unit, 1 DESCRIPTION OF SYMBOLS 3 ... Inverter, 141 ... Latch, 142 ... Latch, 200 ... Detection part, 210 ... Base part, 210b ... Connection terminal, 210c ... Connection terminal, 211 ... Joint part, 212 ... Movable part, 213 ... Acceleration detection element, 213a ... Vibration beam, 213b ... vibration beam, 214e ... external connection terminal, 214f ... external connection terminal, 220 ... package, 224 ... internal terminal, 225 ... internal terminal, 227 ... external terminal, 228 ... external terminal, 330 ... exclusive OR circuit

Claims (9)

A digital filter for processing a frequency delta-sigma modulated delta-sigma modulated signal,
Comprising a plurality of filters including at least one moving average filter;
The bit width of the first signal output from the predetermined filter of the plurality of filters is the bit width of the second signal processed by the predetermined filter by reducing bits including the least significant bit. A digital filter characterized by being made smaller.   The digital filter according to claim 1, wherein a signal output from at least one of the plurality of filters is down-sampled. The plurality of filters are electrically connected in series,
3. The bit width of a signal input to the first-stage filter among the plurality of filters is smaller than a bit width necessary for expressing an absolute value of a signal input to the first-stage filter. Digital filter.   4. The digital filter according to claim 1, further comprising: a correction unit configured to perform correction using a correction value on a signal output from the predetermined filter among the plurality of filters.   The digital filter according to claim 1, wherein all of the plurality of filters are moving average filters.   The digital filter according to any one of claims 1 to 5, wherein a bit width of the first signal is a multiple of four. A reciprocal count value generation circuit that counts a reference clock at a timing defined by a signal under measurement,
A reciprocal count value generation unit for generating a reciprocal count value;
A reciprocal count value generation circuit comprising: the digital filter according to claim 1. A detection unit for detecting a physical quantity;
A physical quantity sensor comprising: the reciprocal count value generation circuit according to claim 7, wherein the signal under measurement output from the detection unit is input.   The physical quantity sensor according to claim 8, wherein the physical quantity is a physical quantity related to vibration.

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