JP2018029136A - Nonvolatile memory element, and analog circuit with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory element having an excellent charge retention property which can reduce the variation of an electric characteristic, and an analog circuit with the nonvolatile memory element.SOLUTION: A nonvolatile memory element M includes a charge holding region 21, and an insulation 20 surrounding the entire surface of a charge holding region 21 and having halogen (for example, fluorine) distributed over at least a part of an area surrounding the entire surface.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a nonvolatile memory element and an analog circuit including the same.

  In general, in a semiconductor device incorporating a reference voltage generation circuit, a reference voltage Vref assumed at the time of design is a desired value due to manufacturing variations such as a threshold voltage Vth of each transistor constituting the reference voltage generation circuit and a resistance value of a resistance element. It may vary greatly without becoming. Therefore, a highly accurate reference voltage generation circuit is required for a semiconductor device that requires a stable reference voltage Vref. In semiconductor devices, in order to correct the reference voltage variation of the reference voltage generation circuit due to manufacturing variations, a number of spare transistors for adjusting the reference voltage by correcting the wiring layer are built in, or adjusted with a laser trimmer after manufacturing Or make it possible. However, when the reference voltage variation of the reference voltage generation circuit is corrected with such a configuration, an increase in the layout area of the reference voltage generation circuit and an increase in man-hours for voltage adjustment become problems. In order to solve this kind of problem, various reference voltage generation circuits have been proposed.

  Patent Document 1 describes a general reference voltage generation circuit. As a reference voltage generation circuit, the gate region and the drain region are connected by utilizing the constant current property of a depletion type MOSFET (metal-oxide film-semiconductor field effect transistor) in which the gate region G and the source region S are connected. In other words, a configuration has been proposed in which a voltage generated in an enhancement type MOSFET that operates at the constant current is used as a reference voltage Vref.

  FIG. 23 shows a general reference voltage generation circuit 100. The reference voltage generation circuit 100 includes a depletion type MOSFET (hereinafter referred to as “depletion type transistor”) Md and an enhancement type MOSFET (hereinafter referred to as “enhancement type transistor”) Me connected in series. The gate region G and the source region S of the depletion type transistor Md are connected. The gate region G and the drain region D of the enhancement type transistor Me are connected. Further, the gate region G and source region S of the depletion type transistor Md are connected to the gate region G and drain region D of the enhancement type transistor Me. A high voltage supply terminal Vdd is provided in the drain region D of the depletion type transistor Md, and a low voltage supply terminal Vss is provided in the source region S of the enhancement type transistor Me. In addition, a voltage output terminal OUT is provided at a connection point between the depletion type transistor Md and the enhancement type transistor Me. In the reference voltage generation circuit 100, the depletion type transistor Md and the enhancement type transistor Me are both N-channel type. The depletion type and the enhancement type are classified according to the relationship between the gate voltage and the drain current. In the depletion type, a channel exists and drain current flows when no gate voltage is applied to the gate region. On the other hand, in the enhancement type, when no gate voltage is applied to the gate region, no channel exists and no drain current flows.

  FIG. 24 is an example of the current / voltage characteristics of the depletion type transistor Md and enhancement type transistor Me provided in the reference voltage generation circuit 100. The horizontal axis represents the gate-source voltage Vgs between the gate region G and the source region S, and the vertical axis represents the drain current Ids. Since the depletion type transistor Md has the gate-source voltage Vgs fixed at 0 V, the drain current of the constant current Iconst flows as long as the drain-source voltage between the drain region D and the source region S is the saturation region. . The drain current of the constant current Iconst also flows through the enhancement type transistor Me connected in series to the depletion type transistor Md. Therefore, the gate-source voltage Vgs of the enhancement type transistor Me where Ids = Iconst can be taken out from the voltage output terminal OUT as the reference voltage Vref.

  When the threshold voltage of the depletion type transistor Md is represented by Vth_d and the threshold voltage of the enhancement type transistor Me is represented by Vth_e, the reference voltage Vref is the sum of the absolute value of the threshold voltage Vth_d and the absolute value of the threshold voltage Vth_e, that is, “Vref = | Vth_d | + | Vth_e | ”.

  However, the reference voltage generation circuit 100 is affected by manufacturing variations in the current / voltage characteristics of the depletion type transistor Md and the current / voltage characteristics of the enhancement type transistor Me. Therefore, Patent Documents 2 and 3 disclose a reference voltage generation circuit using an FET type nonvolatile memory element as a circuit that can extract a highly accurate reference voltage without being affected by manufacturing variations. The reference voltage generation circuit as disclosed in Patent Documents 2 and 3 has substantially the same configuration as the reference voltage generation circuit 100 shown in FIG. 23, and the depletion type transistor Md and the enhancement type transistor Me have nonvolatile storage. An element is used. The reference voltage generation circuits disclosed in Patent Documents 2 and 3 use the same type of non-volatile memory element and adjust the amount of charge injected into the floating gate region included in the non-volatile memory element, thereby reducing the depletion type MOSFET and the enhancement. A type MOSFET is formed. The nonvolatile memory element has a control gate region and a floating gate region, and the threshold voltage Vth can be controlled by injecting and discharging electrons into the floating gate region. For this reason, the reference voltage generation circuit can trim the threshold voltage Vth later even if manufacturing variations occur. Therefore, in this reference voltage generation circuit, the extracted reference voltage Vref is hardly affected by manufacturing variations.

Japanese Patent Publication No. 4-65546 JP 2002-368107 A JP 2013-246627 A

  However, since the reference voltage generation circuits disclosed in Patent Documents 2 and 3 use a nonvolatile memory element in an analog manner, they have a much higher charge than that used in a so-called nonvolatile memory such as an EEPROM. Retention characteristics are required. Further, when used in an analog circuit such as a reference voltage generation circuit, the layout size of the nonvolatile memory element (for example, the L size or W size of the FET) is also required to be variable depending on the application. For this reason, the flexibility of layout dimensions is required as compared with the case where it is used for a normal nonvolatile memory having a fixed layout. Flexibility of layout dimensions is a very difficult issue in securing the charge retention characteristics of nonvolatile memory elements from the viewpoint of manufacturing technology. Analogs of nonvolatile memory elements used in conventional nonvolatile memories are analog. There is a problem that it is difficult to apply to a circuit.

  An object of the present invention is to provide a nonvolatile memory element having excellent charge retention characteristics that can reduce variation in electrical characteristics, and an analog circuit including the nonvolatile memory element.

  In order to achieve the above object, a nonvolatile memory element according to one embodiment of the present invention includes a charge retention region and a halogen that surrounds the entire surface of the charge retention region and is distributed in at least a part of the region surrounding the entire surface. And an insulator having the following.

In order to achieve the above object, an analog circuit according to the first aspect of the present invention includes the nonvolatile memory element of the present invention.
An analog circuit according to the second aspect of the present invention includes a plurality of the nonvolatile memory elements according to the present invention, wherein at least some of the plurality of nonvolatile memory elements are connected in series, and the plurality of the nonvolatile memory elements are connected in series. A voltage output terminal from which a voltage is output is connected to the connection portion of the nonvolatile memory element.

  In order to achieve the above object, an analog circuit according to a third aspect of the present invention includes a gate region having the charge holding region and the insulator of the first nonvolatile memory element which is the nonvolatile memory element of the present invention. A second control gate region electrically connected to the first control gate region provided in the first non-volatile memory element and a first charge holding region electrically connected to the first charge holding region of the first nonvolatile memory element. A second nonvolatile memory element having a two charge holding region and a gate insulating film formed in contact with the second charge holding region, the charge injection port provided in the first nonvolatile memory element, It is formed in a region not in contact with a current path formed in the second nonvolatile memory element.

In order to achieve the above object, an analog circuit according to a fourth aspect of the present invention includes the nonvolatile memory element according to the present invention, and the area of the element of the nonvolatile memory element is 10 μm ² or more. The characteristic memory element does not have an array structure.

  According to each aspect of the present invention, it is possible to realize a nonvolatile memory element having excellent charge retention characteristics and an analog circuit including the nonvolatile memory element that can reduce variation in electrical characteristics.

1 is a cross-sectional view showing a schematic configuration of a nonvolatile memory element M according to a first embodiment of the present invention. FIG. 6 is a diagram for explaining a state of charge injection and charge discharge of the nonvolatile memory element M according to the first embodiment of the present invention. FIG. 6A is a manufacturing process sectional view (No. 1) of the nonvolatile memory element M according to the first embodiment of the present invention; FIG. 6A is a manufacturing process sectional view (No. 2) of the nonvolatile memory element M according to the first embodiment of the present invention; FIG. 7 is a manufacturing process sectional view (No. 3) of the nonvolatile memory element M according to the first embodiment of the present invention; FIG. 4D is a manufacturing process sectional view (No. 4) of the nonvolatile memory element M according to the first embodiment of the present invention; FIG. 9 is a manufacturing process sectional view (No. 5) of the nonvolatile memory element M according to the first embodiment of the present invention. FIG. 8A is a manufacturing process sectional view of the nonvolatile memory element M according to the first embodiment of the present invention (No. 6), and FIG. 8A is a manufacturing process sectional view of the nonvolatile memory element used as a depletion type transistor; FIG. 8B is a manufacturing process sectional view of the nonvolatile memory element used as the enhancement type transistor. FIG. 7D is a manufacturing process sectional view (No. 7) of the nonvolatile memory element M according to the first embodiment of the present invention. FIG. 9D is a manufacturing process sectional view (No. 8) of the nonvolatile memory element M according to the first embodiment of the present invention. FIG. 9 is a manufacturing process sectional view (No. 9) of the nonvolatile memory element M according to the first embodiment of the present invention. It is a graph which shows the statistical evaluation result for demonstrating the charge retention characteristic of the reference voltage generation circuit 1 using the non-volatile memory element M by 1st Embodiment of this invention. It is a figure which shows the analysis result of the fluorine distribution of the non-volatile memory element M by 1st Embodiment of this invention. 1 is a circuit configuration diagram for explaining a reference voltage generation circuit 1 as an analog circuit according to a first embodiment of the present invention. FIG. 1 is a circuit configuration diagram for explaining a reference voltage generation circuit 2 as an analog circuit according to a first embodiment of the present invention, and is a diagram for explaining a state in which the reference voltage generation circuit 2 outputs a reference voltage Vref. It is. FIG. 2 is a circuit configuration diagram for explaining a reference voltage generation circuit 2 as an analog circuit according to the first embodiment of the present invention, in which a nonvolatile memory element M1 on the upper stage side of the reference voltage generation circuit 2 is adjusted to a depletion state It is a figure for demonstrating. FIG. 2 is a circuit configuration diagram for explaining a reference voltage generation circuit 2 as an analog circuit according to the first embodiment of the present invention, in which a nonvolatile memory element M2 on the lower side of the reference voltage generation circuit 2 is adjusted to an enhancement state It is a figure for demonstrating. FIG. 6 is a cross-sectional view illustrating a schematic configuration of a nonvolatile memory element Mr having no charge injection port, for illustrating a nonvolatile memory element M according to a second embodiment of the present invention. FIG. 6 is a circuit configuration diagram of a nonvolatile memory element M according to a second embodiment of the present invention. FIG. 5 is a circuit configuration diagram for explaining a reference voltage generation circuit 3 as an analog circuit according to a second embodiment of the present invention, and a diagram for explaining a state in which the reference voltage generation circuit 3 outputs a reference voltage Vref. It is. FIG. 6 is a circuit configuration diagram for explaining a reference voltage generation circuit 3 as an analog circuit according to a second embodiment of the present invention, in which a nonvolatile memory element M1 on the upper stage side of the reference voltage generation circuit 3 is adjusted to a depletion state. It is a figure for demonstrating. FIG. 6 is a circuit configuration diagram for explaining a reference voltage generation circuit 3 as an analog circuit according to a second embodiment of the present invention, in which a nonvolatile memory element M2 on the lower side of the reference voltage generation circuit 3 is adjusted to an enhancement state. It is a figure for demonstrating. 1 is a circuit configuration diagram of a conventional reference voltage generation circuit 100. FIG. It is a figure which shows an example of the current / voltage characteristic of the depletion type transistor Md with which the conventional reference voltage generation circuit 100 was equipped, and the enhancement type transistor Me.

[First Embodiment]
A nonvolatile memory element and an analog circuit including the nonvolatile memory element according to a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, as an example of an analog circuit, a reference voltage generation circuit using an N-type nonvolatile memory element including a floating gate region having an insulator containing fluorine and a control gate region will be described. However, the nonvolatile memory element is not limited to this structure as long as it is an active element (transistor) having a charge holding region, and is not limited to an N-type MOSFET. Furthermore, the analog circuit to which the nonvolatile memory element is applied is not limited to the reference voltage generation circuit as long as it is a circuit that uses the nonvolatile memory element in an analog manner. For example, it is also effective for an analog circuit such as an operational amplifier circuit or a comparator circuit that requires accuracy in the threshold voltage of the MOSFET.

  As shown in FIG. 1, the nonvolatile memory element M according to the present embodiment includes a P well region 10 formed on a semiconductor substrate, a floating gate region FG formed on the P well region 10, and a floating gate region FG. And a control gate region CG formed at the same time. In addition, the nonvolatile memory element M includes a drain region D formed on one of the lower sides of the floating gate region FG and a source region S formed on the other of the lower sides of the floating gate region FG. . The drain region D and the source region S are formed in the P well region 10. The nonvolatile memory element M is separated from other nonvolatile memory elements (not shown) formed on the same semiconductor substrate by element isolation regions 41 and 42.

  The floating gate region FG includes a charge holding region 21 and an insulator 20. That is, the nonvolatile memory element M includes a charge holding region 21 and an insulator 20 that surrounds the entire surface of the charge holding region 21 and has halogen (for example, fluorine) distributed in at least a part of the region surrounding the entire surface. It has. In the nonvolatile memory element M according to the present embodiment, the insulator 20 has halogen distributed in at least a part of the region and is disposed so as to surround the charge holding region 20. The insulator 20 is arranged so as to surround the charge holding region 21 so that the halonge element is distributed in all directions surrounding the charge holding region 21, and has halogen distributed in the entire region. That is, the halogen is distributed so as to surround the entire surface of the charge retention region 21, and the insulator 20 is disposed so as to surround the charge retention region 21. As a result, halogen is distributed in all directions of the charge holding region 21. The insulator 20 is formed above the charge retention region 21, a gate insulating film 22 formed below the charge retention region 21, a sidewall oxide film 23 formed by oxidizing the sidewall of the charge retention region 21, and the charge retention region 21. Each region of the insulator 20 surrounding the charge holding region 21 is not necessarily made of the same material, and need not be an insulator formed at the same time. A sidewall 25 is formed around the gate insulating film 22 and the sidewall oxide film 23.

  The halogen content in the insulator 20 may be 0.01 (atm%) or more in at least a part of the region in contact with the charge holding region 21. In addition, the halogen content in the insulator 20 may be 0.05 (atm%) or more in at least a part of the region in contact with the charge holding region 21. Further, the halogen content in the insulator 20 may be 0.1 (atm%) or more in at least a part of the region in contact with the charge holding region 21.

  A tunnel insulating film 221 is formed on the gate insulating film 22. The tunnel insulating film 221 is a portion where the film thickness is relatively thin in the gate insulating film 22. The region of the charge holding region 21 in which the tunnel insulating film 221 is formed serves as a charge injection port 211 for injecting charges into the charge holding region 21 and discharging charges from the charge holding region 21. That is, the charge holding region 21 has a charge injection port 211 for injecting charge and discharging charge.

  The control gate region CG has a polysilicon film 31 formed on the upper insulating film 24. A sidewall 32 formed on the upper insulating film 24 is formed around the polysilicon film 31.

  The drain region D includes an N-type region 11 and an N-type N + region 12 having a higher impurity concentration than the N-type region 11. The N + region 12 is provided to make ohmic contact between the drain region D and a plug 52 described later.

  The source region S includes an N-type region 13 and an N-type N + region 14 having a higher impurity concentration than the N-type region 13. The N + region 14 is provided to make ohmic contact between the source region S and a plug 53 described later. The drain region D and the source region S are defined by the direction of current flow. For this reason, when the current flow direction is reversed with respect to the current assumed in the nonvolatile memory element M shown in FIG. 1, the drain region D shown in FIG. It becomes the drain region D.

  The nonvolatile memory element M includes a protective film 61 formed on the control gate region CG, the floating gate region FG, the drain region D, and the source region S. The protective film 61 has an opening that exposes a part of the polysilicon film 31 in the control gate region CG to the bottom surface. A plug 51 is embedded in the opening. As a result, the plug 51 and the polysilicon film 31 in the control gate region CG are electrically connected.

  The protective film 61 has an opening that exposes a part of the N + region 12 of the drain region D to the bottom surface. A plug 52 is embedded in the opening. Thereby, the plug 52 and the N + region 12 are electrically connected. The protective film 61 is formed with an opening that exposes a part of the N + region 14 of the source region S to the bottom surface. A plug 53 is embedded in the opening. Thereby, the plug 53 and the N + region 14 are electrically connected.

  Although not shown, the plugs 51, 52, 53 are connected to wirings formed on the protective film 61. A voltage of a predetermined level is applied to the control gate region CG, the drain region D, and the source region S of the nonvolatile memory element M from this wiring.

  The threshold voltage Vth of the nonvolatile memory element M is controlled by the amount of charge injected into the floating gate region FG. As shown in FIG. 2A, electrons as charges are injected into the floating gate region FG of the nonvolatile memory element M through the charge injection port 211. In FIG. 2A, hatching is not shown for the cross-section of each component of the nonvolatile memory element M for easy understanding. As shown in FIG. 2B, when electrons are injected into the floating gate region FG, for example, the P well region 10 (that is, the back gate B) and the drain region D are fixed to 0V (0V is applied), A pulse voltage Vpp of 10 V or higher is applied to control gate region CG. As a result, electrons are injected from the drain region D into the charge holding region 21 through the charge injection port 211 as indicated by the upward straight arrow in FIG. On the other hand, as shown in FIG. 2C, when electrons are emitted from the floating gate region FG, for example, the control gate region CG and the P well region 10 (that is, the back gate B) are fixed to 0V (apply 0V). And a pulse voltage Vpp of 10 V or higher is applied to the drain region D. As a result, electrons are emitted from the charge holding region 21 to the drain region D through the charge injection port 211 as indicated by a downward straight arrow in FIG. As described above, the nonvolatile memory element M can control the voltages applied to the control gate region CG, the P well region 10 and the drain region D, and can input and output charges through the charge injection port 211. Since the nonvolatile memory element M does not use the source region S for taking in and out charges, the source region S may be fixed to a predetermined voltage (for example, 0 V) or may be in a floating state. Note that, again, the drain region D and the source region S are defined by the direction of current flow. For this reason, when the direction in which the current flows during circuit operation is reversed with respect to the current assumed in the nonvolatile memory element M shown in FIG. 2, the drain region D shown in FIG. The region S becomes the drain region D.

  Next, a method for manufacturing the nonvolatile memory element M will be described with reference to FIGS. 1 and 3 to 11. 1 and 3 to 11 (except for FIG. 8B), only the nonvolatile memory element M used as a depletion type transistor is illustrated, but the nonvolatile memory element M according to the present embodiment is used. When forming a reference voltage generation circuit (details will be described later), a nonvolatile memory element used as an enhancement type transistor and a nonvolatile memory element used as a depletion type transistor are simultaneously processed so as to have the same structure under the same conditions. I will do it.

  As shown in FIG. 3, element isolation regions (LOCOS) 41 and 42 and a P-well region 10 are formed on a semiconductor substrate (in this embodiment, a silicon substrate is taken as an example).

  Next, as shown in FIG. 4, the source region S above the P well region 10 disposed between the element isolation region 41 and the element isolation region 42 is formed by using a photolithography technique and an ion implantation method. An N-type region 13 is formed at a place, and an N-type region 11 is formed at a place where the drain region D is formed.

  Next, as shown in FIG. 5, an insulating film 22a that will eventually become the gate insulating film 22 is formed on the surface of the silicon substrate.

  Next, as shown in FIG. 6, a part of the insulating film 22a where the charge injection port 211 is provided to the floating gate region FG (see FIG. 1) is removed by photolithography technique and wet etching technique, and charge injection is performed. A thin film region 221a having a thickness (for example, 100 mm) that can be used is formed.

  Next, as shown in FIG. 7, a phosphorus-doped polysilicon film 21a that will eventually become the charge holding region 21 of the floating gate region FG is formed. Further, an oxide / nitride / oxide (ONO) film 24a that finally becomes the upper insulating film 24 is formed on the polysilicon film 21a. The ONO film 24a is configured by combining a silicon oxide film and a silicon nitride film, but the ONO film 24a may be only a pure silicon oxide film or a silicon nitride film.

Next, as shown in FIGS. 8A and 8B, fluorine ions are implanted into the polysilicon film 21a at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 30 keV, for example. As a result, a fluorine existence region 21b in which a relatively large amount of fluorine exists is formed in the polysilicon film 21a. When the nonvolatile memory element M is used in the reference voltage generation circuit, the nonvolatile memory element (see FIG. 8A) that is finally used as a depletion type transistor and the nonvolatile memory element that is finally used as an enhancement type transistor (see FIG. 8 (b)), the same amount of fluorine is implanted into the polysilicon film 21a. As shown in FIG. 8A, in the nonvolatile memory element that is finally used as a depletion type transistor, a thin film region 221a is formed on the N-type region 13 constituting the drain region D. On the other hand, as shown in FIG. 8B, in the nonvolatile memory element that is finally used as an enhancement type transistor, a thin film region 221a is formed on the N type region 11 constituting the source region S.

  Next, as shown in FIG. 9, a part of the insulating film 22a, the polysilicon film 21a, and the ONO film 24a are processed into dimensions according to the circuit application using a photolithography technique and an etching technique. At this time, the polysilicon film 21a and the ONO film 24a are etched so that the thin film region 221a is included below the processed polysilicon film 21a and the ONO film 24a.

Next, as shown in FIG. 10, an oxidation process (for example, 850 ° C. wet oxidation) is performed to oxidize the sidewall of the polysilicon film 21a to form an oxide film 23a, and fluorine implanted into the polysilicon film 21a. Are segregated into the insulating film 22a, the thin film region 221a, the ONO film 24a and the oxide film 23a surrounding the polysilicon film 21a. Since fluorine has a segregation coefficient of about 5.6 × 10 ⁻⁸ at the silicon / silicon oxide film interface, it can be rapidly taken into the silicon oxide film and subjected to segregation in the silicon oxide film when heat treatment is performed. . That is, as indicated by curved arrows in FIG. 10, fluorine can be distributed at a high concentration from the fluorine existing region 21b in all directions surrounding the polysilicon film 21a that becomes the charge holding region 21 by oxidation treatment.

  By etching into a predetermined shape and segregating fluorine, as shown in FIG. 11, the polysilicon film 21a becomes a charge holding region 21, the insulating film 22a becomes a gate insulating film 22, and the thin film region 221a becomes a tunnel insulating film. The oxide film 23 a becomes the sidewall oxide film 23, and the ONO film 24 a becomes the upper insulating film 24. Thus, the floating gate region FG having the charge holding region 21 surrounded by the insulator 20 and provided with the charge injection port 211 is formed.

  Next, a polysilicon film is volume-doped on the entire surface of the silicon substrate and doped with phosphorus, and then a polysilicon film 31 is formed on the floating gate region FG by using a photolithography technique and an etching technique. As a result, a control gate region CG disposed in contact with a part of the upper insulating film 24 is formed.

  Next, as shown in FIG. 1, after removing the insulating film 22 a on the N-type region 11 and the N-type region 13, an insulating film sidewall 25 is formed on each side of the sidewall oxide film 23 and the gate insulating film 22. Then, sidewalls 32 of insulating films are formed on the sides of the polysilicon film 31.

  Next, as shown in FIG. 1, a high-concentration N + region 12 for making ohmic contact with the metal is formed in the contact portion with the N-type region 11, and the contact portion with the metal is formed in the contact portion with the N-type region 13. A high-concentration N + region 14 for forming ohmic contact is formed. As a result, the drain region D is formed on one of the lower sides of the control gate region CG and the floating gate region FG, and the source region S is formed on the other of the both sides.

  Next, as shown in FIG. 1, an insulating protective film 61 is formed on the entire surface of the silicon substrate. The protective film 61 is formed so as to cover the control gate region CG, the floating gate region FG, the drain region D, and the source region S.

  Next, an opening that exposes part of the polysilicon film 31, the N + region 12, and the N + region 14 to the bottom surface is formed in the protective film 61 using a photolithography technique and an etching technique. Next, as shown in FIG. 1, using a thin film formation technique, a metal plug 51 is formed in an opening exposing a part of the polysilicon film 31, and an opening exposing a part of the N + region 12 on the bottom surface. Then, a metal plug 52 is formed, and a metal plug 53 is formed in an opening exposing a part of the N + region 14 on the bottom surface.

Although illustration is omitted, next, wirings electrically connected to the plugs 51, 52, 53 are formed through a general wiring forming process. Through the above steps, as shown in FIG. 1, the nonvolatile memory element M in which fluorine is distributed in all directions of the insulator 20 surrounding the charge holding region 21 is completed. Note that silicide may be formed in the contact portions of the control gate region CG, the source region S, and the drain region D in order to reduce contact resistance. Further, the fluorine content in the insulator 20 is optimally 0.1 to 1 atm% (in the case of SiO ₂ , the concentration is around 1 × 10 ²⁰ cm ⁻³ ), and the fluorine content in the insulator 20 If the amount is too large, the charge retention characteristics of the nonvolatile memory element M deteriorate.

  Next, the charge retention characteristics of the nonvolatile memory element M will be described with reference to FIG. In the nonvolatile memory element M, halogen is distributed in the insulator 20 surrounding the charge holding region 21. Halogen has dangling bond terminations existing in the insulator 20 or at the interface between the insulator 20 and another material body, strain relaxation in the insulator 20, gettering effect of mobile ions, dangling bonds, Defects derived from strain and mobile ions can be reduced. That is, the halogen distributed in the insulator 20 has an effect of suppressing charge leaking through defects in the insulator 20. As a result, the non-volatile memory element M has excellent charge retention characteristics while ensuring flexibility in layout dimensions, and an analog circuit such as a reference voltage generation circuit constituted by the non-volatile memory element M has a stable electrical property. Characteristics can be realized.

  Here, characteristics required for charge retention characteristics of the nonvolatile memory element will be described. In the case of a nonvolatile memory element used in a nonvolatile memory, the threshold voltage Vth of the nonvolatile memory element may be determined as 0 or 1, and the threshold voltage Vth of the nonvolatile memory element indicating 0 or 1 and the threshold determination. There is usually a margin of several volts between the voltage. Therefore, the charge retention characteristics of the non-volatile memory element are somewhat poor. Even when a threshold voltage fluctuation of about several volts occurs, there is often no direct connection to a malfunction. However, when a nonvolatile memory element is used for an analog circuit, for example, in a circuit that requires a highly accurate reference voltage Vref, even if a threshold voltage fluctuation of 0.1 V occurs, a problem occurs immediately. For this reason, when the non-volatile memory element is intended to be used in an analog manner such as a reference voltage generation circuit, the threshold fluctuation of less than 0.1 V is realized while ensuring the flexibility of the layout dimensions. There is a need for a non-volatile memory element having such excellent charge retention characteristics.

Next, a region where halogen is introduced will be described. The region into which the halogen is introduced is at least required to be introduced into the main path through which the charge is released from the charge holding region 21, but is preferably introduced in all directions surrounding the charge holding region 21. . There are various reasons for this, but the main reasons are (1) to (3) below.
(1) Since the nonvolatile memory element according to the present embodiment is used in a circuit that places importance on analog characteristics, the nonvolatile memory element is more strict with respect to characteristic variations than a nonvolatile memory element used in a conventional nonvolatile memory.
(2) In an analog circuit, the layout dimension of an element differs for each application, and a very large size may be used. Therefore, the main path (main surface) of charge leakage varies depending on the layout dimension.
(3) Since the nonvolatile memory element according to the present embodiment does not have a defined array structure like the conventional nonvolatile memory, the environment around the nonvolatile memory element is not the same, and the main cause of charge leakage depends on the environment. The route (main surface) will change.

FIG. 12 shows the charge retention characteristics of a reference voltage generation circuit (details will be described later) in the case where fluorine is distributed in all directions of the insulator 20 surrounding the charge retention region 21 of the nonvolatile memory element M, with 2000 points for each legend. The above is a graph that is statistically expressed using the cumulative frequency distribution. The horizontal axis of the graph shown in FIG. 12 indicates the amount of variation (V) of the reference voltage Vref output by the reference voltage generation circuit before and after baking, and the vertical axis indicates the percentage of cumulative samples (%). The baking condition is 250 ° C. for 10 hours. The curve connected with ◇ marks in FIG. 12 represents the characteristics when the dose of fluorine is the smallest dose amount: 1 × 10 ¹³ cm ⁻² or less (fluorine: ultra-low concentration). This represents the characteristics when the dose of fluorine is the second smallest dose: 5 × 10 ¹³ cm ⁻² (fluorine: low concentration). The curve connected by the Δ mark in FIG. 12 represents the characteristics when the dose of fluorine is the third smallest dose amount: 1 × 10 ¹⁴ cm ⁻² (fluorine: medium concentration). The dose amount with the fourth smallest fluorine injection amount is 5 × 10 ¹⁴ cm ⁻² (fluorine: high concentration). The curve connected with the x mark shows the dose amount with the largest fluorine injection amount: 5 The characteristics in the case of × 10 ¹⁵ cm ^-2 (fluorine: ultra-high concentration) are shown.

  The charge retention characteristics when a general nonvolatile memory element as disclosed in Patent Documents 2 and 3 is used as a constituent element of a reference voltage generation circuit in an analog manner is the same tendency as “fluorine: very low concentration” Indicates. A reference voltage generation circuit using a non-volatile storage element of “fluorine: ultra-low concentration” has a slightly high ratio of showing an abnormal value because of a slightly poor charge retention characteristic. It should be noted that the “slightly bad abnormal value” taken up here is found by statistical evaluation, not intrinsic degradation found by general charge retention characteristic evaluation. For this reason, detection and verification of the effect are difficult, and statistical evaluation as shown in FIG. 12 is necessary. As described above, 0. The somewhat abnormal value of fluctuation of several volts is not a problem in the range where it is used as a normal non-volatile memory, but becomes a problem only when it is used as an element constituting an analog circuit.

  0. It can be seen that the slightly worse abnormal value of several V fluctuations disappears according to the amount of fluorine injected into the insulator 20, as shown in FIG. Further, the fluorine injected into the insulator 20 works effectively for the nonvolatile memory element M having slightly poor charge retention characteristics by selecting an appropriate concentration, and has an effect of improving the charge retention characteristics. On the other hand, fluorine injected into the insulator 20 does not cause a large change in charge retention characteristics in the nonvolatile memory element M that originally exhibits normal charge retention characteristics. However, if too much fluorine is injected into the insulator 20, as shown by “fluorine: ultra-high concentration” in FIG. 12, for example, compared with an optimum fluorine injection amount such as “fluorine: high concentration”. Charge retention characteristics deteriorate.

  FIG. 13A is a TEM image obtained by imaging a cross section of the nonvolatile memory element M in the vicinity of the charge injection port 211 with a transmission electron microscope (TEM). FIG. 13B shows an energy dispersive X-ray spectroscopy (EDX) mapping of fluorine used as a halogen at the same place as in FIG. 13A.

  As shown in FIG. 13A, a tunnel insulating film 221 having a relatively small thickness exists in the gate insulating film 22 between the charge holding region 21 and the source region S. An upper insulating film 24 is present between the charge holding region 21 and the polysilicon film 31. As shown in FIG. 13B, the tunnel insulating film 221 and the upper insulating film 24 are white images unlike the charge holding region 21 and the polysilicon film 31. Thus, it can be seen that the tunnel insulating film 221 and the upper insulating film 24 contain a larger amount of fluorine than the charge holding region 21 and the polysilicon film 31.

  FIG. 13C is a graph showing the fluorine distribution in “A → B” shown in FIG. The horizontal axis of the graph shown in FIG. 13C indicates the depth (nm), and the positions A to B shown in FIG. 13A are represented from left to right. The vertical axis | shaft of the graph shown in FIG.13 (c) has shown the fluorine content rate. “Fluorine: high concentration” indicates that the concentration of fluorine contained in the insulator 20 is the same as “fluorine: high concentration” shown in FIG. It shows that the concentration of fluorine contained therein is the same as “fluorine: super high concentration” shown in FIG.

  As shown in FIG. 13C, at a depth D1 where the polysilicon film 31 exists, a depth D3 where the charge holding region 21 exists, and a depth D5 where the drain region D exists, the fluorine content is almost zero. (Atm%). On the other hand, the fluorine content is relatively high at the depth D2 where the upper insulating film 24 exists and the depth D4 where the tunnel insulating film 221 exists. The fluorine content in the tunnel insulating film 221 and the upper insulating film 24 is about 0.01 (atm%) for “fluorine: low concentration”, and 1.7 to 2.3 (for “fluorine: ultrahigh concentration”). atm%). The effect appears at a content equal to or higher than the content corresponding to the “fluorine: low concentration” sample in FIG. 12, and 0.1 to 1 (atm%) is the optimum concentration.

  As described above, the nonvolatile memory element M according to the present embodiment includes the insulator 20 containing halogen and the charge holding region 21 surrounded by the insulator 20. As a result, the nonvolatile memory element M has a charge retention characteristic that can be used in an analog circuit, and can improve the accuracy of electrical characteristics such as current / voltage characteristics when the analog circuit is configured.

  Next, the analog circuit according to the present embodiment will be described taking the reference voltage generation circuit using the nonvolatile memory element according to the present embodiment as an example. The reference voltage generation circuit as an analog circuit according to the present embodiment is a circuit that generates a reference voltage using a plurality of nonvolatile memory elements in which, for example, fluorine is distributed as halogen around the floating gate region. The reference voltage generation circuit in the present embodiment utilizes that the nonvolatile memory element can be in two states, an enhancement type transistor and a depletion type transistor. The non-volatile memory element used as the enhancement type transistor and the non-volatile memory element used as the depletion type transistor have the same dimensions and structure as the element, and in particular, the halogen content in the insulator is formed to be substantially equal. Has been. Since the halogen present in the insulator has the effect of promoting the oxidation of the insulator and the effect of lowering the dielectric constant of the insulator, both transistors need to have substantially the same halogen content. If the halogen concentrations in the insulators of the two transistors are significantly different, there will be a difference in conductance and temperature characteristics between the nonvolatile memory element used as the enhancement type transistor and the nonvolatile memory element used as the depletion type transistor. That is, a temperature characteristic occurs in the reference voltage generated by the reference voltage generation circuit, causing a problem that the voltage value of the reference voltage deviates from a desired value. This problem can be avoided if the halogen concentrations in the insulators of both transistors are made substantially equal. Here, “substantially equal” means that the difference between the halogen concentration in the insulator of the enhancement type transistor and the halogen concentration in the insulator of the depletion type transistor is within one digit.

  The analog circuit according to the present embodiment is a reference voltage generation circuit that eliminates the manufacturing variation of the reference voltage that is generated based on the difference in the characteristics of the circuit elements constituting the analog circuit. The reference voltage generation circuit according to the present embodiment includes at least one depletion type transistor and at least one enhancement type transistor in which the same current as the current flowing in the depletion type transistor or a related current flows. The depletion type transistor and the enhancement type transistor constituting the reference voltage generation circuit in the present embodiment are nonvolatile memory elements in which halogen (for example, fluorine) is distributed in all directions of the insulator surrounding the charge holding region. Here, the “related current” means a current having a correlation with a current flowing in the depletion type transistor. For example, the “related current” is a current X times the current flowing through the depletion type transistor, or a current obtained by adding the current value Y to the current flowing through the depletion type transistor, which is more complicated than these two examples. I have a relationship. That is, the “related current” is a current represented by a function having a current value flowing through the depletion type transistor as one parameter.

  As shown in FIG. 14, the reference voltage generation circuit 1 in the present embodiment includes a plurality (two in this example) of nonvolatile memory elements M1 and M2. At least some of the plurality of nonvolatile memory elements M1 and M2 (all in this example) are connected in series, and a reference voltage Vref is applied to a connection portion of the plurality of nonvolatile memory elements M1 and M2 connected in series. An output voltage output terminal OUT is connected. Each of the nonvolatile memory element M1 and the nonvolatile memory element M2 has a transistor configuration, and has the same configuration as the nonvolatile memory element M illustrated in FIG.

  The nonvolatile memory element M1 and the nonvolatile memory element M2 are connected in series between a high voltage supply terminal Vdd to which a high voltage is supplied and a low voltage supply terminal Vss to which a low voltage is supplied. Hereinafter, the symbol “Vdd” is also used as a symbol of a high voltage output from the high voltage supply terminal Vdd, and the symbol “Vss” is also used as a symbol of a low voltage output from the low voltage supply terminal Vss. The drain region D of the nonvolatile memory element M1 is connected to the high voltage supply terminal Vdd, and the source region S of the nonvolatile memory element M2 is connected to the low voltage supply terminal Vss. The source region S and the control gate region CG of the nonvolatile memory element M1 are connected to each other, and the drain region D and the control gate region CG of the nonvolatile memory element M2 are connected to each other. Further, the source region S and the control gate region CG of the nonvolatile memory element M1 and the drain region D and the control gate region CG of the nonvolatile memory element M2 are connected to each other. A voltage output terminal OUT is connected to a connection portion between the source region S of the nonvolatile memory element M1 and the drain region D of the nonvolatile memory element M2.

  In the reference voltage generation circuit 1, the nonvolatile memory element M2 on the lower stage side (low voltage supply terminal Vss side) is adjusted to be in an enhancement state, and the nonvolatile memory element M1 on the upper stage side (high voltage supply terminal Vdd side) It is adjusted to become a depletion state. Each of the nonvolatile memory elements M1, M2 has a control gate region CG and a floating gate region FG, and fluorine is distributed as halogen in the insulator 20 (see FIG. 1) around the floating gate region FG. As a result, the nonvolatile memory elements M1 and M2 can be written and erased and can maintain the written state for a long period of time. The threshold voltage of the depletion type transistor is negative, and the threshold voltage of the enhancement type transistor is positive. For this reason, the plurality of nonvolatile memory elements provided in the reference voltage generation circuit 1 as the analog circuit according to the present embodiment include a nonvolatile memory element M1 having at least a negative threshold voltage and a nonvolatile memory having a positive threshold voltage. The element M2 is included.

The area of each of the nonvolatile memory elements M1 and M2 provided in the reference voltage generation circuit 1 may be 10 μm ² or more, 50 μm ² or more, or 100 μm ² or more. The nonvolatile memory elements M1 and M2 do not have an array structure even if they have any of these element areas.

  As shown in FIG. 15, the reference voltage generation circuit 2 which is the analog circuit according to the present embodiment and which can write to the nonvolatile memory elements M1 and M2 has one terminal connected to the drain region D of the nonvolatile memory element M1. The switch SW1 is provided. One of the other terminals of the switch SW1 is connected to the high voltage supply terminal Vdd, the other one of the other terminals of the switch SW1 is connected to the low voltage supply terminal Vss, and the other one of the other terminals of the switch SW1 is It is connected to the application terminal for the pulse voltage Vpp. The reference voltage generation circuit 2 can apply any one of the high voltage Vdd, the low voltage Vss, and the pulse voltage Vpp to the drain region D of the nonvolatile memory element M1 by appropriately switching the switch SW1.

  The reference voltage generation circuit 2 includes a switch SW2 having one terminal connected to the source region S of the nonvolatile memory element M2. One of the other terminals of the switch SW2 is connected to the low voltage supply terminal Vss, and the other terminal of the switch SW2 is connected to an application terminal for the pulse voltage Vpp. The reference voltage generation circuit 2 can apply either one of the low voltage Vss and the pulse voltage Vpp to the source region S of the nonvolatile memory element M2 by appropriately switching the switch SW2.

  The reference voltage generation circuit 2 includes a switch SW6 and a switch SW8 connected in series between the source region S of the nonvolatile memory element M1 and the drain region D of the nonvolatile memory element M2. The source region S of the nonvolatile memory element M1 is connected to one terminal of the switch SW6, and the drain region D of the nonvolatile memory element M2 is connected to one terminal of the switch SW8. The other terminal of the switch SW6 and the other terminal of the switch SW8 are connected.

  The reference voltage generation circuit 2 includes a switch SW5 and a switch SW7 connected in series between the control gate region CG of the nonvolatile memory element M1 and the control gate region CG of the nonvolatile memory element M2. The control gate region CG of the nonvolatile memory element M1 is connected to one terminal of the switch SW5, and the control gate region CG of the nonvolatile memory element M2 is connected to one terminal of the switch SW7. The other terminal of the switch SW5 and the other terminal of the switch SW7 are connected.

  The other terminals of the switch SW5, switch SW6, switch SW7 and switch SW8 are connected to each other. The reference voltage generation circuit 2 includes a voltage output terminal OUT connected to a connection portion where the other terminals of the switch SW5, the switch SW6, the switch SW7, and the switch SW8 are connected to each other.

  The reference voltage generation circuit 2 includes a switch SW3 having one terminal connected to the control gate region CG of the nonvolatile memory element M1, and a switch SW9 having one terminal connected to the other terminal of the switch SW3. One of the other terminals of the switch SW9 is connected to the application terminal of the pulse voltage Vpp, and the other terminal of the switch SW9 is connected to the low voltage supply terminal Vss. The reference voltage generation circuit 2 switches either the pulse voltage Vpp or the low voltage Vss to the control gate region CG of the nonvolatile memory element M1 by appropriately switching the switch SW9 when the switch SW3 is in the connected state (short state). It can be applied.

  The reference voltage generation circuit 2 includes a switch SW4 having one terminal connected to the control gate region CG of the nonvolatile memory element M2, and a switch SW10 having one terminal connected to the other terminal of the switch SW4. One of the other terminals of the switch SW10 is connected to the application terminal of the pulse voltage Vpp, and the other terminal of the switch SW10 is connected to the low voltage supply terminal Vss. The reference voltage generation circuit 2 appropriately switches the switch SW10 when the switch SW4 is in the connected state (short-circuit state), so that one of the pulse voltage Vpp and the low voltage Vss is supplied to the control gate region CG of the nonvolatile memory element M2. It can be applied.

As shown in FIG. 15, the reference voltage generation circuit 2 switches the switches SW <b> 1 to SW <b> 10 to the following state when outputting the reference voltage Vref from the voltage output terminal OUT.
Switch SW1: High voltage supply terminal Vdd side Switch SW2: Low voltage supply terminal Vss side Switch SW3, SW4: Open state (open state)
Switches SW5, SW6, SW7, SW8: Connection state (short state)
Switches SW9 and SW10: Arbitrary (in FIG. 15, low voltage Vss side)

  When the nonvolatile memory element M1 is in a depletion state and the nonvolatile memory element M2 is in the enhancement state, the reference voltage generation circuit 2 generates the reference voltage Vref when the switches SW1 to SW10 are in the switching state illustrated in FIG. . That is, the reference voltage generation circuit 2 includes a switch unit including switches SW1 to SW10 that set each terminal of the nonvolatile memory elements M1 and M2 to a desired potential.

  As shown in FIG. 16, the reference voltage generation circuit 2 switches the switches SW1 to SW10 to the following states at the time of rewriting for setting the nonvolatile memory element M1 to the depletion state. Here, a case where the threshold voltage before adjustment of the nonvolatile memory element M1 is higher than the threshold voltage after adjustment is taken as an example.

Switch SW1: Pulse voltage Vpp side Switch SW2: Low voltage supply terminal Vss side Switch SW3: Connection state (short state)
Switch SW4: Open state (open state)
Switches SW5, SW6, SW7, SW8: Open state (open state)
Switch SW9: Low voltage supply terminal Vss side Switch SW10: Arbitrary (in FIG. 16, the low voltage supply terminal Vss side)

  Therefore, since the pulse voltage Vpp is applied to the drain region D of the nonvolatile memory element M1 and the low voltage Vss is applied to the control gate region CG, the charge holding region 21 is transferred to the drain region D through the charge injection port 211. Electrons are emitted. Thereby, the threshold voltage of the nonvolatile memory element M1 is lowered. On the contrary, when the low voltage Vss is applied to the drain region D of the nonvolatile memory element M1 and the pulse voltage Vpp is applied to the control gate region CG, the charge holding region 21 is supplied from the drain region D through the charge injection port 211. Electrons are injected into the. Thereby, the threshold voltage of the nonvolatile memory element M1 is increased.

As shown in FIG. 17, the reference voltage generation circuit 2 switches the switches SW1 to SW10 to the following states at the time of rewriting for bringing the nonvolatile memory element M2 into the enhancement state. Here, a case where the threshold voltage before adjustment of the nonvolatile memory element M2 is lower than the threshold voltage after adjustment is taken as an example.
Switch SW1: High voltage supply terminal Vdd side Switch SW2: Low voltage supply terminal Vss side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switches SW5, SW6, SW7, SW8: Open state (open state)
Switch SW9: Arbitrary (in FIG. 17, the low voltage supply terminal Vss side)
Switch SW10: Pulse voltage Vpp side

  For this reason, since the low voltage Vss is applied to the source region S of the nonvolatile memory element M2 and the pulse voltage Vpp is applied to the control gate region CG, the source region S is connected to the charge holding region 21 via the charge injection port 211. Electrons are injected. Thereby, the threshold voltage of the nonvolatile memory element M2 is increased. On the contrary, when the pulse voltage Vpp is applied to the source region S of the nonvolatile memory element M2 and the low voltage Vss is applied to the control gate region CG, the source region S is transferred from the charge holding region 21 through the charge injection port 211. Electrons are emitted to Thereby, the threshold voltage of the nonvolatile memory element M2 is lowered.

  As shown in FIGS. 15 to 17, the reference voltage generation circuit 2 rewrites the threshold voltages Vth of the specific nonvolatile memory elements M1 and M2 to desired values by appropriately switching the switches SW1 to SW10, and finally The desired reference voltage Vref can be generated in the state shown in FIG. Needless to say, in the present invention, since the same type of nonvolatile memory element is used as the transistor constituting the reference voltage generation circuit, the conductance and temperature characteristics of the two transistors can be made the same. It is possible to obtain the characteristics of two ideally translated transistors as shown in FIG. The characteristics of the two transistors moved in parallel are the conductance and temperature characteristics when the depletion type transistor Md and the enhancement type transistor Me are configured using different types of transistors as described in Patent Document 1. Is different from transistor to transistor and cannot be exactly realized. That is, in the reference voltage generation circuit as described in Patent Document 1, temperature characteristics are also generated in the reference voltage Vref taken out from the voltage output terminal OUT, but the present invention using the same type of nonvolatile memory element is used. In the reference voltage generation circuit, it is possible to obtain the reference voltage Vref having neither manufacturing variation nor temperature characteristics. Further, the reference voltage Vref to be extracted can be set to an arbitrary value by adjusting the threshold voltage Vth_e of the enhancement type transistor, and the amount of current flowing through the reference voltage generation circuit can be set to an arbitrary value by adjusting the threshold voltage Vth_d of the depletion type transistor. One of the advantages is that the value can be set to.

  As described above, according to the present embodiment, it is possible to realize a nonvolatile memory element having high charge retention characteristics while giving flexibility to the element layout. Therefore, it is possible to realize a highly accurate analog circuit in which deterioration of electrical characteristics is effectively suppressed and the influence of manufacturing variation is extremely small. Moreover, according to this embodiment, the variation in electrical characteristics can be reduced. A nonvolatile memory element having excellent charge retention characteristics and an analog circuit including the nonvolatile memory element can be realized.

[Second Embodiment]
A nonvolatile memory element and an analog circuit including the nonvolatile memory element according to a second embodiment of the present invention will be described with reference to FIGS. The nonvolatile memory element according to the present embodiment includes the nonvolatile memory element M shown in FIG. 1 and the nonvolatile memory element Mr shown in FIG. 18 as a set, and each of the nonvolatile memory element M and the nonvolatile memory element Mr. The floating gate regions are connected to each other, and the control gate regions of the nonvolatile memory element M and the nonvolatile memory element Mr are connected to each other.

  As shown in FIG. 18, the nonvolatile memory element Mr has the same configuration as that of the nonvolatile memory element M except that the nonvolatile memory element Mr does not have a charge injection port. The nonvolatile memory element Mr includes a charge holding region 71 and an insulator 70 that has halogen distributed in at least a part of the region and is disposed so as to surround the charge holding region 71. The insulator 70 includes an upper insulating film 74 formed above the charge holding region 71, a sidewall oxide film 73 formed on the side wall of the charge holding region 71, and a gate insulating film formed below the charge holding region 71. 72. The gate insulating film 72 is not formed with a tunnel insulating film, and the film thickness is substantially constant. That is, the gate insulating film 72 is not formed with a region having a different thickness, such as the tunnel insulating film 221 intentionally formed like the gate insulating film 22 in the first embodiment. The non-volatile memory element Mr has the same configuration as the non-volatile memory element M except that the configuration of the insulator 70 is different from the configuration of the insulator 20, and thus has the same functions and functions. Are denoted by the same reference numerals, and description thereof is omitted.

  As illustrated in FIG. 19, the nonvolatile memory element M according to the present embodiment includes a nonvolatile memory element Mw having the same configuration as the nonvolatile memory element M illustrated in FIG. 1, and a nonvolatile memory element Mr illustrated in FIG. 18. It has. The control gate region CG of the nonvolatile memory element Mw and the control gate region CG of the nonvolatile memory element Mr are connected. The floating gate region FG of the nonvolatile memory element Mw and the floating gate region FG of the nonvolatile memory element Mr are connected.

  As shown in FIG. 20, the reference voltage generation circuit 3 as an analog circuit according to the present embodiment includes a nonvolatile memory element M1 and a nonvolatile memory element M2 connected in series. Each of the nonvolatile memory element M1 and the nonvolatile memory element M2 has the same configuration as the nonvolatile memory element M according to the present embodiment shown in FIG. The nonvolatile memory element M1 includes nonvolatile memory elements M1w and M1r, and the nonvolatile memory element M2 includes nonvolatile memory elements M2w and M2r. The nonvolatile memory element M1w and the nonvolatile memory element M2w have the same configuration as the nonvolatile memory element M shown in FIG. 1, and the nonvolatile memory element M1r and the nonvolatile memory element M2r are nonvolatile memory shown in FIG. It has the same configuration as the element Mr. Therefore, hereinafter, as necessary, reference is made to FIG. 1 in the description of the configuration of the nonvolatile memory elements M1r, M2r, and FIG. 18 is referred to in the description of the configuration of the nonvolatile memory elements M1w, M2w.

  The reference voltage generation circuit 3 includes nonvolatile memory elements (an example of first nonvolatile memory elements) M1w and M2w and nonvolatile memory elements (an example of second nonvolatile memory elements) M1r and M2r. The nonvolatile memory element M1r includes a control gate region (an example of a first control gate region) provided in a gate region of the nonvolatile memory element M1w (an example of a second control gate region) electrically connected to a CG. ) Have CG. Further, the nonvolatile memory element M1r includes a charge holding region (an example of the first charge holding region) 21 (see FIG. 1) of the nonvolatile memory element M1w (a second charge holding region). An example) 71 (see FIG. 18) and a gate insulating film 72 (see FIG. 18) formed in contact with the charge holding region 71. The charge injection port 211 (see FIG. 1) provided in the nonvolatile memory element M1w is formed in a region not in contact with the current path formed in the nonvolatile memory element M1r. The charge injection port 211 provided in the nonvolatile memory element M1w is formed in a current path including the drain region D and the source region S of the nonvolatile memory element M1r and a region that is not in contact with the current path.

  The nonvolatile memory element M2r includes a control gate region (an example of the first control gate region) CG provided in the gate region of the nonvolatile memory element M2w (an example of the second control gate region). ) Have CG. In addition, the nonvolatile memory element M2r includes a charge retention area (an example of the first charge retention area) 21 (see FIG. 1) of the nonvolatile memory element M2w (a second charge retention area). An example) 71 (see FIG. 18) and a gate insulating film 72 (see FIG. 18) formed in contact with the charge holding region 71. The charge injection port 211 (see FIG. 1) provided in the nonvolatile memory element M2w is formed in a region not in contact with the current path formed in the nonvolatile memory element M2r. The charge injection port 211 provided in the nonvolatile memory element M2w is formed in a current path including the drain region D and the source region S of the nonvolatile memory element M2r and a region that is not in contact with the current path.

  The control gate region CG of the nonvolatile memory element M1w provided in the nonvolatile memory element M1 is connected to the control gate region CG of the nonvolatile memory element M1r. The floating gate region FG of the nonvolatile memory element M1w and the floating gate region FG of the nonvolatile memory element M1r are connected. Further, the control gate region CG of the nonvolatile memory element M2w provided in the nonvolatile memory element M2 is connected to the control gate region CG of the nonvolatile memory element M2r. The floating gate region FG of the nonvolatile memory element M2w and the floating gate region FG of the nonvolatile memory element M2r are connected.

  The nonvolatile memory element M1r and the nonvolatile memory element M2r are connected in series between the high voltage supply terminal Vdd and the low voltage supply terminal Vss. More specifically, the drain region D of the nonvolatile memory element M1r is connected to the high voltage supply terminal Vdd. The source region S of the nonvolatile memory element M2r is connected to the low voltage supply terminal Vss. The source region S of the nonvolatile memory element M1r and the drain region D of the nonvolatile memory element M2r are connected.

  The nonvolatile memory element M1w has a first region A1 provided on one of both sides below the floating gate region FG and a second region A2 provided on the other of the both sides. The reference voltage generation circuit 3 includes a switch SW1 having one terminal connected to the first region A1 of the nonvolatile memory element M1w. One of the other terminals of the switch SW1 is connected to the low voltage supply terminal Vss, and the other terminal of the switch SW1 is connected to the application terminal of the pulse voltage Vpp. The reference voltage generation circuit 2 can apply either one of the low voltage Vss and the pulse voltage Vpp to the first region A1 of the nonvolatile memory element M1w by appropriately switching the switch SW1.

  The nonvolatile memory element M2w has a first region A1 provided on one of both sides below the floating gate region FG and a second region A2 provided on the other of the both sides. The reference voltage generation circuit 3 includes a switch SW2 having one terminal connected to the first region A1 of the nonvolatile memory element M2w. One of the other terminals of the switch SW2 is connected to the low voltage supply terminal Vss, and the other terminal of the switch SW2 is connected to an application terminal for the pulse voltage Vpp. The reference voltage generation circuit 3 can apply either one of the low voltage Vss and the pulse voltage Vpp to the first region A1 of the nonvolatile memory element M2w by appropriately switching the switch SW2.

  The reference voltage generation circuit 3 includes a switch SW5 and a switch SW7 connected in series between the control gate region CG of the nonvolatile memory element M1w and the control gate region CG of the nonvolatile memory element M2w. The other terminals of the switches SW5 and SW7 are connected to each other. The other terminals of the switch SW5 and the switch SW7 are connected to a connection portion where the source region S of the nonvolatile memory element M1r and the drain region D of the nonvolatile memory element M2r are connected to each other. The reference voltage generation circuit 3 includes a voltage output terminal OUT that is connected to the connection portion and outputs a reference voltage Vref.

  The reference voltage generation circuit 3 includes a switch SW3 having one terminal connected to the control gate region CG of the nonvolatile memory element M1w, and a switch SW9 having one terminal connected to the other terminal of the switch SW3. One of the other terminals of the switch SW9 is connected to the application terminal of the pulse voltage Vpp, and the other terminal of the switch SW9 is connected to the low voltage supply terminal Vss. The reference voltage generation circuit 3 appropriately switches the switch SW9 when the switch SW3 is in a connected state (short-circuit state), so that one of the pulse voltage Vpp and the low voltage Vss is applied to the control gate region CG of the nonvolatile memory element M1w. It can be applied.

  The reference voltage generation circuit 3 includes a switch SW4 having one terminal connected to the control gate region CG of the nonvolatile memory element M2w, and a switch SW10 having one terminal connected to the other terminal of the switch SW4. One of the other terminals of the switch SW10 is connected to the application terminal of the pulse voltage Vpp, and the other terminal of the switch SW10 is connected to the low voltage supply terminal Vss. The reference voltage generation circuit 3 switches either the pulse voltage Vpp or the low voltage Vss to the control gate region CG of the nonvolatile memory element M2w by appropriately switching the switch SW10 when the switch SW4 is in a connected state (short state). It can be applied.

  The second region A2 of the nonvolatile memory element M1w and the second region A2 of the nonvolatile memory element M2w are like the source region S of the nonvolatile memory element M1 and the drain region D of the nonvolatile memory element M2 in the reference voltage generation circuit 2. It is not connected to and is in a floating state. Note that the nonvolatile memory element M1w and the nonvolatile memory element M2w are regions that exist for charge injection into the floating gate region FG of the nonvolatile memory element M1r or the floating gate region FG of the nonvolatile memory element M2r. Do not pass current. Therefore, the nonvolatile memory element M1w and the nonvolatile memory element M2w do not need to have the source region S and the drain region D, and any form is possible as long as the structure has a charge injection port.

  As shown in FIG. 20, in the reference voltage generation circuit 3, at the time of charge injection, charge is injected into the floating gate region FG through the nonvolatile memory elements M1w and M2w. When the reference voltage generation circuit 3 is operated, a current flows through the nonvolatile memory elements M1r and M2r. In the reference voltage generation circuit 3, the nonvolatile memory element M1 side (that is, the nonvolatile memory elements M1w and M1r) is in a depletion state, and the nonvolatile memory element M2 side (that is, the nonvolatile memory elements M2w and M2r) is in an enhancement state. .

As shown in FIG. 20, when generating the reference voltage Vref, the reference voltage generation circuit 3 switches the switches SW1 to SW5, SW7, SW9, and SW10 to the following states.
Switch SW1: Low voltage supply terminal Vss side Switch SW2: Low voltage supply terminal Vss side Switch SW3, SW4: Open state (open state)
Switches SW5 and SW7: Connection state (short state)
Switches SW9 and SW10: Arbitrary (in FIG. 20, the low voltage supply terminal Vss side)

As shown in FIG. 21, the reference voltage generation circuit 3 switches SW1 to SW5, SW7, SW9, and SW10 at the time of rewriting for setting the nonvolatile memory element M1 side (that is, the nonvolatile memory elements M1w and M1r) to the depletion state. Switch to the following state. Here, a case where the threshold voltage before adjustment on the nonvolatile memory element M1 side is higher than the threshold voltage after adjustment is taken as an example.
Switch SW1: Pulse voltage Vpp side Switch SW2: Low voltage supply terminal Vss side Switch SW3: Connection state (short state)
Switch SW4: Open state (open state)
Switches SW5 and SW7: Open state (open state)
Switch SW9: Low voltage supply terminal Vss side Switch SW10: Arbitrary (in FIG. 21, the low voltage supply terminal Vss side)

  Therefore, since the pulse voltage Vpp is applied to the drain region D of the nonvolatile memory element M1w and the low voltage Vss is applied to the control gate region CG, the charge holding region 21 is transferred to the drain region D via the charge injection port 211. Electrons are emitted. Thereby, the threshold voltage of the nonvolatile memory element M1w is lowered. Conversely, when the low voltage Vss is applied to the drain region D of the nonvolatile memory element M1w and the pulse voltage Vpp is applied to the control gate region CG, the charge holding region 21 is supplied from the drain region D through the charge injection port 211. Electrons are injected into the. Thereby, the threshold voltage of the nonvolatile memory element M1w is increased.

As shown in FIG. 22, the reference voltage generation circuit 3 switches SW1 to SW5, SW7, SW9, and SW10 at the time of rewriting for setting the nonvolatile memory element M2 side (that is, the nonvolatile memory elements M2w and M2r) to the enhancement state. Switch to the following state. Here, a case where the threshold voltage before adjustment on the nonvolatile memory element M2 side is lower than the threshold voltage after adjustment is taken as an example.
Switch SW1: Low voltage supply terminal Vss side Switch SW2: Low voltage supply terminal Vss side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switches SW5 and SW7: Open state (open state)
Switch SW9: Arbitrary (in FIG. 25, the low voltage supply terminal Vss side)
Switch SW10: Pulse voltage Vpp side

  For this reason, since the low voltage Vss is applied to the source region S of the nonvolatile memory element M2w and the pulse voltage Vpp is applied to the control gate region CG, the source region S is transferred to the charge holding region 21 via the charge injection port 211. Electrons are injected. This increases the threshold voltage of the nonvolatile memory element M2w. On the contrary, when the pulse voltage Vpp is applied to the source region S of the nonvolatile memory element M2w and the low voltage Vss is applied to the control gate region CG, the source region S is transferred from the charge holding region 21 via the charge injection port 211. Electrons are emitted to Thereby, the threshold voltage of the nonvolatile memory element M2w is lowered.

  As described above, according to the present embodiment, it is possible to realize a nonvolatile memory element having high charge retention characteristics while giving flexibility to the element layout. Therefore, it is possible to realize a highly accurate analog circuit in which deterioration of electrical characteristics is effectively suppressed and the influence of manufacturing variation is extremely small. Moreover, according to this embodiment, the variation in electrical characteristics can be reduced. A nonvolatile memory element having excellent charge retention characteristics and an analog circuit including the nonvolatile memory element can be realized.

  Further, the nonvolatile memory element and the analog circuit including the nonvolatile memory element according to the present embodiment can adjust the threshold voltage by adjusting the charge amount of the floating gate region FG of the nonvolatile memory elements M1w and M2w. Therefore, according to the first embodiment. Effects similar to those of the nonvolatile memory element and the analog circuit including the nonvolatile memory element are obtained.

  Further, the reference voltage generation circuit 3 in the present embodiment includes the nonvolatile memory element M having the configuration shown in FIG. 19, so that the current path during charge injection and charge discharge and the operation of the reference voltage generation circuit 3 are The current path can be separated. Thereby, the reference voltage generation circuit 3 can prevent unexpected rewriting of the nonvolatile memory element and can improve the reliability.

1, 2, 3, 100 Reference voltage generation circuit 10 Well region 11, 13 N-type region 12, 14 N + region 20, 70 Insulator 21, 71 Charge holding region 21a, 31 Polysilicon film 21b Fluorine existing region 22, 72 Gate Insulating film 22a Insulating film 23 Side wall oxide film 23a Oxide film 24 Upper insulating film 24a ONO film 25, 32 Side wall 41, 42 Element isolation regions 51, 52, 53 Plug 61 Protective film 73 Side wall oxide film 74 Upper insulating film 211 Charge Entrance 221 Tunnel insulating film 221a Thin film region A1 First region A2 Second region B Back gate CG Control gate region D Drain region FG Floating gate region G Gate regions M, M1, M1r, M1w, M2, M2r, M2w, Mr, Mw Nonvolatile memory element Md Depletion type transistor Me Nhansumento type transistor S source region

Claims (16)

A charge retention region;
A non-volatile memory element comprising: an insulator surrounding a whole surface of the charge retention region and having a halogen distributed in at least a part of the region surrounding the whole surface. The nonvolatile memory element according to claim 1, wherein the halogen is distributed so as to surround the entire surface. The nonvolatile memory element according to claim 1, wherein the charge holding region has a charge injection port for injecting a charge. The nonvolatile memory element according to any one of claims 1 to 3, wherein the halogen is fluorine. 5. The nonvolatile memory element according to claim 1, wherein a content ratio of the halogen in the insulator is 0.01 atm% or more in at least a part of the region in contact with the charge holding region. 6. The nonvolatile memory element according to claim 1, wherein a content ratio of the halogen in the insulator is 0.05 atm% or more in at least a part of the region in contact with the charge holding region. 7. The nonvolatile memory element according to claim 1, wherein a content ratio of the halogen in the insulator is 0.1 atm% or more in at least a part of the region in contact with the charge holding region. A gate region having the charge retaining region and the insulator;
A drain region formed on one of both sides below the gate region;
The non-volatile memory element as described in any one of Claim 1-7 provided with the source region formed in the other of the said both sides. An analog circuit comprising the nonvolatile memory element according to claim 1. A plurality of the nonvolatile memory elements according to claim 8,
At least some of the plurality of nonvolatile memory elements are connected in series;
The analog circuit by which the voltage output terminal from which a voltage is output is connected to the connection part of the said several non-volatile memory element connected in series. The plurality of non-volatile storage elements are:
The analog circuit according to claim 10, comprising: a nonvolatile memory element having at least a negative threshold voltage; and a nonvolatile memory element having a positive threshold voltage. The analog circuit according to claim 10 or 11, wherein the halogen content ratios of the plurality of nonvolatile memory elements connected in series are substantially equal to each other. The first control gate region provided in the gate region having the charge holding region and the insulator of the first nonvolatile memory device which is the nonvolatile memory device according to any one of claims 1 to 7, Connected second control gate region,
A second charge retention region electrically connected to the first charge retention region which is the charge retention region of the first nonvolatile memory element;
A second nonvolatile memory element having a gate insulating film formed in contact with the second charge retention region,
The charge injection port provided in the first nonvolatile memory element is an analog circuit formed in a region not in contact with a current path formed in the second nonvolatile memory element. A non-volatile memory element according to claim 1 or 2,
The area of the non-volatile memory element is 10 μm ² or more,
The nonvolatile memory element is an analog circuit having no array structure. The analog circuit according to claim 14, wherein the area of the nonvolatile memory element is 50 μm ² or more. The analog circuit according to claim 15, wherein an area of the nonvolatile memory element is 100 μm ² or more.

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