JP2018022814A - Nitride semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device having sufficiently small electric resistance, whereby a current can flow with high efficiency, and a method of manufacturing the same.SOLUTION: The nitride semiconductor device includes: a tunnel junction layer 15; and a second n-GaN layer 16. An n-type semiconductor impurity is added to the tunnel junction layer 15. The second n-GaN layer 16 is formed above the tunnel junction layer 15. In addition, the tunnel junction layer 15 is characterized in that an interface on a side of the second n-GaN layer 16 is three-dimensionally grown.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a nitride semiconductor device and a method for manufacturing the same.

  Most semiconductor elements are formed by stacking a p-type semiconductor layer and an n-type semiconductor layer. In order to realize an element that operates with high efficiency, a p-type semiconductor layer and an n-type semiconductor layer with low electrical resistance are required. However, a nitride semiconductor useful as a light emitting / receiving element in the ultraviolet / visible wavelength region has a p-type semiconductor layer with an electric resistivity of about 1 Ωcm. This is more than 100 times larger than that of an n-type nitride semiconductor or an infrared semiconductor such as n-type GaAs (gallium arsenide) or p-type GaAs of 0.01 Ωcm or less. Furthermore, there is a problem that p-type AlGaN cannot be obtained with AlGaN having a large band gap and a large AlN (aluminum nitride) molar fraction required in the deep ultraviolet region.

  The tunnel junction is a pn junction in which p-type semiconductor impurities and n-type semiconductor impurities, which are semiconductor impurities, are added to the p-type semiconductor layer and the n-type semiconductor layer, respectively, at a higher concentration than the normal pn junction. As a result, the thickness of the depletion layer formed at the interface between the p-type semiconductor layer and the n-type semiconductor layer in the tunnel junction is smaller than that in a normal pn junction. Thus, when a reverse bias voltage is applied to the p-type semiconductor layer and the n-type semiconductor layer of the tunnel junction, electrons pass through the depletion layer and move from the valence band of the p-type semiconductor layer to the conduction band of the n-type semiconductor layer (tunnel). can do. That is, the tunnel junction can pass a current from the n-type semiconductor layer to the p-type semiconductor layer.

  Therefore, in a nitride semiconductor device, most of the p-type semiconductor layer, which is a source of holes having a low mobility and a large effective mass compared to electrons, has a higher mobility than holes by using a tunnel junction. It can be replaced with an n-type semiconductor layer which is an electron source with a small effective mass. That is, by using a tunnel junction in the nitride semiconductor element, most of the p-type semiconductor layer having a large electric resistance can be replaced with an n-type semiconductor layer having a low electric resistance. If the electrical resistance of the tunnel junction itself can be further reduced, the electrical resistance of the conventional device can be further reduced, and further, the deep ultraviolet light-emitting device that has been delayed in practical use can be put into practical use. . However, nitride semiconductors have a large band gap and it is difficult to increase the acceptor concentration. For this reason, it has been considered that tunnel junctions using nitride semiconductors have difficulty in reducing the electrical resistance.

The nitride semiconductor light emitting devices of Non-Patent Documents 1 and 2 use a GaInN layer as a tunnel junction layer. As a result, in this nitride semiconductor light emitting device, the band gap of the tunnel junction layer is reduced, and a large polarization charge is generated by piezo polarization generated when InN (indium nitride) is added. It is disclosed that an extremely low voltage drop is exhibited in a low current density region (100 A / cm ² or less) necessary for driving an LED which is a light emitting element.

On the other hand, the nitride semiconductor light-emitting device having a tunnel junction of Non-Patent Document 3 is a p-type semiconductor layer on the surface side of the device in a high current density region (-10 kA / cm ² ) necessary for laser driving. It is disclosed that the driving voltage is about 2 V (volt) higher than that of a conventional element having a p-type contact layer.

S. Krishnamoorthy, et al, "Polarization-engineered GaN / InGaN / GaN tunnel diodes", Applied Physics Letter, (USA), November 2010, Vol. 97, Issue 20 M. Kaga, et al, "GaInN-Based Tunnel Junctions in n? P? N Light Emitting Diodes" Japanese Journal of Applied Physics, 2013, Vol. 52, Number8S D. Minamikawa, et al, "GaInN-based tunnel junctions with high InN mole fractions grown by MOVPE" Physica Status Solidi, May 2015, Vol. 252, Issue 5, p. 1127-1131

In order to further reduce the driving voltage for driving the nitride semiconductor device, the depletion layer thickness of the tunnel junction layer is reduced by increasing the concentration of the semiconductor impurity added to the tunnel junction layer. The probability of electrons tunneling through the layer may be increased. However, when the concentration of the semiconductor impurity added to the tunnel junction layer exceeds 1 × 10 ¹⁹ cm ⁻³ , which is a higher concentration, the crystallinity of the tunnel junction layer is lowered and the crystal surface flatness of the tunnel junction layer is good. I know it will disappear. That is, the electrical resistance of the tunnel junction layer can be reduced by increasing the concentration of the semiconductor impurity added to the tunnel junction layer, but the surface flatness of the tunnel junction layer crystal is not good. For this reason, it is considered that the method of adding a higher concentration of semiconductor impurities to the tunnel junction layer is difficult to use for a light emitting element such as a laser that reflects and resonates light on the surface of the crystal.

  The present invention has been made in view of the above-described conventional circumstances, and provides a nitride semiconductor device capable of flowing a current with high efficiency and a method of manufacturing the nitride semiconductor device by sufficiently reducing the electrical resistance of the device. Is a problem to be solved.

Specifically, as a result of intensive studies by the inventors based on the above results, the addition amount of the n-type semiconductor impurity which is a semiconductor impurity in the nitride semiconductor tunnel junction layer is a high concentration of 1 × 10 ²⁰ cm ⁻³ or more. Thus, a tunnel junction layer having a low electric resistance is formed. Then, the semiconductor impurity of the n-GaN layer, which is a surface layer for crystal growth on the surface side of the tunnel junction layer, the surface flatness of the tunnel junction layer crystal that has become unfavorable due to the addition of the n-type semiconductor impurity at a high concentration It is recovered by controlling the concentration, growth conditions, and the like. Thus, the inventors have found a method for obtaining a nitride semiconductor device having low electrical resistance and good crystal surface flatness.

  In the conventional method of manufacturing a semiconductor device, when layers are stacked and crystal growth is performed, the layers are sequentially stacked while maintaining the flatness of the surface of each layer or the interface of the layers to be stacked. As a result, the conventional method for manufacturing a semiconductor element can exhibit the functions of the layers stacked and bonded adjacent to each other, thereby obtaining a higher performance element. On the other hand, in the present invention, in order to give priority to lowering the electric resistance of the element, semiconductor impurities are added to the tunnel junction layer at a higher concentration. Thereby, the surface flatness of the crystal of the tunnel junction layer is not good. Then, the crystal surface flatness of the tunnel junction layer which has become unsatisfactory is recovered by controlling the concentration of semiconductor impurities, the growth conditions, and the like of the layer structure in which the crystal is grown on the surface side of the tunnel junction layer. In this way, a nitride semiconductor device having a good crystal surface flatness is obtained. That is, the present invention is different from the conventional technical common sense.

The nitride semiconductor device of the present invention is
A tunnel junction layer doped with semiconductor impurities;
A surface layer formed above the tunnel junction layer;
With
The interface of the tunnel junction layer on the surface layer side is three-dimensionally grown.

  In this nitride semiconductor device, an island-like crystal is formed on the surface layer side of the tunnel junction layer to which a semiconductor impurity is added, and the island-like crystal is formed along the surface of the layer. It is formed by three-dimensional growth that grows away from the surface. That is, in this nitride semiconductor device, a semiconductor impurity is added to the tunnel junction layer at a high concentration. Thereby, since this nitride semiconductor element can suppress the thickness of the depletion layer formed in the tunnel junction layer, electrons and holes can pass through the depletion layer satisfactorily. Therefore, this nitride semiconductor device can further reduce the electrical resistance of the tunnel junction layer. That is, this nitride semiconductor element can flow a current satisfactorily.

In addition, the method for manufacturing the nitride semiconductor device of the present invention includes:
A tunnel junction layer forming step of forming a tunnel junction layer by adding a three-dimensionally grown amount of semiconductor impurities is provided.

  This method for manufacturing a nitride semiconductor device includes a tunnel junction layer forming step of forming a tunnel junction layer by adding a three-dimensionally grown amount of semiconductor impurities. That is, in this nitride semiconductor device manufacturing method, a high concentration of semiconductor impurities is added to the tunnel junction layer. For this reason, since this nitride semiconductor device manufacturing method can suppress the thickness of the depletion layer formed in the tunnel junction layer, electrons and holes can pass through the depletion layer satisfactorily. Therefore, this nitride semiconductor device manufacturing method can further reduce the electrical resistance of the tunnel junction layer. In other words, this nitride semiconductor device manufacturing method can manufacture a nitride semiconductor device having a tunnel junction layer that allows a current to flow satisfactorily.

  Therefore, the nitride semiconductor device of the present invention has a sufficiently small electric resistance, and thereby allows a current to flow with high efficiency. In addition, the method for manufacturing a nitride semiconductor device of the present invention can manufacture a nitride semiconductor device that has a sufficiently low electrical resistance and can flow current with high efficiency.

FIG. 3 is a schematic view showing a structure in which an element is formed in Example 1. It is a schematic diagram which shows the structure of the layer of the sample of Examples 2-4 and Comparative Examples 1-3, (A) shows the structure of the layer of the sample of Examples 2-4, (B) is Comparative Example 2. 3 shows the layer structure of the three samples, and (C) shows the layer structure of the sample of Comparative Example 1. It is a figure which shows the AFM image of the surface of the 2nd n-GaN layer of the sample of Comparative Examples 1-3, (A) is a comparative example whose addition density | concentration of Si to a tunnel junction layer is 7 * 10 < ¹⁹ > cm < ^-3 >. 2 is an AFM image of the surface of the second n-GaN layer of the sample 1, and (B) shows the second n-GaN of the sample of Comparative Example 2 in which the addition concentration of Si to the tunnel junction layer is 1 × 10 ²⁰ cm ^−3. 2C is an AFM image of the surface of the layer, and FIG. 3C is an AFM image of the surface of the second n-GaN layer of the sample of Comparative Example 3 in which the concentration of Si added to the tunnel junction layer is 2 × 10 ²⁰ cm ^−3. . It is a figure which shows the AFM image of the surface of the tunnel junction layer of the sample of the comparative example 3. FIG. It is a figure which shows the AFM image of the surface of the 2nd n-GaN layer of the sample of Example 2, Comprising: (A) is an AFM image of the surface of the 2nd n-GaN layer when the thickness of 2nd n-GaN layer is 20 nm. (B) is an AFM image of the surface of the second n-GaN layer when the thickness of the second n-GaN layer is 50 nm, and (C) is a second n- when the thickness of the second n-GaN layer is 400 nm. It is an AFM image of the surface of a GaN layer. It is a graph which shows each addition density | concentration of Si and Mg which are the semiconductor impurities of the depth direction of the sample of Example 2 and the comparative example 1, Comprising: (A) is the depth direction of the crystal | crystallization of the sample of Example 2. The additive concentrations of Si and Mg are shown, and (B) shows the additive concentrations of Si and Mg in the crystal depth direction of the sample of Comparative Example 1. It is a graph which shows the magnitude | size of the voltage with respect to the current density of the sample of Examples 2-4 and the comparative example 1. FIG.

  A preferred embodiment of the present invention will be described.

  In the nitride semiconductor device of the present invention, the surface of the surface layer can grow two-dimensionally. In this case, the nitride semiconductor device can cover the tunnel junction layer in which the interface on the surface layer side is three-dimensionally grown with the two-dimensionally grown surface layer. That is, in this nitride semiconductor device, a tunnel junction layer that is three-dimensionally grown by adding a semiconductor impurity at a high concentration is covered with a surface layer that is two-dimensionally grown. Can be used.

  In the nitride semiconductor device of the present invention, the semiconductor impurity may be an n-type semiconductor impurity. In this case, the nitride semiconductor element is formed by adding an n-type semiconductor impurity in such an amount that the interface on the surface layer side of the tunnel junction layer grows three-dimensionally. As a result, the surface layer of this nitride semiconductor element can be formed not with a p-type semiconductor layer but with an n-type semiconductor layer. Thereby, this nitride semiconductor element can make electric resistance smaller.

  The method for manufacturing a nitride semiconductor device of the present invention may include a surface layer forming step of growing a surface layer two-dimensionally above the tunnel junction layer formed by executing the tunnel junction layer forming step. In this case, the nitride semiconductor device manufacturing method can be formed by two-dimensionally growing the surface layer by executing the surface layer forming step. For this reason, this method for manufacturing a nitride semiconductor device can cover the tunnel junction layer grown in three dimensions by stacking the surface layer on the surface side of the tunnel junction layer grown in three dimensions by two-dimensional growth. For this reason, since this method for manufacturing a nitride semiconductor device can use a tunnel junction layer that is three-dimensionally grown by adding semiconductor impurities, the nitride semiconductor device having a tunnel junction layer having a smaller electrical resistance. Can be manufactured.

  In the method for manufacturing a nitride semiconductor device of the present invention, the semiconductor impurity may be an n-type semiconductor impurity. In this case, in this method for manufacturing a nitride semiconductor device, a tunnel junction layer is formed by adding an n-type semiconductor impurity in a three-dimensional growth amount. Thereby, in this method for manufacturing a nitride semiconductor device, the surface layer can be formed of an n-type semiconductor layer instead of a p-type semiconductor layer. Thus, the nitride semiconductor device manufacturing method can manufacture a nitride semiconductor device having a smaller electric resistance.

  Next, Examples 1 to 4 and Comparative Examples 1 to 3 embodying the nitride semiconductor device of the present invention will be described with reference to the drawings.

<Example 1>
Example 1 shows the structure of a nitride semiconductor device common to the samples of Examples 2 to 4 described later and the samples of Comparative Examples 1 to 3, and a manufacturing method thereof. As shown in FIG. 1, the nitride semiconductor device of Example 1 includes a first n-GaN layer 11, a GaInN / GaN five-quantum well active layer 12, a p-AlGaN layer 13, a p-GaN layer 14, a tunnel junction layer 15. And a second n-GaN layer 16 which is a surface layer.

  The nitride semiconductor device of Example 1 includes a GaN template 10 formed on the surface side of a sapphire substrate S (hereinafter referred to as a substrate) (the table is the upper side in FIG. 1, the same applies hereinafter) via a low-temperature deposition buffer layer B. A crystal is grown on the surface of the substrate by laminating using MOCVD (metal organic chemical vapor deposition). The sapphire substrate S has a C-plane ((0001) plane) as the surface.

First, the first n-GaN layer 11 is stacked on the surface of the GaN template 10 formed on the surface side of the substrate to grow a crystal. Specifically, first, a substrate is set in the reaction furnace. Then, NH ₃ (ammonia), which is a raw material of N (nitrogen), and H ₂ (hydrogen), which is a carrier gas, are supplied into the reaction furnace, and the temperature in the reaction furnace is adjusted to set the substrate temperature to 1050 ° C. To. Then, TMGa (trimethylgallium) which is a raw material of Ga (gallium) and SiH ₄ (silane) which is a raw material of Si (silicon) which is an n-type semiconductor impurity which is a semiconductor impurity are supplied into the reaction furnace, A first n-GaN layer 11 having a thickness of 2 μm is stacked and crystal is grown. The supply amount of SiH ₄ into the reaction furnace is adjusted so that the addition concentration of Si as an n-type semiconductor impurity added to the first n-GaN layer 11 is 8 × 10 ¹⁸ cm ⁻³ .

  Next, a GaInN / GaN quintoxide well active layer 12 is stacked on the surface of the first n-GaN layer 11 to grow a crystal. The GaInN / GaN five quantum well active layer 12 has a GaInN well layer (not shown) and a GaN barrier layer (not shown).

First, a GaInN well layer is stacked and crystal is grown. Specifically, the supply of H ₂ , TMGa, and SiH ₄ into the reaction furnace is stopped. Then, N ₂ (nitrogen) is supplied as a carrier gas into the reaction furnace. And the temperature in a reaction furnace is adjusted, and the temperature of a board | substrate shall be 780 degreeC. Then, TEGa (triethylgallium), which is a raw material of Ga, and TMIn (trimethylindium), which is a raw material of In (indium), are supplied into the reaction furnace, and a GaInN well layer having a thickness of 2 nm is stacked to grow crystals. Let

  Next, a GaN barrier layer is stacked on the surface of the GaInN well layer to grow a crystal. Specifically, the supply of TMIn into the reaction furnace is stopped, and a GaN barrier layer having a thickness of 10 nm is stacked to grow a crystal. A pair of GaInN quantum well layers and GaN barrier layers grown in this way is used as a pair, and five pairs of these pairs are stacked to grow a crystal. Thus, the GaInN / GaN quintet well active layer 12 is formed. Then, the supply of TEGa and TMIn into the reaction furnace is stopped.

Next, a p-AlGaN layer 13 is stacked on the surface of the GaInN / GaN quintet well active layer 12 to grow a crystal. Specifically, the carrier gas supplied into the reactor is switched from N ₂ to H ₂ . And the temperature in a reaction furnace is adjusted and the temperature of a board | substrate shall be 1000 degreeC. In the reactor, TMGa, TMAl (trimethylaluminum) which is a raw material of Al (aluminum), and Cp ₂ Mg (cyclopentadienylmagnesium) which is a raw material of Mg (magnesium) which is a p-type semiconductor impurity which is a semiconductor impurity. ), A p-AlGaN layer 13 having a thickness of 20 nm is stacked, and a crystal is grown. The supply amount of Cp ₂ Mg into the reaction furnace is adjusted so that the concentration of Mg as a p-type semiconductor impurity added to the p-AlGaN layer 13 is 2 × 10 ¹⁹ cm ⁻³ .

Next, the p-GaN layer 14 is stacked on the surface of the p-AlGaN layer 13 and crystal is grown. Specifically, the supply of TMAl into the reaction furnace is stopped, and a 160-nm-thick p-GaN layer 14 is stacked to grow crystals. The concentration of Mg which is a p-type semiconductor impurity added to the p-GaN layer 14 is 4 × 10 ¹⁹ cm ⁻³ . Then, the supply of TMGa and Cp ₂ Mg into the reaction furnace is stopped, and the carrier gas is switched from H ₂ to N ₂ . And the temperature in a reaction furnace is adjusted, and the temperature of a board | substrate shall be 720 degreeC.

Next, the tunnel junction layer 15 is formed on the surface of the p-GaN layer 14. The tunnel junction layer 15 has a p ^++- GaInN layer (not shown) and an n ^++- GaN layer (not shown). Here, p ⁺⁺ means a state where Mg which is a p-type semiconductor impurity is added at a high concentration, and n ⁺⁺ means a state where Si which is an n-type semiconductor impurity is added at a high concentration.

TEGa, Cp ₂ Mg, and a predetermined amount of TMIn are supplied into the reaction furnace. In this way, a p ^++- GaInN layer having a thickness of 2 nm is grown. The flow rate of Cp ₂ Mg is adjusted so that the concentration of Mg, which is a p-type semiconductor impurity added to the p ^++- GaInN layer, is 1 to 2 × 10 ²⁰ cm ⁻³ . The molar fraction of InN in the p ^++- GaInN layer is 0.35. Thus, the crystal growth of the p ^++- GaInN layer is completed.

Next, an n ^++- GaN layer is stacked on the surface of the p ^++- GaInN layer to grow a crystal. Specifically, after a p ^++- GaInN layer is stacked and crystal is grown, the supply of Cp ₂ Mg and TMIn to the reactor is stopped. Then, SiH ₄ is supplied into the reactor, and an n ^++- GaN layer having a thickness of 15 nm is stacked to grow crystals. The flow rate of SiH ₄ is adjusted so that the concentration of Si, which is an n-type semiconductor impurity added to the n ⁺⁺ -GaN layer, is 1 × 10 ²⁰ cm ⁻³ or more. That is, the n-type semiconductor impurity which is a semiconductor impurity is added to the tunnel junction layer 15.

Next, the second n-GaN layer 16 is stacked on the surface of the tunnel junction layer 15 to grow a crystal. Specifically, the carrier gas supplied into the reactor is switched from N ₂ to H ₂ . Then, the temperature of the substrate is adjusted to 980 ° C. by adjusting the temperature in the reaction furnace. Then, the second n-GaN layer 16 is stacked with a thickness of 400 nm and crystal is grown. The concentration of Si that is an n-type semiconductor impurity added to the second n-GaN layer 16 is 1 × 10 ¹⁹ cm ⁻³ . It should be noted that the growth pressure, which is the atmospheric pressure in the reaction furnace in which the second n-GaN layer 16 is stacked to grow crystals, can be adjusted to a desired value. Then, the supply of TMGa and SiH ₄ into the reaction furnace is stopped to finish the crystal growth. Then, the carrier gas supplied into the reactor is switched from H ₂ to N ₂ . Then, when the temperature in the reaction furnace is adjusted and the temperature of the substrate becomes 400 ° C. or lower, the supply of NH ₃ into the reaction furnace is stopped. Then, after the temperature of the substrate reaches room temperature, the inside of the reaction furnace is purged and the substrate is taken out from the reaction furnace.

  Next, an element capable of current injection is formed by using the substrate thus grown by crystal growth and having a layer structure.

  First, in a plan view from the surface, a mesa structure 20 having a circular shape with a diameter of 35 μm is formed on a substrate. Specifically, the mesa structure 20 is formed on the substrate using photolithography and dry etching. More specifically, a circular photoresist or metal mask having a diameter of 35 μm is formed on the surface of the second n-GaN layer 16 which is stacked and grown on the top surface of the substrate (not shown). The portion directly under the photoresist or metal mask is not removed by etching. The region where the photoresist or the metal mask is not formed is etched until the first n-GaN layer 11 is exposed on the surface. Thus, the mesa structure 20 having a circular shape with a diameter of 35 μm is formed on the substrate.

Next, the substrate on which the mesa structure 20 is formed is annealed in an O ₂ (oxygen) atmosphere at 725 ° C. for 30 minutes, and the embedded p-AlGaN layer 13, p-GaN layer 14, and tunnel junction layer 15 Mg of the p ^++- GaInN layer is activated. Here, the activation refers to p-AlGaN layer 13, p-GaN layer 14 to which Mg is added by removing H (hydrogen) bonded to Mg, which is a p-type semiconductor impurity, to activate Mg, And improving the electrical conductivity of the p ⁺⁺ -GaInN layer of the tunnel junction layer 15. By activating in this way, the etching has deactivated Mg from the side surfaces of the p-AlGaN layer 13, the p-GaN layer 14, and the p ^++- GaInN layer of the tunnel junction layer 15 whose side surfaces are exposed by etching. To leave.

  Next, the first electrode 21 and the second electrode 22 are formed. Specifically, the first electrode 21 having a circular shape is formed on the surface of the mesa structure 20. In addition, an annular second electrode 22 is formed on the exposed surface of the first n-GaN layer 11 so as to surround the periphery of the mesa structure 20. The first electrode 21 and the second electrode 22 are Ti / Al / Ti / Au. The first electrode 21 and the second electrode 22 are formed in a lump. Thus, the nitride semiconductor device of Example 1 is formed in which current flows from the first electrode 21 through the tunnel junction layer 15 and the GaInN / GaN quintet well active layer 12 to the second electrode 22.

<Comparative Examples 1-3>
Using the method for manufacturing a nitride semiconductor device of Example 1, samples of Comparative Examples 1 to 3 were produced. Specifically, the samples of Comparative Examples 1 to 3 change the additive concentration of Si added to the n ^++- GaN layer of the tunnel junction layer 15 in the nitride semiconductor device manufacturing method of Example 1. . In the samples of Comparative Examples 1 to 3, the growth pressure, which is the atmospheric pressure in the reaction furnace when the second n-GaN layer 16 is stacked and crystal is grown, is set to 90 kPa. Table 1 shows the additive concentration of Si added to each of the n ^++- GaN layers of the tunnel junction layer 15 of the samples of Comparative Examples 1 to 3.

The sample of Comparative Example 1 is a crystal grown while always maintaining good surface flatness. As shown in FIG. 3A, the sample of Comparative Example 1 has an atomic layer step formed on the surface of the second n-GaN layer 16, and it can be seen that the surface flatness is good. The sample of Comparative Example 1 has an RMS (root mean square) value of the surface level difference of 0.3 nm. That is, the sample of Comparative Example 1 has good surface flatness of the surface 16C of the second n-GaN layer 16 as shown in FIG. In addition, since the sample of Comparative Example 1 was crystal-grown while always maintaining good surface flatness, the surface 15C of the n ^++- GaN layer of the tunnel junction layer 15 is also considered to have good surface flatness. .

  As shown in FIG. 3B, the sample of Comparative Example 2 has a plurality of pits P <b> 1 that are crystal defects formed on the surface of the second n-GaN layer 16. The sample of Comparative Example 2 has a surface level difference RMS value of 1.48 nm. Further, as shown in FIG. 3C, the sample of Comparative Example 3 has a plurality of pits P <b> 2 having a larger area on the surface of the second n-GaN layer 16 than the sample of Comparative Example 2. The sample of Comparative Example 3 has a surface level difference RMS value of 19.0 nm. For this reason, when the concentration of Si added to the tunnel junction layer 15 is higher, the surface flatness of the device is greatly affected, and therefore the optical and electrical properties of the device are significantly affected. I understood.

Further, FIG. 4 shows the result of suspending the crystal growth of the sample of Comparative Example 3 once the crystal growth of the tunnel junction layer 15 is completed, and observing the surface of the tunnel junction layer 15 by AFM. Samples of Comparative Example 3, a high concentration (2 × 10 ²⁰ cm ^-3) in the thickness of the ⁿ ++ -GaN layer of the tunnel junction layer 15 with the addition of Si despite 15nm and ^thin, the n ++ -GaN layer It was found that the surface was growing three-dimensionally and the surface flatness began to become poor. The sample of Comparative Example 3 at this time has an RMS value of the surface level difference of 0.67 nm. Here, three-dimensional growth refers to the direction in which island-like crystals independent from the surroundings are formed on the surface of the layer where the crystal is growing, and the island-like crystals are along the surface of the layer and away from the surface of the layer. To grow into. The surface of the three-dimensionally grown crystal has poor surface flatness.

That is, in the sample of Comparative Example 3, the surface flatness of the surface 15B of the n ⁺⁺ -GaN layer of the tunnel junction layer 15 and the surface 16B of the second n-GaN layer 16 is not good as shown in FIG. . In addition, since the sample of Comparative Example 2 has a plurality of pits P1 that are crystal defects formed on the surface of the second n-GaN layer 16, the n ^++- GaN of the tunnel junction layer 15 is the same as the sample of Comparative Example 3. It is considered that the surface flatness of the surface 15B of the layer is not good.

  On the other hand, the surface flatness of the surface 16C of the second n-GaN layer 16 is better than that of the samples of Comparative Examples 2 and 3 in the sample of Comparative Example 1, but the concentration of Si added to the tunnel junction layer 15 Therefore, the electrical resistance of the tunnel junction layer 15 is higher than that of the samples of Comparative Examples 2 and 3.

<Examples 2 to 4>
A quantum well layer or the like is formed by stacking extremely thin layers (several nm). For this reason, in the prior art, in order to obtain a layer with good surface flatness, it is common to perform crystal growth by slowing the growth rate of stacking and crystal growth. In addition, in the prior art, when forming an element structure by laminating layers, if the surface flatness of the layer once laminated and crystal growth is not good, it is determined that a good element structure cannot be obtained at that time. Thus, it has been generally performed to stop crystal growth.

  However, the inventors have made the surface junction of the tunnel junction layer 15 intentionally stacked and crystal-grown once unsatisfactory, and further, the second n−, which is a surface layer that is stacked on the tunnel junction layer 15 and crystal-grown. By controlling the concentration of semiconductor impurities and the growth conditions of the GaN layer 16 to fill the crystal surface of the tunnel junction layer 15 whose surface flatness is no longer good, a sample in which the surface flatness of the crystal is restored to a good one Produced. Specifically, the samples of Examples 2 to 4 were produced using the nitride semiconductor device manufacturing method of Example 1.

More specifically, the samples of Examples 2 to 4 are tunnel junctions when the n ^++- GaN layer of the tunnel junction layer 15 is stacked and grown in the nitride semiconductor device manufacturing method of Example 1. The tunnel junction layer 15 is formed by adding a certain amount of n-type semiconductor impurities while adjusting the growth rate so that the layer 15 grows three-dimensionally (tunnel junction layer forming step). Then, the second n-GaN layer 16 is two-dimensionally grown on the upper side of the tunnel junction layer 15 formed by executing the tunnel junction layer formation step (surface layer formation step). That is, the samples of Examples 2 to 4 include the tunnel junction layer 15 to which the n-type semiconductor impurity is added and the second n-GaN layer 16 formed on the upper side of the tunnel junction layer 15. The interface of the tunnel junction layer 15 on the layer 16 side is three-dimensionally grown.

In the surface layer forming step, the growth pressure, which is the atmospheric pressure in the reaction furnace, is set to 20 kPa as compared to the conditions when the samples of Comparative Examples 1 to 3 are manufactured, and NH ₃ which is a raw material of N which is a group V element and The temperature of the substrate at the time of increasing the Group V source / Group III source supply ratio, which is the supply ratio into the reactor with TEGa, which is the Group III element Ga source, or when growing the crystal by stacking Or higher. Thereby, in the samples of Examples 2 to 4, when the second n-GaN layer 16 is stacked and the crystal grows, the crystal can easily grow two-dimensionally. That is, in the samples of Examples 2 to 4, the surface of the second n-GaN layer 16 is two-dimensionally grown. Here, the two-dimensional growth is crystal growth in a direction along the surface of the layer on the surface of the layer where the crystal is growing. An atomic layer step is formed on the surface of the two-dimensionally grown crystal, and the surface flatness is good.

In the tunnel junction layer forming step, the samples of Examples 2 to 4 are Si added to the n ^++- GaN layer of the tunnel junction layer 15 in order to make the electrical resistance of the tunnel junction layer 15 smaller than that of the samples of Comparative Examples 1 to 3. Is changed to a higher concentration than the samples of Comparative Examples 1 to 3. Table 2 shows the addition concentration of Si added to each of the n ^++- GaN layers of the samples of Examples 2 to 4.

  The change in surface flatness with respect to the layer thickness of the sample of Example 2 produced in this way was examined. Specifically, in the surface layer forming step of the sample of Example 2, the state of the crystal surface of the second n-GaN layer 16 when the thickness of the second n-GaN layer 16 is 20 nm, 50 nm, and 400 nm. 5A to 5C show the results of observation using AFM.

  As shown in FIG. 5A, in the sample of Example 2, when the thickness of the second n-GaN layer 16 is 20 nm (hereinafter referred to as a layer thickness of 20 nm), the crystal is three-dimensionally grown. The RMS value of the surface step at this time is 1.24 nm. As shown in FIG. 5B, in the sample of Example 2, when the thickness of the second n-GaN layer 16 is 50 nm (hereinafter referred to as a layer thickness of 50 nm), the crystal starts to grow two-dimensionally. The RMS value of the surface step at this time is 3.89 nm. As shown in FIG. 5C, the sample of Example 2 shows that when the thickness of the second n-GaN layer 16 is 400 nm, an extremely flat surface on which atomic layer steps are observed is formed. It was. The RMS value of the surface step at this time is 0.28 nm. Note that the RMS value when the layer thickness is 50 nm is larger than the RMS value when the layer thickness is 20 nm. This is presumably because in the process of crystal growth of the second n-GaN layer 16, the three-dimensional crystal growth continued until at least the thickness of the second n-GaN layer 16 reached 50 nm. Further, in the samples of Example 3 and Example 4, the RMS values of the surface steps when the thickness of the second n-GaN layer 16 was 400 nm were 0.22 nm and 0.26 nm, respectively.

That is, in the samples of Examples 2 to 4, Si is added to the n ⁺⁺ -GaN layer of the tunnel junction layer 15 at a higher concentration than the samples of Comparative Examples 1 to 3 as shown in FIG. It is considered that the surface flatness of the surface 15A of the n ^++- GaN layer of the tunnel junction layer 15 is not good. In addition, the samples of Examples 2 to 4 have atomic layer steps formed, and the RMS value is smaller than the surface of the second n-GaN layer 16 of the sample of Comparative Example 1 having good surface flatness. That is, the samples of Examples 2 to 4 have good surface flatness of the surface 16A of the second n-GaN layer 16.

FIGS. 6A and 6B show the results of elemental analysis in the depth direction of Mg and Si for the sample of Example 2 and the sample of Comparative Example 1, respectively. As shown in FIG. 6 (B), the sample of Comparative Example 1 which was laminated and crystal-grown while always maintaining good surface flatness had a Mg addition concentration of 1 × 10 ²⁰ cm ^{− in the} tunnel junction layer 15. ³ and the addition concentration of Si is 7 × 10 ¹⁹ cm ⁻³ . Further, it was found that the sample of Comparative Example 1 had a higher Mg concentration in the second n-GaN layer 16 than the sample of Example 2. This is considered to be due to Mg being taken in during the crystal growth of the second n-GaN layer 16 due to the memory effect of Mg. As a result, the electrons added by adding Si to the second n-GaN layer 16 are electrically canceled by the holes added by taking Mg into the second n-GaN layer 16, and the second n− It was also found that the electrical resistance of the GaN layer 16 was increased.

Further, as shown in FIG. 6A, the sample of Example 2 has a Mg addition concentration of 2 × 10 ²⁰ cm ⁻³ and a Si addition concentration of 5 × 10 ²⁰ cm ^{− in the} tunnel junction layer 15. ³ . The sample of Example 2 has a lower Mg concentration in the second n-GaN layer 16 than the sample of Comparative Example 1.

  The following can be considered as this cause. It is considered that Mg added to the tunnel junction layer 15 is easily diffused from the C plane ((0001) plane) and is difficult to diffuse from a plane that is not the C plane. When the tunnel junction layer 15 grows three-dimensionally, the proportion of the area of the C plane formed on the surface of the tunnel junction layer 15 decreases, and the proportion of the area of the surface that is not the C plane increases. This is considered to be because Mg added to the tunnel junction layer 15 is prevented from diffusing from the tunnel junction layer 15.

  That is, at the time of crystal growth of the tunnel junction layer 15, once the surface flatness of the tunnel junction layer 15 is made poor, Mg added to the tunnel junction layer 15 is difficult to diffuse from the tunnel junction layer 15. It has been found that the electric resistance of the tunnel junction layer 15 can be further reduced by suppressing the concentration of Mg added to the tunnel junction layer 15 from being lowered. Furthermore, it is also possible to suppress the electrons added by adding Si to the second n-GaN layer 16 from being electrically canceled by the holes added by taking Mg into the second n-GaN layer 16. Therefore, it was found that the electrical resistance of the second n-GaN layer 16 can be further reduced. That is, by growing the tunnel junction layer 15 three-dimensionally, Mg contained in each of the tunnel junction layer 15 and the second n-GaN layer 16 formed by crystal growth by stacking on the tunnel junction layer 15 is formed. The concentration can be adjusted.

FIG. 7 shows the results of measuring the magnitude of the voltage with respect to the current density by applying a voltage to each of the samples of Examples 2 to 4 and Comparative Example 1. In the samples of Examples 2 to 4, the drive voltage is greatly reduced as compared with the sample of Comparative Example 1. In particular, at a current density of 3 kA / cm ² , the samples of Examples 2 and 3 have a drive voltage lower by about 10 V (volts) than the sample of Comparative Example 1. That is, the tunnel junction layer 15 is intentionally grown three-dimensionally to form a tunnel junction layer 15 with poor surface flatness, and then the second n-GaN layer 16 is stacked on the tunnel junction layer 15 to form a two-dimensional crystal. Grow to restore good surface flatness. Thus, it was found that a nitride semiconductor device having a smaller electric resistance and better surface flatness and excellent characteristics as a light emitting device can be obtained.

  As described above, in this nitride semiconductor element, an island-like crystal is formed in which the interface on the second n-GaN layer 16 side of the tunnel junction layer 15 to which the n-type semiconductor impurity is added is independent from the surroundings. Is formed by three-dimensional growth that grows in a direction along the surface of the layer and in a direction away from the surface of the layer. That is, in this nitride semiconductor element, the n-type semiconductor impurity is added to the tunnel junction layer 15 at a high concentration. Thereby, since this nitride semiconductor element can suppress the thickness of the depletion layer formed in the tunnel junction layer 15, electrons and holes can pass through the depletion layer satisfactorily. For this reason, the nitride semiconductor element can further reduce the electrical resistance of the tunnel junction layer 15. That is, this nitride semiconductor element can flow a current satisfactorily.

  The method for manufacturing a nitride semiconductor device further includes a tunnel junction layer forming step of forming a tunnel junction layer 15 by adding an n-type semiconductor impurity in a three-dimensional growth amount. That is, in this method for manufacturing a nitride semiconductor device, high-concentration n-type semiconductor impurities are added to the tunnel junction layer 15. For this reason, since this nitride semiconductor device manufacturing method can suppress the thickness of the depletion layer formed in the tunnel junction layer 15, electrons and holes can pass through the depletion layer satisfactorily. For this reason, this method for manufacturing a nitride semiconductor device can further reduce the electrical resistance of tunnel junction layer 15. That is, this method for manufacturing a nitride semiconductor device can manufacture a nitride semiconductor device having a tunnel junction layer 15 through which a current can flow satisfactorily.

  Therefore, the nitride semiconductor element has a sufficiently small electric resistance, and thereby allows a current to flow with high efficiency. In addition, this nitride semiconductor device manufacturing method can manufacture a nitride semiconductor device that has a sufficiently small electrical resistance, and that allows a current to flow with high efficiency.

  In this nitride semiconductor device, the surface of the second n-GaN layer 16 is two-dimensionally grown (the RMS value of the surface step of the crystal is 0.28 nm or less). Therefore, in this nitride semiconductor device, the tunnel junction layer 15 in which the interface on the second n-GaN layer 16 side is three-dimensionally grown can be covered with the second n-GaN layer 16 that is two-dimensionally grown. That is, in this nitride semiconductor element, the tunnel junction layer 15 that is three-dimensionally grown by adding a high concentration of n-type semiconductor impurities is covered with the second n-GaN layer 16 that is two-dimensionally grown, and therefore, a smaller electric resistance is obtained. The provided tunnel junction layer 15 can be used for the device.

  In this nitride semiconductor device, the semiconductor impurity is an n-type semiconductor impurity. For this reason, in this nitride semiconductor element, an n-type semiconductor impurity is added in such an amount that the interface on the surface layer side of the tunnel junction layer 15 grows three-dimensionally to form a tunnel junction layer. Thereby, in this nitride semiconductor device, the second n-GaN layer 16 can be formed not by the p-type semiconductor layer but by the n-type semiconductor layer. Thereby, this nitride semiconductor element can make electric resistance smaller.

  In addition, the method for manufacturing a nitride semiconductor device includes a surface layer forming step in which the second n-GaN layer 16 is two-dimensionally grown above the tunnel junction layer 15 formed by executing the tunnel junction layer forming step. . Therefore, in the method for manufacturing a nitride semiconductor device, the second n-GaN layer 16 can be formed by two-dimensional growth by executing the surface layer forming step. For this reason, in this nitride semiconductor device manufacturing method, the second n-GaN layer 16 is two-dimensionally grown and stacked on the surface side of the three-dimensionally grown tunnel junction layer 15, thereby forming the three-dimensionally grown tunnel junction layer 15. Can be covered. For this reason, since this method for manufacturing a nitride semiconductor device can use the tunnel junction layer 15 that is three-dimensionally grown by adding an n-type semiconductor impurity, the tunnel junction layer 15 having a smaller electric resistance is provided. A nitride semiconductor device can be manufactured.

  In this method for manufacturing a nitride semiconductor device, the semiconductor impurity is an n-type semiconductor impurity. Therefore, in this method for manufacturing a nitride semiconductor device, the tunnel junction layer 15 is formed by adding an n-type semiconductor impurity in a three-dimensional growth amount. Thereby, in the method for manufacturing the nitride semiconductor element, the second n-GaN layer 16 can be formed not by the p-type semiconductor layer but by the n-type semiconductor layer. Thus, the nitride semiconductor device manufacturing method can manufacture a nitride semiconductor device having a smaller electric resistance.

The present invention is not limited to the first to fourth embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.
(1) In Examples 1 to 4, the back side of the tunnel junction layer has a general blue LED structure. However, the present invention is not limited to this, and the voltage drop in the high current density region is greatly improved. Alternatively, a surface emitting laser structure in which a multilayer reflector is provided on the back side of the first n-GaN layer may be used.
(2) In Examples 1 to 4, Mg is used as the p-type semiconductor impurity. However, the present invention is not limited thereto, and may be Zn, Be, Ca, Sr, Ba, or the like, which are p-type semiconductor impurities. .
(3) In Examples 1 to 4, Si is used as the n-type semiconductor impurity. However, the present invention is not limited to this, and Ge or the like, which is an n-type semiconductor impurity, may be used.
(4) In Examples 1 to 4, the p-AlGaN layer is laminated on the surface of the GaInN / GaN quintet well active layer. However, the present invention is not limited to this, and the p-AlGaN layer is formed on the surface of the GaInN quantum well active layer. The AlGaN layer may not be stacked.
(5) In Examples 1 to 4, the sapphire substrate is used. However, the present invention is not limited to this, and other substrates such as a gallium nitride substrate and an AlN substrate may be used.
(6) In Example 1-4, although the 2nm thickness of ^p ++ -GaInN layer of the tunnel junction layer, is not limited to this, even if the thickness of the ^p ++ -GaInN layer of the tunnel junction layer smaller than 2nm It may be larger than 2 nm.
(7) In Examples 1 to 4, the thickness of the n ^++- GaN layer of the tunnel junction layer is 15 nm. However, the thickness is not limited to this, and the thickness of the n ^++- GaInN layer of the tunnel junction layer may be less than 15 nm. It may be larger than 15 nm.
(8) In Examples 1 to 4, the InN molar fraction of the p ^++- GaInN layer of the tunnel junction layer is set to 0.35. However, the present invention is not limited to this, and the InN molar fraction of the p ^++- GaInN layer of the tunnel junction layer is used. The rate may be less than 0.35 or greater than 0.35.
(9) In Examples 1 to 4, the MOCVD method is used for stacking and crystal growth. However, the present invention is not limited thereto, and other methods such as HVPE and LPEE may be used for stacking and crystal growth. .

15 ... Tunnel junction layer 16 ... Second n-GaN layer (surface layer)

Claims (6)

A tunnel junction layer doped with semiconductor impurities;
A surface layer formed above the tunnel junction layer;
With
The nitride semiconductor device, wherein an interface of the tunnel junction layer on the surface layer side is three-dimensionally grown.   The nitride semiconductor device according to claim 1, wherein a surface of the surface layer is two-dimensionally grown. The semiconductor impurity is
The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is an n-type semiconductor impurity.   A method of manufacturing a nitride semiconductor device comprising a tunnel junction layer forming step of forming a tunnel junction layer by adding a three-dimensionally grown semiconductor impurity.   5. The nitride semiconductor according to claim 4, further comprising a surface layer forming step of two-dimensionally growing a surface layer on the upper side of the tunnel junction layer formed by executing the tunnel junction layer forming step. Device manufacturing method. The semiconductor impurity is
6. The method for manufacturing a nitride semiconductor device according to claim 4, wherein the nitride semiconductor device is an n-type semiconductor impurity.