JP2018006420A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device having better switching characteristics while suppressing increase in on-voltage of an IGBT region, in a semiconductor device in which a diode region and the IGBT region are formed on the same semiconductor substrate adjacently in a surface direction of the semiconductor substrate.SOLUTION: Lifetime control regions are formed on a diode drift layer around an anode layer and on an IGBT drift layer around a buffer layer. Further, on the IGBT drift layer, a lifetime control region located at least between the two lifetime control regions, and whose thickness in a vertical direction becomes gradually thicker by gradually deepening a boundary with the IGBT drift layer.SELECTED DRAWING: Figure 1

Description

  The technology disclosed by the present invention relates to a semiconductor device.

Patent Document 1 proposes a structure in which a lifetime control region is provided in a diode region and an IGBT region in a semiconductor device in which an IGBT region and a diode region are formed on the same substrate.
Specifically, in the diode region, a lifetime control region is formed in the drift layer near the anode layer, and in the IGBT region, a lifetime control region is formed in the drift layer near the buffer layer. Thereby, turn-off loss can be reduced in the diode region and the IGBT region.
Furthermore, in the structure shown in FIG. 1 of Patent Document 1, a lifetime control region is provided in the drift layer near the body layer on the boundary side between the IGBT region and the diode region in the IGBT region. Hole injection into the diode region can be suppressed.
In the structure shown in FIG. 6 of Patent Document 1, the boundary between the IGBT region and the diode region in the IGBT region is deepened with a certain gradient toward the boundary with respect to the back surface of the semiconductor substrate. It is formed from the lifetime area.

JP 2012-43891 A

In the semiconductor device disclosed in Patent Document 1, the lifetime control region is formed at a certain depth from the surface of the semiconductor substrate on the boundary side between the IGBT region and the diode region in the IGBT region. Alternatively, it is formed from the lifetime region so as to become deeper with a certain gradient toward the boundary with respect to the back surface of the semiconductor substrate. However, in actuality, in the IGBT region, the holes injected from the body layer to the drift layer during diode operation become thinner in the depth direction from the front surface to the back surface of the semiconductor substrate, and in the vicinity of the diode region. It is distributed so that becomes darker. Therefore, in the semiconductor device disclosed in Patent Document 1, the hole concentration distribution cannot be considered, and the effect of suppressing the hole injection from the IGBT region to the diode region is insufficient.
In addition, when the lifetime region is formed, turn-off loss can be reduced, but the on-voltage of the IGBT region increases. Therefore, it is necessary to keep the lifetime area within a minimum range.

  The present specification is a semiconductor device in which a diode region and an IGBT region are formed on the same semiconductor substrate, and provides a semiconductor device having better switching characteristics while suppressing an increase in on-voltage of the IGBT region. It is.

  The present specification provides a semiconductor device in which a diode region and an IGBT region are formed adjacent to the same semiconductor substrate in the surface direction of the semiconductor substrate. In this semiconductor device, the diode region includes a first conductivity type anode layer formed on the front surface side of the semiconductor substrate, a second conductivity type diode drift layer formed on the back surface side of the anode layer, and a diode drift. A second conductivity type cathode layer having a higher impurity concentration of the second conductivity type than the layer and formed on the back side of the diode drift layer. The IGBT region is formed on the second conductivity type emitter region formed on the front surface side of the semiconductor substrate, the first conductivity type body layer formed on the back surface side of the emitter region, and the back surface side of the body layer. The second conductivity type IGBT drift layer, the first conductivity type collector layer formed on the back side of the IGBT drift layer, and the surface of the semiconductor substrate, penetrating the emitter region and the body layer And a trench gate reaching the IGBT drift layer. Furthermore, the first lifetime control region formed in the diode drift layer and the IGBT drift layer are formed at a position deeper than the first lifetime control region in the depth direction from the front surface to the back surface of the semiconductor substrate. Formed in the IGBT drift layer, and formed between at least the first lifetime control region and the second lifetime control region in the depth direction, and toward the diode region. And a third lifetime control region formed so that the thickness in the vertical direction gradually increases as the boundary with the drift layer gradually increases.

According to the above configuration, in addition to the two lifetime control regions respectively formed in the diode drift layer near the anode layer and the IGBT drift layer near the buffer layer, the IGBT drift layer includes at least the two lifetime control regions. And a lifetime control region in which the boundary with the IGBT drift layer is gradually deepened. Therefore, in the IGBT region, the concentration decreases in the depth direction from the front surface to the back surface of the semiconductor substrate, and holes distributed so as to increase in concentration near the diode region flow into the drift layer of the diode region. It can be effectively suppressed. Therefore, the reverse current generated during the reverse recovery operation of the diode is suppressed.
In addition, by forming the lifetime control region along the hole distribution of the IGBT drift layer, the formation range of the lifetime control region is minimized, and the rise of the on-voltage that is in a trade-off relationship with the turn-off loss is suppressed. Can do.

It is sectional drawing of the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device concerning an embodiment, and is a figure showing a sectional view of a semiconductor device before a crystal defect formation process. It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment, Comprising: It is a figure which shows sectional drawing of the semiconductor device at the time of a crystal defect formation process. (Formation of diode lifetime control region 39) It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment, Comprising: It is a figure which shows sectional drawing of the semiconductor device at the time of a crystal defect formation process. (Formation of the second portion 59b of the IGBT lifetime control region 59) It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment, Comprising: It is a figure which shows sectional drawing of the semiconductor device at the time of a crystal defect formation process. Formation of first portion 59a of IGBT lifetime control region 59) It is a figure explaining the manufacturing method of the semiconductor device concerning an embodiment, and is a figure showing a sectional view of a semiconductor device after an ion implantation process. It is a figure explaining the manufacturing method of the semiconductor device concerning an embodiment, and is a figure showing a sectional view of a semiconductor device after an annealing process. It is sectional drawing of the semiconductor device which concerns on a comparison form.

(Semiconductor device)
A semiconductor device according to an embodiment disclosed in this specification will be described.
As shown in FIG. 1, the semiconductor device 10 according to the embodiment includes a semiconductor substrate 12, a metal layer formed on the front surface and the back surface of the semiconductor substrate 12, an insulating film, and the like. A diode region 20 and an IGBT region 40 are formed in the semiconductor substrate 12.

  An anode electrode 22 is formed on the surface of the semiconductor substrate 12 in the diode region 20. An emitter electrode 42 is formed on the surface of the semiconductor substrate 12 in the IGBT region 40. A common electrode 60 is formed on the back surface of the semiconductor substrate 12.

  The diode drift layer 28 is formed below the anode layer 26. The diode drift layer 28 is n-type. The diode drift layer 28 includes an upper drift layer 28a and a lower drift layer 28b. The upper drift layer 28a has a lower impurity concentration than the lower drift layer 28b.

  The cathode layer 30 is formed below the diode drift layer 28. The cathode layer 30 is formed in a range exposed on the back surface of the semiconductor substrate 12. The cathode layer 30 is n-type and has a high impurity concentration. The cathode layer 30 is ohmically connected to the common electrode 60.

  A diode is formed by the anode layer 26, the diode drift layer 28, and the cathode layer 30.

  In the IGBT region 40, an emitter region 44, a body layer 48, an IGBT drift layer 50, a collector layer 52, a gate electrode 54, and the like are formed.

  A plurality of trenches are formed on the surface of the semiconductor substrate 12 in the IGBT region 40. A gate insulating film 56 is formed on the inner surface of each trench. A gate electrode 54 is formed inside each trench. The surface of the gate electrode 54 is covered with an insulating film 58. The gate electrode 54 is insulated from the emitter electrode 42.

  The emitter region 44 is formed in a range exposed on the surface of the semiconductor substrate 12. The emitter region 44 is formed in a range in contact with the gate insulating film 56. The emitter region 44 is n-type and has a high impurity concentration. The emitter region 44 is ohmically connected to the emitter electrode 42.

  The body layer 48 is p-type. The body layer 48 includes a body contact region 48a and a low concentration body layer 48b. The body contact region 48 a is formed in a range exposed on the surface of the semiconductor substrate 12. The body contact region 48 a is formed between the two emitter regions 44. The body contact region 48a has a high impurity concentration. The body contact region 48 a is ohmically connected to the emitter electrode 42. The low concentration body layer 48b is formed under the emitter region 44 and the body contact region 48a. The low concentration body layer 48 b is formed in a shallower range than the lower end of the gate electrode 54. The impurity concentration of the low-concentration body layer 48b is lower than that of the body contact region 48a. The emitter region 44 is separated from the IGBT drift layer 50 by the low-concentration body layer 48b. The gate electrode 54 is opposed to the low-concentration body layer 48 b in a range separating the emitter region 44 and the IGBT drift layer 50 through the gate insulating film 56.

  The IGBT drift layer 50 is formed below the body layer 48. The IGBT drift layer 50 is n-type. The IGBT drift layer 50 includes a drift layer 50a and a buffer layer 50b. The drift layer 50 a is formed below the body layer 48. The drift layer 50a has a low impurity concentration. The drift layer 50a has substantially the same impurity concentration as the upper drift layer 28a of the diode region 20, and is a layer continuous with the upper drift layer 28a. The buffer layer 50b is formed below the drift layer 50a. The buffer layer 50b has a higher impurity concentration than the drift layer 50a. The buffer layer 50b has substantially the same impurity concentration as the lower drift layer 28b of the diode region 20, and is a layer continuous with the lower drift layer 28b.

  The collector layer 52 is formed below the IGBT drift layer 50. The collector layer 52 is formed in a range exposed on the back surface of the semiconductor substrate 12. The collector layer 52 is p-type and has a high impurity concentration. The collector layer 52 is ohmically connected to the common electrode 60.

  An IGBT is formed by the emitter region 44, the body layer 48, the IGBT drift layer 50, the collector layer 52, and the gate electrode 54.

  A diode lifetime control region 39 is formed in the upper drift layer 28 a of the diode drift layer 28. In the diode lifetime control region 39, there are crystal defects formed by implanting charged particles into the semiconductor substrate 12. The crystal defect density in the diode lifetime control region 39 is higher than that of the surrounding upper drift layer 28a. The lifetime control region 39 is formed at a depth near the anode layer 26. The diode lifetime control area 39 corresponds to the first lifetime control area in the claims.

  An IGBT lifetime control region 59 is formed in the drift layer 50 a of the IGBT drift layer 50. In the IGBT lifetime control region 59, there are crystal defects formed by implanting charged particles into the semiconductor substrate 12. The crystal defect density in the IGBT lifetime control region 59 is higher than that of the surrounding drift layer 50a.

  The IGBT lifetime control region 59 has a first portion 59a and a second portion 59b. The first portion 59a is formed at a depth near the buffer layer 50b. The second portion 59 b is formed at a depth between the lifetime control region 39 and the first portion 59 a of the lifetime control region 59 in the depth direction from the front surface to the back surface of the semiconductor substrate 12, and the diode region 20. It is formed so as to become deeper gradually. The first portion 59a of the IGBT lifetime control region 59 corresponds to the second lifetime control region in the claims, and the second portion 59b of the IGBT lifetime control region 59 is the third lifetime in the claims. Corresponds to the control area.

(Operation of semiconductor device diode)
The operation of the diode of the semiconductor device 10 will be described. When a voltage (that is, forward voltage) that makes the anode electrode 22 positive is applied between the anode electrode 22 and the common electrode 60, the diode is turned on. That is, a current flows from the anode electrode 22 to the common electrode 60 via the anode layer 26, the diode drift layer 28, and the cathode layer 30.

  When the voltage applied to the diode is switched from the forward voltage to the reverse voltage, the diode performs a reverse recovery operation. That is, holes that existed in the diode drift layer 28 when the forward voltage is applied are discharged to the anode electrode 22, and electrons that existed in the diode drift layer 28 when the forward voltage is applied are discharged to the common electrode 60. As a result, a reverse current flows through the diode. The reverse current decays in a short time, and thereafter, the current flowing through the diode becomes substantially zero. The crystal defects in the diode lifetime control region 39 function as carrier recombination centers. Therefore, during the reverse recovery operation, most of the carriers in the diode drift layer 28 disappear due to recombination in the diode lifetime control region 39. Therefore, in the semiconductor device 10, the reverse current generated during the reverse recovery operation of the diode is suppressed.

(Operation of IGBT of semiconductor device)
The operation of the IGBT of the semiconductor device 10 will be described. When a voltage that makes the common electrode 60 positive is applied between the emitter electrode 42 and the common electrode 60 and an ON potential (potential higher than a potential necessary for forming a channel) is applied to the gate electrode 54, the IGBT is turned on To do. That is, a channel is formed in the low-concentration body layer 48 b in the range in contact with the gate insulating film 56 by applying the on potential to the gate electrode 54. Then, electrons flow from the emitter electrode 42 to the common electrode 60 through the emitter region 44, the channel, the IGBT drift layer 50, and the collector layer 52. Further, holes flow from the common electrode 60 to the emitter electrode 42 through the collector layer 52, the IGBT drift layer 50, the low-concentration body layer 48b, and the body contact region 48a. That is, a current flows from the common electrode 60 to the emitter electrode 42.

  When the potential applied to the gate electrode 54 is switched from the on potential to the off potential, the IGBT is turned off. That is, holes that existed in the IGBT drift layer 50 at the time of ON are discharged to the common electrode 60, and electrons that existed in the IGBT drift layer 50 at the time of ON are discharged to the emitter electrode 42. As a result, a reverse current flows through the IGBT. The reverse current decays in a short time, and thereafter, the current flowing through the IGBT becomes substantially zero. In the IGBT lifetime control region 59, the crystal defect particularly in the first portion 59a functions as a carrier recombination center. Therefore, during the reverse recovery operation, most of the carriers in the IGBT drift layer 28 disappear due to recombination in the IGBT lifetime control region 59. Therefore, in the semiconductor device 10, the reverse current generated when the IGBT is turned off is suppressed.

  Further, when the diode is on, the body layer 48 of the IGBT region 40 is close to the diode region 20, the IGBT drift layer 50 is close to the diode region 20, and the cathode layer 30 of the diode region 20 is IGBT. A portion close to the region 40 may operate as a parasitic diode. In this case, the holes injected into the IGBT drift layer 50 from the body layer 48 side are distributed so that the concentration decreases in the direction from the front surface to the back surface of the semiconductor substrate, and the concentration increases in the vicinity of the diode region. The holes injected into the IGBT drift layer 50 move toward the cathode layer 30, and holes accumulate in the drift layer 28 in the diode region 20.

  However, in the semiconductor device 10 according to FIG. 1, the drift layer 50 a of the IGBT drift layer 50 includes the lifetime control region 39 and the lifetime control region 59 in the depth direction from the front surface to the back surface of the semiconductor substrate 12. The second portion 59b of the lifetime control region 59 is formed so as to have a depth between the first portions 59a and a predetermined gradient toward the diode region 20. For this reason, the second portion 59b of the IGBT lifetime control region 59 functions as a recombination center of holes, the holes disappear due to the recombination, and the holes supplied to the IGBT drift layer 50 become drift layers 28 in the diode region 20. Can be effectively suppressed. Therefore, in the semiconductor device 10, the reverse current generated during the reverse recovery operation of the diode is suppressed.

  Further, by forming the second portion 59b of the lifetime control region 59 along the hole distribution of the IGBT drift layer 50, the formation range of the second portion 59b is minimized, and the on-voltage having a trade-off relationship with the turn-off loss. Can be suppressed.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 10 will be described. After a plurality of element structures of the semiconductor device 10 according to FIG. 1 are formed on a semiconductor wafer, the semiconductor device 10 is manufactured by separating each semiconductor device by dicing or the like.

  The first manufacturing method of the semiconductor device 10 includes a crystal defect forming step, an ion implantation step, and an annealing step.

  FIG. 2 is a view showing a cross section of a part of a semiconductor wafer according to the method for manufacturing the semiconductor device 10. A wafer 610 shown in FIG. 2 shows a state before the diode lifetime control region 39, the IGBT lifetime control region 59, the cathode layer 30, and the common electrode 60 of the semiconductor device 10 are formed. The element structure of the device 10 has already been formed. A p-type collector layer 652 is formed on the back side of the wafer 610. In the wafer 610, a region that becomes the diode region 20 of the semiconductor device 10 of FIG. 1 after the manufacturing process is completed is indicated by a diode formation region 620, and a region that becomes the IGBT region 40 is indicated by an IGBT formation region 640. Components similar to those of the semiconductor device 10 of FIG. 1 are denoted by the same reference numerals. In each step of the first manufacturing method, the diode lifetime control region 39, the IGBT lifetime control region 59, and the cathode layer 30 of the semiconductor device 10 are formed.

  In the crystal defect forming step, after the diode lifetime control region 39 is formed, the IGBT lifetime control region 59 is formed.

  For the formation of the diode lifetime control region 39, a mask 701 having a surface substantially parallel to the semiconductor substrate 10 is used. As shown in FIG. 3, charged particles are irradiated from the surface side of the mask 701 in a direction perpendicular to the surface of the wafer 610 to form crystal defects in the diode formation region 620 of the wafer 610. The charged particles are irradiated with the irradiation energy adjusted so as to stop at the upper drift layer 28 a of the diode drift layer 28. As a result, a region having a high crystal defect density is formed in the upper drift layer 28 a and becomes a diode lifetime control region 39.

  Next, a crystal defect forming step for forming the IGBT lifetime control region 59 will be described. In the present embodiment, the first portion 59a is formed after the second portion 59b is formed.

  As shown in FIG. 4, the second portion 59b is formed by covering the entire upper surface of the wafer 610 in the diode formation region 620 and forming a slope inclined at a constant angle toward the diode formation region 620 in the IGBT formation region 640. A mask 702 having the same is used. When the charged particles are irradiated from the surface side of the mask 702 from the direction perpendicular to the surface of the wafer 610, the second in the IGBT lifetime region 59 is deepened with a certain gradient toward the diode region side. A portion 59b is formed.

  As shown in FIG. 5, a mask 703 having a surface substantially parallel to the semiconductor substrate 10 is used for forming the first portion 59a. The charged particles are irradiated from the back surface side of the mask 701 in a direction perpendicular to the back surface of the wafer 610 to form crystal defects in the IGBT formation region 640 of the wafer 610. The charged particles are irradiated with the irradiation energy adjusted so as to stop at the drift layer 50 a of the IGBT drift layer 50. As a result, a region having a high crystal defect density is formed in the drift layer 50 a and becomes the first portion 59 a of the IGBT lifetime control region 59.

  Next, an ion implantation process is performed. In the ion implantation process, as shown in FIG. 6, n-type impurity ions are implanted into the back surface of the wafer 610 by using a mask 704, and a portion of the collector layer 652 on the back surface of the wafer 610 is n. An ion-implanted region 630 in which mold ions are implanted is formed.

  Next, the mask 704 is removed, and then an annealing process for the wafer 610 is performed. In the annealing step, an annealing process is performed on the portion 630 which is an ion implantation region. When the annealing process is performed, the portion 630 becomes the n-type cathode layer 30. As a result, as shown in FIG. 7, the back surface of the wafer 610 can have two layers of the collector layer 52 and the cathode layer 30. Furthermore, the semiconductor device 10 according to the embodiment can be formed by forming the common electrode 60 on the back surface of the wafer 610 and dicing the semiconductor electrode into individual semiconductor devices.

  In the semiconductor device manufacturing method described above, by irradiating charged particles from the surface side of the semiconductor substrate 10, the diode lifetime control region 39 and the 12th portion 59 a of the IGBT lifetime control region 59 are formed. By irradiating charged particles from the back side, the first portion 59a of the IGBT lifetime control region 59 is formed.

  Therefore, in the semiconductor device manufactured by the manufacturing method of this embodiment, the diode lifetime control region 39 and the IGBT lifetime control region 59 are formed as shown in FIG. Note that “·” in the drawing is a part of the diode lifetime control region 39 and the IGBT lifetime control region 59 that are damaged by the passage of charged particles, and “×” is the end of the charged particle implantation. This is the area where the lifetime is the shortest.

  As shown in the comparative form of FIG. 8, the diode drift layer 28 is compared with the case where the diode lifetime control region 39 and the IGBT lifetime control region 59 are formed by implantation from one surface (surface) of the semiconductor substrate 10. In addition, the amount of defects formed in the IGBT drift layer 58 can be reduced, and the leakage current can be reduced.

  The structure and the manufacturing method shown in the above embodiment are examples, and the present invention is not limited to the structure and the manufacturing method described above, and other structures and manufacturing methods including the features of the present invention can be used. .

  For example, in the above embodiment, the diode lifetime control region 39 and the IGBT lifetime control region 59 are formed after the element structure shown in FIG. 2 is formed, but the diode lifetime is included in the process of forming the element structure. A step of forming the control region 39 and the IGBT lifetime control region 59 may be provided.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The invention described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the configurations illustrated in the present specification or the drawings can achieve a plurality of objects at the same time, and achieving one of these objects has technical utility.

10: Semiconductor layer 20: Diode region 22: Anode electrode 26: Anode layer 28: Diode drift layer 28a: Upper drift layer 28b: Lower drift layer 30: Cathode layer 39: Diode lifetime control region (first lifetime region)
40: IGBT region 42: Emitter electrode 44: Emitter region 48: Body layer 48a: High concentration body layer 48b: Low concentration body layer 50: IGBT drift layer 50a: Drift layer 50b: Buffer layer 52: Collector layer 54: Gate electrode 56 : Gate insulating film 58: Insulating film 59: IGBT lifetime control region 59a: First portion (second lifetime region)
59b: Second part (third lifetime region)
60: Common electrode 610: Wafer 620: Diode formation region 640: IGBT formation region 701-704: Mask

Claims (1)

A diode device and an IGBT region are formed on the same semiconductor substrate adjacent to the surface direction of the semiconductor substrate,
The diode region is
A first conductivity type anode layer formed on the surface side of the semiconductor substrate;
A second conductivity type diode drift layer formed on the back side of the anode layer;
A second conductivity type cathode layer having a second conductivity type impurity concentration higher than that of the diode drift layer and formed on the back side of the diode drift layer;
With
The IGBT region is
A second conductivity type emitter region formed on the surface side of the semiconductor substrate;
A body layer of a first conductivity type formed on the back side of the emitter region;
A second conductivity type IGBT drift layer formed on the back side of the body layer;
A collector layer of a first conductivity type formed on the back side of the IGBT drift layer;
A trench gate formed on a surface of the semiconductor substrate, penetrating the emitter region and the body layer and reaching the IGBT drift layer;
With
A first lifetime control region formed in the diode drift layer;
A second lifetime control region formed in the IGBT drift layer and formed at a position deeper than the first lifetime control region in a depth direction from the front surface to the back surface of the semiconductor substrate;
Formed in the IGBT drift layer, formed between at least the first lifetime control region and the second lifetime control region in the depth direction, and with the IGBT drift layer toward the diode region A third lifetime control region formed such that the thickness in the vertical direction gradually increases as the boundary gradually deepens;
A semiconductor device.

Images