JP2017163210A - Time measuring circuit and temperature sensor circuit having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a temperature sensor circuit including a time measurement circuit. A temperature sensor circuit 1 includes an oscillation circuit 2 that generates a clock signal CLK, a delay circuit 4 that generates a delay signal S2 that delays a low frequency signal S1, and an edge between a low frequency signal S1 and a delay signal S2. Counter circuit 5 that counts the corresponding delay time based on the clock signal CLK, measures the time corresponding from the edge of the delay signal S2 to the edge of the clock signal CLK immediately after the edge of the delay signal S2, and measures that time to the edge of the clock signal CLK. The difference time measuring circuit 7 for measuring the difference time subtracted from the period of is provided. The delay time of the delay signal S2 is measured based on the sum of the time corresponding to the count number of the counter circuit 5 and the difference time. [Selection diagram] Fig. 1

Description

  The technology disclosed in this specification relates to a time measurement circuit. The technology disclosed in this specification further relates to a temperature sensor circuit including a time measurement circuit.

  A time measurement circuit that measures time using a clock signal is known. Such a time measuring circuit is required in various situations. For example, Patent Document 1 discloses a temperature sensor circuit including this type of time measurement circuit. In the temperature sensor circuit of Patent Document 1, a second pulse signal obtained by delaying the first pulse signal is generated, and the time measurement circuit counts the delay time of the second pulse signal based on the clock signal. Since the delay time of the second pulse signal has temperature dependent characteristics, the temperature is measured from the count number.

  FIG. 10 illustrates a timing chart of a time measuring circuit that measures time using a clock signal. The interval between the edges of the first pulse signal P1 rising at the timing T1 and the second pulse signal P2 rising at the timing T2 is the measurement target time. The time measuring circuit counts the target time based on the clock signal CLK.

JP 2013-185985 A

FIG. 11 shows details of a timing chart at the end timing of the target time (corresponding to the timing T2 of the rising edge of the second pulse signal P2). In this example, the count number C _N when time T3 is a rising edge of the clock signal CLK at immediately before the end time T2 of the target time is output as the measurement result of the target time. As shown in FIG. 11, the time between timings T3 and T2 is included in the measurement target time, but the time measurement circuit cannot measure this time. Thus, the time measuring circuit cannot measure a time shorter than the cycle of the clock signal at the end timing of the target time. There is a need for a time measurement circuit that can measure time more accurately. Furthermore, in order to measure temperature more accurately, a temperature sensor circuit including such a time measurement circuit is also required.

  One embodiment of the time measurement circuit disclosed in the present specification measures a target time corresponding to the edge between the first pulse signal and the second pulse signal. One embodiment of the time measurement circuit includes an oscillation circuit, a counter circuit, and a differential time measurement circuit. The oscillation circuit generates a clock signal. The counter circuit counts the target time based on the clock signal. The difference time measurement circuit measures a time corresponding to the edge of the clock signal immediately after the edge of the second pulse signal from the edge of the second pulse signal, and measures a difference time obtained by subtracting the time from the period of the clock signal. The target time is measured based on the sum of the time corresponding to the count number of the counter circuit and the difference time.

  According to the time measuring circuit of the above embodiment, the measured differential time corresponds to the time from the edge of the clock signal immediately before the end time of the target time to the end timing of the target time. For this reason, the time measuring circuit of the above embodiment can accurately measure the target time.

  One embodiment of the temperature sensor circuit disclosed in this specification includes an oscillation circuit, a delay circuit, a counter circuit, and a differential time measurement circuit. The oscillation circuit generates a clock signal. The delay circuit generates a second pulse signal obtained by delaying the first pulse signal. The delay time of the second pulse signal has temperature dependent characteristics. The counter circuit counts a delay time corresponding to the edge between the first pulse signal and the second pulse signal based on the clock signal. The difference time measurement circuit measures a time corresponding to the edge of the clock signal immediately after the edge of the second pulse signal from the edge of the second pulse signal, and measures a difference time obtained by subtracting the time from the period of the clock signal. The delay time of the second pulse signal is measured based on the sum of the time corresponding to the count number of the counter circuit and the difference time.

  According to the temperature sensor circuit of the above embodiment, the measured difference time corresponds to the time from the edge of the clock signal immediately before the end timing of the delay time of the second pulse signal to the end timing of the delay time. For this reason, since the temperature sensor circuit of the said embodiment can measure the delay time of a 2nd pulse signal correctly, it can measure temperature correctly.

It is a block diagram which shows the outline of a temperature sensor circuit. It is a figure which shows the outline of the ring oscillator contained in an oscillation circuit. It is a figure which shows the outline of the inverter chain contained in a delay circuit. It is a circuit diagram of the CMOS inverter which comprises a ring oscillator and an inverter chain. It is a figure which shows the outline of a difference time measurement circuit. It is a circuit diagram of a pair of CMOS inverter which comprises the delay element contained in the delay unit of a difference time measurement circuit. It is a timing chart which shows the mode of operation of a temperature sensor circuit. It is a timing chart which shows the mode of operation | movement of a temperature sensor circuit, and shows the detail of the timing chart in the completion | finish timing of delay time. It is a figure which shows the outline of the difference time measurement circuit of another example. It is a timing chart which shows the mode of operation of the conventional time measuring circuit. It is a timing chart which shows the mode of operation of the conventional time measuring circuit, and shows the details of the timing chart at the end timing of the measurement target time.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  One embodiment of a time measuring circuit disclosed in the present specification measures a target time corresponding to an edge between a first pulse signal and a second pulse signal, and can be used in various applications. . One embodiment of the time measurement circuit may include an oscillation circuit, a counter circuit, and a differential time measurement circuit. The oscillation circuit generates a clock signal. The counter circuit counts the target time based on the clock signal. The difference time measurement circuit measures a time corresponding to the edge of the clock signal immediately after the edge of the second pulse signal from the edge of the second pulse signal, and measures a difference time obtained by subtracting the time from the period of the clock signal. The time measuring circuit disclosed in this specification may further include a control circuit that generates a control signal synchronized with the edge of the clock signal immediately after the edge of the second pulse signal. In this case, the differential time measuring circuit may be configured to measure a time corresponding to the edge between the second pulse signal and the control signal and measure a differential time obtained by subtracting the time from the period of the clock signal. . In the time measuring circuit disclosed in this specification, the target time is measured based on the sum of the time corresponding to the count number of the counter circuit and the difference time.

  One embodiment of the temperature sensor circuit disclosed in this specification may include an oscillation circuit, a delay circuit, a counter circuit, and a differential time measurement circuit. The oscillation circuit generates a clock signal. The delay circuit generates a second pulse signal obtained by delaying the first pulse signal. The delay time of the second pulse signal has temperature dependent characteristics. The counter circuit counts a delay time corresponding to the edge between the first pulse signal and the second pulse signal based on the clock signal. The difference time measurement circuit measures a time corresponding to the edge of the clock signal immediately after the edge of the second pulse signal from the edge of the second pulse signal, and measures a difference time obtained by subtracting the time from the period of the clock signal. The temperature sensor circuit disclosed in this specification may further include a control circuit that generates a control signal synchronized with the edge of the clock signal immediately after the edge of the second pulse signal. In this case, the differential time measuring circuit may be configured to measure a time corresponding to the edge between the second pulse signal and the control signal and measure a differential time obtained by subtracting the time from the period of the clock signal. . In the temperature sensor circuit disclosed in this specification, the delay time of the second pulse signal is measured based on the sum of the time corresponding to the count number of the counter circuit and the difference time.

  In one embodiment of the time measurement circuit or the temperature sensor circuit disclosed in this specification, the difference time measurement circuit may include an N-stage parallel delay unit parallel circuit and a latch circuit. In the delay unit parallel circuit, a delay unit is provided in each stage, the second pulse signal is input to each delay unit, and the delay unit delays the second pulse signal as the number of stages increases. Time increases. The latch circuit latches the output of each delay unit in synchronization with the edge of the control signal. The differential time measuring circuit of this aspect can have a high time resolution because a delay due to fan-out is suppressed.

In one embodiment of the time measuring circuit or the temperature sensor circuit disclosed in this specification, each delay unit may be configured by connecting a number of delay elements corresponding to the number of stages in series. In this case, N of the number of stages of the delay unit parallel circuit is T _RO / T _D −1 where the period of the clock signal is T _RO and the delay time of the delay element is T _D. According to this aspect, the delay unit parallel circuit can have the number of stages corresponding to the period _{TRO of the} clock signal. For this reason, the difference time can be easily measured from the digital value obtained by the difference time measurement circuit. Further, if necessary, the digital time obtained by the differential time measurement circuit may be inverted to measure the differential time. In one aspect embodying such an embodiment, the oscillation circuit may include a ring oscillator in which (N + 1) CMOS inverters are connected in a ring shape. Each delay element may have a pair of CMOS inverters connected in series. The delay time of the CMOS inverter of the ring oscillator may coincide with the delay time of the CMOS inverter of the delay element. Alternatively, in another aspect embodying such an embodiment, the oscillation circuit may include a ring oscillator in which (N + 1) CMOS inverters are connected in a ring shape. Each of the delay elements may have one CMOS inverter. The delay time of the CMOS inverter of the ring oscillator may coincide with the delay time of the CMOS inverter of the delay element. In the latch circuit, the latch characteristic corresponding to the odd-numbered stage of the delay unit parallel circuit and the latch characteristic corresponding to the even-numbered stage of the delay unit parallel circuit may be reversed.

  As shown in FIG. 1, the temperature sensor circuit 1 is a one-chip circuit, and includes an oscillation circuit 2, a frequency dividing circuit 3, a delay circuit 4, a counter circuit 5, a control circuit 6, and a differential time measuring circuit 7. Prepare.

  The oscillation circuit 2 is configured to generate a clock signal CLK. The clock signal CLK is a rectangular wave with a duty ratio of 50%, for example. The frequency dividing circuit 3 is configured to convert the clock signal CLK into a low frequency signal S1 having a low frequency. For example, the frequency dividing circuit 3 reduces the frequency of the clock signal CLK to 1/1024 times or 1/2048 times. The delay circuit 4 generates a delay signal S2 (an example of the second pulse signal described in the claims) obtained by delaying the low-frequency signal S1 (an example of the first pulse signal described in the claims). It is configured.

  The counter circuit 5 is configured to count the time difference between the low frequency signal S1 and the delay signal S2 (corresponding to the delay time of the delay signal S2) based on the clock signal CLK. The counter circuit 5 is configured to reset the counter value at the rising edge of the low frequency signal S1, and to latch the counter value at the rising edge of the delay signal S2. The counter circuit 5 is configured to output the measured clock number as a digital output value Di.

  The control circuit 6 is configured to generate a control signal S3 that rises in synchronization with the rising edge of the clock signal CLK immediately after the rising edge of the delay signal S2. For example, the control circuit 6 is configured by a D-type flip-flop so that the delay signal S2 is input to the D terminal and is latched at the rising edge of the clock signal CLK.

  The difference time measuring circuit 7 is configured to measure a time between the rising edge of the delay signal S2 and the rising edge of the control signal S3, and to measure a difference time obtained by subtracting the time from the period of the clock signal CLK. . The differential time measuring circuit 7 is configured to output the measured differential time as a digital output value Dd. As will be described later, the temperature sensor circuit 1 is configured to measure the temperature from the sum of the digital output value Di of the counter circuit 5 and the digital output value Dd of the difference time measurement circuit 7.

As shown in FIG. 2, the oscillation circuit 2 includes a ring oscillator in which a plurality of first inverters INV1 are connected in a ring shape. The period T _RO of the clock signal CLK generated by the oscillation circuit 2 is expressed by the following formula 1.

Here, M is the number of stages (M ≧ 3) of the first inverter INV1, _{T 1} is the delay time per one stage of the first inverter INV1. In this example, the ring oscillator has a nine-stage first inverter INV1. Therefore, the period T _RO of the clock signal CLK generated by the oscillation circuit 2 is 18T ₁ .

  As shown in FIG. 3, the delay circuit 4 is configured by an inverter chain in which a plurality of second inverters INV2 are connected in series. In this example, the inverter chain includes a 50-stage second inverter INV2.

  As shown in FIG. 4, the first inverter INV1 of the ring oscillator and the second inverter INV2 of the inverter chain are both connected in series between the positive power supply line (Vdd line) and the negative power supply line (Vss). A CMOS having one transistor Tr1 and a second transistor Tr2 is provided. The first transistor Tr1 is a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source is connected to the Vdd line, and the drain is connected to the drain of the second transistor Tr2. The second transistor Tr2 is an n-type MOSFET, the drain is connected to the drain of the first transistor Tr1, and the source is connected to the negative power supply line Vss. The connection point between the first transistor Tr1 and the second transistor Tr2 is connected to the gate of the transistor constituting the next stage CMOS inverter.

  The temperature sensor circuit 1 is configured such that the channel length modulation effect by the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator is different from the channel length modulation effect by the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. It is characterized by being. Specifically, when the gate width is constant, the gate lengths of the transistors Tr1 and Tr2 constituting the first inverter INV1 are shorter than the gate lengths of the transistors Tr1 and Tr2 constituting the second inverter INV2. Yes. In this example, the gate length of the first transistor Tr1 of the first inverter INV1 is shorter than the gate length of the first transistor Tr1 of the second inverter INV2, and the gate length of the second transistor Tr2 of the first inverter INV1 is The gate length of the second transistor Tr2 of the second inverter INV2 is shorter. Instead of this example, only the gate length of either the first transistor Tr1 or the second transistor Tr2 of the first inverter INV1 may be short.

  Usually, the transistors Tr1 and Tr2 have a lower operating current at a higher temperature than a lower temperature, and the operating speed is reduced. For this reason, in the first inverter INV1 of the ring oscillator, the operation speed decreases at a temperature higher than the low temperature, and therefore the cycle of the oscillating clock signal CLK increases (frequency decreases). That is, the cycle of the clock signal CLK has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. Also, in the second inverter INV2 of the inverter chain, the operation speed decreases at a temperature higher than the low temperature, so that the delay time of the delay signal S2 increases. That is, the delay time of the delay signal S2 also has a positive temperature dependency characteristic that increases with a substantially linear function with respect to the temperature. Here, the channel length modulation effect refers to the amount of current increase in the saturation region of the IV characteristics. For this reason, that the channel length modulation effect is different means that the amount of current increase in the saturation region of the IV characteristic is different. In this embodiment, the gate lengths of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are shorter than the gate lengths of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Regarding the current increase amount at, the transistors Tr1 and Tr2 constituting the first inverter INV1 are larger than the transistors Tr1 and Tr2 constituting the second inverter INV2. For this reason, when the temperature changes from low to high, the amount of current change in the transistors Tr1 and Tr2 of the ring oscillator is relatively small, and the amount of current change in the transistors Tr1 and Tr2 of the inverter chain is relatively large. As a result, when the temperature changes from low to high, the amount of decrease in the operating speed of the ring oscillator is relatively small, and the amount of decrease in the operating speed of the inverter chain is relatively large.

  In the temperature sensor circuit 1, the channel length modulation effect of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator is different from the channel length modulation effect of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Therefore, in this embodiment, when the temperature is changed from low temperature to high temperature, the amount of decrease in the operating speed of the ring oscillator is different from the amount of decrease in the operating speed of the inverter chain, and the temperature of the clock signal CLK generated by the ring oscillator is different. The dependency characteristic is different from the temperature dependency characteristic of the delay signal S2 generated by the inverter chain. As described above, the cycle of the clock signal CLK has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. The delay time of the delay signal S2 also has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. Further, the rate of change of the delay time of the delay signal S2 with respect to the temperature (ratio of the delay time at any temperature when the delay time of the reference temperature is “1”) is the rate of change of the cycle of the clock signal CLK with respect to the temperature (The ratio of the period at an arbitrary temperature when the period is "1"), and the temperature-dependent characteristics of the two are different.

  As described above, when the temperature dependency characteristic of the clock signal CLK generated by the ring oscillator is different from the temperature dependency characteristic of the delay signal S2 generated by the inverter chain, the number of clocks measured by the counter circuit 5 becomes the temperature. It fluctuates with respect to it. In the temperature sensor circuit 1, a digital output value Di including temperature information can be obtained by utilizing the difference between the temperature dependence characteristic of the clock signal CLK and the temperature dependence characteristic of the delay signal S2.

As shown in FIG. 5, the differential time measuring circuit 7 includes an N-stage parallel delay unit parallel circuit 12 and a latch circuit 14. The delay unit parallel circuit 12 includes delay units 12 _{1 to} 12 _N provided in each stage. The delay signal S2 is input to each of the delay units 12 _{1 to} 12 _N. Each of the delay units 12 _{1 to} 12 _N is configured by connecting one or a plurality of delay elements 11 in series. In the delay unit parallel circuit 12, each of the delay units 12 _{1 to} 12 _N is configured so that the number of delay elements 11 connected in series increases as the number of stages increases. A matching number of delay elements 11 are connected in series. As shown in FIG. 5, a delay unit 121 composed of one delay element 11 is provided in the _first stage, and a delay unit composed of two delay elements 11 is provided in the second stage. 12 ₂ is provided, in the third stage and the delay unit 12 ₃ is provided composed of three delay elements 11, the delay unit made up of N delay elements 11 in the N-th stage 12 _N are provided. As a result, the delay time in which the delay units 12 ₁ -12 _N delay the delay signal S2 increases as the number of stages increases.

  As shown in FIG. 6, the delay element 11 includes a pair of third inverters INV3 connected in series. The third inverter INV3 constituting the delay element 11 is composed of a CMOS having the same form as the first inverter INV1 constituting the oscillation circuit 2. That is, the channel length modulation effect by the transistors Tr1 and Tr2 constituting the third inverter INV3 of the delay element 11 and the channel length modulation effect by the transistors Tr1 and Tr2 constituting the first inverter INV1 of the oscillation circuit 2 coincide with each other. The delay time of the three inverters INV3 and the delay time of the first inverter INV1 are the same.

As shown in FIG. 5, the latch circuit 14 includes N latch units 14 _{1 to} 14 _N. Each of the latch units 14 _{1 to} 14 _N is provided corresponding to each of the delay units 12 _{1 to} 12 _N. Each of the latch units 14 _{1 to} 14 _N receives the output of each of the delay units 12 _{1 to} 12 _{N to} the D terminal and is latched at the rising edge of the control signal S3 from the control circuit 6 (see FIG. 1). In addition, it is composed of a D-type flip-flop.

  FIG. 7 shows how the temperature sensor circuit 1 measures the delay time of the delay signal S2. In this example, the time from timing T1 to timing T2 corresponds to the delay time of the delay signal S2. Timing T1 corresponds to the rising edge of the low frequency signal S1, and timing T2 corresponds to the rising edge of the delay signal S2 (see FIGS. 1 and 3).

  As described above, in the temperature sensor circuit 1, the counter circuit 5 counts the delay time of the delay signal S2 based on the clock signal CLK, whereby the digital output value Di corresponding to the substantial delay time is obtained. The temperature sensor circuit 1 further measures a time shorter than the cycle of the clock signal CLK with high resolution at the end timing T2 of the delay time of the delay signal S2 by using the differential time measurement circuit 7. This is shown in FIG.

FIG. 8 shows details of a timing chart at the end timing T2 of the delay time of the delay signal S2. In this example, the count number when time T3 when the clock signal CLK rises immediately before the end time T2 of the delay time of the delay signal S2 is C _N. The count number C _N corresponds to the digital output value Di as described above. The count number at the timing T4 when the clock signal CLK rises immediately after the end timing T2 of the delay time of the delay signal S2 is CN _{+ 1} . As described above, the control signal S3 is a signal that rises in synchronization with the timing T4. The difference time measuring circuit 7 first measures the time between the timing T2 and the timing T4, and subtracts the measured time from the cycle of the clock signal, thereby obtaining the time between the timing T3 and the timing T2, that is, the time to be measured. Ask for.

As described above, the differential time measuring circuit 7 includes the delay unit parallel circuit 12 that sequentially delays the delay signal S2 as the number of stages increases. The latch circuit 14 of the differential time measuring circuit 7 latches the delay signal S2 that is sequentially delayed in synchronization with the control signal S3. Therefore, of the output D ₁ -D _N from each of the latch circuit 14, the output D ₁ -D _N corresponding to the time from the rising edge of the delay signal S2 to the rising edge of the control signal S3 is "1" Become. That is, the number of bits of “1” corresponds to the time between timing T2 and timing T4.

Here, if the delay time of the delay element 11 included in the delay unit parallel circuit 12 of the differential time measurement circuit 7 and T _D, the delay time T _D is the time resolution of the delay unit parallel circuit 12. N of the number of stages of the delay unit parallel circuit 12 is set so as to satisfy the following formula.

As described above, the third inverter INV3 constituting the delay element 11 has the same form as the first inverter INV1 constituting the oscillation circuit 2. Therefore, if the delay time of the first inverter INV1 and _{T 1,} the delay time _{T D} of the configured delay element 11 by a pair of third inverter INV3, a 2T _1. Further, as shown in Formula 1, the period T _RO of the clock signal CLK generated by the oscillation circuit 2 is 2M · T ₁ , and in this example, 18T ₁ (M = 9). For this reason, by setting the number N of stages of the delay unit parallel circuit 12 to 8, the differential time measurement circuit 7 can measure the time with a resolution eight times the cycle of the clock signal CLK.

When the number of stages of delay units parallel circuit 12 is set to such a relationship, the number of bits corresponding to "0" of the output D ₁ -D _N from each of the latch units 14 ₁ -14 _N is, the timing This corresponds to the time between T3 and timing T2, that is, the time to be measured. Differential time measurement circuit 7, by inverting the output D ₁ -D _N from each of the latch units 14 ₁ -14 _N, can be obtained difference time obtained by subtracting from the period of the clock signal CLK the measurement time. The difference time measurement circuit 7 encodes this difference time and outputs it as a digital output value Dd (see FIG. 1). In this example, by inverting the output D ₁ -D _N from each of the latch units 14 ₁ -14 _N, an example is shown for outputting a difference time as the bit number of "1", inverts Alternatively, the number of bits may be output as “0”.

  Thus, the temperature sensor circuit 1 can measure the time between the timing T3 and the timing T2 with high resolution. Therefore, the temperature sensor circuit 1 can more accurately measure the delay time of the delay signal S2 based on the sum of the digital output value Di of the counter circuit 5 and the digital output value Dd of the difference time measurement circuit 7. Thereby, the temperature sensor circuit 1 can measure a more accurate temperature based on the delay time of the delay signal S2.

Further, the differential time measuring circuit 7 of the temperature sensor circuit 1 is characterized in that the delay units 12 _{1 to} 12 _{N of} the delay unit parallel circuit 12 are configured to be connected in N stages in parallel. For example, even if a delay unit in which N delay elements are connected in series is configured and the output of each delay element is latched by a latch unit, the differential time can be measured. However, in such a series-type delay unit, the delay due to fan-out increases due to the parasitic capacitance between each output of the delay elements and the latch unit, and the time resolution is greatly reduced. On the other hand, in the parallel delay unit parallel circuit 12, the parasitic capacitance between the delay element 11 and the latch units 14 _{1 to} 14 _N is one in each stage, and the delay due to fan-out is suppressed. For this reason, the differential time measuring circuit 7 of the temperature sensor circuit 1 can have high time resolution.

FIG. 9 shows a differential time measuring circuit 7 of a modification. In the differential time measuring circuit 7 of this example, the delay element 11 constituting the delay units 12 _{1 to} 12 _N is configured by one third inverter INV3 (a pair of third inverters in FIG. 6). Example in which one third inverter INV3 is removed from INV3). Furthermore, the latch characteristics of each of the latch units 14 _{1 to} 14 _N of the latch circuit 14 are configured to be reversed between the odd-numbered stage and the even-numbered stage. Specifically, the odd-numbered latch units 14 _{1 to} 14 _N are latched at the rising edge of the control signal S3, and the even-numbered latch units 14 _{1 to} 14 _N are latched at the falling edge of the control signal S3. Has been. In this example, since the time resolution of the delay unit parallel circuit 12 is T1, the delay time of the delay signal S2 can be measured more accurately. Thereby, the temperature sensor circuit 1 can measure a more accurate temperature based on the delay time of the delay signal S2. Furthermore, this example is also useful in that the circuit area and generated noise are reduced.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: Temperature sensor circuit 2: Oscillator circuit 3: Frequency divider circuit 4: Delay circuit 5: Counter circuit 6: Control circuit 7: Difference time measurement circuit 11: Delay element 12: Delay unit parallel circuit 14: Latch circuit

Claims (12)

A time measuring circuit for measuring a target time corresponding to an edge between the first pulse signal and the second pulse signal,
An oscillation circuit for generating a clock signal;
A counter circuit that counts the target time based on the clock signal;
A differential time measurement for measuring a time corresponding to an edge of the clock signal immediately after the edge of the second pulse signal from an edge of the second pulse signal and measuring a differential time obtained by subtracting the time from the period of the clock signal. A circuit, and
The time measurement circuit, wherein the target time is measured based on a total of the time corresponding to the count number of the counter circuit and the difference time. A control circuit for generating a control signal synchronized with an edge of the clock signal immediately after an edge of the second pulse signal;
The difference time measuring circuit is configured to measure a time corresponding to an edge between the second pulse signal and the control signal and measure the difference time obtained by subtracting the time from the period of the clock signal. The time measuring circuit according to claim 1. The differential time measuring circuit is
An N-stage parallel delay unit parallel circuit, wherein a delay unit is provided in each stage, and the second pulse signal is input to each of the delay units, and the delay unit increases with an increase in the number of stages. A delay unit parallel circuit that increases a delay time for delaying the second pulse signal;
The time measuring circuit according to claim 2, further comprising: a latch circuit that latches each output of the delay unit in synchronization with an edge of the control signal. Each of the delay units is configured by connecting a number of delay elements corresponding to the number of stages in series,
The N number of stages of the delay units parallel circuit, the period of the clock signal and T _RO, when the delay time of the delay element and T _D, a _{T RO /} T D _-1, the time measurement circuit according to claim 3. The oscillation circuit has a ring oscillator in which (N + 1) CMOS inverters are connected in a ring shape,
Each of the delay elements has a pair of CMOS inverters connected in series,
The time measuring circuit according to claim 4, wherein a delay time of the CMOS inverter of the ring oscillator matches a delay time of the CMOS inverter of the delay element. The oscillation circuit has a ring oscillator in which (N + 1) CMOS inverters are connected in a ring shape,
Each of the delay elements has one CMOS inverter,
The delay time of the CMOS inverter of the ring oscillator matches the delay time of the CMOS inverter of the delay element,
5. The time measuring circuit according to claim 4, wherein in the latch circuit, a latch characteristic corresponding to an odd-numbered stage of the delay unit parallel circuit is opposite to a latch characteristic corresponding to an even-numbered stage of the delay unit parallel circuit. A temperature sensor circuit,
An oscillation circuit for generating a clock signal;
A delay circuit for generating a second pulse signal obtained by delaying the first pulse signal, wherein the delay time of the second pulse signal has a temperature-dependent characteristic;
A counter circuit that counts a delay time corresponding to an edge between the first pulse signal and the second pulse signal based on the clock signal;
A differential time measurement for measuring a time corresponding to an edge of the clock signal immediately after the edge of the second pulse signal from an edge of the second pulse signal and measuring a differential time obtained by subtracting the time from the period of the clock signal. A circuit, and
The temperature sensor circuit, wherein the delay time of the second pulse signal is measured based on a sum of the time corresponding to the count number of the counter circuit and the difference time. A control circuit for generating a control signal synchronized with an edge of the clock signal immediately after an edge of the second pulse signal;
The difference time measuring circuit is configured to measure a time corresponding to an edge between the second pulse signal and the control signal and measure the difference time obtained by subtracting the time from the period of the clock signal. The temperature sensor circuit according to claim 7. The differential time measuring circuit is
An N-stage parallel delay unit parallel circuit, wherein a delay unit is provided in each stage, and the second pulse signal is input to each of the delay units, and the delay unit increases with an increase in the number of stages. A delay unit parallel circuit that increases a delay time for delaying the second pulse signal;
The temperature sensor circuit according to claim 8, further comprising: a latch circuit that latches an output of each of the delay units in synchronization with an edge of the control signal. Each of the delay units is configured by connecting a number of delay elements corresponding to the number of stages in series,
The N number of stages of the delay units parallel circuit, the period of the clock signal and T _RO, when the delay time of the delay element and T _D, a _{T RO /} T D _-1, a temperature sensor circuit of claim 9. The oscillation circuit has a ring oscillator in which (N + 1) CMOS inverters are connected in a ring shape,
Each of the delay elements has a pair of CMOS inverters connected in series,
The temperature sensor circuit according to claim 10, wherein a delay time of the CMOS inverter of the ring oscillator matches a delay time of the CMOS inverter of the delay element. The oscillation circuit has a ring oscillator in which (N + 1) CMOS inverters are connected in a ring shape,
Each of the delay elements has one CMOS inverter,
The delay time of the CMOS inverter of the ring oscillator matches the delay time of the CMOS inverter of the delay element,
11. The temperature sensor circuit according to claim 10, wherein the latch circuit has a reverse latch characteristic corresponding to an odd-numbered stage of the delay unit parallel circuit and a latch characteristic corresponding to an even-numbered stage of the delay unit parallel circuit.

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