JP2017157701A - Printed Wiring Board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board having high connection reliability.SOLUTION: A circuit board 10 of an embodiment has an upper mounting face and a lower mounting face. The upper mounting face has upper pads for mounting first electronic components and the lower mounting face has first pads for connection with a mother board and second pads for mounting second electronic components. The circuit board has a lower first solder resist layer formed on the lower mounting face and a lower second solder resist layer formed under the lower first solder resist layer. The lower second solder resist layer has a second hole for exposing all of the second pads and third openings for exposing the first pads individually. The second electronic component is stored in the second hole.SELECTED DRAWING: Figure 1

Description

The present invention relates to a printed wiring board having pads on both sides for mounting electronic components.

Patent document 1 is disclosing the manufacturing method of the printed wiring board which has a dam.

JP 2013-131714 A

[Problems of Patent Document 1]
According to FIG. 1 of Patent Document 1, Patent Document 1 forms a resin insulating layer formed of a layer made of a thermosetting resin composition and a layer made of a photocurable resin composition on the surface of the substrate. . And according to FIG. 2 of patent document 1, patent document 1 forms the dam in the layer which consists of a photocurable resin composition, and forms the opening part which penetrates a resin insulating layer. The component mounting portion is exposed through the opening. Then, patent document 1 has formed the solder ball in the opening part. According to FIG. 2B of Patent Document 1, the diameter of the opening formed in the layer made of the thermosetting resin composition and the diameter of the opening formed in the layer made of the photocurable resin composition. Seems the same. For this reason, it is considered difficult for the solder ball to reach the component mounting portion exposed from the opening.

The present invention includes an upper mounting surface having an upper pad for mounting a first electronic component, a first pad for connecting to a motherboard, and a second pad for mounting a second electronic component. A lower mounting surface located on the opposite side of the first upper mounting surface, and a first opening formed under the lower mounting surface and individually exposing the lower pads. A lower first solder resist layer having a portion, a second opening formed under the first lower solder resist layer, and exposing the second pad, and the first pad individually. And a lower second solder resist layer having a third opening. The first opening has a second opening at an interface between the lower first solder resist layer and the lower second solder resist layer, and the third opening is the lower opening. A third opening is provided at an interface between the first solder resist layer and the lower second solder resist layer, and the size of the third opening is larger than the size of the second opening. The lower first solder resist layer around the first opening is exposed.

According to the embodiment of the present invention, the connection reliability between the second electronic component and the printed wiring board and the connection reliability between the printed wiring board and the motherboard can be increased.

FIG. 1A shows a cross section of the printed wiring board of the embodiment, FIG. 1B shows a cross section of an application example of the printed wiring board, and FIG. It is a top view which shows a lower 1st soldering resist layer and a lower pad. 2 (A), 2 (B), 2 (C) and 2 (D) show a method for manufacturing a printed wiring board according to the embodiment, and FIG. 1 shows a solder resist layer. 3 (A), 3 (B), and 3 (C) show an example of a method for forming an upper solder resist layer and a lower solder resist layer, and FIG. 3 (D) and FIG. 3 (E). FIG. 4 is a diagram for explaining a first opening and a third opening.

1A shows a cross section of the printed wiring board 10 of the embodiment, and FIG. 1B shows an application example 100 including the printed wiring board 10 and semiconductor elements 90 and 92 mounted on the printed wiring board 10. The cross section of is shown. As shown in FIG. 1A, the printed wiring board 10 has a circuit board 30. The circuit board 30 has an upper mounting surface F and a lower mounting surface S opposite to the upper mounting surface F. The upper mounting surface F has an upper pad 73F for mounting the first electronic component 90. A plurality of upper pads 73F are formed in the central region of the upper mounting surface F.
The lower mounting surface S has a first pad 73Sp for connecting to the motherboard and a second pad 73Sc for mounting the second electronic component 92. A plurality of lower pads 73S are formed by the plurality of first pads 73Sp and the plurality of second pads 73Sc. The lower pad 73S is formed in almost the entire region of the lower mounting surface S. The plurality of second pads 73Sc are formed concentrated on a predetermined region.
The upper pad 73F and the lower pad 73S are connected by wiring in the circuit board 30 (not shown).

An upper solder resist layer 70F having an opening 71F exposing the upper pad 73F is formed on the upper mounting surface F. The openings 71F expose the upper pads 73F individually. Upper solder bumps 76F are formed on the upper pads 73F. The first electronic component 90 is mounted on the printed wiring board 10 via the solder bumps 76F (FIG. 1B). As shown in FIG. 1B, an underfill 96 is formed between the first electronic component 90 and the upper mounting surface F.

A lower pad 73S including a first pad 73Sp for connecting to the mother board and a second pad 73Sc for mounting the second electronic component is formed under the lower mounting surface S. Then, a lower first solder resist layer 70Sf having a first opening 71S exposing the lower pad 73S is formed under the lower mounting surface S and the lower pad 73S. The first opening 71S exposes the lower pads 73S individually. When the lower pad 73S has a third pad for mounting the third electronic component, the lower first solder resist layer 70Sf has a first opening 71S that exposes the third pad individually.
A lower second solder resist layer 70Ss is formed under the lower first solder resist layer 70Sf. The lower second solder resist layer 70Ss has a second opening 81S2 exposing the second pad 73Sc and a third opening 81S3 exposing the first pad 73Sp. The second opening 81S2 exposes all the second pads 73Sc. All the second pads 73Sc are exposed in one second opening 81S2. There are a plurality of third openings 81S3, and the third openings 81S3 individually expose the first pads 73Sp. When the lower pad 73S has the third pad for mounting the third electronic component, the lower second solder resist layer 70Ss has one fourth opening that exposes all the third pads.
A first solder bump 76Sp for connecting to the mother board and a second solder bump 76Sc for mounting the second electronic component 92 are formed under the first pad 73Sp.

FIG. 1C is a plan view of the printed wiring board 10 obtained by observing the printed wiring board 10 of FIG. 1A from below the lower second solder resist layer 70Ss. FIG. 1A is a cross-sectional view of the printed wiring board 10 between X1 and X1 in FIG.
As shown in FIG. 1C, the second pads 73Sc are formed concentrated in a predetermined area 80. A dotted line in FIG. 1C indicates the outer periphery of the area 80. The lower second solder resist layer 70Ss is not formed in the area 80. The size of the area 80 is larger than the size of the second electronic component. The ratio SZ1 / SZ2 between the size SZ1 of the area 80 and the size SZ2 of the second electronic component is 1.03 or more and 1.1. Even if the second electronic component is mounted under the second pad 73Sc, the second electronic component is accommodated in the second opening 81S2. The thickness of the application example can be reduced.
A lower second solder resist layer 70Ss is formed outside the area 80 including all the second pads 73Sc. Even if the underfill 94 is formed between the lower first solder resist layer 70Sf and the second electronic component, the lower second solder resist layer 70Ss functions as a dam. The first pad 73Sp is hard to get dirty with the underfill 94.

The lower first solder resist layer 70Sf and the lower second solder resist layer 70Ss are formed of the same material. The thickness ts of the lower solder resist layer 70S composed of the lower first solder resist layer 70Sf and the lower second solder resist layer 70Ss is thicker than the thickness tf of the upper solder resist layer 70F.

FIG. 3D shows an enlarged view of the lower first solder resist layer 70Sf and the lower second solder resist layer 70Ss. FIG. 3D shows the first opening 71S and the third opening 81S3. The lower first solder resist layer 70Sf has a lower surface S1 between the lower first solder resist layer 70Sf and the lower second solder resist layer 70Ss, and the lower second solder resist layer 70Ss has an upper surface. S2. The lower second solder resist layer 70Ss has a lower surface S3 opposite to the upper surface S2. FIG. 3E is a view for explaining the diameter of the first opening 71S and the diameter of the third opening 81S3. The first opening 71S tapers from the lower surface S1 toward the lower pad 73S. The first opening 71S has a diameter d4 on the lower pad 73S. The first opening 71S has a diameter d3 on the lower surface S1 of the lower first solder resist layer 70Sf. The diameter d4 is smaller than the diameter d3.
The third opening 81S3 is tapered from the lower surface S3 toward the upper surface S2. The third opening 81S3 has a diameter d2 on the upper surface S2 and a diameter d1 on the lower surface S3. The diameter d2 is smaller than the diameter d1.
The diameter d2 is larger than the diameter d3. The lower surface S1 of the lower first solder resist layer 70Sf around the first opening 71S is exposed by the third opening 81S3. The lower surface S1 of the first solder resist layer 70Sf always exists between the third opening 81S3 and the first opening 71S. That part is referred to as step 82. As shown in FIG. 1C, the shape of step 82 is a ring, the inner diameter of the ring is a diameter d3, and the outer diameter is a diameter d2.
In the printed wiring board 10 of the embodiment, the lower solder resist layer 70S is formed of the lower first solder resist layer 70Sf and the lower second solder resist layer 70Ss. Therefore, the thickness of the lower solder resist layer 70S tends to be thick. However, since the printed wiring board 10 includes the step 82, the first solder bumps 76Sp are likely to come into contact with the first pads 73Sp. The solder bumps 76Sp can be easily formed on the first pads 73Sp.
The connection reliability through the solder bumps 76Sp can be increased.

[Manufacturing Method of Embodiment]
FIG. 2 shows a method for manufacturing the printed wiring board 10 of the embodiment.

An insulating layer 301 having an upper surface US and a lower surface LS opposite to the upper surface is prepared. An upper pad 73F is formed on the upper surface US of the insulating layer 301. A lower pad 73S is formed under the lower surface LS of the insulating layer 301. A via conductor connecting the upper pad 73F and the lower pad 73S is formed in the insulating layer 301. Via conductors are not shown in the figure. The intermediate substrate 302 having the upper mounting surface F and the lower mounting surface S opposite to the upper mounting surface F is obtained. The upper mounting surface F has an upper pad 73F, and the lower mounting surface S has a lower pad 73S. A composition 70Fi for forming the upper solder resist layer 70F is formed on the upper mounting surface F, and a composition 70Si for forming the lower first solder resist layer 70Sf under the lower mounting surface S. Is formed (FIG. 2A). The composition 70Fi and the composition 70Si are cured by light. Alternatively, the composition 70Fi and the composition 70Si are cured by heat. In the embodiment, the upper solder resist layer 70F and the lower first solder resist layer 70Sf are formed by photographic technology (FIG. 2B).

A composition 70Ssi for forming the lower second solder resist layer 70Ss is formed under the lower first solder resist layer 70Sf (FIG. 2C). The composition 70Ssi is cured by light. Alternatively, the composition 70Ssi is cured with heat. In the embodiment, the lower second solder resist layer 70Ss is formed under the lower first solder resist layer 70Sf by photographic technology (FIG. 2D). The circuit board 30 is completed.

Solder balls are mounted on the pads 73F and 73S. Since the step 82 exists, the pad 73S and the solder ball are easily in contact with each other. The solder bumps 76F, 76Sc, and 76Sp are formed on the pads 73F and 73S by reflow. The first electronic component 90 is mounted on the solder bump 76F, and the second electronic component 92 is mounted on the solder bump 76Sc (FIG. 1B).

The opening 71F of the upper solder resist layer 70F, the first opening 71S of the lower first solder resist layer 70Sf, and the second opening 81S2 and the third opening 81S3 of the lower second solder resist layer 70Ss are simultaneously formed. can do. An example is shown below.
A composition 70Si for forming the lower first solder resist layer 70Sf is formed under the lower mounting surface S (FIG. 3A). At this time, the composition 70Fi is not formed on the upper mounting surface F. An exposure process for forming the first opening 71S is performed on the composition 70Si. However, development is not performed. A lower first solder resist layer 70Sf is formed under the lower mounting surface S. The first opening 71S is not formed. The first opening 71S is filled with the composition 70Si. Thereafter, as shown in FIG. 3B, a composition 70Fi for forming the upper solder resist layer 70F on the upper mounting surface F is formed. A composition 70Ssi for forming the lower second solder resist layer 70Ss is formed under the lower first solder resist layer 70Sf. An exposure process for forming the opening 71F is performed on the composition 70Fi. An exposure process for forming the second opening 81S2 and the third opening 81S3 is performed on the composition 70Ssi. Then, development is performed. As shown in FIG. 3C, the opening 71F of the upper solder resist layer 70F, the first opening 71S of the lower first solder resist layer 70Sf, and the second opening of the lower second solder resist layer 70Ss. The part 81S2 and the third opening 81S3 of the lower second solder resist layer 70Ss are formed at the same time. An upper solder resist layer 70F and a lower solder resist layer 70S are formed.

FIG. 2E is an enlarged view of the printed wiring board 10 and shows the lower second solder resist layer 70Ss of the first pad 73Sp, the second pad 73Sc, and the lower first solder resist layer 70Sf.
As shown in FIG. 2E, the first solder resist layer 70Sf on the lower side of the printed wiring board of the embodiment exposes the lower mounting surface S between the first pad 73Sp and the second pad 73Sc. You may have the groove | channel 99 to do. The groove 99 can surround all the second pads 73Sc. The groove 99 can penetrate the lower first solder resist layer 70Sf and the lower second solder resist layer 70Ss. The first pad 73Sp is hardly contaminated by the underfill 94.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 30 Circuit board 70F Upper solder resist layer 70S Lower solder resist layer 70Sf Lower first solder resist layer 70Ss Lower second solder resist layer 71F Opening 71S First opening 73Sp First pad 73Sc Second Pad 76Sp First Solder Bump 76Sc Second Solder Bump 80 Area 81S2 Second Opening 81S3 Third Opening 82 Step

Claims (3)

An upper mounting surface having an upper pad for mounting the first electronic component;
A lower mounting surface having a lower pad including a first pad for connecting to a motherboard and a second pad for mounting a second electronic component, and positioned on the opposite side of the upper mounting surface When,
A lower first solder resist layer formed under the lower mounting surface and having a first opening that individually exposes the lower pads;
A lower second solder resist formed under the lower first solder resist layer and having a second opening that exposes the second pads and a third opening that individually exposes the first pads. A printed wiring board having a layer,
The first opening has a second opening at an interface between the lower first solder resist layer and the lower second solder resist layer, and the third opening is the lower first solder resist layer. There is a third opening at the interface between the solder resist layer and the lower second solder resist layer, the size of the third opening is larger than the size of the second opening, and the third opening is the second opening. The lower first solder resist layer around one opening is exposed. 2. The printed wiring board according to claim 1, further comprising an upper solder resist layer formed on the upper mounting surface and having an opening for individually exposing the upper pads, and the lower first resist layer. The sum of the thickness of the solder resist layer and the thickness of the lower second solder resist layer is thicker than the thickness of the upper solder resist layer. 2. The printed wiring board according to claim 1, wherein the lower first solder resist layer has a groove exposing the lower mounting surface between the first pad and the second pad.

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