JP2017153057A - Reconfigurable semiconductor logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with a current situation in which there is no means for continuing to realize a large capacity, a low cost, and a high speed of an existing logic LSI formed on a plane pattern after the limit of the Moore's Law due to the short channel effects, for example.SOLUTION: The above object is achieved by realizing a desired reconfigurable combination circuit by combining two lamination-type Fe-FET NAND arrays using a multi-stage lamination vertical transistor structure used for a large-capacity lamination-type NAND memory. This can attain a desired combination circuit necessary for a logic LSI. Compared to the case of an existing logic LSI all realized on a plane pattern, a logic circuit can be realized on a much smaller area. In addition, since the multi-stage lamination vertical transistor structure can be used for manufacturing the logic circuit, the manufacturing cost can be reduced significantly than when an existing plane structure is used.SELECTED DRAWING: Figure 1

Description

The present invention relates to a reconfigurable semiconductor logic circuit capable of changing digital logic realized by program information.

In LSIs, planar transistors have been miniaturized according to Moore's Law, and large capacity, low cost, high speed, and low power consumption have been steadily advanced.

As a result, the MPU, which is a representative of logic LSI, realizes GHz operation using 1 billion or more planar transistors, and the NAND flash memory using planar transistors with the largest capacity among memory LSIs. The capacity has been increased up to 64 Gbit (Reference 1).

However, the miniaturization of the planar transistor has recently approached its limit due to the short channel effect and the like.

In order to solve this problem, a three-dimensional transistor resistant to the short channel effect has been developed. A typical example is SGT (Surrounding Gate Transistor) (Reference 2).

Although application of SGT to a single-layer logic LSI is being studied, a proposal for stacking NAND flash memories has been made because the capacity can be easily increased when stacked in the vertical direction (Reference 3).

The originally proposed stacked NAND flash memory has a method of manufacturing memory cells by an independent process for each layer, so that the capacity can be increased by stacking, but the bit cost, which is the cost per bit, is low. did not become.

In order to solve this problem, a multi-stage stacked vertical transistor structure has been proposed (Reference 4, Patent Document 1).

In this method, the gate electrode and the interlayer insulating film between the gate electrodes are stacked as a set of manufacturing steps, and after repeating this set for the number of layers to be stacked, a trench is formed all the way down to the bottom of the substrate. This is a manufacturing technique in which memory cells are formed in the same process all together for several minutes.

By introducing a multi-stage stacked vertical transistor structure, it has become possible for the first time not only to increase the capacity by stacking but also to significantly reduce the bit cost compared to a single layer structure without stacking.

This multi-stage stacked vertical transistor structure was subsequently introduced in earnest in NAND flash memories with the largest capacity (Reference 5).

To date, a stacked NAND flash memory having 32 to 48 layers has been developed, and Toshiba, Samsung, and Intel / Micron are developing and commercializing.

The use of a multistage stacked vertical transistor structure has the characteristics that not only the number of stacked layers can be increased, the capacity can be increased, but also the bit cost can be reduced and the cost can be reduced.

In other words, even after the miniaturization of planar transistors according to Moore's Law has reached the limit, large capacity memories can be stacked with a multistage stacked vertical transistor structure to achieve higher capacity and lower costs as before. It is highly possible.

With the progress of manufacturing technology, the number of stacks can be doubled every few years. As a result, the capacity and cost can be reduced as before.

On the other hand, the current logic LSI, which has a complicated circuit configuration with planar transistors and wiring compared to large-capacity memories, has increased capacity, reduced cost, and increased speed after the limit of transistor miniaturization. Promising candidates that can be promoted have not yet been proposed.
In the future, it is desired to propose means for continuously increasing the capacity, cost and speed of logic LSIs.

JP 2009-4517, Keiyasu Tanaka, Hideaki Aoji, Ryuta Katsumata, Jie Kito, Yoshiaki Fukuzumi, Daigo Kito, Mitsuru Sato, Yasuyuki Matsuoka “Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof”

Reference 1

M.M. Sako et al, “A Low-Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology”, ISSCC Dig. Tech. Papers, 2015.

Reference 2

H. Takato et al. "Impact of SGT for ultra-high density LSIs", IEEE Trans. Electron Devices, vol. 38, pp. 573-578, 1991.

Reference 3

T. T. Endoh et. al. , “Novel Ultra-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE Trans. Electron Devices, vol. 50, nc. 4, pp. 945-951, 2003.

Reference 4

H. Tanaka et al. ,: “Bit Costable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, Symp. on VLSI Technology, 2007.

Reference 5

R. Katsumata et al. , “Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices”, Symp. on VLSI Technology, pp. 136-137, 2009.

Problems to be solved by the invention

At present, there is no means to continuously increase the capacity, cost, and speed of logic LSI even after Moore's Law is limited by the short channel effect.

Means for solving the problem

This was realized by combining two pairs of stacked Fe-FET NAND arrays using a multi-stage stacked vertical transistor structure used in a large capacity stacked NAND memory to realize any reconfigurable combinational circuit. As a result, any combinational circuit necessary for the logic LSI can be realized.

Effect of the invention

According to the present invention, by using the manufacturing technology used in the large-capacity stacked NAND memory, even after the limit of Moore's law due to the short channel effect or the like, the capacity of the logic LSI is continuously increased, the cost is reduced, It is possible to provide means for realizing high speed.

A logic circuit can be realized in a very small area as compared with a conventional logic LSI that has realized all on a plane pattern. In addition, since the multistage stacked vertical transistor structure can be used for the manufacture, the manufacturing cost is significantly reduced as compared with the conventional planar structure.

Hereinafter, an embodiment of a reconfigurable semiconductor logic circuit according to the present invention will be described with reference to the drawings.
[First Embodiment]
(Configuration of the first embodiment)

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a stacked Fe-FET NAND / NAND array according to an embodiment of the present invention. The two types of NAND arrays 201 and 202 are composed of stacked NAND FeRAMs using Fe-FETs as driver transistor portions.

  In this example, eight Fe-FETs connected in series are realized by stacking eight layers in the vertical direction. Eight types of input signals (stacked in eight layers) are input to the gate of the Fe-FET. The gate insulating film of the Fe-FET has a program function. That is, the Fe-FET not only operates as a normal transistor but also has a built-in program function. As a result, eight layers of wiring and Fe-FET can be stacked in an area of only one element as viewed from above.

Arbitrary logic using input signals can be realized in the NAND arrays 201 and 202. When all the signals are used, the output is expressed as an inverted signal of the product of eight kinds of signals. When it is not necessary to use all the stacked transistors, it is realized by performing a program that always makes the passage gate conductive.

めプログラムを行う。For example, in the leftmost NAND of 201 (NAND array 1) in FIG.

Program.

Further, as shown in FIG. 1, NAND logic is realized by using an SGT transistor to which a precharge signal ΦP is input. Further, in order to control the signal flow between 201 (NAND array 1) and 202 (NAND array 2) (separate both at the time of programming and connect them at the time of reading), the transfer control signal 210 (ΦT) is applied to the gate. Connect the connected SGTs. 202 (NAND array 2) calculates and outputs necessary logic using the outputs 203, 204, 205, and 206 of 201 (NAND array 1) as input signals.

In the example of FIG. 1, the number of inputs of 202 (NAND array 2) is smaller than the number of inputs of 201 (NAND array 1). In that case, as shown in FIG. 1, by connecting a passing Fe-FET to the lower part of the NAND array (202 in this case) with a small number of inputs (in FIG. 1, four are connected in series and their gates are connected). The high voltage VPP is always applied to make it conductive) 201 (NAND array 1) and 202 (NAND array 2) always have the same number of connection stages.

This is indispensable for manufacturing 201 (NAND array 1) and 202 (NAND array 2) in the same process step and reducing the manufacturing cost as much as possible. When writing to 202 (NAND array 2), a voltage is applied to WL1-WL4 from the outside of 202 (NAND array 2).

FIG. 2 shows a basic configuration of a stacked NAND FeRAM used for realizing the newly proposed stacked Fe-FET NAND / NAND array of FIG. This has been proposed in the past to realize a high-speed, low-cost nonvolatile memory [Reference 6] [Reference 7].

Like the stacked NAND flash memory that is currently being commercialized, a NAND configuration is formed in the vertical direction (FIG. 2 shows a case where four layers are stacked for simplicity).

In order to realize this stacked structure, a multi-stage stacked vertical transistor structure is used like the stacked NAND flash memory. That is, after repeating the lamination of the inter-WL insulating film 306 and the WL material 301 four times, trenches reaching the bottom of the substrate are formed all at once, and the transistors are formed at once for the four layers. This manufacturing technique is also called a BiCS (Bit-cost-Scalable) technique. For this reason, the low cost (low bit cost) is realized like the stacked NAND flash memory.

The memory cell is written by applying a high voltage (10 V) between the selected WL (for example, WL1) and the selected coated substrate (for example, Vsub1). The threshold voltage of the written memory cell (Fe-FET) can be made positive or negative depending on which is the higher voltage.

At the time of reading, 0 V is applied to the selected WL, and about half of the voltage at the time of writing is applied to the gate of the passing memory cell in the same NAND. Since the Fe-FET used for the memory cell is suitable for high-speed operation, high-speed operation higher than that of the stacked NAND flash memory can be expected.

Next, programming and erasing of the Fe-FET necessary for realizing the stacked Fe-FET NAND / NAND array of FIG. 1 will be described.

FIG. 3 shows the program and erase method. The initial state is an E-type Fe-FET (401) with a threshold voltage of 0.2V. In this state, when a low level of 0 V is applied to the gate of the Fe-FET, the Fe-FET is turned off. When this is programmed, 0V is applied to the gate of the Fe-FET and a high voltage (+ 10V) is applied to the substrate to form a D-type Fe-FET (402) having a threshold voltage of -1V.

The D-type Fe-FET (402) is turned on even when the gate voltage is 0 V, which is a low level. When a logic is realized, the D-type Fe-FET (402) becomes a so-called pass transistor and becomes conductive regardless of the logic. To return from this state to the original E-type Fe-FET state (401), an erase operation is performed in which a voltage opposite to that at the time of programming is applied between the gate of the Fe-FET and the substrate.

Next, the program operation of the stacked Fe-FET NAND / NAND array of FIG. 1 will be described. FIG. 4 shows a method of programming an inverted signal of ABCD realized by the leftmost NAND structure of 201 (NAND array 1).

４１５，４１７にプログラムするためにそのゲートに０Ｖを印加し、選択したＮＡＮＤ構造の基板に高電圧（＋１０Ｖ）を印加する。At the time of programming, it is necessary to apply 0 V to the gate of the Fe-FET to be programmed and a high voltage to the selected NAND structure substrate as shown in FIG. When programming the reverse signal of ABCD

In order to program 415, 417, 0V is applied to its gate, and a high voltage (+ 10V) is applied to the substrate of the selected NAND structure.

An intermediate voltage (+5 V) is applied to the gate so that the four Fe-FETs 410, 412, 414, and 416 to which A, B, C, and D are input are not programmed. By this operation, it is possible to simultaneously program the Fe-FETs in the same NAND structure.

On the other hand, when it is desired to change the realized logic, a voltage opposite to the current program operation is applied to the passing Fe-FET. During programming, ΦP is set to 0 V in order to separate the NAND structure and the power supply voltage VDD. Further, 210 (ΦT) is set to 0 V in order to separate 201 (NAND array 1) and 202 (NAND array 2) during programming.

ラム法に関して述べる。通過Ｆｅ−ＦＥＴにプログラムするためにＷＬ１とＷＬ４に０Ｖを印加し、選択したＮＡＮＤの基板には高電圧（＋１０Ｖ）を印加する。ＷＬ２とＷＬ３がゲートに接続されているＦｅ−ＦＥＴ５０２，５０３はプログラムされないように中間電圧（＋５Ｖ）を印加する。

Describe the Lamb method. In order to program the passing Fe-FET, 0V is applied to WL1 and WL4, and a high voltage (+ 10V) is applied to the substrate of the selected NAND. An intermediate voltage (+5 V) is applied so that the Fe-FETs 502 and 503 whose WL2 and WL3 are connected to the gate are not programmed.

The other applied voltages of ΦP and 210 (ΦT) are the same as those at the time of writing 201 (NAND array 1). If 201 (NAND array 1) and 202 (NAND array 2) are separated during programming, both NAND arrays 201 and 202 can be programmed or erased simultaneously. Alternatively, it is possible to program one and erase the rest.

Next, the read operation of the stacked Fe-FET NAND / NAND array of FIG. 1 will be described. FIG. 6 describes a method of reading an inverted signal of ABCD realized by the leftmost NAND structure of 201 (NAND array 1). The output portion 203 of the NAND is precharged in advance by setting ΦP = 1V during the precharge period. At this time, 210 (ΦT) = 0V and 201 (NAND array 1) and 202 (NAND array 2) are separated.

６０８はあらかじめプログラムされしきい値は−１Ｖになっている為、ゲート電圧が０Ｖでも通過Ｆｅ−ＦＥＴになり電流が流れる。その結果このＮＡＮＤは選択され出力２０３からＡＢＣＤの反転信号が出力される（出力が０Ｖになる）。２０１（ＮＡＮＤアレイ１）の残りのＮＡＮＤ構造でも同様な読み出し動作が行われる。Next, an input signal is input to 201 (NAND array 1) during active time (evaluation time). example

Since 608 is programmed in advance and the threshold value is −1V, even if the gate voltage is 0V, it becomes a passing Fe-FET and current flows. As a result, this NAND is selected and an inverted signal of ABCD is output from the output 203 (output becomes 0V). A similar read operation is performed in the remaining NAND structure 201 (NAND array 1).

Thereafter, 210 (ΦT) = 2V and the output of 201 (NAND array 1) is transferred to 202 (NAND array 2) (WL1-WL4).

法に関して述べる。２０１（ＮＡＮＤアレイ１）からは２０３（ＷＬ１＝０Ｖ），２０４（ＷＬ２＝１Ｖ），２０５（ＷＬ３＝１Ｖ），２０６（ＷＬ４＝０Ｖ）の信号が転送されてくる。

State the law. Signals 203 (WL1 = 0V), 204 (WL2 = 1V), 205 (WL3 = 1V), and 206 (WL4 = 0V) are transferred from 201 (NAND array 1).

される（このＮＡＮＤ構造の出力２０８が０Ｖになる）。Since Fe-FE T701 and 704 input by WL1 and WL4 are programmed in advance, read

(The output 208 of this NAND structure becomes 0V).

Any combinational circuit can be written to and read from the stacked Fe-FET NAND / NAND array by the above procedure. When changing the logic of the combinational circuit, the write operation is performed in the order of erase and program.

Effects of the embodiment

By using the above method, a logic LSI can be realized with a very small pattern area and manufacturing cost as compared with the case (FIG. 8) in which a logic LSI combination circuit is realized using a conventional planar transistor. In the example of FIG. 1, the pattern area of the conventional single layer type is relatively large as 32F * 48F = 1536F2 (F is a design rule), but when using the present invention, 8F * 14F = 112F2 is about 7.3%. (Figure 9 shows the comparison results of areas)

Reference 6

] Koichi Kanno and Shigeyoshi Watanabe "Study on readout method of stacked NAND structure 1-transistor type FeRAM", IEICE C, Vol. J91-C, No11, pp. 668-669, 2008.

Reference 7

Koichi Konno and Shigeyoshi Watanabe, “Design Method of Stacked NAND Structure One-Transistor FeRAM.” Electron Theory (C), Vol. 13C, no. 2, pp. 226-234, 2010.

Other examples

The present invention is not limited to this embodiment. A floating gate transistor or a charge trap transistor used in a stacked 3D flash memory may be used instead of the Fe-FET using a ferroelectric as a transistor for realizing the NAND array. Alternatively, a one-transistor phase change memory (PRAM) using a phase transition of a glass material may be used. Any transistor having a function of storing information with one element can be used as a component of the present invention.
In the first embodiment, NAND logic is realized in the vertical direction by using a multi-stage vertical transistor (basic method of 3D NAND flash memory that is currently being commercialized), but the BiCS technology in a broad sense is used. However, NAND logic may be realized in the horizontal direction. Other various modifications are possible without departing from the spirit of the present invention.

Industrial applicability

The present invention can be applied to all logic LSIs that operate with digital logic currently commercialized, such as system LSIs, logic LSIs, and FPGAs.

It is a block diagram of the reconfigurable semiconductor logic circuit concerning this invention. It is a block diagram of the laminated type FeRAM used for the reconfigurable semiconductor logic circuit concerning this invention. It is explanatory drawing of the program operation | movement of Fe-FET which is a component of the reconfigurable semiconductor logic circuit concerning this invention. It is explanatory drawing of the program operation | movement of the 1st stage NAND array of the reconfigurable semiconductor logic circuit concerning this invention. It is explanatory drawing of the program operation | movement of the 2nd-stage NAND array of the reconfigurable semiconductor logic circuit concerning this invention. It is explanatory drawing of the read-out operation | movement of the 1st NAND array of the reconfigurable semiconductor logic circuit concerning this invention. It is explanatory drawing of the read-out operation | movement of the 2nd-stage NAND array of the reconfigurable semiconductor logic circuit concerning this invention. It is a block diagram of the conventional reconfigurable semiconductor logic circuit. It is a comparison figure of the pattern area of the reconfigurable semiconductor logic circuit of the past and this invention.

201... NAND array 1, 202... NAND array 2, 203-206... 4 output signals of NAND array 1, 207-209... 3 output signals of NAND array 2, 210. ..Connection signal between NAND array 1 and NAND array 2, 211... D type transistor identifier, 301... Word line, 302... Bit line, 303. Ferroelectric film, 305 ... oxide film, 306 ... interlayer insulating film, 307 ... N-type diffusion layer, 308 ... source line, 309 ... SOI substrate, 310 ... Vsub voltage, 311 ... top view, 312 ... equivalent circuit diagram, 313 ... sectional view,
401 ... E type FeFET, 402 ... D type FeFET,
410-417 ... 8 FeFETs constituting the first NAND of the NAND array 1 (when programming), 501-508 ... 8 FeFETs constituting the second NAND of the NAND array 2 ( At the time of programming),
601-608 ... 8 FeFETs constituting the first NAND of the NAND array 1 (when reading), 701-708 ... 8 FeFETs constituting the second NAND of the NAND array 2 ( When reading)

Claims (6)

It has a plurality of NAND logics realized by serially connecting transistors having functions to program and store digital information, and the output of the NAND logic 1 is input to a different NAND logic 2, and the output of the NAND logic 2 is digital A reconfigurable semiconductor logic circuit formed on a semiconductor substrate, wherein the combinational logic can be realized. 2. The reconfigurable semiconductor logic circuit according to claim 1, wherein the NAND logic realized by connecting the transistors in series transmits an output signal in a direction perpendicular to the semiconductor substrate, and the gate electrode of the transistor at the time of manufacture. A reconfigurable semiconductor logic circuit comprising: a plurality of inter-layer insulating films stacked in series and formed; then, adjacent transistors are separated and transistors are formed by a batch etching technique reaching the semiconductor substrate. 3. The reconfigurable semiconductor logic circuit according to claim 1, wherein the transistor uses an Fe-FET that stores digital information in a ferroelectric film. 3. The reconfigurable semiconductor logic circuit according to claim 1, wherein the transistor uses a flash memory that stores digital information in a trap level in a floating gate or a gate insulating film. circuit. 3. The reconfigurable semiconductor logic circuit according to claim 1, wherein the transistor uses a phase change memory for storing digital information in a chalcogenite material. 7. The reconfigurable semiconductor logic circuit according to claim 1, wherein the NAND logic realized by connecting the transistors in series transmits an output signal in a horizontal direction to the semiconductor substrate, and is manufactured. A reconfigurable semiconductor logic circuit characterized in that a transistor gate electrode and an interlayer insulating film are sometimes stacked and formed, and then adjacent transistors are separated and transistors are formed by a batch etching technique reaching the semiconductor substrate.

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