JP2017135294A - Semiconductor device substrate, semiconductor device substrate manufacturing method, semiconductor device, and semiconductor device manufacturing method - Google Patents

Abstract

Kind Code: A1 A semiconductor device substrate capable of patterning with a resist on a base material, growing a plating and making use of a metal three-dimensional structure, and a method for manufacturing the semiconductor device substrate, a semiconductor device, and a semiconductor An apparatus manufacturing method is provided.
A semiconductor device substrate is provided with a semiconductor element and includes a connection terminal (through portion 24-1 of a nucchi element) to an external circuit, the semiconductor element terminal, and the connection terminal And a wiring by plating 25 arranged along the surface of the semiconductor device substrate 1 is provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device substrate, a semiconductor device substrate manufacturing method, a semiconductor device, and a semiconductor device manufacturing method.

  A substrate is produced by patterning with a resist on a base material and growing a plating. Patent Document 1 describes a substrate for a semiconductor device having an electrode including an inclined portion that is formed by a circuit pattern having a single-layer structure and whose side surface is reduced in size as the side approaches the substrate side and is scraped inward. .

JP 2010-219497 A

  However, since the electrodes of the semiconductor device substrate of Patent Document 1 are formed in a single layer structure, wiring routing on the semiconductor device substrate in the semiconductor package is restricted.

According to the first aspect of the present invention, the substrate for a semiconductor device mounts a semiconductor element, includes a connection terminal with an external circuit, connects the terminal of the semiconductor element and the connection terminal, Plating wiring disposed along the surface of the semiconductor device substrate is provided.
According to a second aspect of the present invention, a method for manufacturing a semiconductor device substrate is a method for manufacturing a semiconductor device substrate on which a semiconductor element is mounted, wherein the first opening and the second opening are formed on the conductive substrate. Forming a resist layer having an opening, and connecting the first portion of the conductive substrate facing the first opening to the second portion of the conductive substrate facing the second opening by plating To do.
According to the third aspect of the present invention, the semiconductor device includes a semiconductor element sealed, and includes a connection terminal with an external circuit, and the terminal of the semiconductor element and the connection terminal are at least of the semiconductor device. They are connected by plating wired along one surface.
According to a fourth aspect of the present invention, in a semiconductor device manufacturing method, a semiconductor device substrate manufactured by the semiconductor device substrate of the first aspect or the semiconductor device substrate of the second aspect is provided. The semiconductor element is mounted, and the semiconductor element mounted on the semiconductor device substrate is sealed.
According to a fifth aspect of the present invention, in the semiconductor device manufacturing method, the semiconductor device substrate manufactured by the semiconductor device substrate according to the first aspect or the semiconductor device substrate according to the second aspect is provided. The semiconductor element is mounted, the semiconductor element mounted on the semiconductor device substrate is sealed, and the conductive substrate is peeled from the sealed semiconductor package.

  According to the present invention, it is possible to route a wiring utilizing a three-dimensional structure of metal on a semiconductor device substrate.

1A and 1B are diagrams illustrating a semiconductor device substrate according to an embodiment, in which FIG. 1A is an end view and FIG. 1B is a top view. It is a figure which shows typically the 1st process of manufacture of the board | substrate for semiconductor devices of one Embodiment, FIG. 2 (a) is sectional drawing, FIG.2 (b) is a top view. It is a figure which shows typically the 2nd process of manufacture of the board | substrate for semiconductor devices of one Embodiment. It is a figure which shows typically the 3rd process of manufacture of the board | substrate for semiconductor devices of one Embodiment, FIG. 4 (a) is sectional drawing, FIG.4 (b) is a top view. It is a figure which shows typically the 4th process of manufacture of the board | substrate for semiconductor devices of one Embodiment, Fig.5 (a) is sectional drawing, FIG.5 (b) is a top view. It is a figure which shows typically the 5th process of manufacture of the board | substrate for semiconductor devices of one Embodiment, FIG. 6 (a) is sectional drawing, FIG.6 (b) is a top view. FIG. 7A is a diagram illustrating a semiconductor device according to an embodiment, FIG. 7A is an end view, and FIG. 7B is a plan view as viewed from the bottom. It is an end view which shows the manufacturing process of the semiconductor device of one Embodiment. FIG. 8A is an end view showing a semiconductor device substrate. FIG. 8B is an end view showing the sixth step. FIG. 8C is an end view showing the seventh step. FIG. 8D is an end view showing the eighth step. It is an end view which shows the semiconductor device of one Embodiment.

  Hereinafter, a semiconductor device substrate and a semiconductor device according to an embodiment will be described with reference to the drawings as appropriate. The semiconductor device of this embodiment is manufactured using the substrate for a semiconductor device of this embodiment. Unless otherwise specified, in the semiconductor device substrate 1, the surface on which the conductive substrate 30 is on the surface is the lower surface, and the surface on the opposite side where the plating structure 21 described later is exposed is the upper surface. Further, in the following embodiments, the term “plating” indicates a case where the plating is formed on the metal surface, and also indicates a case where the plating is used separately from the metal formed on the surface. Furthermore, in the present embodiment, the term “connect” includes the meaning that two connected objects can conduct.

  FIG. 1 shows a substrate 1 for a semiconductor device according to the present embodiment, FIG. 1A is an end view taken along the line AA of FIG. 1B, and FIG. 1B is a view in FIG. It is the figure (top view) seen from above. The semiconductor device substrate 1 includes a conductive substrate 30, a resist layer 11, and a plating structure 21. The plating structure 21 is formed by integrally connecting a plurality of plating elements 24. On both sides of the plating element 24 with the resist layer 11 interposed therebetween, surface plating layers 23 and 25 for connection to an external electric circuit of the semiconductor device substrate 1 are formed by bonding or the like.

In the present embodiment, the upper surface of the semiconductor device substrate 1 is used as a bonding surface of the semiconductor element, and the lower surface side of the plating element 24 is used as a connection terminal to the outside of the semiconductor device manufactured using the semiconductor device substrate 1. Configure. Accordingly, the bonding plating 25 is disposed on the upper surface side of the plating element 24 and the exterior mounting plating 23 is disposed on the lower surface side. The bonding plating 25 includes a metal such as silver, palladium, or gold. The exterior mounting plating 23 includes a metal such as gold or palladium.
The composition of the bonding plating 25 and the exterior mounting plating 23 is not particularly limited as long as it facilitates connection processing.

  The conductive substrate 30 is made of copper or stainless steel processed into a plate shape, but is not particularly limited as long as it is a semiconductor substrate that can be plated and etched. The resist layer 11 is preferably made of a permanent resist such as a solder resist. The plating that constitutes the plating element 24 includes a metal such as nickel, but is not particularly limited as long as it can be processed and desired durability as a part of the semiconductor can be obtained.

Each of the plating elements 24 is formed on a cylindrical portion (hereinafter referred to as a penetration portion) 24-1 penetrating the opening of the resist layer 11 and intruding into the conductive substrate 30, and on the upper surface of the semiconductor device substrate 1. And a protruding portion 24-2. The protruding portion 24-2 has an overhang structure in which the outer periphery protrudes beyond the outer periphery of the penetrating portion 24-2. In other words, the protruding portion 24-2 has a wider cross section than the penetrating portion 24-1 in a direction parallel to the upper surface of the semiconductor device substrate 1. Further, at least a part of the cross section of the protrusion 24-2 parallel to the upper surface of the semiconductor device substrate 1 extends radially from the through portion 24-1.
In the present embodiment, the penetrating portion 24-1 of the plating element 24 is configured to have a cylindrical cross section, but the shape is not particularly limited as long as the plating element 24 has an overhang structure.

The plating structure 21 is formed by connecting adjacent plating elements 21, and forms a wiring pattern along the upper surface of the semiconductor device substrate 1. The substrate for a semiconductor device 1 of this embodiment includes a wiring pattern shown radially in the top view of FIG. A broken-line circle in FIG. 1B schematically shows the outer periphery of the cylindrical portion 24-1 of the plating element 21. The same applies to the subsequent drawings.
The circuit pattern of the plating structure 21 is not particularly limited as long as it includes a portion formed along the upper surface of the semiconductor device substrate 1. By appropriately changing the circuit pattern of the plating structure 21, the connection terminals to the outside of the semiconductor package made using the semiconductor device substrate 1 connected to the respective terminals of the semiconductor element via the plating structure 21 are provided. The position can be adjusted.

  The shortest distance between adjacent plating elements 24 (d in FIG. 1) can be designed as appropriate, but is set to, for example, several μm to several hundred μm, preferably 10 μm to 200 μm, and more preferably, 40 μm or more and 120 μm or less. If the shortest distance d between the plating elements 24 is too short, the resulting semiconductor package has too many connection terminals with the outside, and structural features cannot be utilized. If the shortest distance d between the plating elements 24 is too long, the overhanging structure of the protrusion 24-2 becomes large, so that the pitch interval between the terminals that should be insulated originally becomes narrow, and the printed circuit board of the obtained semiconductor package, etc. Precise connection processing is difficult.

(Manufacturing method of substrate 1 for semiconductor device)
The semiconductor device substrate 1 can be efficiently mass-produced at low cost by using the following manufacturing method using, for example, a panel having a size of several tens of cm in length and width. In the following description, a method for manufacturing the semiconductor device substrate 1 including the plating structure 21 in which two adjacent plating elements 24 are connected will be described for easy understanding.

FIG. 2 schematically shows a first step of manufacturing the semiconductor device substrate 1, and FIG. 2A is a cross-sectional view taken along the line BB in FIG. 2B, and FIG. These are the figures which looked at Drawing 2 (a) from the upper part in a figure. The first process is a photolithography process in which a resist layer 11 having a plurality of circular openings 12 is formed on a conductive substrate 30 made of copper or stainless steel. Here, the first opening 12-1 and the second opening 12-2 are formed at positions adjacent to each other so that the grown plating can be connected in the plating process in the later fourth step.
In this embodiment, the resist layer 11 including the circular opening 12 is formed in order to manufacture the substrate 1 for a semiconductor device in which the penetrating part 24-1 of the plating element 24 has a cylindrical shape. The cross-sectional shape may be appropriately designed according to the cross-sectional shape of the penetrating portion 24-1 of the plating element 24.

  In the first step, a resist layer 11 is formed by applying a photoresist on the conductive substrate 30, irradiating a laser beam through a mask having a pattern including a plurality of circular elements, and performing development processing. To do. An excimer laser or the like can be used as the laser device. In the top view of FIG. 2B, the conductive substrate 30 is exposed in the circular opening 12 of the resist layer 11 formed on the semiconductor device substrate 1.

  FIG. 3 is a cross-sectional view schematically showing a second step of manufacturing the semiconductor device substrate 1. The second step is a first etching step for etching the surface of the conductive substrate 30 using the resist layer 11 as a mask. A top view corresponding to the cross-sectional view of FIG. 3 is the same as FIG.

  In the second step, the conductive substrate 30 is etched to a desired depth by dry etching, for example. The etched surface 22 of the conductive substrate 30 is formed in a concave portion of the conductive substrate 30 and faces the opening 12 of the resist layer 11. A surface of the conductive substrate 30 facing the first opening 12-1 is a portion 22-1 and a surface of the conductive substrate 30 facing the second opening 12-2 is a portion 22-2.

  As the etching method in the second step, a general method such as reactive ion etching can be used. The depth at which the conductive substrate 30 is etched can be appropriately adjusted according to the height (standoff structure described later) required for the connection terminal with the outside of the semiconductor package manufactured using the semiconductor device substrate 1. it can. Even if the surface is etched shallowly, the oxide film can be removed and the subsequent plating process can be made efficient. However, it is preferable to adjust the depth to several μm to several tens μm in view of the structure of the obtained semiconductor device More preferably, the depth is adjusted to 5 μm or more and 15 μm or less.

  4 schematically shows a third step of manufacturing the semiconductor device substrate 1. FIG. 4A is a cross-sectional view taken along the line BB in FIG. 4B, and FIG. These are the figures which looked at Fig.4 (a) from the upper direction in the figure. In the fourth step, the exterior mounting plating 23 is formed on the surface 22 of the conductive substrate 30 facing the opening 12 of the resist layer 11 by plating using the conductive substrate 30 as a seed layer. The composition of the exterior mounting plating 23 is not particularly limited, but it is preferable to include, for example, gold plating, palladium plating, and the like, since the connection processing with an external electronic circuit or the like of the obtained semiconductor package becomes particularly easy.

  FIG. 5 schematically shows a fourth step of manufacturing the semiconductor device substrate 1, and FIG. 5A is a cross-sectional view taken along the line BB in FIG. 5B, and FIG. These are the figures which looked at Fig.5 (a) from the upper direction in the figure. In the fifth step, the plating structure 21 is formed on the exterior mounting plating 23 by plating using the exterior mounting plating 23 as a seed layer. Although the plating structure 21 of this embodiment is configured to include nickel plating, the composition is not particularly limited, and a structure suitable for plating processing and use as a part of a semiconductor can be used.

  In the fourth step, after the plating grows from the exterior mounting plating 23 formed on the surface 22 of the conductive substrate 30 facing the opening 12 of the resist layer 11 and fills the opening 12, the semiconductor device It grows spreading in a direction along the upper surface of the substrate 1. From the first part 22-1 and the second part 22-2 of the conductive substrate 30, the plating grown through the first opening 12-1 and the second opening 12-2 is connected, respectively. Adjust the plating time. Since the plating grows at approximately the same speed in each direction perpendicular to the metal surface, when the plating process is performed so that the platings grown from the adjacent openings 12-1 and 12-2 are connected to each other, The height h of the plating element 24 from the surface of the resist layer 11 is greater than half the shortest distance d between the plating elements 24 connected adjacently. That is, 2h ≧ d holds. Alternatively, h1 + h2 ≧ d holds for the heights h1 and h2 of the two plating elements 24 that are adjacently connected. In the next step, plating is further formed on the plating element 24. Similarly, the relationship of 2h ≧ d and h1 + h2 ≧ d is established.

  6 schematically shows a fifth step of manufacturing the semiconductor device substrate 1, and FIG. 6A is a cross-sectional view taken along the line BB of FIG. 6B, and FIG. These are the figures which looked at Drawing 6 (a) from the upper part in a figure. In the fifth step, a bonding plating 25 for facilitating connection processing with a semiconductor element is formed on the plating structure 21 by plating. The composition of the bonding plating 25 is not particularly limited, but it is preferable to include, for example, gold plating, palladium plating, silver plating, etc., because connection processing with a semiconductor element becomes easy.

(Method for manufacturing semiconductor device)
A manufacturing method of the semiconductor device 100 manufactured using the semiconductor device substrate 1 of the present embodiment will be described. The first to fifth steps of manufacturing the semiconductor device 100 are the first to fifth steps of the semiconductor device substrate 1 described above, and the subsequent steps are counted from the sixth.

FIG. 7 shows the semiconductor device 100 of this embodiment, FIG. 7A is an end view of the CC section of FIG. 7B, and FIG. 7B is the lower side in FIG. 7A. It is the figure seen from (bottom view). The semiconductor device 100 includes a semiconductor element 2, a resist layer 11, a plating structure 21, and a sealing resin 37. The plating structure 21 is formed by integrally connecting plating elements 24, and the terminals of the semiconductor element 2 and the protrusions 24-2 of the plating element 24 are connected via bonding plating 25 and bumps 38. The through portion 24-1 of the plating element 24 constitutes a connection terminal with an external electronic circuit or the like of the semiconductor device 100, and is connected to an external electronic circuit or the like via the exterior mounting plating 23. A portion of the semiconductor device 100 that lifts the package body forms a standoff structure 240. The bump 38 includes, for example, gold.
The resist layer 11 may be removed.

The plating structure 21 of the semiconductor device 100 constitutes a wiring along the bottom surface of the semiconductor device 100. In the semiconductor device 100 of the present embodiment, wiring is formed by the plating structure 21 in a radial pattern from the center of the semiconductor device 100 as shown in FIG. The semiconductor element 2 is blocked by the sealing resin 37 and cannot be seen from the bottom surface of the semiconductor device 100, but its outline is indicated by a broken-line rectangle for reference.
Here, the pattern of the circuit using the plating structure 21 can be appropriately configured and is not particularly limited. The phrase “along the bottom surface of the semiconductor device 100” does not limit the point in contact with the bottom surface. Further, according to the characteristics of the semiconductor device 100, the wiring by the plating structure 21 of the present embodiment is used. Can be placed on various surfaces.

  FIG. 8 is an end view of a position corresponding to a CC cut part (FIG. 7B) schematically showing the manufacturing process of the semiconductor device 100 of the present embodiment in time series. FIG. 8A shows the semiconductor device substrate 1 of this embodiment.

  FIG. 8B is an end view showing a sixth step of manufacturing the semiconductor device 100. In the sixth step, the semiconductor element 2 formed and diced on the wafer is mounted on the semiconductor device substrate 1. In the sixth step, the semiconductor element 2 and the protruding portion 24-2 of the plating element 24 of the semiconductor device substrate 1 are connected by flip bonding through the bonding surface plating 25 and the bump 38 using a flip bonding apparatus or the like. To do. Preferably, the semiconductor element 2 has a width of a surface parallel to the semiconductor device substrate smaller than that of the semiconductor device substrate 1. Accordingly, a fan-out type semiconductor package in which connection terminals with the outside are arranged at a desired pitch can be configured.

FIG. 8C is a diagram illustrating a seventh step of manufacturing the semiconductor device 100. In the seventh step, the semiconductor element 2 mounted on the semiconductor device substrate 1 is sealed with a mold resin 37. An epoxy resin or the like can be used as the mold resin.
If it is difficult to fill the space between the semiconductor device substrate 1 and the semiconductor element 2 with a mold resin, a resin such as an underfill is poured into the sealing device to ensure sealing treatment and stress concentration at the joint due to thermal expansion. Can be relaxed.

  FIG. 8D is a diagram illustrating an eighth step of manufacturing the semiconductor device 100. In the eighth step, the conductive substrate 30 constituting the lower surface of the semiconductor device substrate 1 is removed. The conductive substrate 30 is appropriately peeled off by etching or physical pulling. Thereby, the semiconductor device 100 is realized.

  FIG. 9 is an end view of a position corresponding to the CC cut portion (FIG. 7B) of the semiconductor device 100 from which the resist layer 11 has been peeled off. As shown in FIG. 9, the semiconductor device 100 can be configured by physically or chemically peeling and removing the resist layer 11 (see FIG. 8D). Thereby, the height of the standoff structure 240 of the semiconductor device 100 can be adjusted as appropriate.

According to the above-described embodiment, the following operational effects can be obtained.
(1) The substrate 1 for a semiconductor device according to the present embodiment has a semiconductor element 2 mounted thereon, and includes a connection terminal with an external circuit. The terminal of the semiconductor element 2 and the protruding portion 24-2 of the plating element 24 are provided. And a wiring with a plating structure 21 disposed along the surface of the semiconductor device substrate 1. Thereby, in the semiconductor device 100 manufactured using the semiconductor device substrate 1, three-dimensional wiring can be drawn using the plating structure 21, and the plating element 24 that serves as a connection terminal to the outside of the semiconductor device 100 can be penetrated. The part 24-1 can be arranged at a desired position with a fine pitch.

(2) In the semiconductor device substrate 1 of the present embodiment, the semiconductor device substrate 1 includes a plurality of plating elements 24 connected to each other by a plating structure 21. Thereby, the connection process with the external electronic circuit in the semiconductor device 100 manufactured using the board | substrate 1 for semiconductor devices can be made easy and reliable, using the penetration part 24-1 of the plating element 24 suitably.

(3) The substrate 1 for a semiconductor device of this embodiment includes a conductive substrate 30 that can be plated, and a resist layer 11 formed on the conductive substrate 30, and the resist layer 11 has a first opening. 12-1 and a second opening 12-2, passing through the first opening 12-1 and the second opening 12-2, facing the first opening 12-1 of the conductive substrate 30. The part 22-1 to be connected to the part 22-2 facing the second opening 12-2 of the conductive substrate 30 is connected by the plating structure 21. Thereby, the wiring by the plating structure 21 is implement | achieved and the fanout type semiconductor package which can obtain the connection with the semiconductor element 2 via the penetration part 24-2 of a desired position can be comprised.

(4) In the semiconductor device substrate 1 of the present embodiment, the part 22-1 facing the opening 12-1 of the conductive substrate 30 and the part 22-2 facing the opening 12-2 of the conductive substrate 30 are , Each is formed in a recess. Thereby, the semiconductor device 100 manufactured using the semiconductor device substrate 1 has the stand-off structure 240 and can improve the reliability of the connection processing with the printed circuit board or the like.

(5) In the semiconductor device substrate 1 of the present embodiment, the shortest distance d between the first opening 12-1 and the second opening 12-2 is equal to the plating structure 21 of the first opening 12-1. It is shorter than twice the height from the resist layer 11. Thereby, the board | substrate 1 for semiconductor devices can be manufactured efficiently by plating.

(6) In the method for manufacturing the semiconductor device substrate 1 of the present embodiment, the resist layer 11 including the first opening 12-1 and the second opening 12-2 is formed on the conductive substrate 30. The first portion 22-1 facing the first opening 12-1 of the conductive substrate 30 and the second portion 22-2 facing the second opening 12-2 of the conductive substrate 30 are connected by plating. To do. Thereby, fine plated wiring can be realized on the substrate 1 for a semiconductor device.

(7) In the method for manufacturing the semiconductor device substrate 1 according to this embodiment, after the resist layer 11 is formed, the conductive substrate 30 faces the first opening 12-1 and the second opening 12-2, respectively. The surface 22-1 and the region 22-2 are respectively formed in the recesses of the conductive substrate 30 by etching the surface to be etched. Thereby, the standoff structure 240 having a desired height can be efficiently formed in the semiconductor device 100 manufactured using the semiconductor device substrate 1.

(8) The semiconductor device 100 according to the present embodiment includes the through-hole 24-2 in which the semiconductor element 2 is sealed and serves as a connection terminal with an external circuit. The terminal of the semiconductor element 2 and the through-hole 24-2 Are connected by a plating structure 21 wired along the bottom surface of the semiconductor device 100. Thereby, it is possible to configure a fan-out type semiconductor package that can obtain connection with the semiconductor element 2 through the through portion 24-2 at a desired position.

(9) The semiconductor device 100 of the present embodiment includes a plurality of through portions 24-2 connected to each other by the plating structure 21. Accordingly, a desired one of the plurality of through portions 24-2 can be appropriately used for the connection terminal, and can be efficiently manufactured by the method for manufacturing the semiconductor device of the present embodiment.

  The present invention is not limited to the contents of the above embodiment. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Substrate for semiconductor devices, 2 ... Semiconductor element, 11 ... Resist layer, 12, 12-1, 12-2 ... Opening part of resist layer, 21 ... Plating structure, 22, 22-1, 22-2 ... Conductivity A part of the substrate 30 facing the opening 12, 24 ... a plating element, 24-1 ... a through part, 24-2 ... a protrusion, 30 ... a conductive substrate, 100 ... a semiconductor device, 240 ... a stand-off structure.

Claims (12)

A substrate for a semiconductor device on which a semiconductor element is mounted,
The semiconductor device substrate includes a connection terminal with an external circuit,
A semiconductor device substrate comprising a wiring by plating which connects the terminal of the semiconductor element and the connection terminal and is disposed along the surface of the substrate for the semiconductor device. The semiconductor device substrate according to claim 1,
A semiconductor device substrate comprising a plurality of the connection terminals connected to each other by the plating. The substrate for a semiconductor device according to claim 1 or 2,
A conductive substrate that can be plated;
A resist layer formed on the conductive substrate,
The resist layer includes a first opening and a second opening,
A first part that faces the first opening of the conductive substrate through the first opening and the second opening, and a second part that faces the second opening of the conductive substrate Are connected to each other by plating. The substrate for a semiconductor device according to claim 3,
The first part and the second part are semiconductor device substrates formed in concave portions of the conductive substrate, respectively. The substrate for a semiconductor device according to claim 3 or 4,
The shortest distance between the first opening and the second opening is a substrate for a semiconductor device shorter than twice the height of the plating from the resist layer of the first opening. A method for manufacturing a semiconductor device substrate on which a semiconductor element is mounted,
Forming a resist layer having a first opening and a second opening on the conductive substrate;
A method of manufacturing a substrate for a semiconductor device, comprising: connecting a first portion of the conductive substrate facing the first opening and a second portion of the conductive substrate facing the second opening by plating. In the manufacturing method of the board | substrate for semiconductor devices of Claim 6,
After the formation of the resist layer, by etching the surfaces of the conductive substrate that face the first opening and the second opening, respectively, the first part and the second part are respectively A method for manufacturing a substrate for a semiconductor device, which is formed in a recess of a conductive substrate. A semiconductor device in which a semiconductor element is sealed,
The semiconductor device includes a connection terminal with an external circuit,
A semiconductor device in which a terminal of the semiconductor element and the connection terminal are connected by plating wired along at least one surface of the semiconductor device. The semiconductor device according to claim 8,
A semiconductor device comprising a plurality of the connection terminals connected to each other by the plating. A semiconductor device substrate according to any one of claims 1 to 5, or a semiconductor device substrate manufactured by the method for manufacturing a semiconductor device substrate according to claim 6 or 7, wherein Equipped with
A method for manufacturing a semiconductor device, wherein the semiconductor element mounted on the substrate for a semiconductor device is sealed. A semiconductor device substrate according to any one of claims 3 to 5, or a semiconductor device substrate manufactured by the method for manufacturing a semiconductor device substrate according to claim 6 or 7, wherein the semiconductor element is formed on the substrate. Equipped with
Sealing the semiconductor element mounted on the semiconductor device substrate;
A method for manufacturing a semiconductor device, comprising: peeling off the conductive substrate from a sealed semiconductor package. In the manufacturing method of the semiconductor device according to claim 11,
A method for manufacturing a semiconductor device, comprising: removing the resist layer from the sealed semiconductor package.

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