JP2017118320A - Transmitting apparatus and control method of transmitting apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission device which reduces latency in data transfer without reducing yield.SOLUTION: A transmission device comprises: a transmission buffer for holding transmission data; a detection circuit for detecting the presence/absence of a change for each bit in the transmission data; and an output control circuit for controlling output of the transmission data in accordance with detection data in the detection circuit. In the case where bits to be changed detected by the detection circuit are matched with preset bits, the transmission data are transmitted during a period of multiple cycles. In the case where bits to be changed detected by the detection circuit are not matched with preset bits, the transmission data are transmitted during a period of one cycle. Thus, only when transmitting a data pattern in which an error is easily generated, data transfer is performed in multiple cycles, and latency is reduced without reducing yield.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a transmission apparatus and a control method for the transmission apparatus.

  Advances in manufacturing technology have made it possible to realize large-scale integrated circuits with large chip sizes and fine transistor gates. In a large-scale integrated circuit, it is often performed that each functional block is independently mounted and these functional blocks are connected by a bus. Miniaturization in a large-scale integrated circuit brings merit for gate delay, but it has demerits such as increased wiring resistance and proximity capacitance for wiring delay.

  In a large-scale integrated circuit, the number of gates mounted in a chip increases, and the amount of wiring connecting the gates has become enormous. For example, in a long-distance wiring in a large-scale integrated circuit, a yield reduction due to a phenomenon depending on a data pattern that is difficult to predict by STA (static timing analysis) such as the influence of adjacent wiring and the influence of simultaneous switching has occurred. Such yield reduction depending on the data pattern is difficult to avoid by physical implementation.

  In a large-scale integrated circuit, mounting a long distance bus with a low latency and a high yield is an important problem. In order to achieve a high yield, a design with a margin for delay can be considered, but the latency increases. Further, in order to realize low latency, the design is made such that the delay margin is reduced, but in this case, the yield is deteriorated.

  Here, in a large-scale integrated circuit having a long-distance bus, a method of detecting and relieving an error in data transfer via the bus can be considered in order to increase the yield. As this method, there are a method based on retransmission control (for example, refer to Patent Documents 1 and 2) and a method based on error correction using a redundant signal such as a parity code and ECC (Error Correction Code) (for example, refer to Patent Document 3). .

  However, in the method based on the retransmission control, if it is simply performed, even if the data is retransmitted under the same conditions unless the cause of the error is eliminated, the error is not relieved, and the retransmission is repeated, thereby degrading the performance. On the other hand, as disclosed in Patent Document 1, a method for avoiding by changing the transfer path at the time of data retransmission has been proposed, but the circuit scale increases because a plurality of transfer paths are provided. Also, as disclosed in Patent Document 2, a method of relieving by changing the setup factor by temporarily changing the clock cycle has been proposed. However, changing the clock cycle affects a wide range of circuits and affects performance. Becomes larger.

  Also, the error correction method using redundant signals such as ECC increases the wiring density against problems caused by high-density wiring, especially when multi-bit correction is realized. For this reason, the data becomes physically weak, or the data passes through a circuit that performs complicated error correction and error detection, resulting in an increase in latency.

JP 2009-217581 A JP 2004-128963 A JP 2005-354310 A

  In one aspect, an object of the present invention is to provide a transmission apparatus with a low latency in data transfer and a control method thereof without reducing yield.

  One aspect of a transmission apparatus includes a transmission buffer that holds transmission data, a detection circuit that detects whether or not there is a change for each bit in the transmission data, and output control that controls output of transmission data according to detection data in the detection circuit Circuit. The output control circuit transmits the transmission data in a plurality of cycles when the changing bit detected by the detection circuit matches the preset bit, and the changing bit detected by the detection circuit is preset. If the bit does not match, the transmission data is transmitted in one cycle.

  In one aspect of the invention, it is possible to perform data transfer by transmitting in a plurality of cycles only when transmitting a data pattern in which an error is likely to occur according to preset information, without reducing yield. The latency can be reduced.

It is a figure which shows the structural example of the transmitter in 1st Embodiment. It is a figure for demonstrating the data transfer in 1st Embodiment. It is a figure which shows the structural example of the transmitter in 2nd Embodiment. It is a figure for demonstrating the data transfer in 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a block diagram illustrating a configuration example of a transmission device according to the first embodiment. The transmission apparatus according to the first embodiment includes a transmission buffer 110 and a control unit 120 and transmits data input via the latch 130. The latch 130 receives the data DAT1 and the valid signal VLD1 indicating whether or not the data is valid, latches based on a clock signal (not shown), and outputs the data DAT2 and the valid signal VLD2. In the present embodiment, the data DAT1, DAT2, and the data DATO output from the transmission buffer 110 are multi-bit signals that are transferred in parallel, and are assumed to be 64-bit parallel signals as an example below.

  The transmission buffer 110 is, for example, a FIFO (First-In First-Out) buffer, and holds valid data DAT2 in accordance with the valid signal VLD2 output from the latch 130. Further, the transmission buffer 110 holds control information CTS corresponding to the data DAT2 together with the data DAT2. The control unit 120 includes a write pointer (WP) 121, a read pointer (RP) 122, an output control circuit 123, a toggle detection circuit 124, a setting register 125, and a comparison circuit 126.

  The write pointer 121 designates an area in the transmission buffer 110 to which the data DAT2 output from the latch 130 is written. The write pointer 121 updates the write pointer value indicating the write area in the transmission buffer 110 when the valid signal VLD2 indicates that the data DAT2 output from the latch 130 is valid. Data DAT2 is written in the area of the transmission buffer 110 specified by the write pointer value.

  The read pointer 122 designates an area in which data read from the transmission buffer 110 and output is held. The read pointer 122 updates the read pointer value based on the control from the output control circuit 123. Data held in the area of the transmission buffer 110 specified by the read pointer value is output from the transmission device as transmission data DATO.

  The output control circuit 123 controls the output of data held in the transmission buffer 110. If there is a difference between the values indicated by the write pointer 121 and the read pointer 122, the output control circuit 123 determines that there is data to be transmitted to the transmission buffer 110, updates the value of the read pointer 122, and updates the value from the transmission buffer 110. Data DATO is output. Further, the output control circuit 123 refers to the control information CTS held together with the data in the transmission buffer 110 to control the output timing of the valid signal VLDO indicating that the output data DATO is valid, Control the timing for updating values.

  The toggle detection circuit 124 compares the data DAT1 input to the latch 130 and the data DAT2 output from the latch 130 for each bit, and determines whether or not the value is inverted. That is, the toggle detection circuit 124 detects, for each bit, whether or not the data signal DAT2 input to the transmission buffer 110 is inverted before and after.

  The comparison circuit 126 compares the detection result of the toggle detection circuit 124 with the data set in the setting register 125 and outputs a control signal CTS. More specifically, when the comparison circuit 126 detects that the bit specified in the setting register 125 has its value inverted by the toggle detection circuit 124, the control information specifies that the corresponding data is transferred in a plurality of cycles. Output CTS.

  In the setting register 125, data indicating bits that may cause an error in data transfer from the transmission device is set in advance. For a bit that may cause an error in data transfer, for example, a screening test or the like is performed in advance before normal operation of the transmission device, and a data pattern that is likely to cause an error is extracted and set in the setting register 125. The number of data that can be set in the setting register 125 is not limited, and any number of data can be set.

  Next, the operation will be described. The transmission buffer 110 holds the data DAT2 when the valid signal VLD2 output from the latch 130 indicates that the data is valid. At this time, when the bit detected by inversion by the toggle detection circuit 124 matches the bit corresponding to the value set in the setting register 125, the control information CTS indicating that the data DAT2 is likely to cause an error is displayed. Stored in the transmission buffer 110.

  When the output control circuit 123 outputs the data held in the transmission buffer 110 as output data DATO, the output control circuit 123 refers to the control information CTS corresponding to the output data. When the control information CTS indicates that the error is likely to occur, the output control circuit 123 controls to output the data for a plurality of cycles (a period of two or more cycles) when outputting the output data DATO, A period for outputting a valid signal VLDO indicating that data is valid is controlled. On the other hand, when the control information CTS indicates that the data is not likely to cause an error, when the output control circuit 123 outputs the output data DATO, the valid signal VLDO indicating that the data is valid is output only for the period of one cycle. Then output the data.

  For example, it is assumed that data as illustrated in FIG. 2A is input to the transmission buffer 110 as data to be transmitted. At this time, the data shown in FIG. 2B is set in the setting register 125. That is, when the least significant bit is the 0th bit and the 26th bit (202 shown) from the lower side is inverted, it is extracted as an error-prone bit.

  In this case, in the data shown in FIG. 2A, the change portion of the data 201 is a portion where an error is likely to occur. This change is detected by the toggle detection circuit 124 and set in the setting register 125 by the comparison circuit 126. It is determined that the value matches. Based on the determination result, when data is held in the transmission buffer 110, control information CTS indicating that an error is likely to occur is held together with the data.

  When outputting this data held in the transmission buffer 110, the output control circuit 123 outputs the data over a plurality of cycles (a period of two or more cycles) as shown in FIG. 2C based on the control information CTS. . In addition, the output control circuit 123 controls the output timing of the valid signal VLDO so that data can be properly received on the receiving side. In the example shown in FIG. 2C, the valid signal VLDO is changed to indicate that the data is valid one cycle after the output data is changed. When the control signal CTS indicates that the data is not likely to cause an error, the output control circuit 123 outputs a valid signal VLDO indicating that the data is valid when outputting the data for a period of one cycle. .

  Thus, when transferring a data pattern in which an error is likely to occur, by transferring the data pattern in a plurality of cycles (multi-cycle transfer), it is possible to transfer data while suppressing the occurrence of the error. Further, when the data pattern is not likely to cause an error, it is possible to suppress an increase in latency more than necessary by performing transfer in one cycle. As a result, data transfer can be performed by transmitting in a plurality of cycles only when a data pattern that is likely to cause an error is transmitted, and a decrease in yield can be suppressed and an increase in latency can be suppressed.

  In the above description, when a data pattern that is likely to cause an error is transmitted, data to be transmitted later is transferred in a plurality of cycles. However, as shown in FIG. You may make it transmit in several cycles. In this case, it is possible to prevent not only errors due to delay but also errors due to racing. Also, for data patterns before and after an error is likely to occur, for example, each data is output in 3 cycles, and the data is shown to be valid in the second cycle. The occurrence of errors due to can be suppressed.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram illustrating a configuration example of a transmission apparatus according to the second embodiment. The transmission apparatus according to the second embodiment includes a transmission buffer 310, a control unit 320, and an information generation circuit 330, and transmits data and the like to the reception side via latches 351 and 352. The device on the receiving side has an error detection circuit 340 that detects an error in data based on an error detection signal such as a parity code or ECC. In this embodiment, the data DATI and the data DATO are multi-bit signals that are transferred in parallel.

  The transmission buffer 310 is, for example, a FIFO buffer, receives the data DATI, receives a valid signal VLDI indicating whether the data is valid, and holds the data DATI according to the valid signal VLDI. In addition, the transmission buffer 110 holds control information CDI having an error detection signal and a sequence number corresponding to the data DATI generated by the information generation circuit 330 together with the data DATI.

  The control unit 320 includes a write pointer (WP) 321, a read pointer (RP) 322, and an output control circuit 323. The write pointer 321 designates an area in the transmission buffer 310 to which input data DATI is written. The write pointer 321 updates the write pointer value indicating the write area in the transmission buffer 310 when the valid signal VLDI indicates that the data DATI is valid. The input data DATI is written in the area of the transmission buffer 310 specified by the write pointer value.

  The read pointer 322 designates an area where data to be read out and output from the transmission buffer 310 is held. The read pointer 322 updates the read pointer value based on control from the output control circuit 323. Data and control information (error detection signal and sequence number) CDI held in the area of the transmission buffer 310 specified by the read pointer value are output from the transmission device as transmission data DATO and control information CDO.

  The output control circuit 323 controls the output of data held in the transmission buffer 310. When there is a difference between the values indicated by the write pointer 321 and the read pointer 322, the output control circuit 323 determines that there is data to be transmitted to the transmission buffer 310, updates the value of the read pointer 322, and updates the value from the transmission buffer 310. The output timing of the valid signal VLDO indicating that the data is valid is controlled while outputting data and the like. When the output control circuit 323 is notified by the response signal RSI from the receiving side that an error has been detected in the transferred data, the output control circuit 323 retransmits the data after the sequence number in which the error was detected. At this time, the output control circuit 323 performs control so that the data of the sequence number in which the error is detected is output in a plurality of cycles (a period of two cycles or more).

  The information generation circuit 330 generates an error detection signal for the data DATI input to the transmission buffer 320, generates a sequence number related to the data DATI, and outputs it as control information CDI. The error detection circuit 340 detects the presence or absence of an error in the received data based on the data and control information from the transmission buffer 310 received via the latches 351 and 352 and outputs the detection result and the sequence number to the transmission device. To do.

  In this embodiment, as shown in FIG. 4A, in normal data transfer, when one data is transmitted in units of one cycle and an error is detected on the receiving side, a plurality of cycles (for example, the illustrated example) One data is transmitted in two cycles). For example, as shown in FIG. 4B, when an error is detected in the data (DAT) D5 of the sequence number (SQN) 1, the output control circuit 323 reads based on the response signal RSI from the receiving side. The pointer value of the pointer 322 is returned to the pointer value corresponding to the sequence number 1. Then, data after sequence number 1 is retransmitted, and data D4 to D7 corresponding to sequence number 1 in which an error is detected are transmitted in a plurality of cycles.

  In this way, when an error is detected on the receiving side, control is performed so that the data is transferred in multiple cycles (multi-cycle transfer), thereby suppressing a decrease in yield and an increase in latency. Can do.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

110, 310 Transmission buffer 120, 320 Control unit 121, 321 Write pointer 122, 322 Read pointer 123, 323 Output control circuit 124 Toggle detection circuit 125 Setting register 126 Comparison circuit 130, 351, 352 Latch 330 Information generation circuit 340 Error detection circuit

Claims (6)

A transmission buffer that holds transmission data; and
A detection circuit for detecting the presence or absence of a change for each bit in the transmission data;
If the changing bit detected by the detection circuit matches a preset bit, the transmission data is transmitted in a plurality of cycles, and the changing bit detected by the detection circuit is a preset bit. And an output control circuit that transmits the transmission data in one cycle period when the transmission data does not match. A register for setting information indicating a bit to be determined;
The comparison circuit according to claim 1, further comprising: a comparison circuit that determines whether or not the changing bit detected by the detection circuit is a preset bit based on information set in the register. Transmitter device.   The output control circuit transmits transmission data before the transmission data in a period of a plurality of cycles when a changing bit detected by the detection circuit matches a preset bit. Item 3. The transmitter according to Item 1 or 2. An information generation circuit for generating control information including an error detection signal and a sequence number related to transmission data;
A transmission buffer for holding the transmission data and the control information;
When a signal indicating that an error in the transmitted transmission data has been detected is received, the transmission data after the sequence number in which the error has been detected is transmitted again, and the data of the sequence number in which the error has been detected An output control circuit for transmitting in a cycle period. A detection step of detecting the presence or absence of a change for each bit in the transmission data held in the transmission buffer;
If the changing bit detected in the detection step matches a preset bit, the transmission data is transmitted in a plurality of cycles, and the changing bit detected in the detection step is a preset bit. And a transmission control step of transmitting the transmission data in one cycle period when the transmission data does not match. An information generating step for generating control information including an error detection signal and a sequence number related to transmission data;
A holding step of holding the transmission data and the control information in a transmission buffer;
When a signal indicating that an error in the transmitted transmission data has been detected is received, the transmission data after the sequence number in which the error has been detected is transmitted again, and the data of the sequence number in which the error has been detected And an output control step of transmitting in a cycle period.

Images