JP2017112161A - Semiconductor device - Google Patents

Abstract

A trench gate type semiconductor device that reduces on-resistance while relaxing electric field strength at the bottom of a trench.
A P-type protective diffusion layer formed in an N − -type drift layer 2 below a trench 6A and electrically connected to a source electrode 11 is provided. The protective diffusion layer includes a plurality of protective diffusion layers 9A and a plurality of protective diffusion layers 9B1 having a thickness smaller than that of the protective diffusion layer 9A. The protective diffusion layers 9A and the protective diffusion layers 9B1 are in contact with each other and are alternately arranged along the length direction of the trench 6A. At least one of the protective diffusion layers is electrically connected to the source electrode 11.
[Selection] Figure 1

Description

  The present invention relates to electric field concentration relaxation and on-resistance reduction at the bottom of a trench gate of a semiconductor device.

  Electric appliances such as air conditioners or refrigerators, railway inverters, motor control devices for industrial robots, and the like are becoming more power-saving and miniaturized. Therefore, IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductors) are used as switching elements. Insulated gate type semiconductor devices such as Field Effect Transistor) are widely used.

  In recent years, wide band gap semiconductors such as silicon carbide (SiC) have attracted attention as semiconductor materials that can achieve higher breakdown voltage and lower loss, and are being put to practical use in the above products.

  SiC has a dielectric breakdown electric field about an order of magnitude higher than that of silicon, so that a high electric field can be maintained, but a high electric field is similarly applied to an insulating oxide film present in the periphery. Therefore, there is a problem that the insulating oxide film first breaks down at a lower voltage than SiC causes dielectric breakdown, and the element is broken. This is a problem that may also occur with wide band gap semiconductors other than SiC.

  In particular, in a trench gate type (trench type) MOSFET in which a gate electrode is embedded in a semiconductor layer, it is possible to improve channel width density by miniaturizing a cell and to lower on-resistance (Ron) by reducing JFET resistance. However, due to the structure, the electric field tends to concentrate on the bottom of the trench, and the oxide film electric field strength (Eox) increases.

  As a method for reducing the electric field strength of the oxide film, it is conceivable to form a protective diffusion layer at the bottom of the trench. This protective diffusion layer functions to promote depletion of the N-type drift layer when the MOSFET is turned off and to reduce electric field concentration on the trench bottom of the gate electrode. However, since the JFET resistance is increased by the depletion layer extending from the protective diffusion layer, the decrease in the on-resistance and the decrease in the oxide film electric field strength have a trade-off relationship.

  With respect to such a problem, Patent Documents 1 and 2 propose that a P-type protective diffusion layer is selectively provided at the bottom of a trench in an N-type drift layer in a trench gate type MOSFET. According to this, the depletion layer extends from the protective diffusion layer when the gate is in the off state, and protects the insulating film at the bottom of the trench. On the other hand, when the gate is in the on state, the portion where the protective diffusion layer is not formed has a small extension of the depletion layer compared to the portion where the protective diffusion layer is formed. Thus, by selectively forming the protective diffusion layer at the bottom of the trench, the trade-off between the on-resistance and the oxide film electric field strength is improved as compared with the case where the protective diffusion is uniformly formed.

  In Patent Documents 1 and 2, the protective diffusion layer is electrically connected to the base layer, and the potential of the protective diffusion layer is fixed to the source electrode, thereby further reducing the electric field concentration at the bottom of the trench. .

JP 2011-253837 A Special table 2008-516451 gazette

  In Patent Documents 1 and 2, a p-type protective connection layer that connects the p-type base layer and the p-type protective diffusion layer to the trench sidewall in order to fix the potential of the p-type protective diffusion layer selectively formed at the bottom of the trench to the source electrode. Many are formed. Since the p-type protective connection layer narrows the current path during the ON operation, it is necessary to form the p-type protective connection layer to the minimum in order to reduce the ON resistance. However, in Patent Documents 1 and 2, since the p-type protective connection layer is provided for all the p-type protective diffusion layers, the range in which a low-resistance current path can be formed is narrow, and the on-resistance cannot be sufficiently reduced. There was a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to reduce on-resistance while reducing the electric field strength at the bottom of a trench in a trench gate type semiconductor device.

  The first semiconductor device of the present invention is formed partially on the first conductivity type drift layer, the second conductivity type well region partially formed on the surface layer of the drift layer, and on the surface layer of the well region. A first conductivity type impurity region; a first electrode formed through an insulating film in a first trench extending from the surface layer of the impurity region through the well region and into the drift layer; and the well region and the impurity region; A protective diffusion layer comprising: a second electrode that is electrically connected; and a protective diffusion layer of a second conductivity type that is formed in the drift layer below the bottom of the first trench and is electrically connected to the second electrode. Comprises a first protective diffusion layer and a second protective diffusion layer having a thickness smaller than that of the first protective diffusion layer, the first protective diffusion layer and the second protective diffusion layer being in contact with each other and in the length direction of the trench. It is characterized by being alternately arranged along.

  The second semiconductor device of the present invention is formed in the first conductivity type drift layer, the second conductivity type well region partially formed in the surface layer of the drift layer, and partially formed in the surface layer of the well region. A first conductivity type impurity region; a first electrode formed through an insulating film in a first trench extending from a surface layer of the impurity region through the well region and into the drift layer; and the well region and the impurity region; A protective diffusion layer comprising: a second electrode electrically connected; and a protective diffusion layer of a second conductivity type formed in the drift layer below the bottom of the first trench and electrically connected to the second electrode. Comprises a first protective diffusion layer and a second protective diffusion layer having an impurity concentration lower than that of the first protective diffusion layer, the first protective diffusion layer and the second protective diffusion layer being in contact with each other and of the first trench. It is characterized by being alternately arranged along the length direction. .

  The third semiconductor device of the present invention is formed in the first conductivity type drift layer, the second conductivity type well region partially formed in the surface layer of the drift layer, and partially formed in the surface layer of the well region. A first conductivity type impurity region; a first electrode formed through an insulating film in a first trench extending from a surface layer of the impurity region through the well region and into the drift layer; and the well region and the impurity region; A protective diffusion layer comprising: a second electrode electrically connected; and a protective diffusion layer of a second conductivity type formed in the drift layer below the bottom of the first trench and electrically connected to the second electrode. Comprises a first protective diffusion layer and a second protective diffusion layer, and the width of the depletion layer extending from the first protective diffusion layer to the drift layer is larger than the width of the depletion layer extending from the second protective diffusion layer to the drift layer. It is large.

  In the first semiconductor device of the present invention, the protective diffusion layer includes a first protective diffusion layer and a second protective diffusion layer having a thickness smaller than that of the first protective diffusion layer, and the first protective diffusion layer and the second protective diffusion layer. The layers are in contact with each other and are alternately arranged along the length of the trench, and the protective diffusion layer is electrically connected to the second electrode. Therefore, the protective diffusion layer is electrically connected to the second electrode in at least some place of the first protective diffusion layer and the second protective diffusion layer that are alternately arranged along the length direction of the trench. In this case, the entirety is electrically connected to the second electrode. For this reason, the configuration for electrically connecting the second electrode and the protective diffusion layer can be reduced. Further, since the thickness of the second protective diffusion layer is small, the width of the depletion layer extending in the drift layer is smaller than that of the first protective diffusion layer, and the increase in on-resistance due to the second protective diffusion layer is reduced. Therefore, an increase in on-resistance due to the provision of the protective diffusion layer can be suppressed, and both reduction in on-resistance and relaxation of the oxide film electric field strength can be achieved.

  In the second semiconductor device of the present invention, the protective diffusion layer includes a first protective diffusion layer and a second protective diffusion layer having an impurity concentration lower than that of the first protective diffusion layer, and the first protective diffusion layer and the second protective diffusion layer. The diffusion layers are in contact with each other and are alternately arranged along the length direction of the first trench, and the protective diffusion layer is electrically connected to the second electrode. Therefore, the protective diffusion layer is electrically connected to the second electrode in at least some place of the first protective diffusion layer and the second protective diffusion layer that are alternately arranged along the length direction of the trench. In this case, the entirety is electrically connected to the second electrode. For this reason, the configuration for electrically connecting the second electrode and the protective diffusion layer can be reduced. Further, since the impurity concentration of the second protective diffusion layer is small, the width of the depletion layer extending in the drift layer is smaller than that of the first protective diffusion layer, and the increase in on-resistance due to the second protective diffusion layer is reduced. Therefore, an increase in on-resistance due to the provision of the protective diffusion layer can be suppressed, and both reduction in on-resistance and relaxation of the oxide film electric field strength can be achieved.

  In the second semiconductor device of the present invention, the protective diffusion layer includes a first protective diffusion layer and a second protective diffusion layer, the first protective diffusion layer and the second protective diffusion layer are in contact with each other, and the first trench. The widths of the depletion layers alternately arranged along the length direction and extending from the first protective diffusion layer to the drift layer are larger than the widths of the depletion layers extending from the second protective diffusion layer to the drift layer. Therefore, the protective diffusion layer is electrically connected to the second electrode in at least some place of the first protective diffusion layer and the second protective diffusion layer that are alternately arranged along the length direction of the trench. In this case, the entirety is electrically connected to the second electrode. For this reason, the configuration for electrically connecting the second electrode and the protective diffusion layer can be reduced. Further, since the width of the depletion layer extending from the first protective diffusion layer to the drift layer is larger than the width of the depletion layer extending from the second protective diffusion layer to the drift layer, an increase in on-resistance due to the second protective diffusion layer is reduced. . Therefore, an increase in on-resistance due to the provision of the protective diffusion layer can be suppressed, and both reduction in on-resistance and relaxation of the oxide film electric field strength can be achieved.

1 is a perspective view of a semiconductor device according to a first embodiment. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. 1 is a plan view of a semiconductor device according to a first embodiment. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a plan view and a cross-sectional view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a plan view and a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 6 is a plan view and a cross-sectional view of a semiconductor device according to a third embodiment.

  In this specification, the first conductivity type is described as N-type, and the second conductivity type is described as P-type. However, the opposite conductivity type may be used.

<A. Embodiment 1>
<A-1. Configuration>
In the first embodiment, a trench gate type SiC-MOSFET will be described as an example of the semiconductor device of the present invention. FIG. 1 is a perspective view of the SiC-MOSFET 101 according to the first embodiment, and FIG. 2 is a cross-sectional view of the SiC-MOSFET 101. FIG. 2A is a cross-sectional view including the protective diffusion layer 9A along the line AA ′ in FIG. FIG. 2B is a cross-sectional view including the protective diffusion layer 9B1 along the line BB ′ in FIG. FIG. 2C is a cross-sectional view including the protective diffusion layer 9A and the protective connection layer 9S along the line CC ′ in FIG. FIG. 2D is a cross-sectional view including the protective diffusion layers 9A and 9B1 along the line DD ′ in FIG. FIG. 3 is a plan view taken along the line EE ′ of FIG.

  The SiC-MOSFET 101 includes an N + type substrate 1, an N− type drift layer 2, a P type base layer 3, an N type source layer 4, a P + type contact layer 5, a gate insulating film 7, a gate electrode 8, and protective diffusion layers 9A and 9B1. , A protective connection layer 9S, an interlayer insulating film 10, a source electrode 11, and a drain electrode 12.

  A silicon carbide (SiC) substrate is used for the N + type substrate 1. An N− type drift layer 2 having a lower impurity concentration than that of the N + type substrate 1 is formed on the N + type substrate 1, and a P type base layer 3 (well region) is formed on the surface layer of the N− type drift layer 2. An N + type source layer 4 (impurity region) and a P + type contact layer 5 are partially formed on the surface layer of the base layer 3. In this specification, the term “surface layer” is used to mean the surface layer on the upper surface of the object.

  Further, a trench 6A (first trench) extending from the upper surface of the N + type source layer 4 through the P type base layer 3 into the N− type drift layer 2 is formed, and a gate insulating film 7 is formed on the inner wall of the trench 6A. Then, the gate electrode 8 (first electrode) is formed on the gate insulating film 7. Further, a source electrode 11 (second electrode) electrically connected to the P-type base layer 3, the N + -type source layer 4 and the P + -type contact layer 5 is formed, and interlayer insulation is provided between the source electrode 11 and the gate electrode 8. A film 10 is formed, and a drain electrode 12 is formed on the lower surface of the N + type substrate 1.

  In the region of the N − type drift layer 2 in contact with the bottom of the trench 6A, a P-type protective diffusion layer 9A (first protective diffusion layer) is formed at a predetermined interval along the length direction of the trench 6A. A P-type protective diffusion layer 9B1 (second protective diffusion layer) having a thickness smaller than that of the protective diffusion layer 9A is formed between the diffusion layers 9A. Since the protective diffusion layer 9B1 is provided in contact with the protective diffusion layer 9A so as to fill the gap between the protective diffusion layers 9A, the plurality of discrete protective diffusion layers 9A are electrically connected by the protective diffusion layer 9B1. .

  Also, a P-type protective connection layer 9S is formed on the N − -type drift layer 2 on the side wall of the trench 6A (FIG. 2C). Since the protective connection layer 9S is formed in contact with both the protective diffusion layer 9A and the P-type base layer 3, the protective diffusion layer 9A is electrically connected to the P-type base layer 3 through the protective connection layer 9S. In FIG. 2C, the protective connection layer 9S is formed in contact with the protective diffusion layer 9A, but is formed in contact with the protective diffusion layer 9B1, and the protective diffusion layer 9B1 and the P-type base layer 3 are electrically connected. You may connect to. Since the protective diffusion layer 9A and the protective diffusion layer 9B1 are electrically connected as described above, the protective connection layer 9S is in contact with at least one of the protective diffusion layer 9A and the protective diffusion layer 9B1 and the P-type base layer 3. If formed, all of the protective diffusion layers 9A and 9B1 and the P-type base layer 3 can be electrically connected. Thereby, since the potentials of the protective diffusion layer 9A and the protective diffusion layer 9B1 are fixed to the potential of the source electrode 11, the electric field strength of the gate insulating film 7 at the bottom of the trench 6A can be relaxed.

  That is, in the SiC-MOSFET 101, at least one of the protective diffusion layer 9A and the protective diffusion layer 9B1 is electrically connected to the source electrode 11. More specifically, the protective connection layer 9S provided in the N − type drift layer 2 in contact with the side surface of the trench 6A is connected to at least one of the protective diffusion layer 9A and the protective diffusion layer 9B1 and the P-type base layer 3. Thus, the two are electrically connected.

<A-2. Action>
Next, the operation of the SiC-MOSFET 101 will be described.

  As shown in FIG. 2A, in the cross section including the protective diffusion layer 9A, the depletion layer expands from the protective diffusion layer 9A when off, and the gate insulating film 7 is protected from dielectric breakdown.

  As shown in FIG. 2B, a current path having a lower resistance is formed in the cross section including the protective diffusion layer 9B1 than in the cross section including the protective diffusion layer 9A. This is because the protective diffusion layer 9B1 is smaller in thickness than the protective diffusion layer 9A, and therefore, when the impurity concentration of the protective diffusion layer 9B1 and the protective diffusion layer 9A is the same, the pn interface leads to the N− type drift layer 2 side. This is because the extension of the depletion layer is the same, but the width of the depletion layer from the bottom and side walls of the trench is shorter in the protective diffusion layer 9B1 due to the difference in formation depth. In order to achieve this effect, it is desirable that the thickness of the protective diffusion layer 9B1 is not more than half that of the protective diffusion layer 9A.

  As shown in FIG. 2C, in the cross section including the protective connection layer 9S, the protective diffusion layer 9A is connected to the P-type base layer 3 by the protective connection layer 9S. Therefore, the protective diffusion layer 9A and the protective diffusion layer 9B1 are Fixed to the source potential. Therefore, the electric field concentration at the bottom of the trench 6A is alleviated.

  As shown in FIG. 2D, in the cross section including the protective diffusion layer 9A and the protective diffusion layer 9B, the depletion layer expands from the protective diffusion layer 9A and the depletion layer also expands from the protective diffusion layer 9B when off. . Although the width of the depletion layer expanding from the protective diffusion layer 9B is smaller than that from the protective diffusion layer 9A, a sufficient dielectric breakdown electric field can be secured by overlapping each depletion layer.

  As shown in FIG. 3, the plurality of protective diffusion layers 9A formed discretely are electrically connected by a protective diffusion layer 9B. Further, the protective diffusion layers 9A and 9B are connected to the source electrode through the protective connection layer 9S partially formed on the side wall of the trench 6A. Therefore, the formation of the protective connection layer 9S for fixing the protective diffusion layers 9A and 9B to the source potential can be minimized, and a large current path can be secured. For example, in FIG. 3, since the protective connection layer 9S is formed for one of the three protective diffusion layers 9A, the protective connection layer 9S is 1/9 compared to the case where the protective connection layers 9S are provided for all the protective diffusion layers 9A. The protective connection layer 9S can be reduced to about 3, and the on-resistance can be reduced.

<A-3. Manufacturing process>
A method for manufacturing SiC-MOSFET 101 will be described with reference to FIGS. 4 (a), 4 (b), and 4 (c) are cross-sectional views in the process of manufacturing the cross section shown in FIGS. The same applies to FIGS. 5, 6, and 7.

First, an N + type substrate 1 is prepared, and an N− type drift layer 2 is epitaxially grown thereon. The impurity concentration of the N − type drift layer 2 is 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, and the thickness is 5 μm or more and 50 μm or less.

  Next, a P-type base layer 3 and an N + type source layer 4 are formed by ion-implanting a predetermined dopant into the surface layer of the N − type drift layer 2. Here, the P-type base layer 3 is formed by ion implantation of aluminum (Al) which is a P-type impurity. The depth of ion implantation of Al is not less than the thickness of the N − -type drift layer 2 and is about 0.5 μm or more and 3 μm or less. The impurity concentration of Al to be implanted is higher than the N-type impurity concentration of the N − -type drift layer 2. At this time, a region deeper than the Al implantation depth remains as the N − -type drift layer 2. Note that the P-type base layer 3 may be formed by epitaxial growth. Also in this case, the impurity concentration and thickness of the P-type base layer 3 are equivalent to those formed by ion implantation.

The N + type source layer 4 is formed by partially implanting nitrogen (N), which is an N type impurity, into the surface of the P type base layer 3. Thereby, when the gate electrode 8 is formed, the N + type source layer 4 is disposed on both sides thereof. The ion implantation depth of N is made shallower than the thickness of the P-type base layer 3. The impurity concentration of N to be implanted is higher than the P-type impurity concentration of the P-type base layer 3 and is in the range of 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ .

The P + type contact layer 5 is formed by partially ion-implanting aluminum (Al), which is a P type impurity, into the surface of the P type base layer 3. The ion implantation depth of aluminum is made shallower than the thickness of the P-type base layer 3. The impurity concentration of aluminum to be implanted is higher than the P-type impurity concentration of the P-type base layer 3 and is in the range of 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ .

  Subsequently, a silicon oxide film 13 is deposited on the surface of the N − type drift layer 2 to a thickness of about 1 μm to 2 μm, and an etching mask made of a resist material is formed thereon. This etching mask is formed in a pattern in which the formation region of the trench 6A is opened by photolithography. Then, the silicon oxide film 13 is patterned by a reactive ion etching (RIE: REACTION ION ETCHING) process using the etching mask as a mask. That is, the etching mask pattern is transferred to the silicon oxide film 13. The patterned silicon oxide film 13 becomes an etching mask for the next step.

  A trench 6A penetrating the N + type source layer 4 and the P type base layer 3 is formed in the N− type drift layer 2 by RIE using the patterned silicon oxide film 13 as a mask (FIG. 4). The depth of the trench 6A is not less than the depth of the P-type base layer 3, and is not less than 0.5 μm and not more than 3 μm.

  Thereafter, an implantation mask 14A having a pattern opened to the trench 6A where the protective diffusion layer 9A is to be formed is formed at the bottom of the trench 6A. Then, a P-type protective diffusion layer 9A is formed at the bottom of the trench 6A by ion implantation using the implantation mask 14A as a mask (FIG. 5). Here, Al is used as the P-type impurity. Instead of the implantation mask 14A, a patterned silicon oxide film 13 used as an etching mask when forming the trench 6A may be used. Thereby, simplification of a manufacturing process and cost reduction can be aimed at.

  Thereafter, the implantation mask 14A is removed, and an implantation mask 14B having a pattern opened to the trench 6A where the protective diffusion layer 9B1 is to be formed at the bottom of the trench 6A is formed. Then, a P-type protective diffusion layer 9B1 is formed at the bottom of the trench 6A by ion implantation using the implantation mask 14B as a mask (FIG. 6). The opening pattern of the implantation mask 14B may be formed in a pattern corresponding to the layout in which the protective diffusion layers 9A are electrically connected by the protective diffusion layer 9B1, and is not limited to the selectively opened pattern as described above. . For example, it may be a simple stripe pattern having an opening in the trench 6A. Thereby, the problem of the mask alignment position accuracy with respect to the length direction of the trench 6A can be avoided.

  The protective diffusion layer 9B1 may be formed simultaneously with the formation of the protective diffusion layer 9A using the silicon oxide film 13 or the implantation mask 14A. In this case, it is necessary to adjust the thickness, etching conditions, and pattern of the silicon oxide film 13 or the implantation mask 14A so that the protective diffusion layer 9B1 can be formed over the silicon oxide film 13 or the implantation mask 14A. Thereby, the number of masks can be reduced and the manufacturing cost can be reduced.

  Thereafter, the implantation mask 14B is removed, and an implantation mask 14C having a pattern opened to the trench 6A where the protective connection layer 9S is to be formed on the side surface of the trench 6A is formed. Then, a P-type protective connection layer 9S is formed on the side wall of the trench 6A by oblique ion implantation (FIG. 7).

  The protective diffusion layer 9A, the protective diffusion layer 9B1, and the protective connection layer 9S are ion-implanted with high energy from the surface of the N − type drift layer 2 to the depth corresponding to the bottom of the trench 6A before the trench 6A is formed. May be formed. This eliminates the need for high-precision patterning conditions for opening a mask with respect to the trench 6A, so that the conditions for patterning accuracy of photolithography are relaxed.

  Next, after removing the implantation mask 14C, annealing for activating the N and Al ions implanted in the steps so far is performed using a heat treatment apparatus. This annealing is performed in an inert gas atmosphere such as argon (Ar) gas, and the temperature is set to 1300 ° C. to 1900 ° C. and the time is set to 30 seconds to 1 hour.

  Then, after a silicon oxide film is formed on the entire surface of the N − type drift layer 2 including the inside of the trench 6A, polysilicon is deposited by a low pressure CVD method and patterned or etched back to thereby provide gate insulation in the trench 6A. A film 7 and a gate electrode 8 are formed (FIG. 8). The silicon oxide film to be the gate insulating film 7 may be formed by thermally oxidizing the surface of the N − type drift layer 2 or may be formed by being deposited on the N − type drift layer 2.

  Subsequently, after the interlayer insulating film 10 is formed on the entire surface of the N − type drift layer 2 by low pressure CVD, patterning is performed leaving a portion covering the gate electrode 8. Further, the source electrode 11 is formed by depositing an electrode material such as an Al alloy on the entire surface of the N − type drift layer 2. Finally, by depositing an electrode material such as an Al alloy on the lower surface of the N + type substrate 1 to form the drain electrode 12, the SiC-MOSFET 101 having the configuration shown in FIG. 1 is obtained.

<A-4. Modification>
The arrangement interval of the protective diffusion layers 9A in the longitudinal direction of the trench 6A, in other words, the width of the protective diffusion layer 9B is not particularly limited. In FIG. 2D, the widths of the protective diffusion layer 9A and the protective diffusion layer 9B1 (the left-right direction in FIG. 2D) are the same, but the width of the protective diffusion layer 9B is protected and diffused as shown in FIG. It may be larger than the layer 9A or may be smaller.

  In FIGS. 1 and 2, the protective diffusion layer 9A and the protective diffusion layer 9B are formed only immediately below the trench 6A. However, in order to protect the corner at the bottom of the trench 6A where the electric field strength is strongest, The protective diffusion layer 9B may be formed to cover not only the trench 6A but also the bottom corner (FIG. 10). Although only the protective diffusion layer 9A is shown in FIG. 10, the same applies to the protective diffusion layer 9B.

  The protective connection layer 9S is formed not on the side surface of the trench 6A but on the entire side in the longitudinal direction, rather than the entire length. If it is partially formed, the formation location of the protective connection layer 9S is not particularly limited. For example, in FIG. 3, the protective connection layer 9S is formed on the side surfaces on both sides of the trench 6A at a ratio of one for the three protective diffusion layers 9A, but may be formed only on one side surface of the trench 6A (see FIG. 3). 11). Alternatively, the protective connection layer 9S may be formed on the left side surface of the trench 6A at a certain location, and may be formed on the right side surface of the trench 6A at another location (FIG. 12). As shown in FIGS. 11 and 12, by reducing the formation area of the protective connection layer 9S, the on-resistance can be reduced as compared with the case where the protective connection layer 9S is formed on both side surfaces of the trench 6A. Further, the arrangement interval of the protective connection layers 9S may be changed, for example, by forming the protective connection layers 9S at a ratio of one for each of the two protective diffusion layers 9A (FIG. 13). When the arrangement interval of the protective connection layer 9S is shortened, the formation area increases. However, since the area occupied by the depletion layer extending from the protective connection layer 9S increases, the electric field strength at the bottom of the trench 6A can be further relaxed.

  Further, the protective connection layer 9S is not provided only around the side surface of the trench 6A, but extends in the normal direction from the side surface of the trench 6A and is provided between the adjacent trenches 6A, and below the adjacent trenches 6A. The protective diffusion layers 9A and 9B1 provided on the substrate may be connected (FIG. 14). In this case, since the area occupied by the depletion layer extending from the protective connection layer 9S is increased as compared with the case where the protective connection layer 9S is provided only around the side surface of the trench 6A, the electric field strength at the bottom of the trench 6A is further relaxed. I can do it.

  FIG. 3 shows a state in which the protective diffusion layers 9A and the protective diffusion layers 9B1 are alternately arranged at the bottom of all the plurality of trenches 6A provided in a stripe shape. However, such a configuration in which the protective diffusion layers 9A and the protective diffusion layers 9B1 are alternately arranged is not necessarily provided for all of the plurality of trenches 6A. For example, as shown in FIG. 15, only a protective diffusion layer 9 </ b> A may be provided below a part of the trench 6 </ b> A. According to such a configuration, since the formation area of the protective diffusion layer 9A is increased as compared with the configuration shown in FIG. 3, the depletion layer is easy to spread, and the electric field strength at the bottom of the trench 6A can be further relaxed. Or about some trenches 6A, only protective diffusion layer 9B1 may be provided in the downward direction. In this case, since the formation area of the protective diffusion layer 9B1 increases as compared with the configuration shown in FIG. 3, the depletion layer spreads and the current path increases, so that the on-resistance can be further reduced.

  Further, when the protective diffusion layers 9A and the protective diffusion layers 9B1 are alternately arranged at the bottom of both of the two adjacent trenches 6A, the arrangement pitch may be shifted between the adjacent trenches 6A. FIG. 16 is a configuration diagram of an SiC-MOSFET 101A according to such a modification. FIG. 16A is a plan view of the N− type drift layer 2 as viewed from the N + type substrate 1 side, and FIG. 16B is a cross-sectional view taken along the line AA ′ of FIG. The AA ′ cross section is a cross section in the direction normal to the side surface of the trench 6A, in other words, the direction perpendicular to the length direction of the trench 6A.

  As shown in FIG. 16A, in the SiC-MOSFET 101A, the protective diffusion layers 9A and the protective diffusion layers 9B1 are alternately arranged along the length direction at the bottoms of the plurality of trenches 6A having the same length direction. Is done. As shown in FIG. 16B, a protective diffusion layer 9B1 is formed on the bottom surface of the trench 6A adjacent to the trench 6A on which the protective diffusion layer 9A is formed on the bottom surface, and further on the bottom surface of the adjacent trench 6A. A protective diffusion layer 9A is formed. As described above, the protective diffusion layers 9A and the protective diffusion layers 9B1 are alternately formed in the AA ′ cross section. This means that when the width of the protective diffusion layer 9A and the width of the protective diffusion layer 9B1 is one pitch, the arrangement of the protective diffusion layers 9A and 9B1 is shifted by a half pitch between the adjacent trenches 6A. I can say that. However, the width for shifting the pitch is not limited to the half pitch. When the protective diffusion layers 9A and 9B1 are arranged in this manner, the depletion layer spreads from the protective diffusion layer 9A where the depletion layer easily spreads to the protective diffusion layer 9B1 where the bottom of the adjacent trench 6A hardly spreads in the off state. The electric field strength at the bottom can be further relaxed.

  In the above description, the plurality of trenches 6A have the same length direction and are arranged in stripes. However, the arrangement shape of the trench 6A is not limited to this. For example, as shown in FIG. 17, the trenches 6A may be arranged in a lattice pattern. In other words, the trench 6A includes a plurality of trenches 6A having the same length direction and trenches 6A having a length direction perpendicular to these trenches 6A. In this manner, by arranging the trenches 6A in a lattice shape, it is possible to increase the channel density, so that the resistance can be further reduced. Further, since the arrangement density of the protective diffusion layer 9A and the protective diffusion layer 9B1 is increased, the depletion layers are easily overlapped, and the electric field strength at the bottom of the trench 6A can be further relaxed.

  In the above description, the SiC-MOSFET is taken as an example. However, even in a trench type semiconductor device using a wide band gap semiconductor other than SiC, the on-resistance is reduced and the electric field strength of the insulating film at the bottom of the trench is reduced. Therefore, the present invention can be applied. Further, the present invention can be applied to IGBT as well as MOSFET.

  The semiconductor device described in this embodiment can be applied to a power conversion device such as an inverter or a converter. The power converter is used for applications such as in-vehicle use, electric railway use, industrial use, and consumer use.

<B. Second Embodiment>
<B-1. Configuration>
FIG. 18 is a cross-sectional view showing a configuration of SiC-MOSFET 102 that is the semiconductor device according to the second embodiment. The cross section shown in FIG. 18 corresponds to the DD ′ cross section of FIG. 1 in terms of the SiC-MOSFET 101 according to the first embodiment.

  In the SiC-MOSFET 101, a protective diffusion layer 9A and a protective diffusion layer 9B1 having a thickness smaller than that of the protective diffusion layer 9A and an equivalent impurity concentration are provided. The reason why the thickness of the protective diffusion layer 9B1 is smaller than that of the protective diffusion layer 9A is to make the width of the depletion layer extending from the protective diffusion layer 9B1 to the N-type drift layer 2 smaller than that of the protective diffusion layer 9A.

  On the other hand, in the SiC-MOSFET 102, instead of the protective diffusion layer 9B1, a P-type protective diffusion layer 9B2 having the same thickness and a lower impurity concentration than the protective diffusion layer 9A is provided. The configuration of the SiC-MOSFET 102 other than the protective diffusion layer 9B2 is the same as that of the SiC-MOSFET 101.

  When the impurity concentration of the protective diffusion layer is lowered, the P-type space charge is reduced, so that the space charge is balanced by reducing the depletion layer width on the N− type drift layer 2 side. That is, in the protective diffusion layer 9B2 having a lower impurity concentration than the protective diffusion layer 9A, since the extension of the depletion layer to the N− type drift layer 2 becomes small, a low-resistance current path can be formed. Therefore, the same effect as in the first embodiment can be obtained.

  In this embodiment, the extension of the depletion layer is reduced by making the impurity concentration of the protective diffusion layer 9B1 lower than that of the protective diffusion layer 9A. However, by adjusting both the impurity concentration and the thickness, the protective diffusion layer 9A and the protection diffusion layer 9B1 are protected. The effect of this embodiment can also be obtained by controlling the extension of the depletion layer of the diffusion layer 9B1 and reducing the extension of the depletion layer of the protective diffusion layer 9B1.

<C. Embodiment 3>
<C-1. Configuration>
FIG. 19 is a configuration diagram of SiC-MOSFET 103 which is a semiconductor device according to the third embodiment. FIG. 19A is a plan view of the N − type drift layer 2 as viewed from the N + type substrate 1 side, and FIG. 19B is a cross-sectional view taken along the line AA ′ of FIG. This AA ′ cross section is a cross section in a direction normal to the side surface of the trench 6A, in other words, a direction perpendicular to the length direction of the trench 6A. In the SiC-MOSFET 101 according to the first embodiment, the cross section A in FIG. This corresponds to a cross section taken along the line −B ′, that is, FIG.

  The SiC-MOSFET 103 includes a P-type protective diffusion layer 9 </ b> C (third protective diffusion layer) in addition to the configuration of the SiC-MOSFET 101. The protective diffusion layer 9 </ b> C is formed in the N− type drift layer 2 below the P type base layer 3, and faces the trench 6 </ b> A through the N− type drift layer 2. The protective diffusion layer 9C only needs to be formed at the same depth as the bottom of the trench 6A, and the electric field strength at the bottom of the trench 6A where the electric field strength is strongest by the depletion layer extending from the protective diffusion layer 9C to the N− type drift layer 2. Can be relaxed.

  In FIG. 19B, the protective diffusion layer 9C is formed at a position shallower than the protective diffusion layer 9B1, but if it is formed at a position deeper than the protective diffusion layer 9B1, the electric field strength at the bottom of the trench 6A is further relaxed. I can do it. In FIG. 19B, the protective diffusion layer 9C is provided in contact with the P-type base layer 3, but may not be in contact with the P-type base layer 3.

  In particular, when the protective connection layer 9S is provided only in contact with the protective diffusion layer 9A, the protective connection layer 9S is not provided at the bottom of the trench 6A where the protective diffusion layer 9B1 is formed, and thus the trench 6A where the protective diffusion layer 9A is formed. The electric field strength is not relaxed compared to the bottom. Accordingly, by providing the protective diffusion layer 9C at a position where the protective diffusion layer 9B1 is opposed to the trench 6A formed at the bottom, the electric field strength at the portion can be reduced.

<D. Embodiment 4>
<D-1. Configuration>
FIG. 20 is a configuration diagram of SiC-MOSFET 104 which is a semiconductor device according to the fourth embodiment. 20A is a plan view of the N− type drift layer 2 as viewed from the N + type substrate 1 side, and FIG. 20B is a cross-sectional view taken along the line AA ′ of FIG. The AA ′ cross section is a cross section in the direction normal to the side surface of the trench 6A, in other words, the direction perpendicular to the length direction of the trench 6A. Corresponds to a cross section taken along the line A ′, that is, FIG.

  In the SiC-MOSFET 104, a trench 6B (second trench) having the same depth as the trench 6A is formed in a part of the trench 6A in the length direction in a region sandwiched between the plurality of trenches 6A of the N-type drift layer 2. ing. A protective contact 11A (protective contact layer) made of an electrode material such as an Al alloy and electrically connected to the source electrode 11 is formed in the trench 6B.

  The protective diffusion layers 9A and the protective diffusion layers 9B1 are alternately arranged along the bottom of the trench 6A in the length direction of the trench 6A. Further, the protective diffusion layer 9A is formed across the bottoms of the two trenches 6 sandwiching the trench 6B in the formation region of the trench 6B. Since the trench 6B is formed to the same depth as the trench 6, the protective diffusion layer 9A is formed not only at the trench 6A but also at the bottom of the trench 6B.

  A P + type contact layer 5 (contact region) is formed between the trench 6B and the protective diffusion layer 9A, and the protective diffusion layer 9A is a source via the P + type contact layer 5 and the protective contact 11A (protective contact layer). It is electrically connected to the electrode 11 and fixed at the source potential.

  The interlayer insulating film 10 covers not only the upper surface of the gate electrode 8 but also the side surface of the trench 6A facing the protective contact 11A.

  In FIG. 20, the protective diffusion layer 9A is formed over the bottoms of the two trenches 6A sandwiching the trench 6B. However, the protective diffusion layer 9B1 may be formed instead of the protective diffusion layer 9A.

  With such a configuration, the protective diffusion layer 9A or the protective diffusion layer 9B1 is electrically connected via the protective contact 11A. In the first embodiment, the protective diffusion layer 9A and the protective diffusion layer 9B1 are electrically connected to the source electrode 11 via the P-type protective connection layer 9S formed in the N − type drift layer 2 along the side surface of the trench 6A. Although connected, the electric field strength at the bottom of the trench 6A can be further relaxed by connecting to the lower resistance via the protective contact 11A.

  In the present invention, within the scope of the invention, the embodiments can be modified or omitted as appropriate (each embodiment can be freely combined or each).

  1 N + type substrate, 2 N− type drift layer, 3 P type base layer, 4 N type source layer, 5 P + type contact layer, 6A, 6B trench, 7 gate insulating film, 8 gate electrode, 9A, 9B1, 9B2, 9C protective diffusion layer, 9S protective connection layer, 10 interlayer insulating film, 11 source electrode, 11A protective contact, 12 drain electrode, 13 silicon oxide film, 14A, 14B, 14C implantation mask, 101, 101A, 102, 103, 104 SiC -MOSFET.

Claims (13)

A first conductivity type drift layer;
A second conductivity type well region partially formed in a surface layer of the drift layer;
A first conductivity type impurity region partially formed in a surface layer of the well region;
A first electrode formed through an insulating film in a first trench extending from a surface layer of the impurity region to the inside of the drift layer through the well region;
A second electrode electrically connected to the well region and the impurity region;
A protective diffusion layer of a second conductivity type formed in the drift layer below the bottom of the first trench and electrically connected to the second electrode;
The protective diffusion layer includes a first protective diffusion layer and a second protective diffusion layer having a thickness smaller than that of the first protective diffusion layer,
The first protective diffusion layer and the second protective diffusion layer are in contact with each other and are alternately disposed along the length direction of the first trench,
Semiconductor device. A first conductivity type drift layer;
A second conductivity type well region partially formed on a surface layer of the drift layer;
A first conductivity type impurity region partially formed in a surface layer of the well region;
A first electrode formed through an insulating film in a first trench extending from the surface layer of the impurity region to the inside of the drift layer through the well region;
A second electrode electrically connected to the well region and the impurity region;
A protective diffusion layer of a second conductivity type formed in the drift layer below the bottom of the first trench and electrically connected to the second electrode;
The protective diffusion layer includes a first protective diffusion layer and a second protective diffusion layer having an impurity concentration lower than that of the first protective diffusion layer,
The first protective diffusion layer and the second protective diffusion layer are in contact with each other and are alternately disposed along the length direction of the first trench,
Semiconductor device. A first conductivity type drift layer;
A second conductivity type well region partially formed on a surface layer of the drift layer;
A first conductivity type impurity region partially formed in a surface layer of the well region;
A first electrode formed through an insulating film in a first trench extending from the surface layer of the impurity region to the inside of the drift layer through the well region;
A second electrode electrically connected to the well region and the impurity region;
A protective diffusion layer of a second conductivity type formed in the drift layer below the bottom of the first trench and electrically connected to the second electrode;
The protective diffusion layer includes a first protective diffusion layer and a second protective diffusion layer,
The first protective diffusion layer and the second protective diffusion layer are in contact with each other and alternately disposed along the length direction of the first trench,
The width of the depletion layer extending from the first protective diffusion layer to the drift layer is larger than the width of the depletion layer extending from the second protective diffusion layer to the drift layer,
Semiconductor device. The protective diffusion layer covers a corner of the bottom of the first trench,
The semiconductor device according to claim 1. A plurality of the first trenches;
In the first trench, the first protective diffusion layer and the second protective diffusion layer are alternately arranged in contact with each other along the length direction of the first trench,
In another of the first trenches, either the first protective diffusion layer or the second protective diffusion layer is disposed along the length direction of the first trench.
The semiconductor device according to claim 1. The first protective diffusion layer and the second protective diffusion layer are arranged by shifting the arrangement between two adjacent first trenches,
The semiconductor device according to claim 1. The plurality of first trenches are arranged such that the length direction is in a lattice shape,
The semiconductor device according to claim 1. A second conductive type third protective diffusion layer formed between the adjacent first trenches and not contacting the first trenches and below the bottom of the well region;
The semiconductor device according to claim 1. A protective connection layer provided on the drift layer in contact with a side surface of the first trench and connecting at least one of the first protective diffusion layer and the second protective diffusion layer and the well region;
The protective diffusion layer is electrically connected to the second electrode through the protective connection layer,
The semiconductor device according to claim 1. A plurality of the first trenches;
The protective connection layer connects the protective diffusion layers below the adjacent first trenches,
The semiconductor device according to claim 9. A protective contact layer formed in a second trench provided in the drift layer and in contact with the second electrode;
The protective diffusion layer includes a contact region in contact with the protective contact layer,
The semiconductor device according to claim 1. The drift layer is made of a wide band gap semiconductor,
The semiconductor device according to claim 1. The drift layer is made of silicon carbide,
The semiconductor device according to claim 12.

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