JP2017092168A - Semiconductor module and power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module which bonds a semiconductor chip and a wiring layer with higher heat resistance and higher durability, and a power converter.SOLUTION: A semiconductor module 200 comprises: an insulation substrate 210; a wiring layer 212 formed on the insulation substrate; a semiconductor chip 100 arranged so as to be superposed on the wiring layer, and having a terminal electrically connected to the wiring layer; and a metallic sintered bonding layer 214 fixing and electrically connecting between the wiring layer and the semiconductor chip, and the wiring layer has a groove part at the inside of the outer edge of the overlapping semiconductor chip in plan view.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor module and a power conversion device, and is suitable for application to equipment using a motor, for example.

  In power converters such as inverters, power semiconductor modules using IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), etc. are used as switching elements. Since the semiconductor chips used in such a semiconductor module each handle a large current of several hundreds A, each semiconductor chip performs a switching operation with a large amount of heat generation.

  Patent Document 1 discloses a configuration in which the thickness of the bonding material at the bonding portion between the metal substrate and the semiconductor element is increased from the center of the semiconductor element to the outer peripheral portion.

JP2015-015335A

  In recent years, further miniaturization of semiconductor modules has been demanded, and the heat generation density tends to further increase. In order to ensure heat resistance, high lead solder having a melting point of about 300 ° C. and a lead content of 85% or more has been conventionally used for joining the semiconductor chip and the wiring layer. However, as lead-free soldering of semiconductor devices has progressed, Sn-Cu solder, Sn-Ag solder, Sn-Sb solder, and the like are known as lead-free solder materials, but these have a melting point of about 200 ° C. Yes, the material was insufficient in terms of heat resistance.

  On the other hand, sintered joining using the low-temperature firing function of silver or copper nanoparticles is known as an alternative material. In silver nanoparticles having a particle size of 100 nm or less, the number of constituent atoms is decreased, the surface area ratio to the volume of the particles is rapidly increased, and the melting point and sintering temperature are greatly reduced as compared with the bulk state. By using this low-temperature firing function to sinter silver particles together, they change into bulk silver after bonding, and at the same time are bonded by metal bonds at the bonding interface, so they have extremely high heat resistance and high resistance. Has heat dissipation.

  In such a sintered joining method, the sintered density of the joining layer is improved through a pressurizing process, and thus the joining material sometimes protrudes outside the semiconductor chip during pressurization. Since no pressure is applied to the part where the bonding material protrudes, the sinterability becomes brittle, and if this brittle part peels off, it may cause a short circuit between the gate and the emitter, for example, which may reduce the manufacturing yield. It was.

  On the other hand, when the operating temperature of the semiconductor chip is increased, there is a difference between the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the wiring material. Thermal fatigue occurs while repeating the operation (ON / OFF operation), and there is a possibility that the joint may be destroyed by use.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor module and a power conversion device that join a semiconductor chip and a wiring layer with higher heat resistance and higher durability.

  In order to solve such a problem, a semiconductor module according to the present invention includes an insulating substrate, a wiring layer formed on the insulating substrate, and a terminal that is disposed on the wiring layer and is electrically connected to the wiring layer. And a metal sintered bonding layer that fixes and electrically connects between the wiring layer and the semiconductor chip, and the wiring layer overlaps in plan view A semiconductor module having a groove inside an outer edge of a chip.

  Moreover, the power converter device of this invention is equipped with two or more semiconductor modules of this invention, The waveform signal of a different timing is input into any two gates among these semiconductor modules, The power converter device characterized by the above-mentioned. It is.

  According to the present invention, in a semiconductor module and a power conversion device, a semiconductor chip and a wiring layer can be bonded with higher heat resistance and higher durability.

It is a top view which shows the semiconductor module which concerns on one embodiment of this invention. It is a figure which shows the AA cross section of the semiconductor module of FIG. It is sectional drawing shown about a semiconductor chip and its periphery. It is the cross-sectional schematic for demonstrating the wiring layer and sintered joining layer which overlap with a semiconductor chip. It is a plane schematic diagram for demonstrating the wiring layer and sintered joining layer which overlap with a semiconductor chip. FIG. 6 is a view showing an example in which the groove portion of the wiring layer is formed inside the active area, with the same field of view as FIG. 5. It is a graph which shows the power cycle test result of the 1st example of formation of a sintered joining layer, and a comparative sample. It is a circuit diagram shown about embodiment of the power converter device using the semiconductor module of this Embodiment.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, similar elements are denoted by the same reference numerals, and redundant description is omitted.

(1) Configuration of Semiconductor Module 200 in the Present Embodiment FIGS. 1 and 2 are diagrams showing a semiconductor module 200 according to an embodiment of the present invention. FIG. 1 is a plan view, and FIG. It is a figure which shows -A cross section. As shown in these drawings, in the semiconductor module 200, the semiconductor chip 100 is attached to the wiring layer 212 formed on the insulating substrate 210 made of ceramics via the sintered bonding layer 214 made of a sintered metal of Cu, Bonding wires 207 attached to terminals on the semiconductor chip 100 are connected to another wiring layer 212 formed on the insulating substrate 210. Further, the wiring layer 205 formed on the insulating substrate 210 is bonded to the support member 201 via the solder layer 204. A case 202 is attached to the support member 201 so as to surround the insulating substrate 210, and a wire 208 electrically connected to another terminal on the semiconductor chip 100 is connected to the external terminal 216 attached to the case 202. It is connected. The insulating substrate 210 is sealed with a sealing material 206 in the case 202 including the semiconductor chip 100 and the like.

  Here, the insulating substrate 210 is not limited to ceramics, and a substrate made of another insulating material such as a resin can be used. The wiring layers 212 and 205 are copper wirings, but other conductive materials may be used. In FIG. 1, eight semiconductor chips 100 are depicted in the semiconductor module 200, but the number of semiconductor chips 100 used in the semiconductor module 200 may be one or plural. In addition, although the sintered metal of the sintered bonding layer 214 is Cu, other metals such as Ag may be used.

  FIG. 3 is a cross-sectional view showing the semiconductor chip 100 and its periphery. In the present embodiment, the semiconductor chip 100 is a 12 mm × 12 mm IGBT chip, but it may be a semiconductor chip of another size or a semiconductor chip of another configuration such as a MOSFET. The collector electrode 102 of the semiconductor chip 100 is bonded to the wiring layer 212 on the insulating substrate 210 by the sintered bonding layer 214. The emitter electrode 101 of the semiconductor chip 100 is connected to another wiring layer 212 on the ceramic insulating substrate 210 by a bonding wire 207.

  FIGS. 4 and 5 are a schematic cross-sectional view and a schematic plan view for explaining the wiring layer 212 and the sintered bonding layer 214 that overlap the semiconductor chip 100, respectively. As shown in these drawings, the wiring layer 212 has a groove 217 inside the outer edge of the semiconductor chip 100 in a plan view (FIG. 5), and the sintered bonding layer 214 is disposed in the groove 217. (FIG. 6). With such a configuration, it is possible to suppress the protrusion of the sintered bonding layer 214 that occurs when the semiconductor chip 100 is sintered and bonded onto the wiring in the process of pressurizing the semiconductor chip 100. For this reason, the protruding portion of the sintered bonding layer 214 is peeled off, and defects such as a short circuit between the gate and the emitter can be prevented. In addition, since the sintered bonding layer 214 formed in the groove 217 has a lower density than the other portions, it can absorb thermal strain due to repeated switching operations, and becomes a thicker sintered bonding layer 214. Further, cracks are less likely to occur, and progress can be suppressed even if cracks occur.

  Here, the groove 217 may be formed outside the active area 109 of the semiconductor chip 100. By forming the outer surface of the active area 109 in this way, the sintered bonding layer 214 in the active area 109 becomes an area having a higher density, that is, a higher conductivity. Therefore, resistance of a current flowing through the semiconductor chip 100 is suppressed. In addition, since the sintered bonding layer 214 has a lower density outside the active area 109, it can absorb the thermal strain due to repeated switching operations, and the thicker sintered bonding layer 214. Further, cracks are less likely to occur, and progress can be suppressed even if cracks occur.

  However, the groove portion 217 may be formed inside the active area 109. In particular, when the density of the sintered bonding layer 214 in the groove portion 217 is sufficient, the collector electrode 102 of the semiconductor chip 100, the wiring layer 212, and the like. As shown in FIG. 6, the active area 109 has a small influence on the conductivity between the collector electrode 102 and the wiring layer 212 of the semiconductor chip 100 due to, for example, the case where the junction of the active area 109 has a sufficient density. It may be formed inside. The groove part 217 in FIG. 6 has a groove part that vertically and horizontally crosses the active area 109 in addition to a groove part that surrounds the outside of the active area 109. Here, as a method for forming the groove 217 provided in the wiring layer 212, for example, pressing, etching, cutting, or the like can be used.

  In the sintered bonding layer 214 that overlaps the semiconductor chip 100, the sintered density of the sintered bonding layer 214 that overlaps the active area 109 is higher than the sintered density of the sintered bonding layer 214 that overlaps the region other than the active area 109. It is desirable to increase it by 10% or more. As a result of simulation analysis, it was confirmed that when it is 10% or more, the thermal stress resistance is improved about twice, and as a result, the power cycle resistance is improved more than 10 times that of the conventional solder.

(2) Joining material and joining method used for forming sintered joining layer Known materials and methods can be applied as joining materials and joining methods for forming the sintered joining layer. For example, as the bonding material, a material containing copper oxide particles having an average particle diameter of 1 nm to 5 μm and an organic solvent can be used. By using this bonding material and bonding in a hydrogen atmosphere, the members can be bonded. In particular, excellent bonding strength can be obtained for Cu and Ni electrodes. In this joining, the copper oxide particle precursor is reduced, copper particles having an average particle size of 100 nm or less are generated at that time, and the phenomenon that joining is performed by the fusion of the copper particles to each other is utilized. . The copper particles having an average particle size of 100 nm or less are generated, the copper particles are fused with each other, and the mechanism of joining is as follows: (1) The generated copper particles of 100 nm or less form a thin film layer on the surface of the counterpart electrode; ) This layer is grown in the same direction as the crystal growth direction of the counterpart metal electrode plate (Cu, Ni, etc.). (3) Further, the sintered layer is formed by the fusion of copper particles that did not contribute to the formation of the thin film layer. That is, a bonding layer is formed and bonding is achieved. The precursor copper oxide particles may be cuprous oxide or cupric oxide. Since metal oxide particles made of copper oxide generate only oxygen during reduction, the residue after joining hardly remains, and the volume reduction rate is very small. The average particle size of the copper oxide particles used here is 1 nm or more and 5 μm or less. When the average particle size is larger than 5 μm, metal copper particles having a particle size of 100 nm or less are less likely to be generated during bonding. This is because the gaps between the particles increase, and it becomes difficult to obtain a dense bonding layer. The reason why the thickness is 1 nm or more is that it is difficult to actually produce a cupric oxide particle precursor having an average particle size of 1 nm or less. In the bonding process in the first formation example described later, (1) heat at 60 ° C. is applied for about 10 minutes, and pressure is simultaneously applied in a hydrogen atmosphere. (2) The temperature is increased to 300 ° C. while applying pressure, Although the process is held for 15 minutes, other bonding processes can be used.

  The bonding material is a method of applying only to the required part using a metal mask with an opening of the application part, a method of applying to the required part using a dispenser, and opening only a required part of a water-repellent resin containing silicone or fluorine. By applying a coated metal mask or mesh mask, or by applying a photosensitive water-repellent resin on a substrate or electronic component, and then exposing and developing to remove the portion where the bonding material is to be applied. After applying the water-repellent resin to the substrate or the electronic component after removing the water-repellent resin on the substrate or the electronic component, the portion to which the bonding material is applied is removed by a laser, and then the bonding paste is applied to the opening. be able to. These coating methods can be used in combination according to the area and shape of the electrodes to be joined.

  At the time of bonding, in order to generate metal particles having a particle size of 100 nm or less from the metal particle precursor, and to perform metal bonding by fusion of metal particles having a particle size of 100 nm or less while discharging organic substances in the bonding layer, It is preferable to apply heat and a pressure of 0.01 to 5 MPa. The atmosphere during bonding may be a reducing atmosphere containing hydrogen or formic acid, or a non-oxidizing atmosphere. Pure metal ultrafine particles are generated by heat reduction at the time of joining, and these pure metal ultraparticles are fused together to become a bulk. The melting temperature after becoming bulk is the same as the melting temperature of metals in the normal bulk state, and the ultrafine metal particles are melted by low-temperature heating, and after melting, they are heated to the melting temperature in the bulk state. It does not re-melt until This is because when pure metal ultrafine particles are used, bonding can be performed at a low temperature, and the melting temperature is improved after bonding. The advantage of not melting. As the sintered bonding layer, sintered silver can be applied in addition to sintered copper, but it is more preferable to use sintered copper. This is because sintered copper has less vacancy diffusion than sintered silver, and void generation due to temperature rise is suppressed. By using the bonding material and the bonding method described above for bonding the electrodes of the semiconductor chip, it is possible to obtain excellent bonding reliability.

(3) First Formation Example of Sintered Joining Layer In the first formation example of the sintered joining layer 214 in the present embodiment, the sintered joining layer 214 is composed of 88 wt% cupric oxide particles (after joining). It was formed using a bonding material in which pure copper) and 12 wt% diethylene glycol monobutyl ether were mixed. The thickness of the sintered bonding layer 214 is 80 μm. The groove 217 is formed with a depth of 20 micrometers and is filled with the sintered bonding layer 214.

  A method for forming the sintered bonding layer 214 of the first formation example will be described. A bonding material is printed by a metal mask on a bonding portion on the wiring layer 212 of the insulating substrate 210, and the semiconductor chip 100 is disposed thereon. Next, the pressure is increased to 0.01 MPa, and the temperature is increased to 300 ° C. in hydrogen and held for 15 minutes. In addition, although the pressure was kept applied in this formation example, pressurization is not essential when the temperature is maintained at 300 ° C. Through the above process, the collector electrode 102 of the semiconductor chip 100 and the wiring layer 212 in which the groove 217 is formed are joined by the sintered joining layer 214. In this forming method, the sintered density of the flat portion of the sintered bonding layer 214 was about 80% (porosity 20%), and the sintered density of the groove portion 217 was about 50% (porosity 50%).

  A power cycle test was performed on the semiconductor module 200 manufactured in this example. In the power cycle test, a predetermined current is passed through the semiconductor chip 100 for a predetermined time to cause the semiconductor chip 100 to generate heat, and after raising the temperature to a predetermined temperature Tjmax (175 ° C. in this test), the current is turned off, This is a test in which heat generation and cooling of the semiconductor chip 100 are repeated in which power is supplied again after cooling to temperature (room temperature in this test), and is one of important reliability tests in the semiconductor module 200.

  FIG. 7 is a graph showing the power cycle test results. Reference numeral 502 indicates a test result for the first formation example. The horizontal axis of the graph shows the number of cycles of heat generation and cooling, and the vertical axis shows the transition of the Tjmax value. Although the Tjmax value is set to 175 ° C., damage occurs in the lower chip joint and the upper chip joint of the semiconductor chip 100, and the value increases as the damage further progresses. In this test, the lifetime was determined when the rate of increase from the set Tjmax value increased by 15% of the set value. For comparison, a comparative sample formed under the same conditions with a structure in which the groove 217 is not provided is produced, and the result of performing the power cycle test in the same manner is also indicated by reference numeral 501. Tjmax is 150 ° C.

  In FIG. 7, in the comparative sample 501, a short circuit failure occurred between the gate and the emitter about 10,000 times, and the test could not be continued. The target cycle test number was 100,000 times or more, which was about 1/10 of the target. This is probably because the comparative sample 501 had a large amount of protrusion of the sintered layer, which peeled off and caused a short circuit between the wirings. On the other hand, in the semiconductor module 200 of the first formation example 502, the cycle life was about 500,000 times, which showed a significant improvement in reliability. In the semiconductor module 200 of the first formation example 502, the thermal strain concentrated on the end of the sintered bonding layer 214 is reduced, and the life of the bonded portion can be extended.

(4) Second Formation Example of Sintered Joining Layer In the second formation example, an example will be described in which the sintered joining layer 214 is formed by adjusting predrying conditions during joining. A bonding material is printed by a metal mask on a bonding portion on the wiring layer 212 of the insulating substrate 210, and the semiconductor chip 100 is disposed thereon. In this state, heat at 60 ° C. in the atmosphere is applied for about 20 minutes. Next, the pressure is increased to 0.1 MPa, the temperature is increased in hydrogen to 300 ° C. at a rate of temperature increase of 5 ° C./min, and held for 15 minutes. Through the above process, the semiconductor chip 100 and the wiring layer 212 were bonded via the sintered bonding layer 214.

  As a result, the flat portion sintered density of the sintered bonding layer 214 was about 90% (porosity 10%), and the sintered density of the groove portion 217 of the sintered bonding layer 214 was about 80% (porosity 20%). . After applying the bonding material, it was pre-dried for a long time, so that the sintering proceeded at a high density even in the groove portion 217 having a small pressure.

  As a result of conducting a power cycle test on the semiconductor module 200 manufactured in the second formation example, the cycle life was about 700,000 times, and a significant improvement in reliability could be achieved. The lifetime was improved compared to the first example. Since the sintered density of the groove part 217 was increased, it is considered that there was an effect of reducing damage to the semiconductor element.

(5) Effects of the present embodiment The semiconductor module 200 of the present embodiment is arranged with the insulating substrate 210, the wiring layer 212 formed on the insulating substrate 210, and the wiring layer 212. The wiring layer 212 includes a semiconductor chip 100 having one terminal 102 that is electrically connected, and a metal sintered bonding layer 214 that fixes and electrically connects the wiring layer 212 and the semiconductor chip 100. Has a groove 217 inside the outer edge of the semiconductor chip 100 that overlaps in plan view, so that the sintered bonding layer 214 is formed without protruding from the semiconductor chip 100. 214 can be formed. For this reason, the protrusion of the sintered bonding layer 214 causes the protrusion to peel off, for example, between the gate and the emitter. Such as short circuit can be suppressed. Further, since the recessed portion of the groove portion 217 becomes a sintered bonding layer 214 having a lower density than the other portions, it can absorb thermal strain due to repeated switching operation, and the thicker sintered bonding layer 214 Therefore, cracks are less likely to occur, and progress can be suppressed even if cracks occur. Therefore, the joining portion of the semiconductor chip 100 having sufficient sinterability and durability can be obtained.

  Further, the groove portion 217 can have a shape that surrounds the outside of the active area of the semiconductor chip 100 in plan view. In this case, the sintered bonding layer 214 in the active area 109 is further increased by doing so. The area of high density, that is, high conductivity, can suppress the resistance of the current flowing through the semiconductor chip 100, and the sintered bonding layer 214 having a lower density is formed outside the active area 109. Thermal strain due to repetition can be absorbed. Further, since the sintered joining layer 214 becomes thicker, cracks are less likely to occur, and progress can be suppressed even if cracks occur.

  Moreover, the groove part 217 may be formed inside the shape surrounding the outside of the active area 109. In this case, the occurrence of cracks in the sintered bonding layer 214 can be suppressed even in the active area, and the progress can be suppressed even if a crack occurs.

  Further, the density of the sintered bonding layer 214 overlapping the active area 109 can be made higher than the density of the sintered bonding layer 214 overlapping the groove 217. By doing so, the sintered bonding layer 214 in the active area 109 is made to have a higher density, that is, a highly conductive area, and the resistance of the current flowing through the semiconductor chip 100 can be suppressed, and the active area 109 On the outside, since the sintered bonding layer 214 has a lower density, it can absorb thermal strain due to repeated switching operations, and since it becomes a thicker sintered bonding layer 214, cracks are less likely to occur, Even if a crack occurs, the progress can be suppressed.

(6) Other Embodiments FIG. 8 is a circuit diagram showing an embodiment of a power conversion device 300 using the semiconductor module 200 described above. The power conversion apparatus 300 includes a plurality of semiconductor modules 200, and waveform signals with different timings are input to at least two gates among them. Although the inverter device is shown in the circuit of this example, the present invention can be applied to an electric motor and other power conversion devices 300 in addition to the inverter device. By applying the semiconductor module 200 of the above-described embodiment to the power conversion device 300, it can be mounted in a place of a high temperature environment, and long-term reliability can be ensured without having a dedicated cooler. .

  The power conversion device 300 including the inverter device and the electric motor can be incorporated as a power source in a high-speed vehicle or an electric vehicle. In this car, the drive mechanism from the power source to the wheels has been simplified, so the shock at the time of shifting is reduced and smooth running is possible compared to the conventional car that has been shifting due to the difference in gear engagement ratio. Thus, vibration and noise can be reduced as compared with the conventional case.

  Furthermore, the power conversion device 300 in which the semiconductor module 200 of the above-described embodiment is incorporated can be incorporated in an air conditioner. In this case, higher efficiency can be obtained than when a conventional AC motor is used. Thereby, the power consumption at the time of air-conditioning machine use can be reduced. Moreover, the time until the room temperature reaches the set temperature from the start of operation can be shortened compared to the case where the conventional AC motor is used. The power conversion device 300 can be incorporated in a device that stirs or flows other fluid, such as a washing machine, a fluid circulation device, and the like, and can obtain the same effect. In the power conversion device 300 according to the present embodiment, any two of the plurality of semiconductor modules 200 are input with waveform signals having different timings to the gates. Has an effect.

  The present invention can be applied to equipment using a motor, for example.

100 Semiconductor chip 101 Emitter electrode 102 Collector electrode 109 Active area 200 Semiconductor module 201 Support member 202 Case 204 Solder layer 205 Wiring layer 206 Sealing material 207 Bonding wire 208 Wire 210 Insulating substrate 212 Wiring layer 214 Sintered bonding layer 216 External terminal 217 Groove 300 Power Converter 501 Comparative Sample 502 First Formation Example

Claims (5)

An insulating substrate;
A wiring layer formed on the insulating substrate;
A semiconductor chip disposed on the wiring layer and having one terminal electrically connected to the wiring layer;
While fixing between the wiring layer and the semiconductor chip, and comprising a sintered joining layer of metal that is electrically connected,
The wiring layer has a groove on the inner side of the outer edge of the semiconductor chip that overlaps in a plan view. The semiconductor module according to claim 1,
The groove part has a shape surrounding the outside of the active area of the semiconductor chip in plan view. The semiconductor module according to claim 2,
The groove is also formed inside the active area. A semiconductor module, wherein: The semiconductor module according to any one of claims 1 to 3,
The semiconductor module according to claim 1, wherein a density of the sintered bonding layer superimposed on the active area is higher than a density of the sintered bonding layer superimposed on the groove. A plurality of semiconductor modules according to any one of claims 1 to 3,
Waveform signals having different timings are input to any two gates of the plurality of semiconductor modules.

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