JP2017085040A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which characteristic deterioration is suppressed.SOLUTION: A semiconductor device 1 for which microwave signals are inputted and outputted includes a semiconductor substrate 2 having a principal surface 2a, a first side face, and a second side face, a circuit 3 provided on the principal surface 2a, an output terminal 4 provided on the first side face of the circuit 3, and connected with the circuit 3, an input terminal 5 provided on the second side face of the circuit 3, and connected with the circuit 3, and a conductive layer 6 provided on the circuit 3, and to which a reference voltage is inputted. The conductive layer 6 is provided with a slit 21 extending to cross a straight line SL connecting the output terminal 4 and input terminal 5 in the plan view.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  In recent years, a semiconductor chip such as a microwave integrated circuit (hereinafter referred to as MMIC: Monolithic Microwave Integrated Circuit) to / from which a high frequency signal such as a millimeter wave band is input / output is mounted on a substrate by a surface mounting technique using a spherical bump. The An electromagnetic field generated between the semiconductor chip mounted in this way and the substrate may affect the operation of the circuit unit provided in the semiconductor chip. In this case, the isolation characteristics of the semiconductor chip are significantly deteriorated.

  For example, Patent Document 1 below discloses a technique in which a shield plating layer is provided between a main body of a semiconductor chip and spherical bumps that are external electrodes. When this semiconductor chip is mounted on the substrate via the bumps, an electromagnetic field generated between the semiconductor chip and the substrate can be blocked by the shield plating layer.

Japanese Patent No. 4010236

  However, in Patent Document 1, for example, a signal output from the output terminal may be fed back (feedback) to the input terminal via the shield plating layer. The deterioration of the characteristics of the semiconductor chip due to the signal feedback becomes conspicuous with downsizing. For this reason, there is a need for a technique for suppressing the deterioration of the characteristics of a semiconductor chip without depending on the chip size or the like.

  An object of this invention is to provide the semiconductor device by which characteristic deterioration is suppressed.

  A semiconductor device for inputting and outputting a microwave signal according to one aspect of the present invention includes a semiconductor substrate having a main surface, a first side surface, and a second side surface, a circuit portion provided on the main surface, and a circuit portion. An output terminal provided on the first side surface and connected to the circuit unit; an input terminal provided on the circuit unit and on the second side surface; connected to the circuit unit; and provided on the circuit unit. A conductive layer to which a reference potential is input, and the conductive layer is provided with a slit extending so as to intersect a straight line connecting the output terminal and the input terminal in plan view.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device by which characteristic deterioration is suppressed can be provided.

FIG. 1A is a schematic plan view of a semiconductor device 1 according to this embodiment. FIG. 1B is a sectional view taken along line Ib-Ib in FIG. FIG. 2A is a schematic plan view showing a semiconductor device 1A according to a first modification. FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. FIG. 3 is an equivalent circuit diagram including the semiconductor substrate 2, the conductive layer 6, and the wiring bodies 31 and 41 in FIG. FIG. 4A is a schematic plan view showing a semiconductor device 1B of the second modification. FIG. 4B is a sectional view taken along line IVb-IVb in FIG. FIG. 5A shows a plan view of the measurement sample of Example 1. FIG. FIG. 5B is an enlarged view of the slit and its periphery in FIG. FIG. 6 is a graph showing the simulation results of the isolation characteristics of each measurement sample.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described. One embodiment of the present invention is a semiconductor device to which a microwave signal is input / output, a semiconductor substrate having a main surface, a first side surface, and a second side surface, a circuit unit provided on the main surface, and a circuit An output terminal provided on the first side surface and connected to the circuit unit; an input terminal provided on the second side surface and connected to the circuit unit; and on the circuit unit A conductive layer to which a reference potential is input, and the conductive layer is provided with a slit extending so as to intersect a straight line connecting the output terminal and the input terminal in plan view is there.

  In this semiconductor device, the conductive layer to which the reference potential is input is provided on a circuit portion provided on the main surface of the semiconductor substrate. This conductive layer can function as a shield that prevents interference of electromagnetic fields from the outside with respect to the circuit portion. The conductive layer is provided with a slit extending so as to intersect with a straight line connecting the output terminal and the input terminal in plan view. In this case, the microwave signal that propagates through the conductive layer and returns from the output terminal to the input terminal along the straight line is blocked by the slit. Thereby, since the propagation path of the microwave signal in the conductive layer can be lengthened, the microwave signal is hardly input to the input terminal. Therefore, it becomes difficult for a microwave signal propagating through the conductive layer to be input to the circuit portion, so that deterioration in characteristics of the semiconductor device is suppressed.

  The semiconductor substrate further includes a third side surface facing the second side surface, the second side surface is adjacent to the first side surface, and the slit extends from the edge of the second side surface of the conductive layer to the third side surface side. It may be provided to extend. In this case, among the microwave signals to be fed back from the output terminal to the input terminal, the signal propagating through the conductive layer on the second side surface is blocked by the slit. Therefore, since the propagation path of the microwave signal propagating through the conductive layer can be further increased, the microwave signal is more difficult to be input to the input terminal.

  The slit may separate the conductive layer into a first region on the output terminal side and a second region on the input terminal side. In this case, the microwave signal flowing in the first region is blocked by the slit and does not propagate to the second region. Therefore, since the microwave signal propagates through the conductive layer and is not input to the input terminal, the deterioration of the characteristics of the semiconductor device is preferably suppressed.

  When the wavelength of the microwave signal is λ, the length of the slit may be larger than λ / 8 and smaller than 3λ / 8. In this case, since the slit also functions as an open stub, the slit end surface forms a short surface with respect to the microwave signal, and propagation of the microwave signal can be more effectively suppressed.

  The semiconductor device may further include power supply wiring provided to overlap the slit. In this case, signal propagation between the input terminal and the output terminal via the power supply wiring is suppressed, and higher isolation can be realized.

  The wiring body further includes a wiring body that is connected to the semiconductor substrate and the conductive layer and that surrounds the circuit portion on the main surface. The wiring body includes a plurality of wiring layers that are connected to each other and stacked on each other. And may be electrically insulated from the input terminal and the output terminal. In this case, the microwave signal propagated from the output terminal to the conductive layer can be released to the outside through the wiring body and the capacitor using the semiconductor substrate as a dielectric. Thereby, characteristic deterioration of the semiconductor device is suitably suppressed.

[Details of the embodiment of the present invention]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted.

  FIG. 1A is a schematic plan view of a semiconductor device 1 according to this embodiment. FIG. 1B is a sectional view taken along line Ib-Ib in FIG. A semiconductor device 1 shown in FIGS. 1A and 1B is an MMIC to which a microwave signal is input and output, and is used in a millimeter wave band of 30 GHz to 300 GHz, for example. The semiconductor device 1 is provided on a semiconductor substrate 2 having a main surface 2 a, a circuit unit 3 provided on the main surface 2 a, an output terminal 4 and an input terminal 5 provided on the circuit unit 3, and the circuit unit 3. And a conductive layer 6 that is electrically insulated from the output terminal 4 and the input terminal 5, a first external terminal 7 provided on the output terminal 4, a second external terminal 8 provided on the input terminal 5, and a conductive material. And a third external terminal 9 provided on the layer 6.

  The semiconductor substrate 2 is a substantially rectangular parallelepiped substrate having side surfaces 2b to 2e in addition to a main surface 2a that is substantially rectangular in plan view. The side surfaces 2b and 2c facing each other include one side of the main surface 2a. The side surfaces 2d and 2e facing each other include the other sides of the main surface 2a. Each of the side surfaces 2b and 2c is adjacent to the side surfaces 2d and 2e. The length of one side of the main surface 2a is, for example, 500 μm or more and 5000 μm or less, and the length of the other side of the main surface 2a is, for example, 500 μm or more and 5000 μm or less. The semiconductor substrate 2 is a GaAs substrate, for example.

  The circuit unit 3 is a part that amplifies the input microwave signal. The circuit portion 3 is a portion formed by being embedded in an insulating layer 11 provided on the main surface 2a. The circuit unit 3 is provided, for example, in a portion surrounded by a broken line in FIG. The circuit unit 3 includes a semiconductor element such as a field effect transistor, a wiring for connecting the semiconductor elements to each other, and a passive element such as a capacitor (the semiconductor element, the wiring, and the passive element are not illustrated). The insulating layer 11 is composed of a plurality of dielectric layers. These dielectric layers are made of an organic resin such as polyimide. The wiring in the circuit unit 3 is stacked in the insulating layer 11. The stacked wirings are connected to each other by, for example, via wirings.

  The output terminal 4 is a terminal for outputting a signal generated in the semiconductor device 1 to the outside. The output terminal 4 is provided at the center on the side surface 2b side (first side surface side) on the insulating layer 11 in which the circuit unit 3 is embedded. Therefore, the output terminal 4 is connected to the circuit unit 3 through the wiring 12 embedded in the insulating layer 11 or the like. The output terminal 4 includes a first region 4 a where the first external terminal 7 is provided, and a second region 4 b for contacting a probe electrode or the like when the semiconductor device 1 is inspected. The first region 4a is located closer to the center of the main surface 2a than the second region 4b in plan view. In other words, the second region 4b is provided closer to the side surface 2b than the first region 4a. The first region 4a is substantially circular in plan view, and the second region 4b is substantially rectangular in plan view. The output terminal 4 is a metal layer made of, for example, gold (Au), and the thickness thereof is, for example, not less than 500 nm and not more than 5000 nm. The output terminal 4 is formed from the same metal layer as the input terminal 5 and the conductive layer 6. For example, the metal layer formed on the insulating layer 11 is etched to form the output terminal 4, the input terminal 5, and the conductive layer 6 simultaneously.

  The input terminal 5 is a terminal for inputting an external signal to the circuit unit 3, and is provided on the side surface 2 d side (second side surface side) on the insulating layer 11 in which the circuit unit 3 is embedded. Therefore, the input terminal 5 is connected to the circuit unit 3 via the wiring 13 embedded in the insulating layer 11 or the like. The input terminal 5 includes a first region 5 a where the second external terminal 8 is provided, and a second region 5 b for contacting a probe electrode or the like when the semiconductor device 1 is inspected. The first region 5a is located closer to the center of the main surface 2a than the second region 5b in plan view. In other words, the second region 5b is provided closer to the side surface 2d than the first region 5a. The first region 5a is substantially circular in plan view, and the second region 5b is substantially rectangular in plan view. Similarly to the output terminal 4, the input terminal 5 is a metal layer made of, for example, gold (Au).

  The conductive layer 6 is a layer to which a reference potential is input from the outside, and is provided on the insulating layer 11. The conductive layer 6 is connected to the circuit unit 3 through at least one wiring among a plurality of wirings (not shown) embedded in the insulating layer 11. The conductive layer 6 constitutes a microstrip line (MSL) with at least one other wiring among the plurality of wirings. The other wiring propagates the microwave signal and connects the circuit unit 3 to the input terminal 5 or the output terminal 4. The conductive layer 6 has a substantially rectangular shape in plan view, a first recess 14 that is recessed from the edge on the side surface 2b side toward the center, and a second recess 15 that is recessed from the edge on the side surface 2d side toward the center. Have In the first recess 14, the output terminal 4 is provided so as not to contact the conductive layer 6. The distance between the conductive layer 6 and the output terminal 4 in plan view (that is, the width of the first recess 14) is, for example, not less than 10 μm and not more than 100 μm. Similarly, the input terminal 5 is provided in the second recess 15 so as not to contact the conductive layer 6. The distance between the conductive layer 6 and the input terminal 5 in plan view (that is, the width of the second recess 15) is, for example, not less than 10 μm and not more than 100 μm.

  The conductive layer 6 is provided with a linear slit 21 extending so as to intersect a straight line SL connecting the output terminal 4 and the input terminal 5 in plan view. The slit 21 is provided on the side surface 2b side of the second recess 15 and extends from the side surface 2d toward the side surface 2e side (third side surface side). Thereby, the conductive layer 6 is positioned on the side surface 2 b side of the slit 21, the second region 6 b positioned on the side surface 2 c side of the slit 21, and the side surface 2 e side of the slit 21. And a third region 6c that connects the first region 6a and the second region 6b. The first region 6a is located closer to the output terminal 4 than the second region 6b, and the second region 6b is located closer to the input terminal 5 than the first region 6a.

  The straight line SL in the present embodiment is a straight line that connects the shortest distance between the output terminal 4 and the input terminal 5. The straight line SL connects the shortest distance between the output terminal 4 and the input terminal 5, and passes through the center of the first region 4 a of the output terminal 4 and the center of the first region 5 a of the input terminal 5.

  The slit 21 has one end 21a and the other end 21b in the longitudinal direction. The one end 21 a is positioned so as to align with the edge on the side surface 2 d side of the conductive layer 6, and the other end 21 b is positioned on the side surface 2 e side with respect to the output terminal 4. The width of the slit 21 is, for example, not less than 1 μm and not more than 100 μm. The length L of the slit 21 depends on, for example, the wavelength λ of the microwave signal input to the semiconductor device 1. In the present embodiment, the length L of the slit 21 is larger than λ / 8 and smaller than 3λ / 8. Further, the slit 21 is formed at the same time when the input terminal 5, the output terminal 4, and the conductive layer 6 are formed. A power supply wiring that overlaps with the slit 21 and is embedded in the insulating layer 11 may be provided. Alternatively, the power supply wiring may be provided on the insulating layer 11 and in the slit 21.

  The 1st external terminal 7, the 2nd external terminal 8, and the 3rd external terminal 9 are provided in order to connect the circuit part 3 and external devices, such as a wiring board. For example, the first external terminal 7 is connected to the input terminal of the external device, the second external terminal 8 is connected to the output terminal of the external device, and the third external terminal 9 is grounded. One first external terminal 7 is provided on the first region 4 a of the output terminal 4, and one second external terminal 8 is provided on the first region 5 a of the input terminal 5. On the other hand, a plurality of third external terminals 9 are provided on the conductive layer 6. In the present embodiment, each of the first external terminal 7, the second external terminal 8, and the third external terminal 9 is a sphere formed of a conductive material such as a metal such as tin, silver, or copper, or an alloy thereof. The shape of the solder ball. In this embodiment, the pitch between the solder balls is set to about 300 μm. The semiconductor device 1 is mounted on a wiring board (not shown) for flip chip mounting. The plurality of third external terminals 9 of the semiconductor device 1 are electrically connected by a metal pattern on the wiring board. Thereby, each of the plurality of third external terminals 9 is electrically connected.

  In the semiconductor device 1 according to the present embodiment described above, the conductive layer 6 to which the reference potential is input is provided on the circuit unit 3 provided on the main surface 2 a of the semiconductor substrate 2. The conductive layer 6 can function as a shield that prevents interference of an external electromagnetic field with respect to the circuit unit 3. The conductive layer 6 is provided with a slit 21 extending so as to intersect with a straight line SL connecting the output terminal 4 and the input terminal 5 in plan view. In this case, a microwave signal that propagates through the conductive layer 6 and attempts to return from the output terminal 4 to the input terminal 5 along the straight line SL is blocked by the slit 21. Thereby, since the propagation path of the microwave signal in the conductive layer 6 can be lengthened, the microwave signal is hardly input to the input terminal 5. Therefore, the microwave signal propagating through the conductive layer 6 is difficult to be input to the circuit unit 3, and the characteristic deterioration of the semiconductor device 1 is suppressed.

  Further, the semiconductor substrate 2 further includes a side surface 2e facing the side surface 2d, the side surface 2d is adjacent to the side surface 2b, and the slit 21 is provided so as to extend from the side surface 2d toward the side surface 2e. Good. In this case, among the microwave signals to be fed back from the output terminal 4 to the input terminal 5, the signal propagating through the conductive layer 6 on the side surface 2 d side is blocked by the slit 21. In other words, the microwave signal that propagates through the conductive layer 6 and attempts to return from the output terminal 4 to the input terminal 5 must pass through all of the first region 6a, the third region 6c, and the second region 6b. . Therefore, since the propagation path of the microwave signal propagating through the conductive layer can be further increased, the microwave signal is more difficult to be input to the input terminal 5. In the semiconductor device 1 of the present embodiment, the first region 6a and the second region 6b of the conductive layer 6 are connected by the third region 6c, so that the first region 6a and the second region 6b of the conductive layer 6 are connected. The fluctuation of the reference potential is suppressed. Thereby, the fluctuation | variation of the microwave signal by which the amplification etc. are made by the circuit part 3 can be suppressed.

  When the wavelength of the microwave signal input / output to / from the semiconductor device 1 is λ, the length L of the slit 21 may be larger than λ / 8 and smaller than 3λ / 8. In this case, since the slit 21 also functions as an open stub, the slit end surface forms a short surface with respect to the microwave signal, and propagation of the microwave signal can be more effectively suppressed.

  Further, the semiconductor device 1 may include a power supply wiring provided so as to overlap the slit 21. In this case, signal propagation between the input terminal 5 and the output terminal 4 via the power supply wiring is suppressed, and higher isolation can be realized.

  FIG. 2A is a schematic plan view showing a semiconductor device 1A according to a first modification. FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. In the first modification, the first external terminal 7, the second external terminal 8, and the third external terminal 9 are omitted.

  As shown in FIGS. 2A and 2B, the semiconductor device 1A includes wiring bodies 31 and 41 that are embedded in the insulating layer 11 and connected to the semiconductor substrate 2 and the conductive layer 6. ing. The wiring body 31 is provided closer to the center side of the main surface 2 a than the wiring body 41, and is electrically insulated from the output terminal 4 and the input terminal 5. The wiring body 41 is provided so as to surround the circuit unit 3 on the main surface 2 a in plan view, and is electrically insulated from the output terminal 4 and the input terminal 5. Specifically, the wiring body 41 is provided along the outer edge of the conductive layer 6. In the present embodiment, the wiring body 41 is provided at least along the arrow A indicated by the phantom line shown in FIG. The wiring body 41 may not be provided on the edge and the periphery of the first recess 14. Similarly, the wiring body 41 may not be provided on the edge and the periphery of the second recess 15.

  An arrow A indicates a path of a microwave signal propagating from the output terminal 4 to the input terminal 5 along the edge of the conductive layer 6. Specifically, the arrow A indicates the edge of the conductive layer 6 located on the side surface 2b side and on the side surface 2e side of the first recess 14, the edge of the conductive layer 6 on the side surface 2e side, and the conductivity on the side surface 2c side. It extends along the edge of the layer 6 and the edge of the conductive layer 6 located on the side surface 2d side and on the side surface 2c side of the second recess 15.

  The wiring body 31 has a plurality of wiring layers 32 to 34 stacked on each other from the semiconductor substrate 2 side, and via wirings 35 to 38 stacked on each other from the semiconductor substrate 2 side. The via wiring 35 is located between the semiconductor substrate 2 and the wiring layer 32 and is in contact with both the semiconductor substrate 2 and the wiring layer 32. The via wiring 36 is located between the wiring layers 32 and 33 and is in contact with both the wiring layers 32 and 33. The via wiring 37 is located between the wiring layers 33 and 34 and is in contact with both the wiring layers 33 and 34. The via wiring 38 is located between the wiring layer 34 and the conductive layer 6 and is in contact with both the wiring layer 34 and the conductive layer 6. The wiring layers 32 to 34 and the via wirings 35 to 38 are metal layers made of, for example, gold (Au). The thickness of the wiring layers 32 to 34 is, for example, not less than 500 nm and not more than 5000 nm, and the thickness of the via wirings 35 to 38 is, for example, not less than 500 nm and not more than 5000 nm.

  The wiring body 41 includes a plurality of wiring layers 42 to 44 stacked on each other from the semiconductor substrate 2 side and via wirings 45 to 48 stacked on each other from the semiconductor substrate 2 side. The wiring layers 42 to 44 are provided along the outer edge of the conductive layer 6 so as to surround the circuit unit 3. Similarly, the via wirings 45 to 48 are also provided along the outer edge of the conductive layer 6.

  The via wiring 45 is located between the semiconductor substrate 2 and the wiring layer 42 and is in contact with both the semiconductor substrate 2 and the wiring layer 42. The via wiring 46 is located between the wiring layers 42 and 43 and is in contact with both the wiring layers 42 and 43. The via wiring 47 is located between the wiring layers 43 and 44 and is in contact with both the wiring layers 43 and 44. The via wiring 48 is located between the wiring layer 44 and the conductive layer 6 and is in contact with both the wiring layer 44 and the conductive layer 6. The wiring layers 42 to 44 and the via wirings 45 to 48 are metal layers made of, for example, gold (Au). The thickness of the wiring layers 42 to 44 is, for example, not less than 500 nm and not more than 5000 nm, and the thickness of the via wirings 45 to 48 is, for example, not less than 500 nm and not more than 5000 nm.

  The wiring layer 32 is formed simultaneously with the wiring layer 42 and is located in the same layer. Similarly, the wiring layer 33 is formed simultaneously with the wiring layer 43 and positioned in the same layer, and the wiring layer 34 is formed simultaneously with the wiring layer 44 and positioned in the same layer. The via wiring 35 is formed simultaneously with the via wiring 45 and is located in the same layer. Similarly, the via wiring 36 is formed simultaneously with the via wiring 46 and located in the same layer, the via wiring 37 is formed simultaneously with the via wiring 47 and located in the same layer, and the via wiring 38 is simultaneously formed with the via wiring 48. Formed and located in the same layer.

  FIG. 3 is an equivalent circuit diagram including the semiconductor substrate 2, the conductive layer 6, and the wiring bodies 31 and 41 in FIG. The equivalent circuit 51 shown in FIG. 3 includes resistance components 52 and 53 provided between the terminals T1 and T2 and an LC component 54 connected between the resistance components 52 and 53. The LC component 54 includes an inductance component 55, a capacitance component 56, and a resistance component 57. One end of the resistance component 52 is connected to the terminal T 1, and the other end of the resistance component 52 is connected to one end of the resistance component 53 and one end of the inductance component 55. The other end of the resistance component 53 is connected to the terminal T2. The other end of the inductance component 55 is connected to one end of the capacitance component 56 and one end of the resistance component 57. The other end of the capacitance component 56 and the other end of the resistance component 57 are grounded. The capacitance component 56 and the resistance component 57 are in a parallel relationship.

  The terminal T1 corresponds to one end A1 of the arrow A in FIG. The terminal T2 corresponds to the other end A2 of the arrow A in FIG. The resistance component 52 corresponds to the conductive layer 6 in FIG. The resistance component 53 corresponds to the conductive layer 6 in FIG. The inductance component 55 of the LC component 54 corresponds to the semiconductor substrate 2 in FIG. The capacitance component 56 and the resistance component 57 of the LC component 54 correspond to the semiconductor substrate 2 in FIG. The capacitance component 56 and the resistance component 57 are connected to the semiconductor substrate 2 and grounded.

  Also in the first modified example described above, the same effects as in the above embodiment are achieved. Furthermore, the semiconductor device 1A includes a wiring body 41 that is connected to the semiconductor substrate 2 and the conductive layer 6 and is provided so as to surround the circuit unit 3 on the main surface 2a. In this case, the microwave signal propagated from the output terminal 4 to the conductive layer 6 can be released to the outside through the wiring body 41 and the capacitance component 56 using the semiconductor substrate 2 as a dielectric. Thereby, characteristic deterioration of the semiconductor device 1A is suitably suppressed.

  FIG. 4A is a schematic plan view showing a semiconductor device 1B of the second modification. FIG. 4B is a sectional view taken along line IVb-IVb in FIG. As shown in FIGS. 4A and 4B, the input terminal 5A of the semiconductor device 1B is provided in the center on the side surface 2c side and faces the output terminal 4. Specifically, the position where the input terminal 5A is provided is point-symmetric with the position where the output terminal 4 is provided with respect to the center of the main surface 2a. For this reason, the straight line SL connecting the output terminal 4 and the input terminal 5A extends along the extending direction of the side surfaces 2d and 2e in plan view. The second recess 15A of the conductive layer 6 is recessed from the edge on the side surface 2c side toward the center.

  The slit 21A extends linearly from the side surface 2d toward the side surface 2e, and separates the conductive layer 6 into a first region 6a on the output terminal 4 side and a second region 6b on the input terminal 5A side. doing. In other words, the first region 6a and the second region 6b of the conductive layer 6 are separated by the slit 21A. Therefore, in the second modification, unlike the embodiment and the first modification, the third region 6c is not provided. The slit 21A is substantially orthogonal to the straight line SL.

  Also in the second modified example described above, the same effects as in the above embodiment are achieved. Further, the microwave signal flowing in the first region 6a is blocked by the slit 21A and does not propagate to the second region 6b. Therefore, since the microwave signal propagates through the conductive layer 6 and is not input to the input terminal 5A, the characteristic deterioration of the semiconductor device 1B is suitably suppressed. The semiconductor device 1 is mounted on a wiring board (not shown) for flip chip mounting. The plurality of third external terminals 9 of the semiconductor device 1 are electrically connected by a metal pattern on the wiring board. Thereby, each of the plurality of third external terminals 9 is electrically connected. Accordingly, the first region 6a and the second region 6b are separated, but are electrically connected to the plurality of third external terminals 9 via the metal pattern on the wiring board. For this reason, the conductive layer 6 can hold the reference potential.

  The semiconductor device according to the present invention is not limited to the above embodiment and the above modifications, and various other modifications are possible. You may combine suitably the description content of the said embodiment and the said modification. For example, the content of the first modification may be combined with the second modification. That is, a wiring body that connects the first region 6 a of the conductive layer 6 of the second modification and the semiconductor substrate 2 and surrounds a part of the circuit unit 3 may be provided. Moreover, you may combine the content of a 2nd modification with the said embodiment. That is, the slit 21B may be provided in the conductive layer 6 of the above embodiment.

  Moreover, in the said embodiment and the said modification, the shape of the slit provided in the conductive layer 6 may be any shape as long as it intersects the straight line SL. The slit provided in the conductive layer 6 may have a curved shape, a wavy shape, or a zigzag shape in plan view. In these cases, the length of the slit corresponds to the total distance from one end to the other end in the longitudinal direction. The slits in the embodiment and the first modification may extend, for example, from an edge on the side surface 2d side toward an edge on the side surface 2b side or an edge on the side surface 2c side. Further, the slit may extend from an edge on the side surface 2b side toward an edge on the side surface 2b side, an edge on the side surface 2c side, or an edge on the side surface 2d side. In addition, you may call the slit of the said embodiment and the said modification as an opening part, a groove | channel, a removal part, or a notch part.

  In the embodiment and the modification, one end and the other end of the slit in the longitudinal direction may be provided in the conductive layer 6. In addition, a plurality of slits may be provided in the conductive layer 6. In this case, it suffices that at least one slit intersects the straight line SL, and not all the slits intersect the straight line SL. When the wavelength of the microwave signal is λ, the length of the slit intersecting the straight line SL should be larger than λ / 8 and smaller than 3λ / 8, and the length of the other slits should be λ / 8 or less. However, it may be 3λ / 8 or more.

  In the embodiment and the modification, the straight line SL may not connect the shortest distance between the output terminal and the input terminal. The straight line SL may be a straight line connecting any one point of the output terminal and any one point of the input terminal. For example, the straight line SL may be a straight line connecting the center of the second region of the output terminal and the center of the second region of the input terminal, or may be a straight line connecting the maximum distance between the output terminal and the input terminal. .

  Moreover, in the said embodiment and the said modification, a semiconductor substrate may be other than a GaAs substrate. For example, the semiconductor substrate may be an AlN substrate, a SiC substrate, or the like. Further, the output terminal, the input terminal, the conductive layer, and the wiring body may be other than the Au layer. For example, the output terminal, the input terminal, the conductive layer, and the wiring body may be a plurality of stacked metal layers or alloy layers. Moreover, the insulating layer which embeds the circuit part 3 may be comprised with the inorganic insulator.

  The present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples. The measurement samples described in the following Examples 1 and 2 and Comparative Examples are hypothetical.

Example 1
FIG. 5A shows a plan view of the measurement sample 60 of Example 1. FIG. FIG. 5B is an enlarged view of the slit 21B in FIG. The measurement sample 60 shown in FIGS. 5A and 5B is an MMIC to which a microwave signal whose frequency is set to 38 GHz is input / output. The measurement sample 60 includes a semiconductor substrate 2 provided with a circuit portion embedded in an insulating layer, an output terminal 4, an input terminal 5, and a conductive layer 6 provided with a slit 21B having two bending points. Prepare. The conductive layer 6 is provided with a recess 16 connected to the slit 21 </ b> B in addition to the first recess 14 and the second recess 15. The recess 16 is provided with a power supply terminal 17, and the power supply terminal 17 is connected to a power supply wiring 18 extending along the shape of the slit 21B. The power supply wiring 18 overlaps with or is included in the slit 21 </ b> B and is connected to the power supply terminal 17. In addition, the conductive layer 6 is appropriately provided with a recess other than the first recess 14, the second recess 15, and the recess 16.

  In the measurement sample 60, the semiconductor substrate 2 is set to a GaAs substrate having a thickness of 275 μm and a relative dielectric constant of 12.9. In addition, when the semiconductor substrate 2 is viewed in plan, the length of the side surfaces 2b and 2c is set to 2270 μm, and the length of the side surfaces 2d and 2e is set to 1630 μm. The output terminal 4, the input terminal 5, and the conductive layer 6 are set to an Au layer having a thickness of 2 μm. The width W of the slit 21B is set to 20 μm, and the length L of the slit 21B is set to 1550 μm. The power supply wiring 18 is set to an Au layer having a width of 15 μm and a thickness of 1 μm. A via wiring connecting the power wiring 18 and the power terminal 17 is set to an Au layer having a thickness of 1.5 μm. The insulating layer for embedding the circuit portion is set to a plurality of polyimide layers. The total thickness of the insulating layer is set to 10.9 μm, and the non-dielectric constant of the insulating layer is set to 3.5. The output terminal 4 and the input terminal 5 are set in a state of being electrically insulated from each other.

(Example 2)
The measurement sample of Example 2 is provided with the wiring body 41 having the wiring layers 42 to 44 and the via wirings 45 to 48 shown in FIG. 2B with respect to the measurement sample 60 of Example 1. is there. Specifically, the wiring layers 42 to 44 of the wiring body 41 are provided along the outer edge of the conductive layer 6. In the measurement sample of Example 2, the thickness of the wiring layers 42 to 44 is set to 1 μm, the thickness of the via wiring 45 is set to 1.4 μm, and the thickness of the via wirings 46 to 48 is 1. Set to 5 μm.

(Comparative example)
In the measurement sample of the comparative example, the slit 21 </ b> B is not formed in the conductive layer 6 with respect to the measurement sample 60 of Example 1.

(Isolation characteristics simulation results)
The measurement samples of Examples 1 and 2 and the comparative example are placed on a base made of alumina and set to a state in which no external noise is input. After setting these measurement samples to the above-described conditions, the isolation characteristics of each measurement sample were simulated. Specifically, the isolation characteristic of each measurement sample to which a signal having a frequency of 35 to 39 GHz was input was simulated. The isolation characteristic is represented by a ratio (decibel (dB)) between input power and output power, and indicates the degree of signal leakage. It is evaluated that the smaller the value of the isolation characteristic, the less the signal is fed back from the output terminal to the input terminal.

  FIG. 6 is a graph showing a simulation result of the isolation characteristics of the measurement sample. A graph 71 shown in FIG. 6 shows the simulation result of Example 1, a graph 72 shows the simulation result of Example 2, and a graph 73 shows the simulation result of the comparative example. As shown in FIG. 6, the isolation characteristics of Examples 1 and 2 were smaller than the isolation characteristics of the comparative example. Specifically, when a 38 GHz signal was input, Example 1 showed -57.1 dB, Example 2 showed -67.4 dB, and Comparative Example showed -49.8 dB. Accordingly, it can be inferred that a signal which propagates through the conductive layer 6 and is to be returned is blocked by the slit 21B, and the isolation characteristic becomes small. Further, the isolation characteristic of Example 2 was smaller than the isolation characteristic of Example 1. Thereby, it can be inferred that a signal which propagates through the conductive layer 6 and is to be returned is radiated to the outside through the wiring body 41 and the semiconductor substrate 2 and the isolation characteristic is further reduced.

(Electromagnetic field simulation)
For each measurement sample, the electric field distribution of the conductive layer 6 when a signal with a frequency of 38 GHz was input under the same conditions as the measurement of the isolation characteristics was simulated. In this case, the electric field density around the output terminal 4 in Examples 1 and 2 was lower than the electric field density around the output terminal 4 in the comparative example. In addition, the electric field density around the input terminal 5 in Example 2 was lower than the electric field density around the input terminal 5 in Example 1.

  DESCRIPTION OF SYMBOLS 1,1A, 1B ... Semiconductor device, 2 ... Semiconductor substrate, 2a ... Main surface, 2b-2e ... Side surface, 3 ... Circuit part, 4 ... Output terminal, 5, 5A ... Input terminal, 6 ... Conductive layer, 6a ... 1st 1 region, 6b ... 2nd region, 6c ... 3rd region, 11 ... insulating layer, 14 ... 1st recessed part, 15, 15A ... 2nd recessed part, 17 ... power supply terminal, 18 ... power supply wiring, 21, 21A, 21B ... Slit, 21a ... one end, 21b ... the other end, 31, 41 ... wiring body, 32-34, 42-44 ... wiring layer, 35-38, 45-48 ... via wiring, 54 ... LC component, 60 ... sample for measurement , A ... arrow, L ... length, SL ... straight line, λ ... wavelength.

Claims (6)

A semiconductor device to which microwave signals are input and output,
A semiconductor substrate having a main surface, a first side surface, and a second side surface;
A circuit portion provided on the main surface;
An output terminal provided on the first side surface on the circuit unit and connected to the circuit unit;
An input terminal provided on the second side surface on the circuit unit and connected to the circuit unit;
A conductive layer provided on the circuit portion to which a reference potential is input;
With
The conductive layer is provided with a slit extending so as to intersect a straight line connecting the output terminal and the input terminal in plan view.
Semiconductor device. The semiconductor substrate further includes a third side surface facing the second side surface,
The second side surface is adjacent to the first side surface;
The semiconductor device according to claim 1, wherein the slit is provided so as to extend from an edge of the second side surface in the conductive layer toward the third side surface side.   The semiconductor device according to claim 1, wherein the slit separates the conductive layer into a first region on the output terminal side and a second region on the input terminal side.   The semiconductor device according to claim 1, wherein when the wavelength of the microwave signal is λ, the length of the slit is greater than λ / 8 and smaller than 3λ / 8.   The semiconductor device according to claim 1, further comprising a power supply wiring provided to overlap the slit. The wiring body further includes a wiring body connected to the semiconductor substrate and the conductive layer and provided to surround the circuit portion on the main surface,
6. The wiring body according to claim 1, wherein the wiring body includes a plurality of wiring layers that are connected to each other and stacked on each other, and is electrically insulated from the input terminal and the output terminal. A semiconductor device according to 1.

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