JP2017069474A - Circuit board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board in which connection reliability of a heat transfer block and a via conductor can be enhanced, and to provide a manufacturing method therefor.SOLUTION: A circuit board 10 has a core substrate 11, a cavity 16 penetrating the core substrate 11, a heat transfer block 17 housed in the cavity 16, build-up layers 20, 20 laminated on the front and back of the core substrate 11, and covering both sides of the cavity 16 and heat transfer block 17, and a via conductor 21D provided in the innermost insulation resin layer 21 of the build-up layers 20, 20, and connecting with the heat transfer block 17. The heat transfer block 17 has a heat transfer foil 17M composed of a heat transfer material, and a metal plating layer 17N formed on at least one of the front and back of the heat transfer foil 17M.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a circuit board in which a heat transfer block is accommodated in a cavity formed in a core substrate, and a manufacturing method thereof.

  Conventionally, as this type of circuit board, one in which a heat conductive block is connected to a via conductor of a buildup layer and used for heat dissipation is known (for example, see Patent Document 1).

JP 2013-135168 (paragraphs [0009] and [0010])

  In the above-described conventional circuit board, if the connection between the heat conductive block and the via conductor becomes weak, it is considered that the heat dissipation function is lowered.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board capable of improving the connection reliability between a heat conductive block and a via conductor and a method for manufacturing the circuit board.

  The invention according to claim 1 made to achieve the above object is laminated on the front and back of the core substrate, the core substrate, the cavity penetrating the core substrate, the heat conductive block accommodated in the cavity, A circuit board having a buildup layer that covers both surfaces of the cavity and the heat transfer block, and a via conductor that is provided on the innermost insulating resin layer of the buildup layer and is connected to the heat transfer block. The heat transfer block is a heat transfer foil made of a heat transfer material, and a metal plating layer formed on at least one of the front and back surfaces of the heat transfer foil, to which the via conductor is connected, Have

The top view of the circuit board concerning a 1st embodiment of the present invention. Plan view of product area on circuit board FIG. 2 is a side sectional view of the circuit board taken along the line AA of FIG. Enlarged side sectional view of metal block Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing the manufacturing process of metal block Side sectional view of PoP including circuit board Side sectional view of the circuit board of the second embodiment Side sectional view of the circuit board of the third embodiment Side sectional view which shows the manufacturing process of the metal block which concerns on 3rd Embodiment Plan view of product area in circuit board according to modification Side sectional view of circuit board according to modification

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. As shown in the plan view of FIG. 1, the circuit board 10 according to the present embodiment has, for example, a frame-shaped discarding region R1 along the outer edge, and the inside of the discarding region R1 is a plurality of squares. It is partitioned into product areas R2. 2 shows one product region R2 in an enlarged manner, and FIG. 3 shows an enlarged cross-sectional structure of the circuit board 10 obtained by cutting the product region R2 along a diagonal line.

  As shown in FIG. 3, the circuit board 10 has a structure having build-up layers 20 and 20 on both front and back surfaces of the core board 11. The core substrate 11 is made of an insulating member. Conductor circuit layers 12 are respectively formed on an F surface 11 </ b> F that is a surface on the front side of the core substrate 11 and a B surface 11 </ b> B that is a surface on the back side of the core substrate 11. Further, the core substrate 11 is formed with a cavity 16 and a plurality of conductive through holes 14.

  The through-holes for conduction 14 communicated with the small-diameter side ends of the tapered holes 14A and 14A, which are perforated from both the F surface 11F and the B surface 11B of the core substrate 11 and gradually reduced in diameter toward the back side. Has an intermediate constricted shape. On the other hand, the cavity 16 has a shape having a rectangular parallelepiped space.

  A plurality of through-hole conductive conductors 15 are formed in each through-hole 14 for conduction to form a plurality of through-hole conductive conductors 15, and the conductive circuit layer 12 on the F surface 11 F and the conductive circuit layer 12 on the B surface 11 B are formed by these through-hole conductive conductors 15. Is connected.

  The cavity 16 accommodates a metal block 17 (corresponding to the “heat transfer block” of the present invention). The metal block 17 is a rectangular parallelepiped made of copper, for example, and the planar shape of the metal block 17 is slightly smaller than the planar shape of the cavity 16. Further, the thickness of the metal block 17, that is, the distance between the first main surface 17 </ b> F that is one surface of the metal block 17 and the second main surface 17 </ b> B that is the other surface of the metal block 17. Is substantially the same as the distance between the outermost surfaces of the conductor circuit layers 12, 12 on the front and back of the core substrate 11. The first main surface 17F of the metal block 17 is substantially flush with the outermost surface of the conductor circuit layer 12 on the F surface 11F of the core substrate 11, while the second main surface 17B of the metal block 17 is B of the core substrate 11. The surface 11B is substantially flush with the outermost surface of the conductor circuit layer 12. A gap between the metal block 17 and the inner surface of the cavity 16 is filled with a filling resin 16J.

  As shown in FIG. 3, both the build-up layer 20 on the F surface 11F side and the build-up layer 20 on the B surface 11B side of the core substrate 11 are in order from the core substrate 11 side, insulative resin layer 21 and conductor layer 22. A solder resist layer 23 is laminated on the conductor layer 22. In addition, a plurality of via holes 21H are formed in the insulating resin layer 21, and the via holes 21H have a tapered shape with a diameter gradually reduced toward the core substrate 11 side. Further, the via holes 21H are filled with plating to form a plurality of via conductors 21D. The via conductors 21D connect the conductor circuit layer 12 and the conductor layer 22 and the metal block 17 and the conductor layer 22. The metal block 17 is connected to the conductor layers 22 and 22 via the four via conductors 21D on both the first main surface 17F side and the second main surface 17B side. Here, the diameter (top diameter) of the via conductor 21D that connects the conductor circuit layer 12 and the conductor layer 22 and the diameter (top diameter) of the via conductor 21D that connects the metal block 17 and the conductor layer 22. May be substantially the same, but may be different.

  As shown in FIG. 3, a plurality of pad holes are formed in the solder resist layer 23, and a part of the conductor layer 22 is located in the pad hole and becomes a pad 26. In the F surface 10F of the circuit board 10, which is the outermost surface of the buildup layer 20 on the F surface 11F of the core substrate 11, a plurality of pads 26 are arranged in two rows along the outer edge portion of the product region R2. The pad 26A group and the small pad 26C group arranged in a plurality of vertical and horizontal rows in an inner region surrounded by the middle pad 26A group. Further, an electronic component mounting portion 26J is composed of the small pads 26C group. Further, for example, as shown in FIG. 2, four small pads 26C arranged on the diagonal line of the product region R2 at the center of the small pad 26C group, and parallel to the diagonal line next to the row of the four small pads 26C. The metal block 17 is disposed at a position directly below the seven small pads 26C, including the three small pads 26C arranged side by side. Of the seven small pads 26C, as shown in FIG. 3, for example, four small pads 26C are connected to the metal block 17 via four via conductors 21D.

  On the B surface 10B of the circuit board 10, which is the outermost surface of the buildup layer 20 on the B surface 11B of the core substrate 11, a large pad 26B larger than the middle pad 26A constitutes a substrate connecting portion, and four via conductors 21D. It is connected to the metal block 17 via.

  Next, the metal block 17 will be described in detail based on the enlarged view shown in FIG. The metal block 17 of this embodiment has a copper plating layer 17N (corresponding to the “metal plating layer” of the present invention) on both sides of the rolled copper foil 17M (corresponding to the “heat transfer foil” of the present invention). Do it. The contact surface between the rolled copper foil 17M and the copper plating layer 17N has an arithmetic average roughness Ra of 0.1 [μm] to 3.0 [μm] (according to the definition of JIS B 0601-1994). ). The first main surface 17F and the second main surface 17B of the metal block 17 (that is, the outermost surfaces of the copper plating layers 17N and 17N on the front and back surfaces of the metal block 17) also have an arithmetic average roughness Ra of 0.1 [μm]. It has a rough surface of ˜3.0 [μm]. The first main surface 17F and the second main surface 17B of the metal block 17 have substantially the same area and are parallel to each other. Further, the side surface of the metal block 17 is orthogonal to the first main surface 17F and the second main surface 17B and is substantially flat.

The circuit board 10 of this embodiment is manufactured as follows.
(1) As shown in FIG. 5 (A), an insulating base 11K made of a reinforcing material such as epoxy resin or BT (bismaleimide triazine) resin and glass cloth, and laminated with copper foil 11C on both sides. Is prepared.

  (2) As shown in FIG. 5B, a tapered hole 14A for forming a conductive through hole 14 (see FIG. 3) by irradiating the insulating base material 11K with, for example, a CO2 laser from the F surface 11F side. Perforated.

  (3) As shown in FIG. 5C, CO2 laser is irradiated to a position directly behind the aforementioned tapered surface 14A on the F surface 11F side of the B surface 11B of the insulating base material 11K, so that the tapered hole 14A is formed. The conductive through hole 14 is formed from the tapered holes 14A and 14A.

  (4) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 11 </ b> C and the inner surface of the conductive through hole 14.

  (5) As shown in FIG. 5D, a predetermined pattern of plating resist 33 is formed on the electroless plating film on the copper foil 11C.

  (6) The electrolytic plating process is performed, and as shown in FIG. 6A, the electrolytic plating is filled in the conductive through holes 14 to form the through-hole conductive conductors 15 and the copper foil 11C on the copper foil 11C. An electrolytic plating film 34 is formed on a portion of the electrolytic plating film (not shown) exposed from the plating resist 33.

  (7) The plating resist 33 is peeled off, and the electroless plating film (not shown) and the copper foil 11C below the plating resist 33 are removed. As shown in FIG. The conductive circuit layer 12 is formed on the F surface 11F of the core substrate 11 and the conductive circuit layer 12 is formed on the B surface 11B of the core substrate 11 by the film 34, the electroless plating film, and the copper foil 11C. Then, the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the B surface 11B are connected by the through-hole conductive conductor 15.

  (8) As shown in FIG. 6C, the cavity 16 is formed in the core substrate 11 by a router or a CO2 laser.

  (9) As shown in FIG. 6D, a tape 90 made of a PET film is stuck on the F surface 11 </ b> F of the core substrate 11 so that the cavity 16 is closed.

  (10) A metal block 17 manufactured by a method described later is prepared.

  (11) As shown in FIG. 7A, the metal block 17 is stored in the cavity 16 with the first main surface 17F facing down by a mounter (not shown).

  (12) As shown in FIG. 7B, a prepreg as an insulating resin layer 21 on the conductive circuit layer 12 on the B surface 11B of the core substrate 11 (a B-stage resin sheet formed by impregnating a core material with a resin) And the copper foil 37 are laminated and then heated and pressed. At that time, the space between the conductor circuit layers 12 and 12 on the B surface 11B of the core substrate 11 is filled with the prepreg, and the thermosetting resin exuded from the prepreg is filled in the gap between the inner surface of the cavity 16 and the metal block 17. Is done.

  (13) As shown in FIG. 7C, the tape 90 is removed.

  (14) As shown in FIG. 7D, the prepreg as the insulating resin layer 21 and the copper foil 37 are laminated on the conductor circuit layer 12 on the F surface 11F of the core substrate 11, and then heated and pressed. At that time, the space between the conductor circuit layers 12 and 12 on the F surface 11F of the core substrate 11 is filled with the prepreg, and the thermosetting resin exuded from the prepreg is filled in the gap between the inner surface of the cavity 16 and the metal block 17. Is done. In addition, the above-described filling resin 16J is formed by the thermosetting resin that oozes out from the prepreg of the F surface 11F and the B surface 11B of the core substrate 11 and fills the gap between the inner surface of the cavity 16 and the metal block 17.

  Insulating resin layer 21 may be a resin film that does not contain a core material instead of prepreg. In that case, a conductor circuit layer can be directly formed on the surface of the resin film by a semi-additive method without laminating a copper foil.

  (15) As shown in FIG. 8A, the insulating resin layers 21 and 21 on both sides of the core substrate 11 formed by the prepreg described above are irradiated with CO2 laser to form a plurality of via holes 21H. . Some of the via holes 21H of the plurality of via holes 21H are arranged on the conductor circuit layer 12, and the other part of the via holes 21H are arranged on the metal block 17. When forming the via hole 21H on the metal block 17, the rough surface of the metal block 17 located on the back side of the via hole 21H may be eliminated by laser light irradiation or desmear treatment after irradiation.

  (16) An electroless plating process is performed, and electroless plating films (not shown) are formed on the insulating resin layers 21 and 21 and in the via holes 21H and 21H.

  (17) As shown in FIG. 8B, a predetermined pattern of plating resist 40 is formed on the electroless plating film on the copper foil 37.

  (18) The electrolytic plating process is performed, and as shown in FIG. 8C, the plating is filled in the via holes 21H and 21H to form the via conductors 21D and 21D. Further, on the insulating resin layers 21 and 21 Electroless plating films 39 and 39 are formed on portions of the electroless plating film (not shown) exposed from the plating resist 40.

  (19) The plating resist 40 is peeled off, and the electroless plating film (not shown) and the copper foil 37 below the plating resist 40 are removed. As shown in FIG. The conductor layer 22 is formed on each insulating resin layer 21 on the front and back of the core substrate 11 by the film 39, the electroless plating film and the copper foil 37. A part of each conductor layer 22 on the front and back of the core substrate 11 and the conductor circuit layer 12 are connected by the via conductor 21D, and another part of each conductor layer 22 and the metal block 17 are connected by the via conductor 21D. Connected.

  (20) As shown in FIG. 9B, solder resist layers 23, 23 are laminated on the respective conductor layers 22 on the front and back of the core substrate 11.

  (21) As shown in FIG. 10, tapered pad holes are formed at predetermined locations of the solder resist layers 23, 23 on the front and back of the core substrate 11. The portion exposed from the hole becomes the pad 26.

  (22) On the pad 26, a nickel layer, a palladium layer, and a gold layer are laminated in this order to form the metal film 41 shown in FIG. Thus, the circuit board 10 is completed. Note that a tin layer may be formed as the metal film 41. Further, instead of the metal film 41, surface treatment with OSP (preflux) may be performed.

  Next, the manufacturing method of the metal block 17 is demonstrated based on FIG.

  (1) A rolled copper foil 50 is prepared.

  (2) The rolled copper foil 50 is immersed in an acid solution (for example, an acid containing sulfuric acid and hydrogen peroxide as main components) stored in a storage tank for a predetermined time, and then washed with water. Thereby, as shown to FIG. 11 (A), both surfaces of the front and back of the rolled copper foil 50 become a rough surface.

  (3) An electrolytic plating process is performed, and a copper plating layer 51 is formed on the rolled copper foil 50 as shown in FIG.

  (4) The metal plate 52 is immersed in an acid solution (for example, an acid containing sulfuric acid and hydrogen peroxide as main components) stored in a storage tank for a predetermined time, and then washed with water. As a result, as shown in FIG. 11C, both the front and back surfaces of the metal plate 52 (that is, the outermost surfaces of the copper plating layers 51, 51) become rough surfaces.

  (5) The metal plate 52 is mechanically divided by a mold or a router, and the metal block 17 is formed as shown in FIG.

This completes the description of the structure and manufacturing method of the circuit board 10 of the present embodiment. Next, the effect of the circuit board 10 will be described together with an example of use of the circuit board 10. The circuit board 10 of this embodiment is used as follows, for example. That is, as shown in FIG. 12, on the aforementioned large, medium, and small pads 26B, 26A, and 26C that the circuit board 10 has, large, medium, and small solder bumps 27B that match the sizes of these pads. 27A and 27C are formed. Then, for example, a CPU 80 having a pad group arranged on the lower surface in the same manner as the small pad group on the F surface 10F of the circuit board 10 is mounted on the small solder bump 27C group in each product region R2 and soldered. A first package substrate 10P is formed. At this time, the CPU 80 has, for example, a ground 4
One pad is connected to the metal block 17 of the circuit board 10 via the via conductor 21D.

  Next, a second package substrate 82P formed by mounting the memory 81 on the F surface 82F of the circuit board 82 is disposed on the first package substrate 10P from above the CPU 80, and the circuit board 82 in the second package substrate 82P is disposed. PoP 83 (Package on Package 83) is formed by soldering the intermediate solder bumps 27A of the circuit board 10 in the first package substrate 10P to the pads provided on the B surface 82B. Note that a resin (not shown) is filled between the circuit boards 10 and 82 in the PoP 83.

  Next, the PoP 83 is disposed on the mother board 84, and the large solder bumps 27B of the circuit board 10 in the PoP 83 are soldered to the pad group of the mother board 84. At this time, for example, a ground pad included in the motherboard 84 is soldered to the pad 26 connected to the metal block 17 in the circuit board 10. When the CPU 80 and the motherboard 84 have pads dedicated for heat dissipation, the pads dedicated for heat dissipation and the metal block 17 of the circuit board 10 may be connected by via conductors 21D.

  When the CPU 80 generates heat, the heat is transferred to the metal block 17 via the via conductor 21D included in the buildup layer 20 on the F surface 10F side of the circuit board 10 on which the CPU 80 is mounted, and the B surface 10B of the circuit board 10 is obtained. Heat is radiated from the metal block 17 to the mother board 84 via the via conductors 21D included in the build-up layer 20 on the side.

  Here, if the difference between the distance between the outermost surfaces of the conductor circuit layers 12 and 12 on the front and back sides of the core substrate 11 and the thickness of the metal block 17 is large, the plating into the via hole 21H is not sufficiently filled, and the metal block It is conceivable that the connection between the via 17 and the via conductor 21 </ b> D is weakened and disconnected, and heat dissipation through the metal block 17 is hindered. Moreover, since the connection surface of the metal block 17 and the via conductor 21D becomes small due to the length of the via conductor 21D, it is conceivable that the heat conduction is not sufficiently performed or the reliability of the connection is lowered.

  On the other hand, in the circuit board 10 of the present embodiment, the metal block 17 is configured by forming the copper plating layers 17N on both the front and back surfaces of the rolled copper foil 17M, so the thickness of the metal block 17 is adjusted. It is easy to do. Thereby, the difference between the distance between the outermost surfaces of the conductor circuit layers 12 and 12 on the front and back sides of the core substrate 11 and the thickness of the metal block 17 can be reduced, and the above-described problem can be prevented. Furthermore, in the circuit board 10 of the present embodiment, the thickness of the metal block 17 is substantially the same as the distance between the outermost surfaces of the conductor circuit layers 12 and 12 on the front and back of the core substrate 11, and therefore the via conductor 21D and The connectivity with the metal block 17 is further improved. Further, the via conductor 21D and the copper plating layer 17N of the metal block 17 are both made of copper plating, and the connection between them is strengthened. Further, since the contact surface between the rolled copper foil 17M and the copper plating layer 17N is a rough surface, the degree of adhesion between the rolled copper foil 17M and the copper plating layer 17N is increased, and the peeling of the copper plating layer 17N is prevented. .

  In the metal block 17 of the present embodiment, the rolled copper foil 17M is used as the “heat transfer foil” of the present invention, but an electrolytic copper foil may be used. In this case, it is conceivable to make the electrolytic copper foil a necessary thickness at the time of producing the electrolytic copper foil, but as the thickness of the copper foil increases, it becomes difficult to obtain by an electrolytic method. After obtaining, it is preferable to adjust by metal plating. In addition, since the rolled copper foil is generally cheaper than the electrolytic copper foil, the cost is reduced by using the rolled copper foil 50 as in the present embodiment.

  By the way, the circuit board 10 repeats thermal expansion and contraction depending on whether or not the CPU 80 is used. Then, due to the difference in thermal expansion / contraction rate between the metal block 17 and the insulating resin layer 21 and the filling resin 16J, there is a concern that the via conductor 21D is peeled off from the metal block 17 together with the insulating resin layer 21. However, in the circuit board 10 of the present embodiment, both the front and back surfaces (the first main surface 17F and the second main surface 17B) of the metal block 17 are rough, so that the metal block 17 and the insulating resin layers 21 and 21 are rough. And the fixation with the filling resin 16J in the cavity 16 can be further strengthened.

[Second Embodiment]
The circuit board 10V of this embodiment is shown in FIG. The circuit board 10 </ b> V is provided with a plurality of cavities 32 that accommodate a multilayer ceramic capacitor 30 in the vicinity of the cavity 16 that accommodates the metal block 17. The multilayer ceramic capacitor 30 has a structure in which, for example, both ends of a ceramic prismatic body are covered with a pair of electrodes 31, 31. In addition, each multilayer ceramic capacitor 30 has a first plane 31F of each electrode 31 of the multilayer ceramic capacitor 30 that is flush with the outermost surface of the conductor circuit layer 12 on the F surface 11F side of the core substrate 11, similarly to the metal block 17. In addition, the second flat surface 31B of each electrode 31 of the multilayer ceramic capacitor 30 is flush with the outermost surface of the conductor circuit layer 12 on the B surface 11B side of the core substrate 11, and is arranged below the electronic component mounting portion 26J. Has been. The via conductors 21 </ b> D included in the build-up layers 20, 20 on the front and back surfaces of the core substrate 11 are connected to the electrodes 31 of the respective multilayer ceramic capacitors 30. When the circuit board 10V is manufactured, the metal block 17 and the multilayer ceramic capacitor 30 are accommodated in the cavities 16 and 32 in the same process.

[Third Embodiment]
In the circuit board 10W of the present embodiment, as shown in FIG. 14, the side surface of the metal block 17W is a groove-shaped side surface 17A that is curved so as to become deeper toward the center. Thereby, the contact area with the filling resin 16J can be made larger than that in which the side surface of the metal block 17 is a flat surface, and the fixing strength can be made higher than in the past.

  The metal block 17W is manufactured, for example, as follows.

  (1) The metal plate 52 is prepared by the method shown in the first embodiment.

  (2) As shown in FIG. 15A, a predetermined pattern of etching resist 60 is formed on the front and back surfaces of the metal plate 52.

  (3) As shown in FIG. 15B, the portion of the metal plate 52 exposed from the etching resist 60 is half-etched by the etching process.

  (4) As shown in FIG. 15C, the metal plate 52 is attached to the support member 61.

  (5) As shown in FIG. 15D, the portion of the metal plate 52 exposed from the etching resist 60 is cut by an etching process. Thereby, the metal block 17W is formed. The etching process is performed until the side surface of the metal block 17W becomes the groove-shaped side surface 17A. That is, both the division and the formation of the groove-shaped side surface 17A are performed by a single etching process.

  (6) As shown in FIG. 15E, after the support member 61 is removed, the etching resist 60 is peeled off.

  (7) The metal block 17W is dried.

Here, when the processing from the metal plate 52 to the metal block 17W is performed by pressing or the like, the outer edge portion of the metal block 17 is sagging and the portion protruding from the first main surface 17F or the second main surface 17B is the conductor layer 22. May cause short circuit. On the other hand, in the circuit board 10 of the present embodiment, since the processing from the metal plate 52 to the metal block 17W is performed by etching, the outer edge of the metal block 17W is the first main surface 17F or the second main surface 17B. Further protrusion can be prevented, and occurrence of a short circuit can be prevented.
[Other Embodiments]

  The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various modifications are possible within the scope of the invention other than the following. It can be changed and implemented.

  (1) In the above embodiment, the copper plating layer 51 is formed on the rolled copper foil 50 and then divided into the metal blocks 17. However, after the rolled copper foil 50 is divided, the copper plating layer is formed. May be. In this case, the entire surface of the metal block 17 is covered with the copper plating layer 17N.

  (2) In the above embodiment, the formation of the rough surfaces on the front and back surfaces of the metal block 17 is performed before the metal plate 52 is divided, but may be performed after the division. In this case, all the surfaces of the metal block 17 (that is, the first main surface 17F, the second main surface 17B, and the side surfaces) are roughened.

  (3) In the above embodiment, the surface is roughened with an acid. However, the surface may be roughened by, for example, spraying particles or pressing an uneven surface.

  (4) In the second embodiment, the multilayer ceramic capacitor 30 is housed in the cavity 32. However, the multilayer ceramic capacitor 30 is not a multilayer ceramic capacitor 30, but other electronic components such as capacitors, resistors, thermistors, coils, and the like. In addition to passive components, active components such as IC circuits may be used.

  (5) The planar shape of the metal block 17 of the above embodiment is rectangular, but it may be other polygonal shapes, may be circular as shown in FIG. It may be oval.

  (6) In the above embodiment, the “heat transfer block” of the present invention is the copper metal block 17. However, the heat transfer block may be made of, for example, copper mixed with molybdenum or tungsten, or aluminum. The heat transfer material such as graphite may be used instead of metal.

  (7) In the above embodiment, the thickness of the metal block 17 is substantially the same as the distance between the outermost surfaces of the conductor circuit layers 12, 12 on the front and back of the core substrate 11. The distance between the outermost surfaces of the layers 12 and 12 may be larger or smaller as shown in FIG. In the circuit board 10 shown in FIG. 17, the first main surface 17F of the metal block 17 is substantially flush with the outermost surface of the conductor circuit layer 12 on the F surface 11F of the core substrate 11, while the second main surface of the metal block 17 is. The surface 17B is positioned above the outermost surface of the conductor circuit layer 12 in the B surface 11B of the core substrate 11. Even in this case, the thickness of the metal block 17 and the distance between the outermost surfaces of the conductor circuit layers 12 and 12 on the front and back of the core substrate 11 are larger than those in which the metal block 17 is composed only of the rolled copper foil 17M. The difference can be reduced, and the connection reliability can be improved.

  (8) In the metal block 17 of the above embodiment, the copper plating layer 17N is formed on both the front and back surfaces of the rolled copper foil 17M, but may be formed only on the front surface or the back surface of the rolled copper foil 17M.

10, 10V, 10W Circuit board 12 Conductor circuit layer 16, 32 Cavity 17, 17W Metal block (Heat transfer block)
17M Rolled copper foil (heat transfer foil)
17N copper plating layer (metal plating layer)
20 Build-up Layer 21 Insulating Resin Layer 21D Via Conductor 22 Conductor Layer 30 Multilayer Ceramic Capacitor (Electronic Component)
50 Rolled copper foil 51 Copper plating layer (metal plating layer)
52 Metal plate

Claims (17)

A core substrate;
A cavity penetrating the core substrate;
A heat conductive block housed in the cavity;
A build-up layer that is laminated on the front and back of the core substrate and covers both the front and back of the cavity and the heat conductive block;
A circuit board having a via conductor provided on the innermost insulating resin layer of the buildup layer and connected to the heat conductive block;
The heat transfer block includes a heat transfer foil made of a heat transfer material, and a metal plating layer formed on at least one of the front and back surfaces of the heat transfer foil and connected to the via conductor. . The circuit board according to claim 1,
The via conductor and the metal plating layer are made of copper plating. The circuit board according to claim 1 or 2,
Both the front and back surfaces covered with the build-up layer of the heat conductive block are rough. The circuit board according to claim 3,
The side surface which connects between the outer edge part of a surface and the outer edge part of a back surface among the said heat conductive blocks is a rough surface. A circuit board according to any one of claims 1 to 4,
The contact surface between the heat transfer foil and the metal plating layer is a rough surface. A circuit board according to any one of claims 1 to 5,
The heat transfer foil is made of a rolled copper foil. A circuit board according to any one of claims 1 to 6,
The metal plating layer is provided on both the front and back surfaces of the heat transfer foil. The circuit board according to claim 7,
The via conductors are connected to both the front and back surfaces of the heat conductive block. The circuit board according to claim 7 or 8,
The said metal plating layer is provided in the side surface which connects between the outer edge part of a surface, and the outer edge part of a back surface among the said heat-transfer foil. A circuit board according to any one of claims 1 to 9,
Having a conductor circuit layer laminated on both front and back surfaces of the core substrate;
The difference between the distance between the outermost surfaces of the conductor circuit layers on the front and back of the core substrate and the thickness of the heat conductive block is the distance between the outermost surfaces of the conductor circuit layers on the front and back of the core substrate and the heat transfer foil. Smaller than the difference in thickness. The circuit board according to claim 10,
The thickness of the heat conductive block is substantially the same as the distance between the outermost surfaces of the conductor circuit layers on the front and back of the core substrate. The circuit board according to claim 10,
The thickness of the heat conductive block is smaller than the distance between the outermost surfaces of the conductor circuit layers on the front and back of the core substrate. A circuit board according to any one of claims 1 to 12,
A plurality of the cavities penetrating the core substrate;
The thermally conductive block housed in any of the cavities;
And any other electronic component housed in the cavity. Forming a cavity in the core substrate;
Preparing a heat transfer block;
Accommodating the thermally conductive block in the cavity;
Laminating build-up layers on the front and back of the core substrate to cover the cavity and the heat conductive block;
In the innermost insulating resin layer of the build-up layer, providing a via conductor connected to the heat conductive block,
The heat transfer block includes a heat transfer foil made of a heat transfer material, and a metal plating layer formed on at least one of the front and back surfaces of the heat transfer foil and connected to the via conductor. To do. A method for manufacturing a circuit board according to claim 14,
Preparation of the heat transfer block
Preparing rolled copper foil,
Forming metal plating layers on both sides of the rolled copper foil;
Cutting the rolled copper foil having the metal plating layer on both front and back surfaces. A method of manufacturing a circuit board according to claim 15,
Before forming the metal plating layer on the rolled copper foil, the method includes roughening both the front and back surfaces of the rolled copper foil. A method for manufacturing a circuit board according to claim 15 or 16,
Before cutting the rolled copper foil having the metal plated layers on both sides, the method includes roughening the metal plated layers on both sides of the rolled copper foil.

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