JP2017055306A - Level shift circuit and driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a signal transfer characteristic.SOLUTION: In an embodiment, a level shift circuit includes a first to an eighth transistors. The first and the second transistors are a first conduction type, and the third to the eighth transistors are a second conduction type. The first transistor is connected to a first node to which a first voltage is supplied, and controlled with an input signal. The third transistor is connected between a third node which outputs a first output signal, and the first transistor. The fourth transistor is connected between a second node to which a second voltage, different from the first voltage, is supplied, and the third node, and controlled with a second output signal. The seventh transistor is provided in parallel to the third and the fourth transistors, and controlled with the second output signal.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a level shift circuit and a driver circuit.

  In recent years, with the demand for lower power consumption and higher functionality of devices, the power supply voltage of integrated circuits such as CPUs has been reduced. On the other hand, a high power supply voltage may be required in a conventionally used system or a system that handles analog signals. When systems operating with different power supply voltages are mixed, a level shift circuit is used to transmit signals between systems. For example, in a driver stage of a motor driver or a DC-DC converter, a control signal generated by a low withstand voltage block such as a control circuit is level-shifted using a level shift circuit, and the level-shifted signal is converted to a high level such as a switch element. It is transmitted to the pressure block.

  As the motor control becomes more precise and the frequency of the DC-DC converter becomes higher, it is required to improve the signal transmission characteristics of the level shift circuit.

JP 2012-33987 A

  The problem to be solved by the present invention is to provide a level shift circuit and a driver circuit that can improve signal transmission characteristics.

  According to the embodiment, the level shift circuit includes a first conductivity type first transistor, a first conductivity type second transistor, a second conductivity type third transistor, and a second conductivity type fourth transistor. , A second conductivity type fifth transistor, a second conductivity type sixth transistor, a second conductivity type seventh transistor, and a second conductivity type eighth transistor. The first transistor is connected to a first node to which a first voltage is supplied and is controlled by an input signal. The second transistor is connected to the first node and controlled by an inverted signal of the input signal. The third transistor is connected between a third node that outputs a first output signal and the first transistor. The fourth transistor is connected between a second node to which a second voltage different from the first voltage is supplied and the third node, and is controlled by a second output signal. The fifth transistor is connected between a fourth node that outputs the second output signal and the second transistor. The sixth transistor is connected between the second node and the fourth node, and is controlled by the first output signal. The seventh transistor is provided in parallel with the third and fourth transistors and is controlled by the second output signal. The eighth transistor is provided in parallel with the fifth and sixth transistors and is controlled by the first output signal.

1 is a circuit diagram of a level shift circuit according to a first embodiment. FIG. It is a wave form diagram of the signal of the level shift circuit of FIG. FIG. 6 is another waveform diagram of signals of the level shift circuit of FIG. 1. It is a circuit diagram of the level shift circuit of a comparative example. It is a wave form diagram of the signal of the level shift circuit of a comparative example. It is another waveform diagram of the signal of the level shift circuit of the comparative example. FIG. 5 is a circuit diagram of a level shift circuit according to a second embodiment. FIG. 6 is a circuit diagram of a level shift circuit according to a third embodiment. FIG. 10 is a circuit diagram of a level shift circuit according to a fourth embodiment. FIG. 10 is a circuit diagram of a level shift circuit according to a fifth embodiment. It is a wave form diagram of the signal of the level shift circuit of FIG. FIG. 11 is another waveform diagram of signals of the level shift circuit of FIG. 10. FIG. 10 is a circuit diagram of a level shift circuit according to a sixth embodiment. FIG. 10 is a circuit diagram of a level shift circuit according to a seventh embodiment. FIG. 10 is a circuit diagram of a level shift circuit according to an eighth embodiment. It is a block diagram which shows the schematic structure of the motor driver which concerns on 9th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. These embodiments do not limit the present invention.

(First embodiment)
FIG. 1 is a circuit diagram of a level shift circuit 10 according to the first embodiment. As shown in FIG. 1, the level shift circuit 10 includes an Nch MOS transistor (first conductivity type first transistor) Mn1, an Nch DMOS transistor (first conductivity type eleventh transistor) Mn2, and an Nch MOS transistor (first conductivity type). Second transistor) Mn11, NchDMOS transistor (first conductivity type twelfth transistor) Mn12, PchDMOS transistor (second conductivity type third transistor) Mp3, and PchMOS transistor (second conductivity type fourth transistor) Mp4, PchDMOS transistor (second conductivity type seventh transistor) Mp5, PchDMOS transistor (second conductivity type fifth transistor) Mp13, PchMOS transistor (second conductivity type sixth transistor) Mp14, PchD It includes an OS transistor (eighth transistor of the second conductivity type) Mp15, an inverter INV1, a. The level shift circuit 10 is configured as a semiconductor integrated circuit.

  The Nch MOS transistors Mn1 and Mn11 and the Pch MOS transistors Mp4 and Mp14 are relatively low withstand voltage transistors.

  The DMOS transistor is a double diffusion MOS transistor. Therefore, the Nch DMOS transistors Mn2 and Mn12 and the Pch DMOS transistors Mp3, Mp5, Mp13, and Mp15 have a higher breakdown voltage and a larger parasitic capacitance than the NchMOS transistors Mn1, Mn11, and the like.

  That is, the breakdown voltages of the NchDMOS transistors Mn2 and Mn12 and the PchDMOS transistors Mp3, Mp5, Mp13 and Mp15 are higher than the breakdown voltages of the NchMOS transistors Mn1 and Mn11 and the PchMOS transistors Mp4 and Mp14.

  The NchMOS transistor Mn1 includes a source (first electrode) connected to a first node N1 to which a first voltage (0 V, ground voltage) is supplied, a drain (second electrode), and a gate to which an input signal Sin is supplied. (Control electrode).

  The Nch DMOS transistor Mn2 has a gate (control electrode) to which the third voltage Vs1 is supplied, and is connected between the drain of the Nch MOS transistor Mn1 and the node N2. Specifically, the source of the Nch DMOS transistor Mn2 is connected to the drain of the Nch MOS transistor Mn1, and the drain of the Nch DMOS transistor Mn2 is connected to the node N2. The third voltage Vs1 has a voltage value between the first voltage (0V) and the second voltage Vin, and is determined according to the breakdown voltage of the Nch MOS transistor Mn1 and the like.

  The inverter INV1 is composed of a low breakdown voltage logic circuit, inverts the input signal Sin, and outputs an inverted signal SinB. The inverter INV1 operates by being supplied with the third voltage Vs1 and the first voltage (0V). The input signal Sin and the inverted signal SinB change between the first voltage (0 V) and the third voltage Vs1.

  The NchMOS transistor Mn11 includes a source (first electrode) connected to the first node N1, a drain (second electrode), a gate (control electrode) to which an inverted signal SinB of the input signal Sin is supplied from the inverter INV1, Have

  The NchDMOS transistor Mn12 has a gate (control electrode) to which the third voltage Vs1 is supplied, a source, and a drain, and is connected between the drain of the NchMOS transistor Mn11 and the node N3. Specifically, the source of the Nch DMOS transistor Mn12 is connected to the drain of the Nch MOS transistor Mn11, and the drain of the Nch DMOS transistor Mn12 is connected to the node N3.

  The Nch MOS transistors Mn1 and Mn11, the NchDMOS transistors Mn2 and Mn12, and the inverter INV1 constitute a low side block 11.

  The PchMOS transistor Mp4 includes a source (first electrode) connected to the second node N4 to which the second voltage Vin is supplied, and a drain (second electrode) connected to the third node N5 that outputs the first output signal So1. ) And a gate (control electrode).

  The PchDMOS transistor Mp3 is supplied with a source (first electrode) connected to the third node N5, a drain (second electrode) connected to the node N2, and a fourth voltage (second voltage Vin−voltage Vs2). And a gate (control electrode). The voltage Vs2 is supplied between the gate of the PchDMOS transistor Mp3 and the second node N4.

  The fourth voltage (second voltage Vin−voltage Vs2) has a voltage value between the first voltage (0V) and the second voltage Vin, and the required first and second output signals So1 and So2 are low. It is decided according to the voltage of the level.

  The PchDMOS transistor Mp5 includes a source (first electrode) connected to the second node N4, a drain (second electrode) connected to the node N2, and a gate (control electrode) connected to the gate of the PchMOS transistor Mp4. Have. That is, the Pch DMOS transistor Mp5 is connected in parallel to the Pch DMOS transistor Mp3 and the Pch MOS transistor Mp4 connected in series. Thereby, more current can be supplied to the node N2.

  The PchMOS transistor Mp14 has a source (first electrode) connected to the second node N4, a fourth node N6 that outputs the second output signal So2, and a drain (second electrode) connected to the gate of the PchMOS transistor Mp4. And a gate (control electrode) connected to the third node N5. The second output signal So2 is an inverted signal of the first output signal So1.

  The PchDMOS transistor Mp13 includes a source (first electrode) connected to the fourth node N6, a drain (second electrode) connected to the node N3, and a gate (control electrode) to which a bias voltage (Vin−Vs2) is supplied. And).

  The PchDMOS transistor Mp15 includes a source (first electrode) connected to the second node N4, a drain (second electrode) connected to the node N3, a gate (control electrode) connected to the third node N5, Have That is, the Pch DMOS transistor Mp15 is connected in parallel to the Pch DMOS transistor Mp13 and the Pch MOS transistor Mp14 connected in series. Thereby, more current can be supplied to the node N3.

  The Pch MOS transistors Mp4 and Mp14, and the Pch DMOS transistors Mp3, Mp5, Mp13, and Mp15 constitute a high side block 12.

  Next, the operation of the level shift circuit 10 will be described.

  FIG. 2 is a waveform diagram of signals of the level shift circuit 10 of FIG. FIG. 2 shows waveforms when the second voltage Vin = 12V, the third voltage Vs1 = 5V, and the voltage Vs2 = 5V, and the input signal Sin changes from the low level (0V) to the high level (5V). The voltage value such as the second voltage Vin is not limited to this example.

  Prior to time t0, since the input signal Sin is at a low level, the Nch MOS transistor Mn1 is off and the Nch MOS transistor Mn11 is on. Therefore, the Nch DMOS transistor Mn2 is off and the Nch DMOS transistor Mn12 is on. Accordingly, the voltage V_N2 of the node N2 and the first output signal So1 are high level (12V), the voltage V_N3 of the node N3 is low level (0V), and the second output signal So2 is low level (7V + Vgs). . Here, Vgs represents the gate-source voltage of the Pch DMOS transistor Mp13. The PchDMOS transistors Mp3, Mp5 and the PchMOS transistor Mp4 are on, and the PchDMOS transistors Mp13, Mp15 and the PchMOS transistor Mp14 are off.

  At time t0, the input signal Sin changes from the low level (0V) to the high level (5V). As a result, the Nch MOS transistor Mn1 and the Nch DMOS transistor Mn2 are turned on, and the Nch MOS transistor Mn11 and the Nch DMOS transistor Mn12 are turned off. As the NchMOS transistor Mn1 and the NchDMOS transistor Mn2 are turned on, the voltage V_N2 decreases from 12V to 0V.

  Further, since the Pch DMOS transistor Mp3 and the Pch MOS transistor Mp4 are on immediately after time t0, the first output signal So1 also decreases as the voltage V_N2 decreases. When the first output signal So1 decreases, the PchMOS transistor Mp14 turns on and the second output signal So2 increases. As the second output signal So2 rises, the Pch DMOS transistor Mp13 is also turned on. Since the Pch DMOS transistor Mp13 is turned on and the Nch MOS transistor Mn11 and the Nch DMOS transistor Mn12 are turned off, the voltage V_N3 increases from 0V to 12V. Then, the Pch MOS transistor Mp4 is turned off, and the Pch DMOS transistor Mp3 is also almost turned off.

  By the way, since the drain of the high breakdown voltage PchDMOS transistors Mp13 and Mp15 and the drain of the high breakdown voltage NchDMOS transistor Mn12 are connected to the node N3, the parasitic capacitance (not shown) of the node N3 is connected to another node. Big compared to. The same applies to the parasitic capacitance of the node N2.

  Here, when the first output signal So1 decreases, the Pch DMOS transistor Mp15 is turned on together with the Pch MOS transistor Mp14. As a result, the parasitic capacitance of the node N3 is charged by the current flowing through the PchDMOS transistor Mp15, and the rise of the voltage V_N3 is accelerated.

  After time t1, the first output signal So1 is stabilized at a low level (7V + Vgs), and the second output signal So2 and the voltage V_N3 are stabilized at a high level (12V). Here, it is assumed that the gate-source voltages Vgs of the PchDMOS transistors Mp3 and Mp13 are substantially equal to each other.

  FIG. 3 is another waveform diagram of the signal of the level shift circuit 10 of FIG. FIG. 3 shows a waveform when the input signal Sin changes from a high level to a low level under the same voltage condition as in FIG.

  The operation principle is the same as in FIG. 2, and when the second output signal So2 is lowered, the Pch DMOS transistor Mp5 is turned on together with the Pch MOS transistor Mp4. As a result, the parasitic capacitance (not shown) of the node N2 is charged by the current flowing through the PchDMOS transistor Mp5, and the rise of the voltage V_N2 is accelerated.

  Therefore, after time t1, the second output signal So2 is stabilized at the low level (7V + Vgs), and the first output signal So1 and the voltage V_N2 are stabilized at the high level (12V).

  In this way, the level shift circuit 10 converts the low voltage side input signal Sin (low level: 0 V, high level: 5 V) into the high voltage side first and second output signals So1, So2 (low level: 7 V + Vgs, High level: 12V) can be level shifted.

  Here, the level shift circuit of the comparative example will be described. FIG. 4 is a circuit diagram of a level shift circuit of a comparative example. The level shift circuit of the comparative example is different from FIG. 1 in that the Pch DMOS transistors Mp5 and Mp15 are not provided.

  FIG. 5 is a waveform diagram of signals of the level shift circuit of the comparative example. FIG. 6 is another waveform diagram of signals of the level shift circuit of the comparative example. FIG. 5 corresponds to FIG. 3, and FIG. 6 corresponds to FIG. In FIGS. 2, 3, 5 and 6, the horizontal scales are the same.

  As shown in FIG. 5, when the voltage V_N3 rises from 0V after the input signal Sin changes from low level (0V) to high level (5V), the parasitic capacitance of the node N3 is charged as compared with FIG. Need a long time. This is because the parasitic capacitance of the node N3 is charged only by the current flowing through the PchDMOS transistor Mp13 and the PchMOS transistor Mp14.

  Further, as the voltage V_N3 increases, the drain-source voltage of the PchDMOS transistor Mp13 and the PchMOS transistor Mp14 decreases, and the current drive capability of the PchDMOS transistor Mp13 and PchMOS transistor Mp14 decreases. This also requires a long time for charging the parasitic capacitance of the node N3.

  Therefore, the time t2 when the voltage V_N3 becomes high level (12V) is later than the time t1 in FIG. Therefore, it takes a longer time than FIG. 2 until the second output signal So2 changes from the low level (7V + Vgs) to the high level (12V). Further, the waveform of the second output signal So2 is more distorted than that in FIG. 2 until the second output signal So2 becomes high level.

  The same applies when the input signal Sin changes from a high level to a low level as shown in FIG.

  Thus, in the present embodiment, the Pch DMOS transistor Mp5 that is turned on or off according to the second output signal So2 and the Pch DMOS transistor Mp15 that is turned on or off according to the first output signal So1 are provided. Yes. Therefore, the parasitic capacitance of the node N2 can be charged by the PchDMOS transistor Mp5 when the voltage V_N2 changes from the low level to the high level, and the parasitic capacitance of the node N3 can be charged by the PchDMOS transistor Mp15 when the voltage V_N3 changes from the low level to the high level.

  Further, as the voltage V_N3 increases, even if the current drive capability of the Pch DMOS transistor Mp13 and the Pch MOS transistor Mp14 connected in series between the node N3 and the second node N4 decreases, the node N3 and the second node N4 The current drive capability of one PchDMOS transistor Mp15 provided between them is unlikely to be lowered. The same applies to the PchDMOS transistor Mp5.

  Thereby, the voltage V_N2 and the voltage V_N3 rise from the low level to the high level faster than the comparative example. Therefore, the first and second output signals So1 and So2 can be switched from low level to high level at high speed.

  Therefore, the delay of the first and second output signals So1, So2 can be reduced. In addition, the waveform distortion of the first and second output signals So1 and So2 can be improved. That is, signal transmission characteristics can be improved.

  In the present embodiment, the Nch DMOS transistor Mn2 is connected between the drain of the NchMOS transistor Mn1 and the node N2, and the Nch DMOS transistor Mn12 is connected between the drain of the NchMOS transistor Mn11 and the node N3, according to the input signal Sin. Thus, the low breakdown voltage NchMOS transistors Mn1 and Mn11 are switched. This makes it possible to reduce the switching current that flows when the input signal Sin is switched, as compared with the case where the high-breakdown-voltage DMOS transistor is switched according to the input signal Sin.

(Second Embodiment)
In the second embodiment, the circuit configuration of the first embodiment is simplified.

  FIG. 7 is a circuit diagram of a level shift circuit 10A according to the second embodiment. In FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals, and different points will be mainly described below. The level shift circuit 10A includes an NchDMOS transistor (first transistor) Mn6 instead of the NchMOS transistor Mn1, includes an NchDMOS transistor (second transistor) Mn16 instead of the NchMOS transistor Mn11, and does not include NchDMOS transistors Mn2 and Mn12. However, this is different from the first embodiment. That is, the configuration of the low side block 11A is simplified.

  The drain of the Nch DMOS transistor Mn6 is directly connected to the node N2. The drain of the Nch DMOS transistor Mn16 is directly connected to the node N3.

  The breakdown voltage of each of the NchDMOS transistors Mn6 and Mn16 and the PchDMOS transistors Mp3, Mp5, Mp13, and Mp15 is higher than that of each of the PchMOS transistors Mp4 and Mp14.

  Also in this embodiment, the basic operation principle is the same as that of the first embodiment. Accordingly, the first and second output signals So1 and So2 can be switched at high speed by reducing the delay of the first and second output signals So1 and So2.

  In addition, according to the present embodiment, the number of MOS transistors is reduced as compared with the first embodiment, so that the circuit area can be reduced.

(Third embodiment)
The third embodiment is different from the first embodiment in that the high voltage side input signal Sin is level-shifted to the low voltage side first and second output signals So1 and So2. Below, it demonstrates centering around difference with 1st Embodiment.

  FIG. 8 is a circuit diagram of a level shift circuit 10B according to the third embodiment. As shown in FIG. 8, the level shift circuit 10B includes a Pch MOS transistor (first conductivity type first transistor) Mp101, a Pch DMOS transistor (first conductivity type eleventh transistor) Mp102, and a Pch MOS transistor (first conductivity type). Second transistor) Mp111, PchDMOS transistor (first conductivity type twelfth transistor) Mp112, NchDMOS transistor (second conductivity type third transistor) Mn103, and NchMOS transistor (second conductivity type fourth transistor) Mn104, NchDMOS transistor (second conductivity type seventh transistor) Mn105, NchDMOS transistor (second conductivity type fifth transistor) Mn113, NchMOS transistor (second conductivity type sixth transistor) It comprises a static) MN114, and eighth transistors) MN115 of NchDMOS transistor (second conductivity type, an inverter INV11, a.

  The PchMOS transistor Mp101 includes a source (first electrode) connected to the first node N1 to which the first voltage Vin is supplied, a drain (second electrode), and a gate (control electrode) to which the input signal Sin is supplied. Have.

  The PchDMOS transistor Mp102 has a gate (control electrode) to which a third voltage (Vin−Vs2) is supplied, and is connected between the drain of the PchMOS transistor Mp101 and the node N2. Specifically, the source of the PchDMOS transistor Mp102 is connected to the drain of the PchMOS transistor Mp101, and the drain of the PchDMOS transistor Mp102 is connected to the node N2. The third voltage (Vin−Vs2) has a voltage value between the first voltage Vin and the second voltage (0V, ground voltage).

  The inverter INV11 is composed of a low breakdown voltage logic circuit, inverts the input signal Sin, and outputs an inverted signal SinB. The inverter INV11 operates by being supplied with the first voltage Vin and the third voltage (Vin−Vs2). The input signal Sin and the inverted signal SinB change between the first voltage Vin and the third voltage (Vin−Vs2).

  The PchMOS transistor Mp111 includes a source (first electrode) connected to the first node N1, a drain (second electrode), and a gate (control electrode) to which an inverted signal of the input signal Sin is supplied from the inverter INV11. Have.

  The PchDMOS transistor Mp112 has a gate (control electrode) to which a third voltage (Vin−Vs2) is supplied, a source, and a drain, and is connected between the drain of the PchMOS transistor Mp111 and the node N3. Yes. Specifically, the source of the PchDMOS transistor Mp112 is connected to the drain of the PchMOS transistor Mp111, and the drain of the PchDMOS transistor Mp112 is connected to the node N3.

  The Pch MOS transistors Mp101 and Mp111, the PchDMOS transistors Mp102 and Mp112, and the inverter INV11 constitute a high side block 11B.

  The Nch MOS transistor Mn104 includes a source (first electrode) connected to the second node N4 to which the second voltage (0 V) is supplied, and a drain (first electrode) connected to the third node N5 that outputs the first output signal So1. 2 electrodes) and a gate (control electrode).

  The NchDMOS transistor Mn103 includes a source (first electrode) connected to the third node N5, a drain (second electrode) connected to the node N2, a gate (control electrode) to which the fourth voltage Vs1 is supplied, Have The fourth voltage Vs1 has a voltage value between the second voltage (0V) and the first voltage Vin.

  The NchDMOS transistor Mn105 includes a source (first electrode) connected to the second node N4, a drain (second electrode) connected to the node N2, and a gate (control electrode) connected to the gate of the NchMOS transistor Mn104. Have. That is, the Nch DMOS transistor Mn105 is connected in parallel to the Nch DMOS transistor Mn103 and the Nch MOS transistor Mn104 connected in series. As a result, more current can flow from the node N2 to the second node N4.

  The NchMOS transistor Mn114 includes a source (first electrode) connected to the second node N4, a fourth node N6 that outputs the second output signal So2, and a drain (second electrode) connected to the gate of the NchMOS transistor Mn104. And a gate (control electrode) connected to the third node N5.

  The NchDMOS transistor Mn113 includes a source (first electrode) connected to the fourth node N6, a drain (second electrode) connected to the node N3, a gate (control electrode) supplied with the fourth voltage Vs1, Have

  The NchDMOS transistor Mn115 includes a source (first electrode) connected to the second node N4, a drain (second electrode) connected to the node N3, a gate (control electrode) connected to the third node N5, Have That is, the Nch DMOS transistor Mn115 is connected in parallel to the Nch DMOS transistor Mn113 and the NchMOS transistor Mn114 connected in series. As a result, more current can flow from the node N3 to the second node N4.

  The Nch MOS transistors Mn104 and Mn114, and the NchDMOS transistors Mn103, Mn105, Mn113, and Mn115 constitute a low side block 12B.

  Thus, in this embodiment, the conductivity type of the MOS transistor of the first embodiment is reversed, and the voltages supplied to the first node N1 and the second node N4 are reversed accordingly.

  The basic operation principle of the level shift circuit 10B is the same as that of the first embodiment.

  Thus, in the present embodiment, the Nch DMOS transistor Mn105 that is turned on or off according to the second output signal So2 and the Nch DMOS transistor Mn115 that is turned on or off according to the first output signal So1 are provided. Yes. Therefore, the parasitic capacitance of the node N2 can be discharged by the NchDMOS transistor Mn105 when the voltage V_N2 changes from the high level to the low level, and the parasitic capacitance of the node N3 can be discharged by the NchDMOS transistor Mn115 when the voltage V_N3 changes from the high level to the low level. Therefore, similarly to the first embodiment, the first and second output signals So1 and So2 can be switched at high speed.

  Further, the input signal Sin on the high voltage side can be level-shifted to the first and second output signals So1 and So2 on the low voltage side.

(Fourth embodiment)
In the fourth embodiment, the circuit configuration of the third embodiment is simplified.

  FIG. 9 is a circuit diagram of a level shift circuit 10C according to the fourth embodiment. In FIG. 9, the same components as those in FIG. 8 are denoted by the same reference numerals, and the differences will be mainly described below. The level shift circuit 10C includes a PchDMOS transistor (first transistor) Mp106 instead of the PchMOS transistor Mp101, a PchDMOS transistor (second transistor) Mp116 instead of the PchMOS transistor Mp111, and does not include the PchDMOS transistors Mp102 and Mp112. However, the third embodiment is different from the third embodiment. That is, the configuration of the high side block 11C is simplified.

  The drain of the Pch DMOS transistor Mp106 is directly connected to the node N2. The drain of the PchDMOS transistor Mp116 is directly connected to the node N3.

  The breakdown voltages of the PchDMOS transistors Mp106 and Mp116 and the NchDMOS transistors Mn103, Mn105, Mn113, and Mn115 are higher than the breakdown voltages of the NchMOS transistors Mn104 and Mn114.

  Also in this embodiment, the basic operation principle is the same as that of the third embodiment. Accordingly, the first and second output signals So1 and So2 can be switched at high speed by reducing the delay of the first and second output signals So1 and So2.

  Further, according to the present embodiment, the number of MOS transistors is reduced as compared with the third embodiment, so that the circuit area can be reduced.

(Fifth embodiment)
The fifth embodiment is different from the first embodiment in that the low level voltage levels of the first and second output signals So1, So2 are stabilized.

  FIG. 10 is a circuit diagram of a level shift circuit 10D according to the fifth embodiment. In FIG. 10, the same reference numerals are given to the components common to FIG. 1, and the differences will be mainly described below. The level shift circuit 10D further includes an Nch MOS transistor (first conductivity type ninth transistor) Mn7 and an Nch MOS transistor (first conductivity type tenth transistor) Mn17 in addition to the configuration of FIG. The Nch MOS transistors Mn7 and Mn17 are provided in the high side block 12D.

  The NchMOS transistor Mn7 includes a drain (first electrode) connected to the third node N5, a source (second electrode) supplied with the fourth voltage (Vin−Vs2), and a gate connected to the fourth node N6. (Control electrode). The NchMOS transistor Mn7 is controlled by the second output signal So2 and is provided to lower the impedance of the third node N5.

  The NchMOS transistor Mn17 includes a drain (first electrode) connected to the fourth node N6, a source (second electrode) supplied with the fourth voltage (Vin−Vs2), and a gate connected to the third node N5. (Control electrode). The NchMOS transistor Mn17 is controlled by the first output signal So1 and is provided so as to lower the impedance of the fourth node N6.

  In the first embodiment, when the first output signal So1 of the third node N5 is at a low level, the Pch MOS transistor Mp4 is off, the Pch DMOS transistor Mp3 is also almost off, and the third node N5 has a fourth voltage ( The signal level is higher by Vgs of the PchDMOS transistor Mp3 than Vin−Vs2). That is, the low-level first output signal So1 has high impedance and is unstable. Further, as shown in FIG. 2, the first output signal So1 temporarily becomes lower than the signal level obtained by adding Vgs to the fourth voltage (Vin−Vs2) immediately after the time t0, and becomes unstable.

  Similarly, when the second output signal So2 of the fourth node N6 is at a low level, the fourth node N6 has a high impedance. Therefore, the second output signal So2 of the fourth node N6 is unstable.

  Therefore, in the first embodiment, when the third node N5 or the fourth node N6 is in an unstable state of high impedance, the presence of capacitive coupling with other wiring responds to changes in signals of other wiring. Thus, the signal level of the first output signal So1 or the second output signal So2 may change. That is, noise resistance may be insufficient. In addition, since the difference between the high level and the low level of the first and second output signals So1 and So2 is decreased by approximately Vgs from the difference between the second voltage Vin and the fourth voltage (Vin−Vs2), the latter stage The circuit margin is reduced. Thus, in the first embodiment, there is room for improving the signal transfer characteristics. The same applies to the second to fourth embodiments.

  In the present embodiment, such points can be improved by providing the Nch MOS transistors Mn7 and Mn17.

  FIG. 11 is a waveform diagram of signals of the level shift circuit 10D of FIG. FIG. 12 is another waveform diagram of the signal of the level shift circuit 10D of FIG. 11 corresponds to FIG. 2, and FIG. 12 corresponds to FIG.

  As shown in FIG. 11, when the first output signal So1 after time t0 is near the low level, the NchMOS transistor Mn7 is turned on by the second output signal So2 higher than 7V, and 7V (fourth voltage) is 3 is supplied to the node N5. Therefore, the low level of the first output signal So1 is stabilized at 7V (fourth voltage).

  As shown in FIG. 12, when the second output signal So2 after time t0 is in the vicinity of the low level, the NchMOS transistor Mn17 is turned on by the first output signal So1 higher than 7V, and 7V (fourth voltage). Is supplied to the fourth node N6. Therefore, the low level of the second output signal So2 is stabilized at 7V (fourth voltage).

  Thus, the third and fourth nodes N5 and N6 are not in high impedance when at the low level. Therefore, even if there is capacitive coupling between the third node N5 or the fourth node N6 and another wiring, the signal level of the first output signal So1 or the second output signal So2 according to a change in the signal of the other wiring. Is hard to change. Therefore, noise resistance can be improved.

  In addition, since the low level of the first and second output signals So1, So2 can be reduced as compared with the first embodiment, the difference between the high level and the low level of the first and second output signals So1, So2 is determined. Can be big.

  Compared to FIG. 2, when the first output signal So1 temporarily decreases to a signal level lower than 7V after time t0, the amount of decrease can be reduced. Therefore, the waveform quality of the first and second output signals So1 and So2 can be improved.

  Thus, according to the present embodiment, the signal transfer characteristics can be improved. The effect of the first embodiment can also be obtained.

(Sixth embodiment)
In the sixth embodiment, the circuit configuration of the fifth embodiment is simplified.

  FIG. 13 is a circuit diagram of a level shift circuit 10E according to the sixth embodiment. In FIG. 13, the same reference numerals are given to the components common to those in FIG. 10, and the differences will be mainly described below. The level shift circuit 10E includes an NchDMOS transistor (first transistor) Mn6 instead of the NchMOS transistor Mn1, includes an NchDMOS transistor (second transistor) Mn16 instead of the NchMOS transistor Mn11, and does not include the NchDMOS transistors Mn2 and Mn12. However, this is different from the fifth embodiment. That is, the configuration of the low side block 11A is simplified.

  The drain of the Nch DMOS transistor Mn6 is directly connected to the node N2. The drain of the Nch DMOS transistor Mn16 is directly connected to the node N3.

  Also in this embodiment, the basic operation principle is the same as that of the fifth embodiment. Therefore, noise resistance can be improved as in the fifth embodiment.

  Further, according to the present embodiment, since the number of MOS transistors is reduced as compared with the fifth embodiment, the circuit area can be reduced.

(Seventh embodiment)
The seventh embodiment is different from the third embodiment in that the high level voltage levels of the first and second output signals So1, So2 are stabilized.

  FIG. 14 is a circuit diagram of a level shift circuit 10F according to the seventh embodiment. In FIG. 14, the same components as those in FIG. 8 are denoted by the same reference numerals, and the differences will be mainly described below. The level shift circuit 10F further includes a Pch MOS transistor (first conductivity type ninth transistor) Mp107 and a Pch MOS transistor (first conductivity type tenth transistor) Mp117 in addition to the configuration of FIG. The Pch MOS transistors Mp107 and Mp117 are provided in the low side block 12F.

  The Pch MOS transistor Mp107 includes a drain (first electrode) connected to the third node N5, a source (second electrode) supplied with the fourth voltage Vs1, and a gate (control electrode) connected to the fourth node N6. And having.

  The PchMOS transistor Mp117 includes a drain (first electrode) connected to the fourth node N6, a source (second electrode) supplied with the fourth voltage Vs1, and a gate (control electrode) connected to the third node N5. And having.

  The basic operation principle of this embodiment is the same as that of the fifth embodiment. That is, when the first output signal So1 is at a high level, the PchMOS transistor Mp107 is turned on by the second output signal So2 at a low level, and the high level of the first output signal So1 is stabilized at the fourth voltage Vs1. Further, when the second output signal So2 is at a high level, the PchMOS transistor Mp117 is turned on by the low-level first output signal So1, and the high level of the second output signal So2 is stabilized at the fourth voltage Vs1. Therefore, noise resistance can be improved as in the fifth embodiment.

  Similarly to the third embodiment, the high voltage side input signal Sin can be level-shifted to the low voltage side first and second output signals So1 and So2.

(Eighth embodiment)
In the eighth embodiment, the circuit configuration of the seventh embodiment is simplified.

  FIG. 15 is a circuit diagram of a level shift circuit 10G according to the eighth embodiment. In FIG. 15, the same reference numerals are given to the components common to FIG. 14, and the differences will be mainly described below. The level shift circuit 10G includes a PchDMOS transistor (first transistor) Mp106 instead of the PchMOS transistor Mp101, a PchDMOS transistor (second transistor) Mp116 instead of the PchMOS transistor Mp111, and does not include the PchDMOS transistors Mp102 and Mp112. However, this is different from the seventh embodiment. That is, the configuration of the low side block 11C is simplified.

  The drain of the Pch DMOS transistor Mp106 is directly connected to the node N2. The drain of the PchDMOS transistor Mp116 is directly connected to the node N3.

  In this embodiment, the basic operation principle is the same as that in the seventh embodiment. Therefore, the effect of the seventh embodiment can be obtained.

  Further, according to the present embodiment, since the number of MOS transistors is reduced as compared with the seventh embodiment, the circuit area can be reduced.

  If it is not necessary to obtain the effect of the first embodiment, the Pch DMOS transistors Mp5 and Mp15 may not be provided in the fifth and sixth embodiments, and the Nch DMOS transistor in the seventh and eighth embodiments. Mn105 and Mn115 may not be provided.

  In each of the above embodiments, an example in which a DMOS transistor is used as a high breakdown voltage MOS transistor has been described. As the high voltage MOS transistor, another name MOS transistor may be used.

(Ninth embodiment)
The ninth embodiment relates to a motor driver (driver circuit) 100 using the level shift circuits 10 and 10B of the first and third embodiments.

  FIG. 16 is a block diagram illustrating a schematic configuration of a motor driver 100 according to the ninth embodiment. The motor driver 100 includes a booster circuit 20, an input buffer circuit 30, a control circuit 40, a level shift unit 50, a high side driver 60, a low side driver 70, a level shift unit 80, and an Nch DMOS transistor (switch element). Mn201 to Mn206.

  The booster circuit 20 boosts the voltage Vbat to generate the second voltage Vin.

  The input buffer circuit 30 generates the control signal S1 according to the enable signal EN and the input signals IN1 to IN6 for controlling the motor M1.

  The control circuit 40 generates control signals D1 to D6 according to the control signal S1.

  The input buffer circuit 30 and the control circuit 40 operate when supplied with the third voltage Vs1 and the first voltage (0 V). Therefore, the control signals S1, D1 to D6 have a low level of the first voltage (0V) and a high level of the third voltage Vs1.

  The level shift unit 50 shifts the level of the control signals D1 to D3 to the control signals D1A to D3A on the high voltage side. In the control signals D1A to D3A, the low level is the fourth voltage (Vin−Vs2), and the high level is the second voltage Vin.

  The level shift unit 50 includes the three level shift circuits 10 of the first embodiment. Each level shift circuit 10 is supplied with the corresponding signal of the control signals D1 to D3 as the input signal Sin, and the first and second output signals So1 and So2 are the corresponding signals of the control signals D1A to D3A. Output. That is, the control signals D1A to D3A are differential signals. Instead of the level shift circuit 10, the level shift circuits 10A, 10D, and 10E of the second, fifth, or sixth embodiment may be used.

  The high side driver 60 operates by being supplied with the second voltage Vin and the fourth voltage (Vin−Vs2), and generates the drive signals H1 to H3 according to the control signals D1A to D3A.

  The low-side driver 70 operates by being supplied with the third voltage Vs1 and the first voltage (0V), and generates drive signals L1 to L3 according to the control signals D4 to D6.

  NchDMOS transistor Mn201 has a gate supplied with drive signal H1, a drain supplied with voltage Vbat, and a source connected to the first input node of motor M1.

  NchDMOS transistor Mn202 has a gate to which drive signal H2 is supplied, a drain to which voltage Vbat is supplied, and a source connected to the second input node of motor M1.

  NchDMOS transistor Mn203 has a gate to which drive signal H3 is supplied, a drain to which voltage Vbat is supplied, and a source connected to the third input node of motor M1.

  The NchDMOS transistor Mn204 has a gate to which the drive signal L1 is supplied, a drain connected to the source of the NchDMOS transistor Mn201, and a source to which the first voltage (0V) is supplied.

  The NchDMOS transistor Mn205 has a gate to which the drive signal L2 is supplied, a drain connected to the source of the NchDMOS transistor Mn202, and a source to which the first voltage (0V) is supplied.

  The NchDMOS transistor Mn206 has a gate to which the drive signal L3 is supplied, a drain connected to the source of the NchDMOS transistor Mn203, and a source to which the first voltage (0V) is supplied.

  Thus, the NchDMOS transistors Mn201 to Mn203 are driven based on the first output signal So1 and the second output signal So2, respectively.

  The level shift unit 80 level-shifts the drive signals H1 to H3 to the low voltage side control signals D1B to D3B. The control signals D1B to D3B have a low level of the first voltage (0V) and a high level of the third voltage Vs1.

  The level shift unit 80 includes three level shift circuits 10B of the third embodiment. Each level shift circuit 10B is supplied with a corresponding signal of the drive signals H1 to H3 as an input signal Sin, and the first and second output signals So1 and So2 are used as corresponding signals of the control signals D1B to D3B. Output. That is, the control signals D1B to D3B are differential signals. Instead of the level shift circuit 10B, the level shift circuits 10C, 10F, and 10G of the fourth, seventh, or eighth embodiment may be used.

  The control circuit 40 adjusts the timing of the control signals D1 to D6 according to the control signals D1B to D3B and the drive signals L1 to L3.

  Thus, according to the present embodiment, the level shift circuit 10 of the first embodiment and the level shift circuit 10B of the third embodiment shift the level of the signal, so that the drive signals H1 to H3 and The control signals D1B to D3B can be switched at high speed. Therefore, the motor M1 can be precisely controlled.

  The level shift circuits 10 and 10A to 10G can be used not only for the motor driver 100 described above but also for various circuits that require signal level shift.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 10A-10G Level shift circuit INV1, INV11 Inverter Mn1 NchMOS transistor (first transistor)
Mn2 NchDMOS transistor (11th transistor)
Mp3 PchDMOS transistor (third transistor)
Mp4 PchMOS transistor (4th transistor)
Mp5 PchDMOS transistor (seventh transistor)
Mn6 NchDMOS transistor (first transistor)
Mn7 NchMOS transistor (5th transistor, 9th transistor)
Mn11 NchMOS transistor (second transistor)
Mn12 NchDMOS transistor (12th transistor)
Mp13 PchDMOS transistor (fifth transistor)
Mp14 PchMOS transistor (6th transistor)
Mp15 PchDMOS transistor (8th transistor)
Mn16 NchDMOS transistor (second transistor)
Mn17 NchMOS transistor (8th and 10th transistors)
Mp101 PchMOS transistor (first transistor)
Mp102 PchDMOS transistor (11th transistor)
Mn103 NchDMOS transistor (third transistor)
Mn104 NchMOS transistor (4th transistor)
Mn105 NchDMOS transistor (seventh transistor)
Mp106 PchDMOS transistor (first transistor)
Mp107 PchMOS transistor (5th transistor, 9th transistor)
Mp111 PchMOS transistor (second transistor)
Mp112 PchDMOS transistor (12th transistor)
Mn113 NchDMOS transistor (5th transistor)
Mn114 NchMOS transistor (sixth transistor)
Mn115 NchDMOS transistor (8th transistor)
Mp116 PchDMOS transistor (second transistor)
Mp117 PchMOS transistor (8th transistor, 10th transistor)
100 Motor driver (driver circuit)

Claims (11)

A first transistor of a first conductivity type connected to a first node to which a first voltage is supplied and controlled by an input signal;
A second transistor of a first conductivity type connected to the first node and controlled by an inverted signal of the input signal;
A third transistor of a second conductivity type connected between a third node that outputs a first output signal and the first transistor;
A fourth transistor of a second conductivity type, connected between a second node supplied with a second voltage different from the first voltage and the third node, and controlled by a second output signal;
A fifth transistor of a second conductivity type connected between a fourth node that outputs the second output signal and the second transistor;
A sixth transistor of a second conductivity type connected between the second node and the fourth node and controlled by the first output signal;
A seventh transistor of a second conductivity type provided in parallel with the third and fourth transistors and controlled by the second output signal;
An eighth transistor of a second conductivity type provided in parallel with the fifth and sixth transistors and controlled by the first output signal;
A level shift circuit comprising: A ninth transistor controlled by the second output signal and provided to lower the impedance of the third node;
A tenth transistor controlled by the first output signal and provided to lower the impedance of the fourth node;
The level shift circuit according to claim 1, comprising: A first electrode having a control electrode to which a third voltage having a voltage value between the first voltage and the second voltage is supplied and connected between the first transistor and the third transistor; An eleventh transistor of the type;
A control electrode to which the third voltage is supplied; a twelfth transistor of the first conductivity type connected between the second transistor and the fifth transistor;
The level shift circuit of Claim 1 or Claim 2 provided with these.   Each of the first transistor, the second transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor has a breakdown voltage of each of the fourth transistor and the sixth transistor. The level shift circuit according to claim 1, wherein the level shift circuit is higher than a withstand voltage.   5. The level shift circuit according to claim 4, wherein each of the first transistor, the second transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor is a DMOS transistor.   The breakdown voltage of each of the third transistor, the seventh transistor, the fifth transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor is the first transistor, the second transistor, and the fourth transistor. 4. The level shift circuit according to claim 3, wherein the level shift circuit is higher than a breakdown voltage of each of the transistor and the sixth transistor.   The level shift circuit according to claim 6, wherein each of the third transistor, the seventh transistor, the fifth transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor is a DMOS transistor. A first transistor of a first conductivity type connected to a first node to which a first voltage is supplied and controlled by an input signal;
A second transistor of a first conductivity type connected to the first node and controlled by an inverted signal of the input signal;
A third transistor of a second conductivity type connected between a third node that outputs a first output signal and the first transistor;
A fourth transistor of a second conductivity type, connected between a second node supplied with a second voltage different from the first voltage and the third node, and controlled by a second output signal;
A fifth transistor of a second conductivity type connected between a fourth node that outputs the second output signal and the second transistor;
A sixth transistor of a second conductivity type connected between the second node and the fourth node and controlled by the first output signal;
A seventh transistor controlled by the second output signal and provided to lower the impedance of the third node;
An eighth transistor controlled by the first output signal and provided to lower the impedance of the fourth node;
A level shift circuit comprising:   The input signal and the inverted signal vary between the first voltage and a third voltage, and the third voltage has a voltage value between the first voltage and the second voltage. The level shift circuit according to claim 1 or 8.   The level shift circuit according to any one of claims 1 to 9, wherein the second output signal is an inverted signal of the first output signal. A level shift circuit according to any one of claims 1 to 10,
A switch element driven based on the first output signal and the second output signal;
A driver circuit comprising:

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