JP2017054899A - Semiconductor device, display device, electronic apparatus using the display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a low manufacturing cost. A semiconductor device comprising a transistor, a first insulating film, and a capacitive element including a second insulating film between a pair of electrodes, wherein the transistor is a first on the first insulating film. Oxide semiconductor film, the second insulating film on the first oxide semiconductor film, the second oxide semiconductor film on the second insulating film, the first oxide semiconductor film and the second It has a third insulating film on the oxide semiconductor film, and the first oxide semiconductor film has a channel region overlapping the second oxide semiconductor film, a source region in contact with the third insulating film, and the like. It has a drain region in contact with a third insulating film, and the source region and drain region have one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas. One of the pair of electrodes of the capacitive element includes a second oxide semiconductor film. [Selection diagram] Fig. 1

Description

  One embodiment of the present invention relates to a semiconductor device, a display device, and an electronic device using the display device. One embodiment of the present invention relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a display device, an electronic device, a manufacturing method thereof, or a driving method thereof. In particular, one embodiment of the present invention relates to a semiconductor device including a transistor and a capacitor, for example.

  Transistors used in many flat panel displays typified by liquid crystal display devices and light-emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon, or polycrystalline silicon formed on a glass substrate. . In addition, a transistor including the silicon semiconductor is used for an integrated circuit (IC) or the like.

  In recent years, a technique using a metal oxide exhibiting semiconductor characteristics for a transistor instead of a silicon semiconductor has attracted attention. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor. For example, a technique is disclosed in which a transistor using zinc oxide or an In—Ga—Zn-based oxide as an oxide semiconductor is manufactured, and the transistor is used for a switching element of a pixel of a display device or the like (Patent Document 1). And Patent Document 2).

JP 2007-123861 A JP 2007-96055 A

  An object of one embodiment of the present invention is to provide a semiconductor device including an oxide semiconductor film having conductivity. Another object of one embodiment of the present invention is to provide a semiconductor device in which a capacitance value is increased while increasing an aperture ratio. Another object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing cost. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is a semiconductor device including a transistor, a first insulating film, and a capacitor including a third insulating film between a pair of electrodes. The transistor is over the first insulating film. A first oxide semiconductor film, a second insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the second insulating film, a first oxide semiconductor film, and A third insulating film over the second oxide semiconductor film, the first oxide semiconductor film including a channel region overlapping with the second oxide semiconductor film and a source in contact with the third insulating film A drain region in contact with the third insulating film, and the source region and the drain region include one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas. In the semiconductor device, one of the pair of electrodes of the capacitor element includes the second oxide semiconductor film. That.

  In addition, the semiconductor device includes a transistor, a first insulating film, and a capacitor including a third insulating film between a pair of electrodes. The transistor includes a gate electrode and the first electrode over the gate electrode. An insulating film, a first oxide semiconductor film on the first insulating film, a second insulating film on the first oxide semiconductor film, and a second oxide semiconductor on the second insulating film A first oxide semiconductor film and a third insulating film over the second oxide semiconductor film, wherein the first oxide semiconductor film overlaps with the second oxide semiconductor film A source region in contact with the third insulating film, and a drain region in contact with the third insulating film, wherein the source region and the drain region are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine , Titanium, or a rare gas, and one of the pair of electrodes of the capacitor is the second Including an oxide semiconductor film, a semiconductor device is also an embodiment of the present invention.

  In addition, the semiconductor device includes a transistor, a first insulating film, and a capacitor including a third insulating film between a pair of electrodes. The transistor includes a gate electrode and the first electrode over the gate electrode. An insulating film, a first oxide semiconductor film on the first insulating film, a second insulating film on the first oxide semiconductor film, and a second oxide semiconductor on the second insulating film And a third insulating film over the first oxide semiconductor film and the second oxide semiconductor film, the gate electrode being electrically connected to the second oxide semiconductor film, The first oxide semiconductor film includes a channel region overlapping with the second oxide semiconductor film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The drain region can be hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or rare Have one or more of the scan, one of the pair of electrodes of the capacitor comprises a second oxide semiconductor film, a semiconductor device is also an embodiment of the present invention.

  In addition, the transistor is electrically connected to the source region through the fourth insulating film over the third insulating film and the opening provided in the third insulating film and the fourth insulating film. And the above-described semiconductor device including the second conductive film electrically connected to the drain region through the opening provided in the third insulating film and the fourth insulating film. It is one embodiment of the invention.

  The fourth insulating film, the fifth conductive film over the first conductive film, and the second conductive film, and the third conductive film over the fifth insulating film, and a pair of electrodes of the capacitor The above-described semiconductor device in which the other includes a third conductive film is also one embodiment of the present invention.

  The semiconductor device of one embodiment of the present invention is the above semiconductor device in which the capacitor has a light-transmitting property in visible light.

  In the above semiconductor device, the first oxide semiconductor film and the second oxide semiconductor film are In-M-Zn oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Sn, or Hf is preferred).

  In the above semiconductor device, the third insulating film preferably contains nitrogen or hydrogen.

  In the above semiconductor device, the second insulating film preferably contains oxygen.

  Further, a display device including the above semiconductor device and a liquid crystal element is also one embodiment of the present invention.

  An electronic device including the above semiconductor device and a switch, a speaker, a display portion, or a housing is also one embodiment of the present invention.

  According to one embodiment of the present invention, a semiconductor device including a conductive oxide semiconductor film can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device in which a capacitance value is increased while increasing an aperture ratio can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low manufacturing cost can be provided. According to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. The figure explaining a band structure. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. FIG. 10 is a top view illustrating one embodiment of a display device and a circuit diagram illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. The block diagram and timing chart figure of a touch sensor. FIG. 6 illustrates a pixel including a touch sensor. FIG. 9 illustrates operation of a touch sensor and a pixel. The cross-sectional schematic which shows the system of a touch panel. The cross-sectional schematic which shows the system of a touch panel. The top view which shows arrangement | positioning of the electrode of a touch sensor. FIG. 6 is a top view illustrating one embodiment of a pixel. FIG. 14 is a cross-sectional view illustrating one embodiment of a pixel. FIG. 6 is a circuit diagram illustrating one embodiment of a pixel. FIG. 6 is a top view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. The perspective view which shows the structure of a touch panel. Sectional drawing which shows the structure of a touchscreen. The top view which shows the structure of a touch sensor. The top view which shows the structure of a touch sensor electrode. The top view which shows the structure of a touch sensor. The top view which shows the structure of a touch sensor electrode. FIG. 6 illustrates a structure of a light-emitting element. The figure explaining a display module. 10A and 10B each illustrate an electronic device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, one embodiment of the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the gist and scope of the present invention. The Therefore, one embodiment of the present invention is not construed as being limited to the description of the following embodiment modes. In the embodiments described below, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatch patterns in different drawings, and description thereof is not repeated.

  Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

  In addition, the first and second ordinal numbers used in this specification and the like are given in order to avoid mixing of constituent elements, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating film”.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. Further, the boundary between “semiconductor” and “insulator” is ambiguous, and there is a case where it cannot be strictly distinguished. Therefore, the “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. Alternatively, the “insulator” in this specification and the like can be referred to as a “semi-insulator” in some cases.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. Further, the boundary between the “semiconductor” and the “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases.

  Note that the functions of the “source” and “drain” of the transistor may be interchanged when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  Note that in this specification and the like, patterning uses a photolithography process. However, the patterning is not limited to the photolithography process, and a process other than the photolithography process can be used. The mask formed in the photolithography process is removed after the etching process.

  Note that in this specification and the like, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen, preferably 55 to 65 atomic% oxygen and 1 atomic% nitrogen. More than 20 atomic%, silicon is included in a range of 25 atomic% to 35 atomic%, and hydrogen is included in a range of 0.1 atomic% to 10 atomic%. The silicon nitride oxide film refers to a film having a nitrogen content higher than that of oxygen as a composition. Preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, and silicon is included. This refers to a concentration range of 25 atomic% to 35 atomic% and hydrogen in a concentration range of 0.1 atomic% to 10 atomic%.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<Configuration Example 1 of Semiconductor Device>
1A is a top view of the semiconductor device 100 of one embodiment of the present invention, and FIG. 1B illustrates a cross-sectional view taken along the dashed-dotted line AB in FIG. This corresponds to a cross-sectional view of a cut surface between alternate long and short dash lines E-F. Note that in FIG. 1A, some components (such as a gate insulating film) of the semiconductor device 100 are not illustrated in order to avoid complexity. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 1A.

  A dashed line AB in FIG. 1A indicates the channel length direction of the transistor 150. A one-dot chain line EF indicates the channel width direction of the transistor 150. Note that in this specification, the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode). In a horizontal plane, it means a direction perpendicular to the channel length direction.

  A semiconductor device 100 illustrated in FIGS. 1A and 1B includes a transistor 150 including a first oxide semiconductor film 108 and a capacitor 160 including an insulating film between a pair of electrodes. Note that in the capacitor 160, one of the pair of electrodes is the second oxide semiconductor film 111b, and the other of the pair of electrodes is the conductive film 123.

  The transistor 150 includes a gate electrode 106 over the substrate 102, an insulating film 104 functioning as a gate insulating film over the gate electrode 106, a first oxide semiconductor film 108 over the insulating film 104, and a first oxide semiconductor. The insulating film 110 over the film 108, the second oxide semiconductor film 111a over the insulating film 110, and the insulating film 116 over the insulating film 104, the first oxide semiconductor film 108, and the second oxide semiconductor film 111a And having. Note that the first oxide semiconductor film 108 includes a channel region 108 i overlapping with the second oxide semiconductor film 111 a, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.

  In the transistor 150, the gate electrode 106 functions as a first gate electrode, and the second oxide semiconductor film 111a functions as a second gate electrode. The second oxide semiconductor film 111 a is electrically connected to the gate electrode 106 through the opening 142 provided in the insulating film 104 and the insulating film 110. That is, the gate electrode 106 and the second oxide semiconductor film 111a have the same potential. Note that in the transistor 150, the gate electrode 106 and the second oxide semiconductor film 111a may operate independently and be supplied with different potentials. The transistor 150 may not have the gate electrode 106 (see FIG. 1C).

  The insulating film 116 includes nitrogen or hydrogen. When the insulating film 116 is in contact with the source region 108s and the drain region 108d, nitrogen or hydrogen in the insulating film 116 is added to the source region 108s and the drain region 108d. In the source region 108s and the drain region 108d, the carrier density is increased by adding nitrogen or hydrogen. Note that in the first oxide semiconductor film 108, the source region 108 s and the drain region 108 d are illustrated with hatching changed from the channel region 108 i (see FIG. 1B).

  The transistor 150 includes the insulating film 118 over the insulating film 116, the conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.

  Note that in this specification and the like, the insulating film 104 is a first insulating film, the insulating film 110 is a second insulating film, the insulating film 116 is a third insulating film, and the insulating film 118 is a fourth insulating film. In some cases, the insulating film 122 described later is referred to as a fifth insulating film. The conductive film 112 functions as a gate electrode, the conductive film 120a functions as one of a source electrode and a drain electrode, and the conductive film 120b functions as the other of the source electrode and the drain electrode. Have

  The insulating film 110 functions as a gate insulating film. In addition, the insulating film 110 has an excess oxygen region. When the insulating film 110 includes the excess oxygen region, excess oxygen can be supplied to the channel region 108 i included in the first oxide semiconductor film 108. Accordingly, oxygen vacancies that can be formed in the channel region 108i can be filled with excess oxygen, so that a highly reliable semiconductor device can be provided.

  Note that in order to supply excess oxygen into the first oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the first oxide semiconductor film 108. Note that in this case, excess oxygen contained in the insulating film 104 can be supplied to the source region 108s and the drain region 108d included in the first oxide semiconductor film 108. When excess oxygen is supplied into the source region 108s and the drain region 108d, the resistance of the source region 108s and the drain region 108d may increase.

  On the other hand, when the insulating film 110 formed over the first oxide semiconductor film 108 includes excess oxygen, excess oxygen can be selectively supplied only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density in the source region 108s and the drain region 108d is selectively increased, so that the source region 108s and the drain region 108d It can suppress that resistance becomes high.

  The source region 108s and the drain region 108d included in the first oxide semiconductor film 108 preferably each include one or more elements that form oxygen vacancies or the following elements that are bonded to oxygen vacancies. As an element that forms oxygen vacancies or an element that combines with oxygen vacancies, typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like can be given. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. The element that forms oxygen vacancies is added to the source region 108 s and the drain region 108 d by diffusion of the constituent elements of the insulating film 116 into the source region 108 s and the drain region 108 d, or by impurity addition treatment.

  When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut, so that an oxygen vacancy is formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.

  An insulating film 122 and a conductive film 123 are formed in this order over the insulating film 118, the conductive film 120a, and the conductive film 120b. An opening 143 reaching the second oxide semiconductor film 111b is formed in the insulating film 116 and the insulating film 118, and the conductive film 120b and the second oxide semiconductor film 111b are electrically connected to each other through the opening 143. It is connected to the. The second oxide semiconductor film 111b functions as, for example, a pixel electrode. The conductive film 123 has a function as a common electrode, for example.

  Note that the second oxide semiconductor film 111b may function as a common electrode, and the conductive film 123 may function as a pixel electrode (see FIG. 2A). 2A, the conductive film 123 is electrically connected to the conductive film 120b through an opening 144 provided in the insulating film 122. Further, instead of the second oxide semiconductor film 111b, the first oxide semiconductor film 108b formed at the same time as the first oxide semiconductor film 108 may function as a pixel electrode (FIG. 2 (B)). The first oxide semiconductor film 108b may function as a common electrode, and the conductive film 123 may function as a pixel electrode (see FIG. 2C).

  Further, an auxiliary electrode may be connected to the conductive film 123 having a function of a common electrode. In the case where the second oxide semiconductor film 111b functions as a pixel electrode of the transmissive liquid crystal display device, the auxiliary electrode is preferably provided at a position that does not overlap with the second oxide semiconductor film 111b. For example, a conductive film 124 functioning as an auxiliary electrode may be provided over the conductive film 123 (see FIGS. 3A and 3B). A conductive film 120c that can be formed at the same time as the conductive films 120a and 120b may be provided as an auxiliary wiring of the conductive film 123 (see FIGS. 4A and 4B). 4A and 4B, the conductive film 120 c is electrically connected to the conductive film 123 through an opening 145 provided in the insulating film 122. 3B and 4B correspond to cross-sectional views of the cut surface between the dashed-dotted line AB and the dashed-dotted line CG in FIGS. 3A and 4A, respectively. .

  The capacitor 160 includes a second oxide semiconductor film 111 that functions as one of a pair of electrodes over the insulating film 110, and an insulating film 116 that functions as a dielectric film over the second oxide semiconductor film 111. The insulating film 118 and the insulating film 122 and the conductive film 123 functioning as the other of the pair of electrodes over the insulating film 122 are included. That is, the second oxide semiconductor film 111b has a function as a pixel electrode and a function as an electrode of a capacitor. The conductive film 123 has a function as a common electrode and a function as an electrode of a capacitor.

  Note that the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b preferably include the same metal element. By using the same metal element for the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b, a manufacturing apparatus (eg, a film formation apparatus or a processing apparatus) is used in common. Therefore, the manufacturing cost can be suppressed.

  In the semiconductor device 100 illustrated in FIGS. 1A and 1B, the second oxide semiconductor film 111a functioning as a gate electrode of the transistor 150 and the second oxide semiconductor film 111b functioning as a pixel electrode are formed using the same material at the same time. Form. With such a structure, the number of steps for manufacturing the semiconductor device can be reduced and manufacturing cost can be suppressed.

  Further, the capacitor 160 has a light-transmitting property. That is, the second oxide semiconductor film 111b, the conductive film 123, and the insulating films 116, 118, and 122 included in the capacitor 160 are each formed using a light-transmitting material. In this manner, since the capacitor 160 has a light-transmitting property, the capacitor 160 can be formed large (in a large area) in a region other than a portion where a transistor is formed in a pixel, so that the capacitance value can be increased while increasing the aperture ratio. An increased semiconductor device can be obtained. As a result, a semiconductor device having excellent display quality can be obtained.

  Note that in the transistor 150, the channel region 108i of the first oxide semiconductor film 108 has a higher resistivity than the source region 108s and the drain region 108d. In addition, since the second oxide semiconductor films 111a and 111b function as electrodes, the resistivity is lower than that of the channel region 108i of the first oxide semiconductor film 108.

  Here, a method for controlling the resistivity of the first oxide semiconductor film 108 and the second oxide semiconductor film 111 is described below.

<Method for controlling resistivity of oxide semiconductor>
An oxide semiconductor film that can be used for the first oxide semiconductor film 108 and the second oxide semiconductor film 111 has a resistivity depending on oxygen vacancies in the film and / or the concentration of impurities such as hydrogen and water in the film. It is a semiconductor material that can control. Therefore, by selecting treatment for increasing the oxygen vacancy and / or impurity concentration or treatment for reducing the oxygen vacancy and / or impurity concentration for the first oxide semiconductor film 108 and the second oxide semiconductor film 111, The resistivity of each oxide semiconductor film can be controlled.

  Specifically, plasma treatment is performed on the oxide semiconductor film in a region where low efficiency is desired to be reduced, oxygen vacancies in the oxide semiconductor film are increased, and / or hydrogen, water, or the like in the oxide semiconductor film By increasing the amount of impurities, an oxide semiconductor film with high carrier density and low resistivity can be obtained. Further, an insulating film containing hydrogen is formed in contact with the oxide semiconductor film, and hydrogen is diffused from the insulating film containing hydrogen, for example, the insulating film 116 into the oxide semiconductor film, whereby the carrier density is high and the resistivity is high. A low oxide semiconductor film can be obtained. At this time, the oxide semiconductor film functions as an oxide conductor (OC: Oxide Conductor). For example, the second oxide semiconductor films 111a and 111b function as a semiconductor before the step of increasing oxygen vacancies in the film or diffusing hydrogen as described above. Has a function as a conductor.

  On the other hand, the channel region 108 i of the first oxide semiconductor film 108 is not in contact with the insulating film 116 containing hydrogen by providing the insulating film 110. By applying an insulating film containing oxygen to at least one of the insulating films 104 and 110, in other words, an insulating film capable of releasing oxygen, oxygen is added to a region of the oxide semiconductor film which is to be the channel region 108i. Can be supplied. The channel region 108 i to which oxygen is supplied becomes an oxide semiconductor film with high resistivity by filling oxygen vacancies in the film or at the interface. Note that as the insulating film from which oxygen can be released, for example, a silicon oxide film or a silicon oxynitride film can be used.

  In order to obtain an oxide semiconductor film with low resistivity, hydrogen, boron, phosphorus, or nitrogen is implanted into the oxide semiconductor film by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. May be.

  Further, in order to obtain an oxide semiconductor film with low resistivity, plasma treatment may be performed on the oxide semiconductor film. For example, the plasma treatment typically includes plasma treatment using a gas containing one or more selected from rare gases (He, Ne, Ar, Kr, Xe), hydrogen, and nitrogen. . More specifically, plasma treatment in an Ar atmosphere, plasma treatment in a mixed gas atmosphere of Ar and hydrogen, plasma treatment in an ammonia atmosphere, plasma treatment in a mixed gas atmosphere of Ar and ammonia, or nitrogen For example, plasma treatment in an atmosphere.

  Through the above plasma treatment, the oxide semiconductor film forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). The oxygen deficiency may be a factor that generates carriers. Further, when hydrogen is supplied from the vicinity of the oxide semiconductor film, more specifically, from an insulating film in contact with the lower side or the upper side of the oxide semiconductor film, the oxygen vacancies and hydrogen are combined to form carriers. It may generate electrons.

On the other hand, an oxide semiconductor film in which oxygen vacancies are filled and the hydrogen concentration is reduced can be said to be a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Here, the substantially intrinsic, the carrier density of the oxide semiconductor film, 8 × ^{10 11} pieces / cm less than ^3, preferably less than 1 × ¹⁰ 11 / cm ^3, more preferably 1 × ^{10 10} pieces / cm It means less than ³ . A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low defect level density; therefore, the trap level density can be reduced.

Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length L of 10 μm. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less. Therefore, the transistor 150 in which the above-described high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film region is used for the channel region 108i has a small variation in electric characteristics and has high reliability.

As the insulating film 116, for example, an insulating film containing hydrogen, in other words, an insulating film capable of releasing hydrogen, typically a silicon nitride film, is used, so that the first oxide semiconductor film 108 and the second oxide film Hydrogen can be supplied to the oxide semiconductor films 111a and 111b. As the insulating film capable of releasing hydrogen, the concentration of hydrogen contained in the film is preferably 1 × 10 ²² atoms / cm ³ or more. By forming such an insulating film in contact with the oxide semiconductor film, hydrogen can be effectively contained in the oxide semiconductor film. As described above, the resistivity of the oxide semiconductor film can be controlled by changing the structures of the insulating films in contact with the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b.

  Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to become water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated.

The channel region 108 i of the first oxide semiconductor film 108 is preferably reduced as much as possible. Specifically, in the channel region 108i, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm 3. ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less More preferably, it is 1 × 10 ¹⁶ atoms / cm ³ or less.

On the other hand, the hydrogen concentration contained in the source region 108s, the drain region 108d, and the second oxide semiconductor films 111a and 111b of the first oxide semiconductor film 108 is 8 × 10 ¹⁹ atoms or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, more preferably 5 × 10 ²⁰ or more. Alternatively, the concentration of hydrogen contained in these oxide semiconductor films is twice or more, preferably 10 times or more, as compared to the channel region 108i. In addition, the resistivity of these oxide semiconductor films is preferably 1 × 10 ⁻⁸ times or more and less than 1 × 10 ⁻¹ times the resistivity of the channel region 108 i, typically 1 × 10 ⁻³ Ωcm. The resistivity is preferably 1 × 10 ⁻³ Ωcm or more and less than 1 × 10 ⁻¹ Ωcm, more preferably less than 1 × 10 ⁴ Ωcm.

  Here, details of other components of the semiconductor device 100 illustrated in FIGS. 1A and 1B will be described below.

<Board>
There is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. It is also possible to apply a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc., and a semiconductor element provided on these substrates May be used as the substrate 102. When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation. By using a large area substrate such as a generation (2950 mm × 3400 mm), a large display device can be manufactured. Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 150, the capacitor 160, and the like may be formed directly over the flexible substrate.

  In addition to these, a transistor can be formed using various substrates as the substrate 102. The kind of board | substrate is not limited to a specific thing. Examples of the substrate include a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded film, and a fibrous material. Or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

  Note that a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on another substrate. As an example of the substrate on which the transistor is transferred, in addition to the substrate on which the transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp), There are synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

<First insulating film>
The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating film 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film from which oxygen is released by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.

  The thickness of the insulating film 104 can be greater than or equal to 50 nm, or greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 It is possible to reduce oxygen vacancies contained in 108i.

  The insulating film 104 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and may be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104. In this manner, oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

<First oxide semiconductor film and second oxide semiconductor film>
The first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b each include at least indium (In), zinc (Zn), and M (Al, Ti, Ga, Y, Zr, La, Ce, Sn, or A film represented by an In-M-Zn oxide containing a metal such as Hf is preferably included. In addition, in order to reduce variation in electrical characteristics of the transistor including the oxide semiconductor, a stabilizer is preferably included together with the transistor.

  Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like, including the metals described in M above. Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb). ), Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

  Examples of oxide semiconductors included in the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b include an In—Ga—Zn-based oxide, an In—Al—Zn-based oxide, and In—Sn. -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho- Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide , In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide , Can be used In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide.

  Note that here, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

  Further, the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b may include the same metal element among the above oxides. By using the same metal element for the first oxide semiconductor film 108 and the second oxide semiconductor film 111, manufacturing cost can be reduced. For example, manufacturing costs can be reduced by using metal oxide targets having the same metal composition. In addition, when a metal oxide target having the same metal composition is used, an etching gas or an etching solution for processing the oxide semiconductor film can be used in common. Note that the first oxide semiconductor film 108 and the second oxide semiconductor film 111 may have different compositions even though they have the same metal element. For example, a metal element in a film may be detached during a manufacturing process of a transistor and a capacitor to have a different metal composition.

  Note that when the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b are In-M-Zn oxides, the atomic ratio of In to M is 100 atomic% of the sum of In and M. In, preferably, In is higher than 25 atomic%, M is less than 75 atomic%, more preferably, In is higher than 34 atomic%, and M is less than 66 atomic%.

  The channel region 108i has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of the transistor 150 can be reduced by using an oxide semiconductor with a wide energy gap.

  The thickness of the first oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm. The thickness of the second oxide semiconductor films 111a and 111b is 3 nm to 100 nm, preferably 30 nm to 70 nm, more preferably 30 nm to 50 nm.

  In the case where the oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b are In-M-Zn oxides, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxides Preferably satisfies In ≧ M and Zn ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, etc. are preferable. Note that the atomic ratio of the oxide semiconductor film 108 to be formed may vary by about plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 4: 2. : It may be in the vicinity of 3. In the case where an atomic ratio of In: Ga: Zn = 5: 1: 7 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 5: 1: 6. May be near.

As the channel region 108i, an oxide semiconductor film with low carrier density is used. For example, the channel region 108 i has a carrier density of 1 × 10 ¹⁷ pieces / cm ³ or less, preferably 1 × 10 ¹⁵ pieces / cm ³ or less, more preferably 1 × 10 ¹³ pieces / cm ³ or less, more preferably 1 ×. An oxide semiconductor film with a density of 10 ¹¹ pieces / cm ³ or less is used.

  Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the first oxide semiconductor film 108 are appropriately Preferably.

When the first oxide semiconductor film 108 contains silicon or carbon which is one of Group 14 elements, oxygen vacancies increase in the first oxide semiconductor film 108 and become n-type. Therefore, the concentration of silicon or carbon in the first oxide semiconductor film 108 (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm 3. ³ or less.

In the channel region 108i, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. . When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the first oxide semiconductor film 108.

In addition, when nitrogen is contained in the channel region 108i, electrons as carriers are generated, the carrier density is increased, and the channel region 108i is likely to be n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less. .

Further, in the channel region 108 i, the carrier density of the oxide semiconductor film can be reduced by reducing the impurity element. For this reason, in the channel region 108i, the carrier density is 1 × 10 ¹⁷ pieces / cm ³ or less, or 1 × 10 ¹⁵ pieces / cm ³ or less, or 1 × 10 ¹³ pieces / cm ³ or less, or 1 × 10 ¹¹ pieces. / Cm ³ or less.

  By using an oxide semiconductor film having a low impurity concentration and a low density of defect states as the channel region 108i, a transistor having more excellent electrical characteristics can be manufactured. Here, the low impurity concentration and the low density of defect states (there are few oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. Alternatively, it is called intrinsic or substantially intrinsic. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film easily has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have characteristics with extremely low off-state current. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a small variation in electrical characteristics and may be a highly reliable transistor.

  On the other hand, the source region 108 s and the drain region 108 d are in contact with the insulating film 116. When the source region 108s and the drain region 108d are in contact with the insulating film 116, nitrogen or hydrogen is added from the insulating film 116 to the source region 108s and the drain region 108d, so that the carrier density is increased.

  Further, the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b may have a non-single-crystal structure. The non-single-crystal structure includes, for example, a CAAC-OS (C Axis-Aligned-Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

  Note that the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b include an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single region. A single layer film having two or more kinds of crystal structure regions or a structure in which these films are stacked may be used.

  Note that the first oxide semiconductor film 108 is an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, or a mixed film including two or more kinds of single crystal structures. May be. For example, the mixed film may include two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. For example, the mixed film has a stacked structure of two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. May have.

  Note that in the first oxide semiconductor film 108, the channel region 108i may have different crystallinity from the source region 108s and the drain region 108d. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when the impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 108d are damaged, and crystallinity is lowered.

<Second insulating film>
The insulating film 110 functions as a gate insulating film of the transistor 150. The insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly the channel region 108i. For example, the insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, a region in the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using at least the oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.

  The thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.

The insulating film 110 preferably has few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) be small. For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. As the insulating film 110, a silicon oxide film or a silicon oxynitride film whose spin density due to the E ′ center is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less is used. Good.

In addition, in the insulating film 110, a signal due to nitrogen dioxide (NO ₂ ) may be observed in addition to the above signal. The signal is split into three signals by N nuclear spins, each having a g value of 2.037 or more and 2.039 or less (referred to as the first signal), and a g value of 2.001 or more and 2.003. The g value is observed below (referred to as the second signal) and from 1.964 to 1.966 (referred to as the third signal).

For example, as the insulating film 110, an insulating film whose spin density due to nitrogen dioxide (NO ₂ ) is 1 × 10 ¹⁷ spins / cm ³ or more and less than 1 × 10 ¹⁸ spins / cm ³ is preferably used.

Note that nitrogen oxide (NO _x ) containing nitrogen dioxide (NO ₂ ) forms a level in the insulating film 110. The level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide (NOx) diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 110 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, when the insulating film 110 is a film with a low content of nitrogen oxides, the threshold voltage shift of the transistor can be reduced.

For example, a silicon oxynitride film can be used as the insulating film that emits less nitrogen oxide (NO _x ). The silicon oxynitride film is a film in which the amount of ammonia released is larger than the amount of nitrogen oxide (NO _x ) released in a temperature programmed desorption gas analysis (TDS). The discharge amount is 1 × 10 ¹⁸ pieces / cm ³ or more and 5 × 10 ¹⁹ pieces / cm ³ or less. Note that the amount of ammonia released is the total amount when the temperature of the heat treatment in TDS is in the range of 50 ° C. to 650 ° C. or 50 ° C. to 550 ° C.

Since nitrogen oxide (NO _x ) reacts with ammonia and oxygen in the heat treatment, nitrogen oxide (NO _x ) is reduced by using an insulating film that releases a large amount of ammonia.

Note that when the insulating film 110 is analyzed by SIMS, the nitrogen concentration in the film is preferably 6 × 10 ²⁰ atoms / cm ³ or less.

Further, as the insulating film 110, hafnium silicate (HfSiO _x ), hafnium silicate added with nitrogen (HfSi _x O _y N _z ), hafnium aluminate added with nitrogen (HfAl _x O _y N _z ), hafnium oxide, or the like High-k materials may be used. By using the high-k material, gate leakage of the transistor can be reduced.

<Third insulating film>
The insulating film 116 includes nitrogen or hydrogen. The insulating film 116 may contain fluorine. An example of the insulating film 116 is a nitride insulating film. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon nitride fluoride, silicon fluoronitride, or the like. The concentration of hydrogen contained in the insulating film 116 is preferably 1 × 10 ²² atoms / cm ³ or more. The insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Therefore, the impurity (nitrogen or hydrogen) concentration in the source region 108s and the drain region 108d in contact with the insulating film 116 is increased, and the carrier density of the source region 108s and the drain region 108d can be increased.

<Fourth insulating film>
As the insulating film 118, an oxide insulating film can be used. As the insulating film 118, a stacked film of an oxide insulating film and a nitride insulating film can be used. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used.

  The insulating film 118 is preferably a film that functions as a barrier film for hydrogen, water, and the like from the outside.

  The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

<Conductive film>
The conductive films 120a and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. In addition, as the conductive films 120a and 120b, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above metal element as a component, It can be formed using an alloy or the like in which the above metal elements are combined. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. In addition, the conductive films 120a and 120b may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding Two-layer structure in which tungsten film is laminated on titanium film, two-layer structure in which tungsten film is laminated on tantalum nitride film or tungsten nitride film, two-layer structure in which copper film is laminated on copper film containing manganese, on titanium film A two-layer structure in which a copper film is laminated, a titanium film, an aluminum film is laminated on the titanium film, and a three-layer structure in which a titanium film is formed thereon, and a copper film is laminated on a copper film containing manganese Further, there is a three-layer structure on which a copper film containing manganese is formed. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

  In particular, the conductive films 120a and 120b are preferably formed using a material containing copper. When a material containing copper is used for the conductive films 120a and 120b, the resistance can be reduced. For example, signal delay or the like can be suppressed even when a large-area substrate is used as the substrate 102.

  The conductive film 123 includes indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin oxide containing titanium oxide. A light-transmitting conductive material such as indium zinc oxide or indium tin oxide containing silicon (In-Sn-Si oxide: also referred to as ITSO). Note that these conductive materials having a light-transmitting property may be used for the conductive films 120a and 120b. The conductive films 120a and 120b can have a stacked structure of the above light-transmitting conductive material and the above metal element.

  The conductive film 124 and the conductive film 120c can be formed using a material similar to that of the conductive film 120a and the conductive film 120b.

<Fifth insulating film>
As the insulating film 122 functioning as a protective insulating film of the transistor 150, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a plasma CVD method, a sputtering method, or the like An insulating film containing one or more of yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film can be used. Alternatively, the insulating film 122 can be formed using a material similar to that of the third insulating film or the fourth insulating film.

<Configuration Example 2 of Semiconductor Device>
Next, a structure different from the semiconductor device 100 illustrated in FIGS. 1A and 1B is described with reference to FIGS.

  FIG. 5A is a cross-sectional view of the semiconductor device 100A, and FIG. 5B is a cross-sectional view of the semiconductor device 100B. Note that top views of the semiconductor device 100A and the semiconductor device 100B are the same as those of the semiconductor device 100 illustrated in FIG. 1A, and thus description thereof is omitted here.

  A transistor 150A included in the semiconductor device 100A illustrated in FIG. 5A is different from the transistor 150 included in the semiconductor device 100 described above in the shapes of the insulating film 110 and the second oxide semiconductor film 111a. Specifically, in the cross section of the transistor in the channel length (L) direction, the transistor 150 has a tapered shape in the insulating film 110 and the second oxide semiconductor film 111a, whereas the transistor 150A has an insulating shape. The shapes of the film 110 and the second oxide semiconductor film 111a are rectangular. More specifically, in the transistor 150, the upper end portion of the second oxide semiconductor film 111 a is formed inside the lower end portion of the insulating film 110 in the cross section in the channel length (L) direction of the transistor. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the second oxide semiconductor film 111a. On the other hand, in the transistor 150A, the upper end portion of the second oxide semiconductor film 111a and the lower end portion of the insulating film 110 are formed at approximately the same position in a cross section of the transistor in the channel length (L) direction.

  The transistor 150 can be formed by processing the second oxide semiconductor film 111a and the insulating film 110 with the same mask and combining wet etching and dry etching. The transistor 150A can be formed by processing the second oxide semiconductor film 111a and the insulating film 110 with the same mask and collectively processing them using a dry etching method.

  A structure like the transistor 150 is preferable because coverage with the insulating film 116 is improved. On the other hand, a structure like the transistor 150A is preferable because end portions of the source region 108s and the drain region 108d and the second oxide semiconductor film 111a are formed at approximately the same position.

  A transistor 150B included in the semiconductor device 100B illustrated in FIG. 5B is different in the shapes of the second oxide semiconductor film 111a and the insulating film 110 from the transistor 150A described above. Specifically, in the transistor 150B, the position of the lower end portion of the second oxide semiconductor film 111a and the upper end portion of the insulating film 110 are different in a cross section in the channel length (L) direction of the transistor. The lower end portion of the second oxide semiconductor film 111 a is formed inside the upper end portion of the insulating film 110.

  For example, the second oxide semiconductor film 111a and the insulating film 110 are processed with the same mask, the second oxide semiconductor film 111a is processed with a wet etching method, and the insulating film 110 is processed with a dry etching method. Thus, the structure of the transistor 150B can be obtained.

  In addition, with the structure of the transistor 150B, the region 108f may be formed in the first oxide semiconductor film 108 in some cases. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

  The region 108f functions as either a high resistance region or a low resistance region. The high-resistance region is a region that has the same resistance as that of the channel region 108 i and does not overlap with the second oxide semiconductor film 111 a that functions as a gate electrode. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. In the case where the region 108f functions as an offset region, the region 108f may be 1 μm or less in the cross section in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 150B.

  The low resistance region is a region having a lower resistance than the channel region 108i and a higher resistance than the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. In the case where the region 108f functions as an LDD region, electric field relaxation in the drain region is possible, so that variation in threshold voltage of the transistor due to the electric field in the drain region can be reduced.

  Note that in the case where the region 108f is an LDD region, for example, nitrogen or hydrogen is supplied from the insulating film 116 to the region 108f or the second oxide semiconductor film 111a and the insulating film 110 are used as a mask. By adding an impurity element from above the oxide semiconductor film 111 a and the insulating film 110, the impurity can be formed by adding the impurity to the first oxide semiconductor film 108 through the insulating film 110.

<Configuration Example 3 of Semiconductor Device>
Next, a structure different from that of the semiconductor device 100 illustrated in FIGS. 1A and 1B is described with reference to FIGS.

  6A is a cross-sectional view of the semiconductor device 100C, FIG. 6B is a cross-sectional view of the semiconductor device 100D, and FIG. 7A is a cross-sectional view of the semiconductor device 100E. FIG. 8B is a cross-sectional view of the semiconductor device 100F, and FIG. 8 is a cross-sectional view of the semiconductor device 100G. Note that top views of the semiconductor device 100C, the semiconductor device 100D, the semiconductor device 100E, the semiconductor device 100F, and the semiconductor device 100G are the same as those of the semiconductor device 100 illustrated in FIG. 1A; therefore, description thereof is omitted here. To do.

  The transistor 150C included in the semiconductor device 100C, the transistor 150D included in the semiconductor device 100D, the transistor 150E included in the semiconductor device 100E, the transistor 150F included in the semiconductor device 100F, and the transistor 150G included in the semiconductor device 100G are described above. The structures of the transistor 150A and the first oxide semiconductor film 108 are different. Other configurations are similar to those of the transistor 150A described above, and have the same effects.

  The first oxide semiconductor film 108 included in the transistor 150C illustrated in FIG. 6A includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor. An oxide semiconductor film 108_3 over the film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.

  A first oxide semiconductor film 108 included in the transistor 150D illustrated in FIG. 6B includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3.

  A first oxide semiconductor film 108 included in the transistor 150E illustrated in FIG. 7A includes an oxide semiconductor film 108_1 over the insulating film 104 and an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

  A first oxide semiconductor film 108 included in the transistor 150F illustrated in FIG. 7B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor. An oxide semiconductor film 108_3 over the film 108_2. The channel region 108i has a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3. The source region 108s and the drain region 108d each have an oxide semiconductor film. A two-layer structure of 108_1 and the oxide semiconductor film 108_2. Note that in the cross section in the channel width (W) direction of the transistor 150F, the oxide semiconductor film 108_3 covers side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

  The first oxide semiconductor film 108 included in the transistor 150G illustrated in FIG. 8 includes the oxide semiconductor film 108_2 over the insulating film 104 and the oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. The channel region 108i has a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3, and the source region 108s and the drain region 108d have a single layer structure of the oxide semiconductor film 108_2, respectively. is there. Note that in the cross section in the channel width (W) direction of the transistor 150G, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.

  In the side surface of the channel region 108i in the channel width (W) direction or in the vicinity thereof, defects (for example, oxygen vacancies) are likely to be formed due to damage in processing, or contamination due to adhesion of impurities. Therefore, even when the channel region 108i is substantially intrinsic, application of stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing the low resistance (n Type) area. When the side surface in the channel width (W) direction of the channel region 108i or the vicinity thereof is an n-type region, a parasitic channel may be formed because the n-type region serves as a carrier path.

  Thus, in the transistor 150F and the transistor 150G, the channel region 108i has a stacked structure, and the side surface of the channel region 108i in the channel width (W) direction is covered with one layer of the stacked structure. With this structure, defects on the side surface of the channel region 108i or the vicinity thereof can be suppressed, or adhesion of impurities to the side surface of the channel region 108i or the vicinity thereof can be reduced.

<Band structure>
Here, the band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110, the band structure of the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110, and the insulating film 104, A band structure of the oxide semiconductor films 108_1 and 108_2 will be described with reference to FIGS. 9A to 9C show a band structure in the channel region 108i.

  FIG. 9A illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110. FIG. 9B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. FIG. 9C illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1 and 108_2, and the insulating film 110. Note that the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.

  FIG. 9A illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110, and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. An oxide semiconductor film is used, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 2 as an oxide semiconductor film 108_3 is used. It is a band diagram.

  FIG. 9B illustrates a case where a silicon oxide film is used as the insulating films 104 and 110 and a metal oxide atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the oxide semiconductor film 108_2. An oxide semiconductor film formed using an object target is used, and the oxide semiconductor film 108_3 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 1: 3: 2. FIG. 10 is a band diagram of a structure using an oxide semiconductor film.

  FIG. 9C illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110 and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed using an oxide semiconductor film.

  As shown in FIG. 9A, in the oxide semiconductor films 108_1, 108_2, and 108_3, the energy level at the lower end of the conduction band changes gently. In addition, as illustrated in FIG. 9B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. In addition, as illustrated in FIG. 9C, in the oxide semiconductor films 108_1 and 108_2, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.

  In order to form a continuous bond with the oxide semiconductor films 108_1, 108_2, and 108_3, each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.

  With the structure illustrated in FIGS. 9A to 9C, the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure. I understand.

  Note that by providing the oxide semiconductor films 108_1 and 108_3, trap levels that can be formed in the oxide semiconductor film 108_2 can be separated from the oxide semiconductor film 108_2.

  In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the trap level. . Accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, a structure in which the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 is preferable. By doing so, electrons are unlikely to accumulate in the trap level, the on-state current of the transistor can be increased, and field effect mobility can be increased.

  The oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.

  With such a structure, the oxide semiconductor film 108_2 serves as a main current path. In other words, the oxide semiconductor film 108_2 functions as a channel region, and the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed. With such a structure, interface scattering hardly occurs at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.

  The oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions. Alternatively, in the oxide semiconductor films 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is lower than that of the oxide semiconductor film 108_2, and the energy level at the bottom of the conduction band is an oxide. A material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used. In addition, in order to suppress the difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to apply a material closer to the vacuum level than 0.2 eV than the energy level at the lower end of the band, preferably a material closer to the vacuum level of 0.5 eV or more.

  In this embodiment, the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2. Although the configuration using the film is exemplified, the configuration is not limited thereto. For example, as the oxide semiconductor films 108_1 and 108_3, In: Ga: Zn = 1: 1: 1 [atomic ratio], In: Ga: Zn = 1: 1: 1.2 [atomic ratio], In: Ga : Zn = 1: 3: 4 [atomic ratio], In: Ga: Zn = 1: 3: 6 [atomic ratio], In: Ga: Zn = 1: 4: 5 [atomic ratio], In: Using an oxide semiconductor film formed using a metal oxide target of Ga: Zn = 1: 5: 6 [atomic ratio] or In: Ga: Zn = 1: 10: 1 [atomic ratio] Also good. Alternatively, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements Ga: Zn = 10: 1 may be used as the oxide semiconductor films 108_1 and 108_3. In this case, as the oxide semiconductor film 108_2, an oxide semiconductor film formed using a metal oxide target with a metal element atomic ratio of In: Ga: Zn = 1: 1: 1 is used, and the oxide semiconductor film 108_1. , 108_3, an oxide semiconductor film formed using a metal oxide target with a metal element atomic ratio of Ga: Zn = 10: 1 can have an energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. The oxide semiconductor films 108_1 and 108_3 are preferable because the difference from the energy level at the lower end of the conduction band can be 0.6 eV or more.

  Note that in the case where a metal oxide target with In: Ga: Zn = 1: 1: 1 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2). In the case where a metal oxide target with In: Ga: Zn = 1: 3: 4 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) in some cases. In the case where a metal oxide target with In: Ga: Zn = 1: 3: 6 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) in some cases.

<Method for Manufacturing Semiconductor Device>
Next, an example of a method for manufacturing the semiconductor device illustrated in FIG. 1 is described with reference to FIGS. 10A to 13B are cross-sectional views in the channel length (L) direction and the channel width (W) direction for describing a method for manufacturing the transistor 150 and the capacitor 160.

  First, the gate electrode 106 is formed over the substrate 102. Next, the insulating film 104 is formed over the substrate 102 and the gate electrode 106, and an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film is processed into an island shape, so that the oxide semiconductor film 107 is formed (see FIG. 10A).

  In this embodiment, a sputtering method is used as the gate electrode 106, and a stacked film of a tantalum nitride film with a thickness of 50 nm and a copper film with a thickness of 100 nm is formed. Note that as a method for processing the conductive film to be the gate electrode 106, one or both of a wet etching method and a dry etching method may be used. Here, after the copper film is etched by a wet etching method, the conductive film is processed by etching the tantalum nitride film by a dry etching method, whereby the gate electrode 106 is formed.

  The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, a plasma CVD apparatus is used as the insulating film 104 to form a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film.

  Alternatively, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Examples of oxygen added to the insulating film 104 include oxygen radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions. Examples of the addition method include an ion doping method, an ion implantation method, and a plasma treatment method. Alternatively, after a film for suppressing desorption of oxygen is formed over the insulating film, oxygen may be added to the insulating film 104 through the film.

  A conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten is used as the above-described film for suppressing desorption of oxygen. Can be formed.

  In addition, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with a microwave to generate high-density oxygen plasma.

  The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that the oxide semiconductor film 107 can be processed by forming a mask over the oxide semiconductor film by a lithography process and then etching part of the oxide semiconductor film using the mask. Alternatively, the element-separated oxide semiconductor film 107 may be directly formed by a printing method.

  In the case of forming an oxide semiconductor film by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are used as appropriate. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

  Note that when the oxide semiconductor film is formed, for example, when a sputtering method is used, the substrate temperature is set to 150 ° C. to 750 ° C., 150 ° C. to 450 ° C., or 200 ° C. to 350 ° C. Forming a film is preferable because crystallinity can be improved.

  Note that in this embodiment, a sputtering apparatus is used as the oxide semiconductor film 107, and an In—Ga—Zn metal oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio] is used as a sputtering target. ]) Is used to form an oxide semiconductor film having a thickness of 35 nm.

  Alternatively, after the oxide semiconductor film 107 is formed, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

  The heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, or the like. The treatment time may be 3 minutes or more and 24 hours or less.

  For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed, heat treatment is performed, so that the hydrogen concentration obtained by SIMS in the oxide semiconductor film is 5 × 10 ¹⁹ atoms / cm ^3. Or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less.

  Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 10B).

  As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film can be formed using a plasma enhanced chemical vapor deposition apparatus (a PECVD apparatus or simply a plasma CVD apparatus). In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

  In addition, as the insulating film 110_0, a PECVD apparatus in which an oxidizing gas with respect to a deposition gas is greater than 20 times and less than 100 times, or greater than or equal to 40 times and less than or equal to 80 times and a pressure in the treatment chamber is less than 100 Pa or less than 50 Pa is used. Thus, a silicon oxynitride film with a small amount of defects can be formed.

  In addition, as the insulating film 110_0, the substrate placed in the processing chamber evacuated in the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa. Hereinafter, a dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 110_0 under conditions where the pressure is higher than or equal to 100 Pa and lower than or equal to 250 Pa and high-frequency power is supplied to an electrode provided in the treatment chamber.

  Alternatively, the insulating film 110_0 may be formed by a plasma CVD method using a microwave. Microwave refers to the frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature and a low electron energy. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110_0 with little plasma damage to the deposition surface and deposits and few defects can be formed.

The insulating film 110_0 can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. Use of silicon-containing compounds such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) it can. By using a CVD method using an organosilane gas, the insulating film 110_0 with high coverage can be formed.

  In this embodiment, as the insulating film 110_0, a silicon oxynitride film with a thickness of 100 nm is formed using a PECVD apparatus.

  Next, after a mask is formed by lithography at a desired position over the insulating film 110_0, the insulating film 110_0 and a part of the insulating film 104 are etched to form an opening 143 that reaches the gate electrode 106 (see FIG. (See FIG. 10C).

  As a method for forming the opening 143, one or both of a wet etching method and a dry etching method may be used. In this embodiment, the opening 143 is formed using a dry etching method.

  Next, the oxide semiconductor film 111_0 is formed over the insulating film 110_0 so as to cover the opening 143. When the oxide semiconductor film 111_0 is formed, oxygen is added from the oxide semiconductor film 111_0 to the insulating film 110_0 (see FIG. 10D).

  Note that in FIG. 10D, oxygen added to the insulating film 110_0 is schematically represented by an arrow.

  As a formation method of the oxide semiconductor film 111_0, a sputtering method is preferably used in an atmosphere containing oxygen gas at the time of formation. By forming the oxide semiconductor film 111_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be preferably added to the insulating film 110_0. Note that a method for forming the oxide semiconductor film 111_0 is not limited to a sputtering method, and other methods such as an ALD method may be used.

  In this embodiment, as the oxide semiconductor film 111_0, an IGZO film (In: Ga: Zn = 4: 2: 4.1) which is an In—Ga—Zn oxide with a thickness of 50 nm is formed by a sputtering method. Alternatively, an oxygen addition treatment may be performed on the insulating film 110_0 before the oxide semiconductor film 111_0 is formed or after the oxide semiconductor film 111_0 is formed. The method may be similar to the addition of oxygen that can be performed after the insulating film 104 is formed.

  Next, a mask 140 is formed at a desired position over the oxide semiconductor film 111_0 by a lithography process (see FIG. 11A).

  Next, etching is performed from above the mask 140 to process the conductive film 112_0 and the insulating film 110_0. After that, the mask 140 is removed, so that the island-shaped oxide semiconductor film 111 and the island-shaped insulating film 110 are formed (see FIG. 11B).

  In this embodiment, the conductive film 112_0 and the insulating film 110_0 are processed by a dry etching method.

  Note that when the oxide semiconductor film 111_0 and the insulating film 110 are processed, the thickness of the oxide semiconductor film 107 in a region where the oxide semiconductor film 111 is not overlapped may be thin. Alternatively, when the oxide semiconductor film 111_0 and the insulating film 110 are processed, the thickness of the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap may be reduced. Further, when the oxide semiconductor film 111_0 and the insulating film 110_0 are processed, an etchant or an etching gas (eg, chlorine) is added to the oxide semiconductor film 107, or the oxide semiconductor film 111_0 or the insulating film In some cases, the constituent element 110 — 0 is added to the oxide semiconductor film 107.

  Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the oxide semiconductor film 111. Note that when the insulating film 116 is formed, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. The oxide semiconductor film 107 in contact with the insulating film 110 serves as a channel region 108i. Thus, the first oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed. In addition, when the insulating film 116 is formed, the oxide semiconductor film 111 in contact with the insulating film becomes the second oxide semiconductor films 111a and 111b (see FIG. 11C).

  Note that in FIG. 11C, the film and the region whose resistance has been reduced by the formation of the insulating film 116 are illustrated with hatching changed from that before the resistance is reduced.

  The insulating film 116 can be formed by selecting the material described above. In this embodiment, a 100-nm-thick silicon nitride oxide film is formed as the insulating film 116 using a PECVD apparatus.

  By using a silicon nitride oxide film as the insulating film 116, nitrogen or hydrogen in the silicon nitride oxide film can be supplied to the source region 108s and the drain region 108d in contact with the insulating film 116.

  Further, an impurity element is added to the oxide semiconductor film 107 and / or the oxide semiconductor film 111 before the insulating film 116 is formed, or the oxide film is interposed through the insulating film 116 after the insulating film 116 is formed. An impurity element addition treatment may be performed on the semiconductor film 107 and / or the oxide semiconductor film 111.

  Examples of the impurity element addition treatment include an ion doping method, an ion implantation method, and a plasma treatment method. In the case of the plasma treatment method, the impurity element can be added by performing plasma treatment by generating plasma in a gas atmosphere containing the impurity element to be added. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

Note that as source gases for impurity elements, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H _2, and rare gas One or more can be used. Alternatively, one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas can be used. Note that typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

Alternatively, after adding a rare gas, one of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ The above may be added to the oxide semiconductor film 107. Or, after adding one or more of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ , rare A gas may be added to the oxide semiconductor film 107.

  Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 12A).

  The insulating film 118 can be formed by selecting any of the materials described above. In this embodiment, a 300-nm-thick silicon oxynitride film is formed as the insulating film 118 using a PECVD apparatus.

  Next, after a mask is formed by lithography at a desired position of the insulating film 118, a part of the insulating film 118 and the insulating film 116 is etched, so that the opening 141a reaching the source region 108s and the drain region 108d are formed. An opening 141b reaching and an opening 142 reaching the second oxide semiconductor film 111b are formed (see FIG. 12B).

  As a method for etching the insulating film 118 and the insulating film 116, one or both of a wet etching method and a dry etching method may be used. In this embodiment, the insulating film 118 and the insulating film 116 are processed using a dry etching method.

  Next, a conductive film is formed over the source region 108s, the drain region 108d, the second oxide semiconductor film 111b, and the insulating film 118 so as to cover the openings 141a, 141b, and 142, and the conductive film is formed into a desired shape. The conductive films 120a and 120b are formed by processing into a shape. Note that at this point, the transistor 150 is formed (see FIG. 12C).

  The conductive films 120a and 120b can be formed by selecting the materials described above. In this embodiment, a stacked film of a 50-nm-thick tungsten film and a 400-nm-thick copper film is formed as the conductive films 120a and 120b using a sputtering apparatus.

  Note that as a method for processing the conductive film to be the conductive films 120a and 120b, one or both of a wet etching method and a dry etching method may be used. In this embodiment, after the copper film is etched by a wet etching method, the conductive film is processed by etching the tungsten film by a dry etching method, so that the conductive films 120a and 120b are formed.

  Next, the insulating film 122 is formed over the conductive films 120a and 120b and the insulating film 118 (see FIG. 13A).

  The insulating film 122 can be formed by selecting the material described above. In this embodiment, as the insulating film 122, a silicon nitride film with a thickness of 100 nm is formed using a plasma CVD apparatus.

  Next, a conductive film is formed over the insulating film 122, and the conductive film is processed into a desired shape, whereby the conductive film 123 is formed. Note that the capacitor 160 is formed at this time (see FIG. 13B). Note that in the case where the resistance value of the conductive film 123 is higher than a desired value, a conductive film serving as an auxiliary electrode may be formed over the conductive film 123.

  The conductive film 123 can be formed by selecting any of the materials described above. In this embodiment, as the conductive film 123, indium tin oxide with a thickness of 100 nm is formed using a sputtering apparatus.

  Through the above steps, the semiconductor device 100 (the transistor 150 and the capacitor 160) illustrated in FIG. 1 can be manufactured.

  Note that as a film included in the transistor 150 (an insulating film, a metal oxide film, an oxide semiconductor film, a conductive film, or the like), in addition to the above formation method, a sputtering method, a chemical vapor deposition (CVD) method, or a vacuum evaporation method is used. It can be formed using a pulse laser deposition (PLD) method or an ALD method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma enhanced chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. An example of the thermal CVD method is a metal organic chemical deposition (MOCVD) method.

  In the thermal CVD method, the inside of a chamber is set to atmospheric pressure or reduced pressure, and a source gas and an oxidant are simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. Thus, the thermal CVD method is a film forming method that does not generate plasma, and thus has an advantage that no defect is generated due to plasma damage.

A thermal CVD method such as an MOCVD method can form a film such as the above-described conductive film, insulating film, oxide semiconductor film, or metal oxide film. For example, an In—Ga—Zn—O film is formed. In this case, trimethylindium (In (CH ₃ ) ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), and dimethyl zinc are used (Zn (CH ₃ ) ₂ ). Without being limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) is used instead of dimethylzinc. You can also.

In the case where a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] ₄ ) ) Or tetrakis (ethylmethylamide) hafnium) or the like, and two gases of ozone (O ₃ ) are used as an oxidizing agent.

When an aluminum oxide film is formed by a film forming apparatus using ALD, a source gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA, Al (CH ₃ ) ₃ )) containing a solvent and an aluminum precursor is used. Two types of gas, H ₂ O, are used as the oxidizing agent. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

Further, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

Further, when a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then WF ₆ gas and H ₂ gas. To form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

In the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, an In—O layer is formed using In (CH ₃ ) ₃ gas and O ₃ gas. Then, a GaO layer is formed using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using Zn (CH ₃ ) ₂ gas and O ₃ gas. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of an oxide semiconductor that can be used for a transistor and a capacitor of the semiconductor device of one embodiment of the present invention will be described.

  Hereinafter, the structure of the oxide semiconductor is described.

  In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, the CAAC-OS will be described.

A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to the crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 14E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 14E is considered to be caused by the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 14E is considered to be due to the (110) plane and the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

FIG. 15A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 15A shows a pellet that is a region where metal atoms are arranged in a layered manner. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

15B and 15C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 15D and 15E are images obtained by performing image processing on FIGS. 15B and 15C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is obtained by performing a fast Fourier transform (FFT) process on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 15D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 15E, a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding lattice points around the lattice points in the vicinity of the dotted line, a distorted hexagon, pentagon and / or heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ³ , more preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm 3. An oxide semiconductor having a carrier density of ³ or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 16B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 16B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagon is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

FIG. 16D illustrates a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a fine crystal oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 17 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 17A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 17B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIG. 17A and FIG. 17B, it can be seen that in the a-like OS, a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as an InGaZnO ₄ crystal part. Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 18 is an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 18, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative irradiation amount of electrons related to the acquisition of the TEM image or the like. As shown in FIG. 18, in the crystal part (also referred to as initial nucleus) which was about 1.2 nm in the initial observation by TEM, the cumulative dose of electrons (e ⁻ ) is 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 18 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, a display device 80 which is one embodiment of the present invention will be described with reference to FIGS.

  In the display device 80 illustrated in FIG. 19A, the pixel portion 71, the scanning line driver circuit 74, and the signal line driver circuit 76 are arranged in parallel or substantially in parallel, and the potential is generated by the scanning line driver circuit 74. And m scanning lines 77, each of which is arranged in parallel or substantially in parallel, and n signal lines 79 whose potentials are controlled by the signal line driving circuit 76. Further, the pixel unit 71 includes a plurality of pixels 70 arranged in a matrix. Further, along the signal line 79, each has a common line 75 arranged in parallel or substantially in parallel. Further, the scanning line driving circuit 74 and the signal line driving circuit 76 may be collectively referred to as a driving circuit unit.

  Each scanning line 77 is electrically connected to n pixels 70 arranged in one of the pixels 70 arranged in m rows and n columns in the pixel portion 71. Each signal line 79 is electrically connected to m pixels 70 arranged in any column among the pixels 70 arranged in m rows and n columns. m and n are both integers of 1 or more. Each common line 75 is electrically connected to m pixels 70 arranged in any row among the pixels 70 arranged in m rows and n columns.

  FIG. 19B illustrates an example of a circuit configuration that can be used for the pixel 70 of the display device 80 illustrated in FIG.

  A pixel 70 illustrated in FIG. 19B includes a liquid crystal element 51, a transistor 52, and a capacitor 55.

  One of the pair of electrodes of the liquid crystal element 51 is connected to the transistor 52, and the potential is appropriately set according to the specifications of the pixel 70. The other of the pair of electrodes of the liquid crystal element 51 is connected to the common line 75, and a common potential (common potential) is applied to the potential. The alignment state of the liquid crystal included in the liquid crystal element 51 is controlled by data written in the transistor 52.

  The liquid crystal element 51 is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used in the liquid crystal element 51, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

  In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with several weight percent or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic. In addition, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .

  As a driving method of the display device 80 including the liquid crystal element 51, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned Micro) mode, and the like. An OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like can be used.

  The display device 80 may be a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, or the like can be used.

  In this embodiment mode, a horizontal electric field method, typically an FFS mode and a DPS mode described later will be mainly described.

  In the structure of the pixel 70 illustrated in FIG. 19B, one of a source electrode and a drain electrode of the transistor 52 is electrically connected to the signal line 79, and the other is electrically connected to one of the pair of electrodes of the liquid crystal element 51. Connected. The first gate electrode of the transistor 52 is electrically connected to the scan line 77. The transistor 52 has a function of controlling data writing of the data signal. The transistor 52 includes a second gate electrode that is electrically connected to the first gate electrode. That is, in the transistor 52, the first gate electrode and the second gate electrode have the same potential. Note that the first gate electrode and the second gate electrode may operate independently and be supplied with different potentials. For example, the second gate electrode may be electrically connected to a wiring 78 having a function of applying a potential different from that of the scan line 77 (see FIG. 19C). Further, the transistor 52 may not have the first gate electrode or the second gate electrode.

  In the structure of the pixel 70 illustrated in FIG. 19B, one of the pair of electrodes of the capacitor 55 is connected to the other of the source electrode and the drain electrode of the transistor 52. The other of the pair of electrodes of the capacitor 55 is electrically connected to the common line 75. The value of the potential of the common line 75 is appropriately set according to the specifications of the pixel 70. The capacitor 55 has a function as a storage capacitor for storing written data. Note that in the display device 80 driven in the FFS mode, one of the pair of electrodes of the capacitor 55 is part or all of one of the pair of electrodes of the liquid crystal element 51, and the other of the pair of electrodes of the capacitor 55 Is a part or all of the other of the pair of electrodes of the liquid crystal element 51.

<Configuration example of element substrate>
Next, a specific configuration of the element substrate included in the display device 80 will be described. First, FIG. 20 shows a top view of a plurality of pixels 70a, 70b, and 70c included in the display device 80 driven in the FFS mode.

  In FIG. 20, the conductive film 13 functioning as a scanning line is provided to extend in a direction substantially orthogonal to the signal line (left and right direction in the figure). The conductive film 21a functioning as a signal line is provided to extend in a direction (vertical direction in the drawing) substantially orthogonal to the scanning line. Note that the conductive film 13 functioning as a scan line (the scan line 77 in FIG. 19A) is electrically connected to the scan line driver circuit 74, and the conductive film 21a functioning as a signal line (FIG. 19A). ) Is electrically connected to the signal line driver circuit 76 (see FIG. 19A).

  The transistor 52 is provided in the vicinity of the intersection of the scanning line and the signal line. The transistor 52 includes a conductive film 13 functioning as a first gate electrode, a first gate insulating film (not shown in FIG. 20), and a first oxide semiconductor film 18 formed over the first gate insulating film. , Conductive films 21a and 21b that function as one or the other of the source electrode and the drain electrode, the second gate insulating film formed on the channel region 18i, and the second gate insulating film formed on the second gate insulating film, respectively. The second oxide semiconductor film 19a functions as the second gate electrode. Note that the first oxide semiconductor film 18 includes a channel region 18i overlapping with the second oxide semiconductor film 19a, a first source / drain region 18_1 in contact with the conductive film 21a, and a second region in contact with the conductive film 21b. And a source / drain region 18_2. The second oxide semiconductor film 19a is electrically connected to the conductive film 13 through an opening provided in the first gate insulating film and the second gate insulating film.

  The conductive film 13 also functions as a scan line, and a region overlapping with the first oxide semiconductor film 18 functions as a first gate electrode of the transistor 52. The conductive film 21a also functions as a signal line, and a region overlapping with the first source / drain region 18_1 functions as a source electrode or a drain electrode of the transistor 52. In FIG. 20, the conductive film 13 has an end portion located outside the end portion of the channel region 18i in the top surface shape. For this reason, the conductive film 13 functions as a light shielding film that blocks light from a light source such as a backlight. As a result, the channel region 18 i included in the transistor is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed.

  Further, the conductive film 21b is electrically connected to the second oxide semiconductor film 19b having a function of a pixel electrode. In addition, an insulating film (not illustrated in FIG. 20) is provided over the second oxide semiconductor film 19b, and a conductive film 29 is provided over the insulating film.

  The conductive film 29 has a striped region extending in a direction crossing the signal line. The striped region is connected to a region extending in a direction parallel or substantially parallel to the signal line. Therefore, in the plurality of pixels included in the display device 80, the conductive film 29 having a striped region has the same potential in each region.

  The capacitor 55 is formed in a region where the second oxide semiconductor film 19b and the conductive film 29 overlap. The second oxide semiconductor film 19b and the conductive film 29 have a light-transmitting property. That is, the capacitive element 55 has translucency.

  Since the capacitor 55 has a light-transmitting property, the capacitor 55 can be formed large (in a large area) in the pixel 70. Therefore, it is possible to obtain a display device that can be typically set to 50% or more, preferably 60% or more while increasing the aperture ratio, and has an increased capacitance value. For example, in a display device with high resolution, for example, a liquid crystal display device, the area of a pixel is reduced and the area of a capacitor element is also reduced. For this reason, in a display device with high resolution, the capacitance value stored in the capacitor element is small. However, since the capacitor 55 described in this embodiment has a light-transmitting property, the aperture ratio can be increased while obtaining a sufficient capacitance value in each pixel by providing the capacitor in the pixel. Typically, it can be suitably used for a high-resolution display device having a pixel density of 200 ppi or more, further 300 ppi or more, and further 500 ppi or more.

  Further, in the liquid crystal display device, as the capacitance value of the capacitor element is increased, the period during which the alignment of the liquid crystal molecules of the liquid crystal element can be kept constant can be increased in a situation where an electric field is applied. When a still image is displayed, the period can be lengthened, so that the number of times image data is rewritten can be reduced and power consumption can be reduced. In addition, with the structure described in this embodiment, the aperture ratio can be increased even in a high-resolution display device, so that light from a light source such as a backlight can be used efficiently and power consumption of the display device can be reduced. Can be reduced.

  Next, FIG. 21 shows a cross-sectional view taken along one-dot chain line Q1-R1 and one-dot chain line S1-T1 in FIG. A transistor 52 illustrated in FIG. 21 is a top-gate transistor. Note that an alternate long and short dash line Q1-R1 is a cross-sectional view of the transistor 52 in the channel length direction and the capacitor 55, and a cross-sectional view at S1-T1 is a cross-sectional view of the transistor 52 in the channel width direction.

  A transistor 52 illustrated in FIG. 21 includes the conductive film 13 functioning as a first gate electrode provided over the substrate 11. In addition, the insulating film 12 formed over the substrate 11 and the conductive film 13, the first oxide semiconductor film 18 having a region overlapping with the conductive film 13 functioning as a gate electrode with the insulating film 12 interposed therebetween, An insulating film 14 overlapping with the channel region 18 i included in the first oxide semiconductor film 18 on the first oxide semiconductor film 18 and a second gate electrode functioning as the second gate electrode overlapping with the insulating film 14 on the insulating film 14. 2 oxide semiconductor film 19a. An insulating film 15 and an insulating film 16 are provided in this order over the insulating film 12, the first oxide semiconductor film 18, and the second oxide semiconductor film 19a. The conductive film 21a is electrically connected to the first source / drain region 18_1 included in the first oxide semiconductor film 18 through an opening provided in the insulating film 15 and the insulating film 16. The conductive film 21b is electrically connected to the second source / drain region 18_2 included in the first oxide semiconductor film 18 through an opening provided in the insulating film and the insulating film 16. An insulating film 17 is provided over the insulating film 16, the conductive film 21 a, and the conductive film 21 b, and a conductive film 29 is provided over the insulating film 17.

  The transistor 52 is a dual-gate transistor in which the conductive film 13 is a first gate electrode, the second oxide semiconductor film 19a is a second gate electrode, and the channel region 18i is sandwiched between two upper and lower gate electrodes.

  The capacitor 55 includes a second oxide semiconductor film 19b that functions as one of the pair of electrodes of the insulating film 14, and an insulating film that functions as a dielectric film over the second oxide semiconductor film 19b. 15, the insulating film 16 and the insulating film 17, and the conductive film 29 having a function as the other of the pair of electrodes on the insulating film 17.

  Note that the cross-sectional view of one embodiment of the present invention is not limited to this. Various configurations are possible. For example, the second oxide semiconductor film 19b may have a slit. Alternatively, the second oxide semiconductor film 19b may have a comb shape.

  For the structure of the display device 80 of one embodiment of the present invention, the structure of the semiconductor device described in Embodiment 1 can be referred to. That is, the substrate 102 can be referred to for the material and manufacturing method of the substrate 11. For the material and the manufacturing method of the conductive film 13, the gate electrode 106 can be referred to. For the material and manufacturing method of the insulating film 12, the insulating film 104 can be referred to. The material and the manufacturing method of the first oxide semiconductor film 18 can be referred to the first oxide semiconductor film 108. For materials and manufacturing methods of the second oxide semiconductor films 19a and 19b, the second oxide semiconductor films 111a and 111b can be referred to, respectively. For the materials and manufacturing methods of the conductive films 21a and 21b, the conductive films 120a and 120b can be referred to, respectively. For the materials and manufacturing methods of the insulating film 15, the insulating film 16, and the insulating film 17, the insulating film 116, the insulating film 118, and the insulating film 122 can be referred to, respectively. For the material and manufacturing method of the conductive film 29, the conductive film 123 can be referred to.

<Configuration Example of Element Substrate (Modification 1)>
Next, FIG. 22 shows a top view of a plurality of pixels 70d, 70e, and 70f having a configuration different from that of the pixel shown in FIG.

  In FIG. 22, the conductive film 13 functioning as a scanning line is provided extending in the left-right direction in the drawing. The conductive film 21a functioning as a signal line is provided so as to extend in a direction (vertical direction in the figure) substantially perpendicular to the scanning line so that a part of the conductive film 21a is bent (V-shaped). Note that the conductive film 13 functioning as a scan line is electrically connected to the scan line driver circuit 74, and the conductive film 21a functioning as a signal line is electrically connected to the signal line driver circuit 76 ( (See FIG. 19A).

  The transistor 52 is provided in the vicinity of the intersection of the scanning line and the signal line. The transistor 52 includes a conductive film 13 functioning as a first gate electrode, a first gate insulating film (not shown in FIG. 22), and a first oxide semiconductor film 18 formed over the first gate insulating film. , Conductive films 21a and 21b that function as one or the other of the source electrode and the drain electrode, the second gate insulating film formed on the channel region 18i, and the second gate insulating film formed on the second gate insulating film, respectively. The second oxide semiconductor film 19a functions as the second gate electrode. Note that the first oxide semiconductor film 18 includes a channel region 18i overlapping with the second oxide semiconductor film 19a, a first source / drain region 18_1 in contact with the conductive film 21a, and a second region in contact with the conductive film 21b. And a source / drain region 18_2. The second oxide semiconductor film 19a is electrically connected to the conductive film 13 through an opening provided in the first gate insulating film and the second gate insulating film.

  The conductive film 13 also functions as a scan line, and a region overlapping with the first oxide semiconductor film 18 functions as a first gate electrode of the transistor 52. The conductive film 21a also functions as a signal line, and a region overlapping with the first source / drain region 18_1 functions as a source electrode or a drain electrode of the transistor 52. In FIG. 22, the conductive film 13 has an end portion located outside the end portion of the channel region 18i in the top surface shape. For this reason, the conductive film 13 functions as a light shielding film that blocks light from a light source such as a backlight. As a result, the channel region 18 i included in the transistor is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed.

  Further, the conductive film 21b is electrically connected to the second oxide semiconductor film 19b having a function of a pixel electrode. The second oxide semiconductor film 19b is formed in a comb shape. In addition, an insulating film (not shown in FIG. 22) is provided over the second oxide semiconductor film 19b, and a conductive film 29 is provided over the insulating film.

The conductive film 29 is formed in a comb-teeth shape so as to mesh with the second oxide semiconductor film 19b in the top view so as to partially overlap with the second oxide semiconductor film 19b. The conductive film 29 is connected to a region extending in a direction parallel or substantially parallel to the scanning line. Therefore, in the plurality of pixels included in the display device 80, the conductive film 29 has the same potential in each region. Note that the second oxide semiconductor film 19b and the conductive film 29 have a V-shape that is bent along the signal line (conductive film 21a).

  The capacitor 55 is formed in a region where the oxide semiconductor film 19b and the conductive film 29 overlap. The oxide semiconductor film 19b and the conductive film 29 have a light-transmitting property. That is, the capacitive element 55 has translucency.

  23 is a cross-sectional view taken along one-dot chain line Q2-R2 and one-dot chain line S2-T2 in FIG. A transistor 52 illustrated in FIG. 23 is a top-gate transistor. Note that an alternate long and short dash line Q2-R2 is a channel length direction of the transistor 52 and a cross-sectional view of the capacitor 55, and a cross-sectional view at S2-T2 is a cross-sectional view of the transistor 52 in the channel width direction.

  A transistor 52 illustrated in FIG. 23 includes the conductive film 13 functioning as a first gate electrode provided over the substrate 11. In addition, the insulating film 12 formed over the substrate 11 and the conductive film 13, the first oxide semiconductor film 18 having a region overlapping with the conductive film 13 functioning as a gate electrode with the insulating film 12 interposed therebetween, An insulating film 14 overlapping with the channel region 18 i included in the first oxide semiconductor film 18 on the first oxide semiconductor film 18 and a second gate electrode functioning as the second gate electrode overlapping with the insulating film 14 on the insulating film 14. 2 oxide semiconductor film 19a. An insulating film 15 and an insulating film 16 are provided in this order over the insulating film 12, the first oxide semiconductor film 18, and the second oxide semiconductor film 19a. The conductive film 21a is electrically connected to the first source / drain region 18_1 included in the first oxide semiconductor film 18 through an opening provided in the insulating film 15 and the insulating film 16. The conductive film 21b is electrically connected to the second source / drain region 18_2 included in the first oxide semiconductor film 18 through an opening provided in the insulating film and the insulating film 16. An insulating film 17 is provided over the insulating film 16, the conductive film 21 a, and the conductive film 21 b, and a conductive film 29 is provided over the insulating film 17.

  The transistor 52 is a dual-gate transistor in which the conductive film 13 is a first gate electrode, the second oxide semiconductor film 19a is a second gate electrode, and the channel region 18i is sandwiched between two upper and lower gate electrodes.

  In the pixel illustrated in FIG. 23, the second oxide semiconductor film 19b having a function of a pixel electrode is provided over the insulating film 14 in a region where the alignment of liquid crystal provided over the insulating film 27 and the conductive film 29 is controlled. The conductive film 29 having a function of a common electrode is provided on the insulating film 17. In this manner, a driving method of a display device that controls the alignment of liquid crystal by generating an electric field between a pair of electrodes arranged on different planes can be called a DPS (Differential-Plane-Switching) mode.

  In addition, a region where the second oxide semiconductor film 19b, the insulating film 15, the insulating film 16, the insulating film 17, and the conductive film 29 overlap functions as the capacitor 55.

  In the liquid crystal display device illustrated in FIGS. 22 and 23, a capacitor element included in a pixel is formed with a structure in which the vicinity of each end portion of the second oxide semiconductor film 19b and the conductive film 29 overlaps. With such a configuration, in a large-sized liquid crystal display device, the capacitor element can be formed in an appropriate size without being too large.

  Note that as shown in FIGS. 24 and 25, the second oxide semiconductor film 19b may have a function of a common electrode, and the conductive film 29 may have a function of a pixel electrode. Alternatively, the insulating film 14 may not be provided in a position overlapping with the second oxide semiconductor film 19b (see FIG. 25).

  In addition, as illustrated in FIGS. 26 and 27, the second oxide semiconductor film 19b and the conductive film 29 may not overlap with each other. The positional relationship between the oxide semiconductor film 19b and the conductive film 29 can be determined as appropriate depending on the resolution of the display device and the size of the capacitor in accordance with the driving method.

  In the structure of the pixel shown in FIG. 26, one of the pair of electrodes of the capacitor 55 is the conductive film 21c, and the conductive film 21c is the other of the source electrode and the drain electrode of the transistor 52 through the second oxide semiconductor film 19b. Is electrically connected to the conductive film 21b. The other of the pair of electrodes of the capacitor 55 is electrically connected to the conductive film 29.

  22 and 23, the width (d1) of the region extending in a direction parallel or substantially parallel to the signal line (conductive film 21a) of the oxide semiconductor film 19b is the signal of the conductive film 29. Although it is set as the structure smaller than the width | variety (d2) of the area | region extended in a direction parallel or substantially parallel to a line (refer FIG. 23), it is not restricted to this. As shown in FIGS. 28 and 29, the width d1 may be larger than the width d2. Further, the width d1 and the width d2 may be equal. Further, in one pixel (for example, the pixel 70d), the widths of the plurality of regions extending in the direction parallel to or substantially parallel to the signal line of the oxide semiconductor film 19b and / or the conductive film 29 may be different from each other. .

  30 and 31, the common electrode may be provided on the same layer as the oxide semiconductor film 19b, that is, on the insulating film 14. The common electrode 19c illustrated in FIGS. 30 and 31 can be formed using the same material as the oxide semiconductor film 19b at the same time.

  In the pixel structure illustrated in FIG. 30, one of the pair of electrodes of the capacitor 55 is the second oxide semiconductor film 19b. The other of the pair of electrodes of the capacitor 55 is a conductive film 21 c that is electrically connected to the conductive film 29.

  For the structure of the display device 80 of one embodiment of the present invention, the structure of the semiconductor device described in Embodiment 1 can be referred to. That is, the substrate 102 can be referred to for the material and manufacturing method of the substrate 11. For the material and the manufacturing method of the conductive film 13, the gate electrode 106 can be referred to. For the material and manufacturing method of the insulating film 12, the insulating film 104 can be referred to. The material and the manufacturing method of the first oxide semiconductor film 18 can be referred to the first oxide semiconductor film 108. For materials and manufacturing methods of the second oxide semiconductor films 19a and 19b, the second oxide semiconductor films 111a and 111b can be referred to, respectively. For the materials and manufacturing methods of the conductive films 21a and 21b, the conductive films 120a and 120b can be referred to, respectively. For the materials and manufacturing methods of the insulating film 15, the insulating film 16, and the insulating film 17, the insulating film 116, the insulating film 118, and the insulating film 122 can be referred to, respectively. For the material and manufacturing method of the conductive film 29, the conductive film 123 can be referred to.

  Note that the display device of one embodiment of the present invention may have a touch sensor function. Specifically, the common electrode of the display device, for example, the conductive film 29 may have at least one function of a pair of electrodes constituting the touch sensor. At this time, the display device of one embodiment of the present invention can also be referred to as a touch panel.

  Hereinafter, a driving method, a mode, a structure example, and a structure example of a semiconductor device of one embodiment of the present invention are described with reference to drawings.

[Example of sensor detection method]
FIG. 32A is a block diagram illustrating a structure of a mutual capacitive touch sensor. FIG. 32A shows a pulse voltage output circuit 401 and a current detection circuit 402. In FIG. 32A, as an example, the electrode 421 to which a pulse voltage is applied is shown as six wirings X1-X6, and the electrode 422 for detecting a change in current is shown as six wirings Y1-Y6. Note that the number of electrodes is not limited to this. FIG. 32A illustrates a capacitor 403 which is formed by overlapping the electrode 421 and the electrode 422 or arranging the electrode 421 and the electrode 422 in proximity to each other. Note that the functions of the electrode 421 and the electrode 422 may be interchanged. Alternatively, the pulse voltage output circuit 401 and the current detection circuit 402 may be replaced with each other.

  As an example, the pulse voltage output circuit 401 is a circuit for sequentially applying pulses to the wirings X1 to X6. When a pulse voltage is applied to the wiring of X1-X6, a change occurs in the electric field between the electrode 421 and the electrode 422 forming the capacitor 403. A current flows through the capacitor 403 by the pulse voltage. At this time, depending on whether or not a finger or a pen is present in the vicinity, the electric field generated between the electrodes changes due to shielding by touching the finger or pen. That is, the capacitance value of the capacitor 403 is changed by touching with a finger or a pen. As a result, the magnitude of the current flowing through the capacitor 403 changes depending on the pulse voltage. In this manner, the proximity or contact of the detection object can be detected by utilizing the change in the capacitance value by touching with a finger or a pen.

  The current detection circuit 402 is a circuit for detecting a change in current in the Y1-Y6 wiring due to a change in capacitance value in the capacitor 403. In the Y1-Y6 wiring, the current value detected when there is no proximity or contact with the detected object does not change, but the current value when the capacitance value decreases due to the proximity or contact with the detected object. Detect changes that decrease. The current may be detected by detecting the total amount of current. In that case, detection may be performed using an integration circuit or the like. Alternatively, the current peak value may be detected. In that case, the peak value of the voltage value may be detected by converting the current into a voltage.

  Next, FIG. 32B shows a timing chart of input / output waveforms in the mutual capacitance type touch sensor shown in FIG. In FIG. 32B, it is assumed that the detection target is detected in each matrix in one frame period. FIG. 32B shows two cases, that is, a case where the detected object is not detected (non-touch) and a case where the detected object is detected (touch). In addition, about the wiring of Y1-Y6, the waveform made into the voltage value corresponding to the detected electric current value is shown. Note that a display operation is also performed on the display panel. It is desirable that the timing of the display operation and the timing of the touch sensor operate in synchronization. Note that FIG. 32B illustrates an example in which the display operation is not synchronized.

  A pulse voltage is sequentially applied to the X1-X6 wiring, and the waveform of the Y1-Y6 wiring changes according to the pulse voltage. When there is no proximity or contact of the detection object, the waveform of Y1-Y6 changes uniformly according to the change of the voltage of the wiring of X1-X6. On the other hand, since the current value decreases at the location where the detection object is close or in contact, the waveform of the voltage value corresponding to this also changes.

  As described above, by detecting the change in the capacitance value, it is possible to detect the proximity or contact of the detection target. Note that a detected object such as a finger or a pen may not detect contact with a touch sensor or a touch panel, and may detect a signal even when the object is close.

  Note that FIG. 32B illustrates an example in which a pulse voltage is sequentially applied to the wirings X1 to X6; however, one embodiment of the present invention is not limited thereto. For example, a pulse voltage may be simultaneously applied to a plurality of wirings. For example, first, a pulse voltage is applied to the wirings X1 to X3. Next, a pulse voltage is applied to the wires X2 to X4. Next, a pulse voltage is applied to the wirings X3 to X5. Thus, a pulse voltage may be simultaneously applied to a plurality of wirings. And the sensitivity of a sensor can be raised by calculating the read signal.

  For example, the pulse voltage output circuit 401 and the current detection circuit 402 are preferably formed in one IC. The IC is preferably mounted on a touch panel, for example, or mounted on a substrate in a housing of an electronic device. In addition, in the case of a touch panel having flexibility, the parasitic capacitance increases at the bent portion, and the influence of noise may increase. Therefore, an IC to which a driving method that is not easily affected by noise is applied is used. It is preferable to use it. For example, it is preferable to use an IC to which a driving method for increasing a signal-noise ratio (S / N ratio) is applied.

  In the case of the in-cell type touch sensor, a circuit for driving the display unit is provided. For example, the circuit is a gate line driver circuit, a source line driver circuit, or the like. These circuits may also be formed in the IC. Therefore, at least one of the pulse voltage output circuit 401 or the current detection circuit 402 and at least one of the gate line driver circuit or the source line driver circuit may be formed in one IC. For example, a source line driver circuit is often formed in an IC because of its high driving frequency. The current detection circuit 402 is often formed in an IC because an operational amplifier or the like may be required. Therefore, the source line driver circuit and the current detection circuit 402 may be formed in one IC. In this case, the gate line driver circuit and the pulse voltage output circuit 401 may be formed together with the pixels on the substrate on which the pixels are formed. Alternatively, the source line driver circuit, the current detection circuit 402, and the pulse voltage output circuit 401 may be formed in one IC.

  FIG. 32A illustrates a passive matrix touch sensor in which only a capacitor 403 is provided at a wiring intersection as a touch sensor; however, an active matrix touch sensor including a transistor and a capacitor may be used. .

  Note that although FIG. 32 illustrates the driving method in the case of the mutual capacitance method, one embodiment of the present invention is not limited thereto. For example, a self-capacitance method may be used. In that case, the pulse voltage output circuit 401 also has a function of detecting current. Similarly, the current detection circuit 402 has a function of outputting a pulse voltage. Alternatively, the mutual capacitance method and the self-capacitance method may be switched and operated according to the situation.

[Configuration example of in-cell touch panel]
Here, an example in which at least one of a pair of electrodes constituting a touch sensor is arranged on a substrate (hereinafter also referred to as an element substrate) provided with a display element, a transistor, and the like will be described.

  Hereinafter, a configuration example of a touch panel (a so-called in-cell type) in which a touch sensor is incorporated in a display portion having a plurality of pixels is described. Here, an example in which a liquid crystal element is used as a display element provided in a pixel is shown. Note that one embodiment of the present invention is not limited to this, and various display elements can be used.

  FIG. 33 is an equivalent circuit diagram in part of a pixel circuit provided in the display unit of the touch panel exemplified in this configuration example.

  One pixel includes at least a transistor 463 and a liquid crystal element 464. In addition, the pixel may have a storage capacitor in addition to this. A wiring 461 is electrically connected to the gate of the transistor 463, and a wiring 62 is electrically connected to one of the source and the drain.

  A common electrode of the liquid crystal element 464 included in a plurality of pixels adjacent in the Y direction is electrically connected to form one block. Electrodes 471_1 and 471_2 shown in FIG. 33 are provided so as to extend in the Y direction, and serve as common electrodes in a region where the liquid crystal element 464 is formed (a region in which an electric field generated by the pixel electrode and the common electrode controls liquid crystal alignment). Function. Blocks including a plurality of pixels that share a common electrode with the electrodes 471_1 and 471_2 are referred to as blocks 465_1 and 465_2, respectively.

  In addition, the common electrodes of the liquid crystal elements 464 included in the plurality of pixels adjacent in the X direction across the blocks 465_1 and 465_2 are electrically connected to form one block. Electrodes 472_1 to 472_4 illustrated in FIG. 33 are provided to extend in the X direction and function as common electrodes in a region where the liquid crystal element 464 is formed. Blocks including a plurality of pixels that share a common electrode with the electrodes 472_1 to 472_4 are referred to as a block 467_1 to a block 467_4, respectively. Although only a part of the pixel circuit is shown in FIG. 33, these blocks are actually repeatedly arranged in the X direction and the Y direction.

  With such a configuration, the pair of electrodes constituting the touch sensor and the common electrode of the liquid crystal element included in the pixel circuit can be used. That is, in FIG. 33, the electrodes 471_1 and 471_2 serve as both the common electrode of the liquid crystal element 464 and one electrode of the touch sensor. The electrodes 472_1 to 472_4 also serve as the common electrode of the liquid crystal element 464 and the other electrode of the touch sensor. Therefore, the configuration of the touch panel can be simplified.

  Note that the common electrode of the liquid crystal element 464 included in one pixel can serve as either one electrode or the other electrode included in the touch sensor. In other words, the pixel included in the display portion includes a pixel in which the common electrode also serves as one electrode of the touch sensor (also referred to as a first pixel) and a pixel in which the common electrode also serves as the other electrode of the touch sensor (also referred to as a second pixel). Say). Therefore, in the display portion of the touch panel shown in this configuration example, the top surface shape of one electrode and the other electrode constituting the touch sensor is set arbitrarily according to the arrangement of the first pixel and the second pixel. Can do.

  FIG. 34A is an equivalent circuit diagram showing a connection configuration of a plurality of electrodes 472 extending in the X direction and a plurality of electrodes 471 extending in the Y direction. As an example, the case where the touch sensor is a projection type and a mutual capacitance method is shown. An input voltage (or selection voltage) or a common potential (or a ground potential or a reference potential) can be input to each of the electrodes 471 extending in the Y direction. In addition, a ground potential (or a reference potential) can be input to each of the electrodes 472 extending in the X direction, or the electrode 472 and the detection circuit can be electrically connected. Note that the electrode 471 and the electrode 472 can be interchanged. That is, the electrode 471 and the detection circuit may be connected.

  Hereinafter, the operation of the touch panel described above will be described with reference to FIGS.

  Here, as an example, one frame period is divided into a writing period and a detection period. The writing period is a period in which image data is written to the pixels, and wirings 461 (also referred to as gate lines or scanning lines) are sequentially selected. On the other hand, the detection period is a period during which sensing is performed by the touch sensor, and the electrodes 471 extending in the Y direction are sequentially selected and an input voltage is input.

  FIG. 34B is an equivalent circuit diagram in the writing period. In the writing period, a common potential is input to both the electrode 472 extending in the X direction and the electrode 471 extending in the Y direction.

  FIG. 34C is an equivalent circuit diagram at a certain point in the detection period. In the detection period, each of the electrodes 472 extending in the X direction is electrically connected to the detection circuit. In addition, among the electrodes 471 extending in the Y direction, an input voltage is input to a selected one, and a common potential is input to the other electrodes.

  As described above, it is preferable to provide the image writing period and the period for sensing by the touch sensor independently. For example, it is preferable to perform sensing during a display blanking period. Thereby, it is possible to suppress a decrease in sensitivity of the touch sensor due to noise at the time of pixel writing.

  Note that although an example in which one frame period is divided into a writing period and a detection period is described here, one embodiment of the present invention is not limited thereto. For example, one horizontal period (also referred to as one gate selection period) may be divided into a writing period and a detection period.

  Note that an example in which a pulse voltage is sequentially applied to the electrode 471 is described; however, one embodiment of the present invention is not limited thereto. For example, a pulse voltage may be simultaneously applied to the plurality of electrodes 471. For example, first, a pulse voltage is applied to the first to third electrodes 471. Next, a pulse voltage is applied to the second to fourth electrodes 471. Next, a pulse voltage is applied to the third to fifth electrodes 471. Thus, a pulse voltage may be simultaneously applied to the plurality of electrodes 471. And the sensitivity of a sensor can be raised by calculating the read signal.

  Note that although FIG. 34 illustrates the driving method in the case of the mutual capacitance method, one embodiment of the present invention is not limited thereto. For example, a self-capacitance method may be used. In that case, the circuit that outputs the pulse voltage also has a function of detecting current. Similarly, the detection circuit has a function of outputting a pulse voltage. Alternatively, the mutual capacitance method and the self-capacitance method may be switched and operated according to the situation.

[About touch panel methods]
Hereinafter, several methods applicable to the touch panel of one embodiment of the present invention are described.

  In this specification and the like, the touch panel has a function of displaying (outputting) an image or the like on a display surface, and a function as a touch sensor for detecting that a detection target such as a finger or a stylus touches or approaches the display surface. And having. Accordingly, the touch panel is an embodiment of an input / output device. Therefore, it can be said that the touch panel is a display device with a built-in touch sensor.

  Further, in this specification and the like, a touch panel substrate to which a connector such as an FPC (Flexible Print Circuit) or a TCP (Tape Carrier Package) is attached, or an IC (integrated on glass) method using a COG (Chip On Glass) method. A circuit on which a circuit) is mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

  A capacitive touch sensor applicable to one embodiment of the present invention includes a pair of conductive films. A capacitor is formed between the pair of conductive films. Detection can be performed by utilizing the fact that the capacitance of the pair of conductive films changes when the object to be detected touches or approaches the pair of conductive films.

  Examples of the electrostatic capacity method include a surface electrostatic capacity method and a projection electrostatic capacity method. As the projected capacitance method, there are a self-capacitance method, a mutual capacitance method, etc. mainly due to a difference in driving method. Use of the mutual capacitance method is preferable because simultaneous multipoint detection is possible. Note that one embodiment of the present invention is not limited to this.

  As the display element included in the touch panel of one embodiment of the present invention, a liquid crystal element (vertical electric field method or horizontal electric field method), an optical element using MEMS (Micro Electro Mechanical System), an organic EL (Electro Luminescence) element Various display elements such as a light emitting element such as an inorganic EL element and a light emitting diode (LED) and an electrophoretic element can be used.

  Here, a liquid crystal element to which a lateral electric field method is applied is preferably used as the display element in the display device. Note that when a transparent conductive film is used for the pixel electrode and the common electrode, the pixel electrode and the common electrode can be used as a transmissive display device. On the other hand, when a reflective electrode is used in the pixel electrode or the common electrode, it can be used as a reflective display device. Note that both the pixel electrode and the common electrode may be reflective electrodes. Alternatively, a reflective display device may be provided by providing a reflective electrode separately from the pixel electrode and the common electrode. Note that a reflective display device may be a transflective display device by providing a region through which light from a backlight can pass. For example, a part of the pixel electrode or the common electrode may be a transmission electrode and another part may be a reflection electrode. Note that even when a reflective electrode is used for the pixel electrode or the common electrode, the pixel electrode or the common electrode may be used as a transmissive display device depending on the operation mode of the liquid crystal.

  The display device of one embodiment of the present invention includes at least one of a pair of electrodes (also referred to as a conductive film or a wiring) included in the touch sensor on one of the pair of substrates, so that the display panel and the touch sensor are integrated. It has the structure which became. Therefore, the thickness of the display device is reduced, and a lightweight display device can be realized.

  FIGS. 35A to 35C are cross-sectional schematic diagrams illustrating modes of the touch panel 410 of one embodiment of the present invention.

  The touch panel 410 includes a substrate 411, a substrate 412, an FPC 413, a conductive film 414, a pixel 400a, a pixel 400b, liquid crystal elements 420a and 420b, a coloring film 431, and the like.

  The pixel 400a includes a liquid crystal element 420a, and the pixel 400b includes a liquid crystal element 420b. The liquid crystal element 420a includes a conductive film 419a, a conductive film 429a, and a liquid crystal 423. The liquid crystal element 420b includes a conductive film 419b, a conductive film 429b, and a liquid crystal 423. In FIGS. 35A and 35B, the conductive film 419a and the conductive film 419b function as pixel electrodes. The conductive films 429a and 429b function as a common electrode. FIG. 35A shows an example in which a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied is used as the liquid crystal elements 420a and 420b.

  The conductive films 419a and 419b are provided on the same surface. Alternatively, the conductive films 419a and 419b are formed using the same conductive film. An insulating film 424 is provided over the conductive films 419a and 419b. The conductive films 429a and 429b are provided on the same surface, specifically, the insulating film 424. Alternatively, the conductive films 429a and 429b are formed using the same conductive film. For example, the conductive films 429a and 429b have a comb-like top surface shape or a top surface shape (also referred to as a planar shape) provided with one or more slit-shaped openings.

  The touch sensor can detect using a capacitor formed between the conductive film 429a included in the pixel 400a and the conductive film 429b included in the pixel 400b. With such a structure, the common electrodes (429a and 429b) included in the liquid crystal element can serve as a pair of electrodes functioning as a touch sensor. Therefore, since the process can be simplified, the yield can be improved and the manufacturing cost can be reduced. Note that the conductive films 429 a and 429 b are electrically connected to the FPC 413 attached to the substrate 411 side through the conductive film 414. Alternatively, at least one of the conductive film 429a and the conductive film 429b is connected to a circuit having a function of outputting a pulse voltage. The conductive films 419a and 419b are electrically connected to transistors (not shown). The transistor is electrically connected to a driver circuit (a gate line driver circuit or a source line driver circuit) or the FPC 413.

  For example, the conductive films 429a and 429b in FIG. 35A correspond to the conductive film 29 in FIG. A conductive film 419a and a conductive film 419b in FIG. 35A correspond to the second oxide semiconductor film 19b in FIG.

  Note that in FIG. 35A, the conductive films 419a and 429a (or the conductive films 419b and 429b) have regions that overlap with each other. This region can function as a capacitor. That is, this region can function as a storage capacitor for holding the potential of the pixel electrode. Note that one embodiment of the present invention is not limited to this. For example, the conductive film 419a and the conductive film 429a (or the conductive film 419b and the conductive film 429b) may not overlap each other in a region contributing to display (a so-called opening portion). That is, in the region contributing to display (in the so-called opening), the positions of the end portions of the electrodes may be aligned vertically.

  As shown in FIG. 35B, in addition to the conductive films 429a and 429b, the touch panel 410 is provided with one or more comb-shaped top surfaces or one or more slit-shaped openings in addition to the conductive films 429a and 429b. It may have an upper surface shape. Note that the driving method of the liquid crystal elements 420a and 420b in FIG. 35B is an IPS (In-Plane-Switching) mode. With such a configuration, the size of the storage capacitor can be reduced.

  For example, the conductive films 429a and 429b in FIG. 35B correspond to the conductive films 29 in FIG. A conductive film 419a and a conductive film 419b in FIG. 35B correspond to the second oxide semiconductor film 19b in FIG.

  As shown in FIG. 35C, the conductive films 419a and 419b may function as a common electrode, and the conductive films 429a and 429b may function as pixel electrodes. In FIG. 35C, the touch sensor can detect using a capacitor formed between the conductive film 419a included in the pixel 400a and the conductive film 419b included in the pixel 400b. Note that the conductive films 419 a and 419 b are electrically connected to the FPC 413 attached to the substrate 411 side through the conductive film 414. Alternatively, at least one of the conductive films 419a and 419b is connected to a circuit having a function of outputting a pulse voltage. The conductive films 429a and 429b are electrically connected to a transistor (not shown).

  In FIG. 35B, for the common electrode and the pixel electrode, for example, a non-transparent electrode may be used. For example, a material similar to a conductive material used for a gate electrode or a source electrode and a drain electrode may be used. This is because in the IPS mode, an electric field is hardly applied to the liquid crystal 423 above the electrode. Therefore, it is difficult to control the alignment of the liquid crystal 423. Therefore, it is difficult to be an area that contributes to display. Therefore, it is not necessary to transmit light from the backlight. Therefore, even in a transmissive display device, the common electrode and the pixel electrode may be formed using aluminum, molybdenum, titanium, tungsten, copper, silver, or the like. Note that these electrodes may be formed in a mesh shape or a nanowire shape. The common electrode also functions as an electrode for the touch sensor. Therefore, it is desirable that the resistance value be as low as possible. Therefore, a non-transparent electrode is desirable because it has a lower resistance than a transparent electrode such as indium tin oxide (also referred to as ITO).

  Note that in FIGS. 35A to 35C, a transparent conductive film such as ITO may be used as the common electrode and the pixel electrode. A conductive film having a lower resistance value may be provided as an auxiliary wiring on the transparent conductive film or below the transparent conductive film. As the auxiliary wiring, for example, a material similar to a conductive material used in a gate electrode or a source electrode and a drain electrode may be used. Specifically, aluminum, molybdenum, titanium, tungsten, copper, silver, or the like may be used.

  Note that in the case where an auxiliary wiring is provided over a transparent conductive film, a halftone mask (also referred to as a gray-tone mask or a phase difference mask) is used, and the transparent conductive film and the auxiliary wiring are formed using a single mask. , May be formed. In that case, the transparent conductive film is always provided under the auxiliary wiring. Note that one embodiment of the present invention is not limited to this. The transparent conductive film and the auxiliary wiring may be formed in separate steps using separate masks.

  Note that in FIGS. 35A to 35C, the common electrode may be connected to an auxiliary wiring with a low resistance value. For example, the common electrode and the auxiliary wiring are connected via an opening of an insulating film provided between them. For example, the auxiliary wiring and the gate electrode (or gate signal line) may be formed of the same conductive film. Alternatively, the auxiliary wiring and the source / drain electrode (or source signal line) may be formed of the same conductive film.

  Note that for example, a floating conductive film may be provided over the substrate 412. Examples of such cases are shown in FIGS. 36 (A), 36 (B), and 36 (C). In this manner, the conductive film 428a is provided so as to overlap with the common electrode of the pixel 400a. Similarly, the conductive film 428b is provided so as to overlap with the common electrode of the pixel 400b. Thereby, it will be in the state by which the capacitive element was provided in series. In addition, since the electric field distribution is in an appropriate state, the sensitivity of the touch sensor can be improved. In addition, when the detected object is close to or in contact with the substrate 412, the detected object may be charged with static electricity. In such a case, the effect of static electricity can be reduced by providing the conductive film 428a, the conductive film 428b, and the like over the substrate 412.

  FIG. 37A corresponds to FIGS. 35A and 35B. In the structure illustrated in FIG. 37A, the touch sensor includes a sensor electrode 459a and a sensor electrode 459b. The sensor electrode 459a functions as a common electrode in the pixel 400a and is formed using the same conductive film as the conductive film 429a included in the pixel 400a. The sensor electrode 459b functions as a common electrode in the pixel 400b and is formed using the same conductive film as the conductive film 429b included in the pixel 400b. The sensor electrode 459a has one or more slit-shaped openings 426 in the pixel 400a. The sensor electrode 459b includes one or more slit-shaped openings 426 in the pixel 400b.

  The sensor electrode 459a is provided in an island shape so as to function as a common electrode of the pixel 400a, and is electrically connected to a wiring 453 provided to extend in one direction (for example, the X direction). Further, the sensor electrode 459b is provided so as to extend in a direction (for example, the Y direction) intersecting the one direction. The wiring 453 can be formed at the same time as the source electrode and the drain electrode of the transistor included in the pixels 400a and 400b, for example.

  In addition, as illustrated in FIG. 37B, the sensor electrode 459a is electrically connected to a wiring 453 provided so as to extend in one direction (for example, the X direction), and the sensor electrode 459b intersects the one direction. May be electrically connected to a wiring 454 provided to extend in a direction (for example, the Y direction). At this time, the sensor electrode 459a and the sensor electrode 459b are provided in island shapes so as to function as common electrodes of the pixels 400a and 400b, respectively. The wiring 454 can be formed at the same time as the first gate electrode of the transistor included in the pixels 400a and 400b, for example. Note that one sensor electrode provided in an island shape may be provided so as to function as a common electrode of a plurality of pixels instead of a common electrode of one pixel.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment, a pixel structure including a liquid crystal element that operates in a vertical alignment (VA) mode, which can be applied to the liquid crystal display device of one embodiment of the present invention, will be described with reference to FIGS. To do. 38 is a top view of a pixel included in the liquid crystal display device, and FIG. 39 is a side view including a cross section taken along a cutting line A1-B1 in FIG. FIG. 40A is an equivalent circuit diagram of a pixel included in the liquid crystal display device.

  The VA type is a type of a method for controlling the alignment of liquid crystal molecules of a liquid crystal display panel. The VA liquid crystal display device is a method in which liquid crystal molecules face a vertical direction with respect to a panel surface when no voltage is applied.

  In the present embodiment, the pixel (pixel) is divided into several regions (sub-pixels), and each molecule is devised to tilt the molecules in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

  38, Z1 is a top view of the substrate 602 on which the pixel electrode 611b is formed, Z3 is a top view of the substrate 601 on which the common electrode 671 is formed, and Z2 is common to the substrate 602 on which the pixel electrode 611b is formed. It is a top view of the state where the substrate 601 with the electrode 671 formed thereon is overlaid.

  Over the substrate 602, a transistor 650, a pixel electrode 611b connected to the transistor 650, and a capacitor 661 are formed. A drain electrode 620 b of the transistor 650 is electrically connected to the pixel electrode 611 b through an opening 641 b provided in the insulating film 616 and the insulating film 618. An insulating film 616, an insulating film 618, and an insulating film 622 are provided in this order over the pixel electrode 611b.

  As the transistor 650, any of the transistors described in Embodiment 1 (the transistor 150 and the transistors 150A to 150G) can be used.

  The capacitor 630 includes a capacitor wiring 607 that is a first capacitor wiring, an insulating film 604, and a pixel electrode 611b. The capacitor wiring 607 can be formed of the same material as the gate wiring 606 of the transistor 650 at the same time.

  As the pixel electrode 611b, an oxide semiconductor film with low resistivity described in Embodiment 1 can be used. That is, the second oxide semiconductor film 111b described in Embodiment 1 can be referred to for a material and a manufacturing method of the pixel electrode 611b.

  A slit 674 is provided in the pixel electrode 611b. The slit 674 is for controlling the alignment of the liquid crystal.

  The transistor 651 and the pixel electrode 612b and the capacitor 662 connected to the transistor 651 can be formed in the same manner as the transistor 650, the pixel electrode 611b, and the capacitor 661, respectively. Both the transistor 650 and the transistor 651 are connected to the wiring 620a. The wiring 620a functions as a source electrode in the transistor 650 and the transistor 651. A pixel of the liquid crystal display panel described in this embodiment includes a pixel electrode 611b and a pixel electrode 612b. The pixel electrode 611b and the pixel electrode 612b are subpixels.

  A colored film 673 and a common electrode 671 are formed over the substrate 601, and a protrusion 675 is formed in contact with the common electrode 671. Further, the common electrode 671 is provided with a slit 672. An alignment film 677 is formed on the insulating film 622 on the pixel electrode 611b side, and an alignment film 678 is formed on the common electrode 671 and the protrusion 675 side. A liquid crystal layer 680 is formed between the substrate 602 and the substrate 601.

  The common electrode 671 is preferably formed using a material similar to that of the conductive film 123 described in Embodiment 1. The slit 672 and the protrusion 675 formed in the common electrode 671 have a function of controlling the alignment of the liquid crystal.

  When a voltage is applied to the pixel electrode 611 b provided with the slit 674, electric field distortion (an oblique electric field) is generated in the vicinity of the slit 674. The slits 674, the projections 675 on the substrate 601 side, and the slits 672 are alternately arranged so that an oblique electric field is effectively generated to control the orientation of the liquid crystal, thereby controlling the orientation of the liquid crystal. It is different depending on. That is, the viewing angle of the liquid crystal display panel is widened by multi-domain. Note that a structure in which either the protrusion 675 or the slit 672 is provided on the substrate 601 side may be employed.

  FIG. 39 shows a state where the substrate 602 and the substrate 601 are overlaid and liquid crystal is injected. The pixel electrode 611b, the liquid crystal layer 680, and the common electrode 671 overlap with each other to form a liquid crystal element.

  An equivalent circuit of this pixel structure is shown in FIG. The transistors 650 and 629 are both connected to the gate wiring 606 and the wiring 620a. In this case, operation of the liquid crystal element 681 and the liquid crystal element 682 can be made different by making the potentials of the capacitor wiring 607 and the capacitor wiring 609 different. That is, by controlling the potentials of the capacitor wiring 607 and the capacitor wiring 609 individually, the orientation of the liquid crystal is precisely controlled to widen the viewing angle.

  Note that although the second gate electrode of the transistors 650 and 651 in FIG. 40A is electrically connected to the first gate electrode, the present invention is not limited to this. For example, the second gate electrode may be electrically connected to a wiring 4616 having a function of applying a different potential from the gate wiring 606 (see FIG. 40B).

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 5)
In this embodiment, an example of a display device including the transistor described as an example in the above embodiment will be described below with reference to FIGS.

  FIG. 41 is a top view illustrating an example of the display device. 41 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, a source The driver circuit portion 704 and the gate driver circuit portion 706 are provided so as to surround the sealant 712 and the second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 41, a display element is provided between the first substrate 701 and the second substrate 705.

  In addition, the display device is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 in a region different from the region surrounded by the sealant 712 over the first substrate 701. FPC terminal portion 708 (FPC: Flexible Printed Circuit) is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A wiring 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the wiring 710.

  Further, a plurality of gate driver circuit portions 706 may be provided in the display device. As the display device, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the present invention is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. . Note that a method for connecting a separately formed driver circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

  The pixel portion 702 included in the display device includes a plurality of transistors and a capacitor, and the semiconductor device described in Embodiment 1 can be used. The source driver circuit portion 704 and the gate driver circuit portion 706 each include a plurality of transistors and a wiring contact portion, and the semiconductor device described in Embodiment 2 can be used.

  The display device can have various modes or have various display elements. Display elements include, for example, liquid crystal elements, EL (electroluminescence) elements including LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) (EL elements including organic substances and inorganic substances, organic EL elements, inorganic EL elements). , Transistors (transistors that emit light in response to current), electron-emitting devices, electrophoretic devices, grating light valves (GLV), digital micromirror devices (DMD), DMS (digital micro shutter) devices, MIRASOL (registered trademark) Examples thereof include a display, an IMOD (interference modulation) element, a display element using a micro electro mechanical system (MEMS) such as a piezoelectric ceramic display, and an electrowetting element. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, and the like are changed by an electric or magnetic action may be included. Further, quantum dots may be used as the display element. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. An example of a display device using quantum dots is a quantum dot display. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

  As a display method in the display device, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

  In addition, a colored film (also referred to as a color filter) may be used to display a full color display device using white light (W) in a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like). Good. As the colored film, for example, red (R), green (G), blue (B), yellow (Y), or the like can be used in appropriate combination. By using the colored film, the color reproducibility can be increased as compared with the case where the colored film is not used. At this time, by arranging a region having a colored film and a region having no colored film, white light in the region having no colored film may be directly used for display. By arranging a region that does not have a colored film in part, in a bright display, a decrease in luminance due to the colored film can be reduced, and power consumption can be reduced by about 20% to 30%. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from elements having respective emission colors. . By using a self-luminous element, power consumption may be further reduced than when a colored film is used.

  In this embodiment, a structure of a display device using a liquid crystal element as a display element will be described with reference to FIG. A structure of a display device using an EL element as a display element will be described with reference to FIG.

  42 is a cross sectional view taken along one-dot chain line U-V shown in FIG. A display device 700A illustrated in FIG. 42 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. In addition, the lead wiring portion 711 includes a wiring 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.

  For example, the transistor described in Embodiment 1 (the transistor 150 and the transistors 150A to 150G) can be used as the transistor 750 and the transistor 752.

  The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can reduce a current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

  In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

  As the capacitor 790, the capacitor 160 described in Embodiment 1 can be used. Since the capacitor 790 has a light-transmitting property, the capacitor 790 can be formed large (in a large area) in one pixel included in the pixel portion 702. Thus, a display device with an increased capacitance value while increasing an aperture ratio can be obtained.

  In FIG. 42, insulating films 764, 766, and 768 are provided over the transistor 750.

  The insulating films 764, 766, and 768 can be formed using a material and a manufacturing method similar to those of the insulating films 116, 118, and 122 described in Embodiment 1, respectively. Alternatively, a planarization film may be provided over the insulating film 122.

  The wiring 710 is formed in the same step as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. Note that the wiring 710 may be a conductive film formed in a step different from the source and drain electrodes of the transistors 750 and 752, for example, a conductive film functioning as a gate electrode. For example, when a material containing a copper element is used as the wiring 710, signal delay due to wiring resistance is small, and display on a large screen is possible.

  The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 791, and an FPC 716. Note that the connection electrode 760 is formed in the same step as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 791.

  In addition, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. The first substrate 701 and the second substrate 705 can be formed using a material similar to that of the substrate 102 described in Embodiment 1.

  On the second substrate 705 side, a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.

  A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

  In this embodiment mode, the structure body 778 is provided on the first substrate 701 side; however, the present invention is not limited to this. For example, a structure in which the structure body 778 is provided on the second substrate 705 side or a structure in which the structure body 778 is provided on both the first substrate 701 and the second substrate 705 may be employed.

  The display device 700A includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700A can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 according to voltages applied to the conductive films 772 and 774. The alignment film 746 is provided over the conductive film 772 and the insulating film 768, and the alignment film 748 is provided in contact with the conductive film 774.

  The conductive film 772 is connected to a conductive film functioning as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the insulating film 768 and functions as a pixel electrode, that is, one electrode of the display element. The display device 700A is a so-called transmissive color liquid crystal display device in which a backlight, a sidelight, or the like is provided on the substrate 701 side and displays through a liquid crystal element 775 and a colored film 736.

  As the conductive films 772 and 774, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. The conductive film 772 and the conductive film 774 can be formed using a material similar to that of the conductive film 123 described in Embodiment 1.

  Note that the display device 700A illustrated in FIGS. 41 and 42 is illustrated as a transmissive color liquid crystal display device, but is not limited thereto. For example, the conductive film 772 may be a reflective color liquid crystal display device by using a conductive film that reflects visible light.

  Although not shown in FIG. 42, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used.

  The sealant 712 has at least a function of preventing or suppressing a substance (such as water) that becomes an impurity with respect to the display element or the transistor from entering from the outside. Note that another function 712 may be added to the sealing material. For example, the sealing material 712 may have a function of strengthening a structure, a function of enhancing adhesiveness, a function of enhancing impact resistance, and the like.

  As the sealant 712, a material that does not dissolve in the liquid crystal layer even when in contact with the liquid crystal layer before curing is preferably used. As the sealing material 712, for example, an epoxy resin, an acrylic resin, or the like can be applied. The resin material may be either a thermosetting type or a photocurable type. Alternatively, the sealing material 712 may be a resin in which an acrylic resin and an epoxy resin are mixed. At this time, a UV initiator, a thermosetting agent, a coupling agent, or the like may be mixed. Moreover, a filler may be included.

  Further, as the sealing material, a material similar to that of an adhesive layer 781 described later may be used.

  As a liquid crystal used for the liquid crystal layer 776, the liquid crystal used for the liquid crystal element 51 described in Embodiment 3 can be referred to.

  In addition, as a driving method of a display device including a liquid crystal element, various driving methods described in Embodiment 3 can be applied.

  Subsequently, FIGS. 43 and 44 are cross-sectional views taken along one-dot chain line U-V in the case where the display device illustrated in FIG. 41 includes an EL element instead of a liquid crystal element. Note that the description of FIG. 42 can be used for the same configuration as that of FIG. 42, and therefore, a configuration different from that of FIG.

  A display device 700 </ b> B illustrated in FIG. 43 includes an EL element 785. The EL element 785 includes a conductive film 782, a conductive film 784, and an EL layer 786. The EL layer 786 includes a light-emitting organic compound or a light-emitting inorganic compound. The conductive film 782 is provided over the insulating film 783 and functions as a reflective electrode. The insulating film 783 has a function as a planarization film. An EL layer 786 and a conductive film 784 are provided over the conductive film 782 in this order. As the conductive film 784, a conductive film that transmits visible light can be used. The display device 700B can display an image by bringing the EL layer 786 into a light-emitting state or a non-light-emitting state with a voltage applied to the conductive films 782 and 784.

  The substrate 701 and the substrate 705 are attached to each other with an adhesive layer 781. As the adhesive layer 781, various curable resins such as a UV curable resin, a reaction curable resin, a thermosetting resin, and an anaerobic resin can be used. Examples of these resins include epoxy resins, acrylic resins, silicone resins, phenol resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene vinyl acetate) resins, and the like. In particular, a material with low moisture permeability such as an epoxy resin is preferable. Alternatively, a two-component mixed resin may be used. Further, an adhesive sheet or the like may be used.

  43, the connection electrode 760 includes a conductive film formed in the same step as the conductive film functioning as the first gate electrode of the transistors 750 and 752, a conductive film formed in the same step as the source electrode and the drain electrode, and An example in which a stacked film of conductive films 782 is formed is shown. In the FPC terminal portion 708, various insulating films have openings so that the conductive films constituting the connection electrode 760 are electrically connected to each other.

  43, the pair of electrodes included in the capacitor 790 functions as a conductive film formed in the same step as the conductive film functioning as the first gate electrode of the transistors 750 and 752, and the second gate electrode. An example is shown in which the film is formed in the same step as the oxide semiconductor film.

  The transistor 750 includes a gate electrode above the channel region. Therefore, since the conductive film 782 is provided in a position overlapping with the transistor 750, the aperture ratio of the pixel in the pixel portion 702 can be improved.

  Note that FIG. 43 illustrates a top-emission display device in which light emitted from the EL layer 786 is emitted to the substrate 705 side; however, the display device of one embodiment of the present invention may be a bottom-emission type. In the display device 700C illustrated in FIG. 44, light emitted from the EL layer 786 is emitted to the substrate 701 side. In the case of the bottom emission type, the coloring film 736 and the light shielding film 738 are provided below the EL layer 786, for example, on the insulating film 768.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, a touch panel that can be used for the display device of one embodiment of the present invention will be described with reference to FIGS. In this embodiment, a touch panel using a light-emitting element, specifically, an EL element is illustrated.

[Example of touch panel configuration]
45A and 45B are perspective views of the touch panel 505. FIG. Note that representative components are shown for clarity. FIG. 46A is a cross-sectional view taken along alternate long and short dash line M-N in FIG.

  As shown in FIGS. 45A and 45B, the touch panel 505 includes a display portion 501, a scan line driver circuit 303g (1), a touch sensor 595, and the like. The touch panel 505 includes a substrate 510, a substrate 511, and a substrate 590.

  The touch panel 505 includes a plurality of pixels and a plurality of wirings 311. The plurality of wirings 311 can supply signals to the pixels. The plurality of wirings 311 are routed to the outer peripheral portion of the substrate 510, and a part of them constitutes a terminal 319. The terminal 319 is electrically connected to the FPC 509 (1).

  The touch panel 505 includes a touch sensor 595 and a plurality of wirings 598. The plurality of wirings 598 are electrically connected to the touch sensor 595. The plurality of wirings 598 are routed around the outer periphery of the substrate 590, and a part thereof constitutes a terminal. The terminal is electrically connected to the FPC 509 (2). Note that in FIG. 45B, electrodes, wirings, and the like of the touch sensor 595 provided on the back surface side (the surface side facing the substrate 510) of the substrate 590 are shown by solid lines for clarity.

  As the touch sensor 595, for example, a capacitive touch sensor can be applied. Examples of the electrostatic capacity method include a surface electrostatic capacity method and a projection electrostatic capacity method. Here, a case where a projected capacitive touch sensor is applied is shown.

  As the projected capacitance method, there are mainly a self-capacitance method and a mutual capacitance method due to a difference in driving method. The mutual capacitance method is preferable because simultaneous multipoint detection is possible.

  Note that as the touch sensor 595, various sensors that can detect the proximity or contact of a detection target such as a finger can be used.

  The projected capacitive touch sensor 595 includes an electrode 591 and an electrode 592. The electrode 591 is electrically connected to any one of the plurality of wirings 598, and the electrode 592 is electrically connected to any one of the plurality of wirings 598.

  As shown in FIGS. 45A and 45B, the electrode 592 has a shape in which a plurality of quadrilaterals repeatedly arranged in one direction are connected at corners.

  The electrode 591 has a quadrangular shape, and is repeatedly arranged in a direction intersecting with the direction in which the electrode 592 extends. Note that the plurality of electrodes 591 are not necessarily arranged in a direction orthogonal to the one electrode 592, and may be arranged at an angle of less than 90 degrees.

  The wiring 594 is provided so as to cross the electrode 592. The wiring 594 electrically connects two electrodes 591 sandwiching the electrode 592. At this time, a shape in which the area of the intersection of the electrode 592 and the wiring 594 is as small as possible is preferable. Thereby, the area of the area | region in which the electrode is not provided can be reduced, and the nonuniformity of the transmittance | permeability can be reduced. As a result, luminance unevenness of light transmitted through the touch sensor 595 can be reduced.

  Note that the shapes of the electrode 591 and the electrode 592 are not limited thereto, and various shapes can be employed. For example, a plurality of electrodes 591 may be arranged so as not to have a gap as much as possible, and a plurality of electrodes 592 may be provided with an insulating film interposed therebetween so that a region that does not overlap with the electrodes 591 is formed. At this time, it is preferable to provide a dummy electrode electrically insulated from two adjacent electrodes 592 because the area of a region having different transmittance can be reduced.

  A more specific configuration example of the touch sensor 595 will be described later.

  As shown in FIG. 46A, the touch panel 505 includes a substrate 510, an adhesive layer 503, an insulating film 504, a substrate 511, an adhesive layer 513, and an insulating film 515. In addition, the substrate 510 and the substrate 511 are bonded to each other with an adhesive layer 360.

  The adhesive layer 597 bonds the substrate 590 to the substrate 511 so that the touch sensor 595 overlaps the display portion 501. The adhesive layer 597 has a light-transmitting property.

  The electrodes 591 and 592 are formed using a light-transmitting conductive material. As the light-transmitting conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide to which gallium is added can be used. Note that a film containing graphene can also be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat.

  In addition, it is preferable that the conductive film such as the electrode 591, the electrode 592, and the wiring 594, that is, the resistance value of the material used for the wiring and the electrode included in the touch panel be low. As an example, ITO, indium zinc oxide, ZnO, silver, copper, aluminum, carbon nanotube, graphene, or the like may be used. Furthermore, metal nanowires that are made very thin (for example, a diameter of several nanometers) and are formed using a large number of conductors may be used. Note that a metal nanowire, a carbon nanotube, graphene, or the like may be used for an electrode used for a display element, for example, a pixel electrode or a common electrode because of high transmittance.

  A conductive material having a light-transmitting property is formed over the substrate 590 by a sputtering method, and then unnecessary portions are removed by various patterning techniques such as a photolithography method to form the electrode 591 and the electrode 592. it can.

  The electrodes 591 and 592 are covered with an insulating film 593. An opening reaching the electrode 591 is provided in the insulating film 593, and the wiring 594 electrically connects the adjacent electrodes 591. A light-transmitting conductive material can be used for the wiring 594 because it can increase the aperture ratio of the touch panel. A material having higher conductivity than the electrodes 591 and 592 can be preferably used for the wiring 594 because electric resistance can be reduced.

  Note that an insulating film which covers the insulating film 593 and the wiring 594 can be provided to protect the touch sensor 595.

  In addition, the connection layer 599 electrically connects the wiring 598 and the FPC 509 (2).

  The display portion 501 includes a plurality of pixels 302 arranged in a matrix.

  The pixel 302 has a plurality of subpixels. Each subpixel includes a light emitting element and a pixel circuit.

  The pixel circuit can supply power for driving the light emitting element. The pixel circuit is electrically connected to a wiring that can supply a selection signal. The pixel circuit is electrically connected to a wiring that can supply an image signal.

  The scan line driver circuit 303g (1) can supply a selection signal to the pixel 302.

  The image signal line driver circuit 303 s (1) can supply an image signal to the pixel 302.

  As shown in FIG. 46A, the touch panel 505 includes a substrate 510, an adhesive layer 503, an insulating film 504, a substrate 511, an adhesive layer 513, and an insulating film 515. In addition, the substrate 510 and the substrate 511 are bonded to each other with an adhesive layer 360.

  The substrate 510 and the insulating film 504 are attached to each other with an adhesive layer 503. The substrate 511 and the insulating film 515 are bonded to each other with an adhesive layer 513.

  The substrate 510 and the substrate 511 are preferably flexible.

  Embodiment 1 can be referred to for materials that can be used for the substrate and the insulating film. For materials that can be used for the adhesive layer, Embodiment Mode 5 can be referred to.

  For the adhesive layer, various curable resins such as a photocurable resin such as an ultraviolet curable resin, a reactive curable resin, a thermosetting resin, and an anaerobic resin can be used. Examples of these resins include epoxy resins, acrylic resins, silicone resins, phenol resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene vinyl acetate) resins, and the like. In particular, a material with low moisture permeability such as an epoxy resin is preferable. Alternatively, a two-component mixed resin may be used. Further, an adhesive sheet or the like may be used.

  The pixel 302 includes a sub-pixel 302R, a sub-pixel 302G, and a sub-pixel 302B (only the sub-pixel 302R is illustrated in FIG. 46). The subpixel 302R includes a light emitting module 380R, the subpixel 302G includes a light emitting module 380G, and the subpixel 302B includes a light emitting module 380B.

  For example, the subpixel 302R includes a light emitting element 350R and a pixel circuit. The pixel circuit includes a transistor 302t that can supply power to the light-emitting element 350R. The light emitting module 380R includes a light emitting element 350R and an optical element (for example, a colored film 367R that transmits red light).

  The light-emitting element 350R includes a lower electrode 351R, a semi-transmissive electrode 351Ra, an EL layer 353, and an upper electrode 352 which are stacked in this order (see FIG. 46B). Note that FIG. 46B is an enlarged view of a region 555 in FIG.

  The EL layer 353 includes a first EL layer 353a, an intermediate layer 354, and a second EL layer 353b which are stacked in this order.

  Note that a microcavity structure can be provided in the light-emitting element 350R. Specifically, a film that reflects visible light (for example, the lower electrode 351R in FIG. 46B) and a semi-reflective / semi-transmissive film (for example, FIG. An EL layer may be arranged between the upper electrodes 352) in B). The semi-transmissive electrode 351Ra has a function of an optical adjustment layer, and the sub-pixels 302R, 302G, and 302B each have a different film thickness so that light of a specific wavelength can be efficiently used for each sub-pixel. Can be taken out well. Note that the light-emitting element 350R may have a structure in which the transflective electrode 351Ra is not provided.

  For example, the light-emitting module 380R includes the adhesive layer 360 that is in contact with the light-emitting element 350R and the coloring film 367R (see FIG. 46A).

  The colored film 367R is in a position overlapping the light emitting element 350R. Thus, part of the light emitted from the light emitting element 350R passes through the adhesive layer 360 and the colored film 367R and is emitted to the outside of the light emitting module 380R as indicated by the arrows in the drawing.

  The touch panel 505 includes a light shielding film 367BM. The light shielding film 367BM is provided so as to surround a colored film (for example, the colored film 367R).

  The touch panel 505 has an antireflection layer 367p at a position overlapping the display portion 301. For example, a circularly polarizing plate can be used as the antireflection layer 367p.

  The touch panel 505 includes an insulating film 321. The insulating film 321 covers the transistor 302t and the like. Note that the insulating film 321 can be used as a layer for planarizing unevenness caused by a pixel circuit or an imaging pixel circuit. Further, an insulating film in which a layer capable of suppressing diffusion of impurities into the transistor 302t and the like is stacked can be applied to the insulating film 321. In this embodiment, an example in which the insulating film 321 is a two-layer stack is shown, but the insulating film 321 may be a single layer or a stack of three or more layers.

  The touch panel 505 includes a partition wall 328 that overlaps an end portion of the lower electrode 351R. Note that a spacer for controlling the distance between the substrate 510 and the substrate 511 may be provided over the partition wall 328.

  The scan line driver circuit 303g (1) includes a transistor 303t and a capacitor 303c. Note that the driver circuit can be formed over the same substrate in the same process as the pixel circuit.

  Note that as the transistor included in the touch panel 505 (eg, the transistor 302t and the transistor 303t), the transistor described in Embodiment 1 (the transistor 150, the transistors 150A to 150G) can be used.

[Configuration example of touch sensor]
Hereinafter, a more specific configuration example of the touch sensor 595 will be described with reference to the drawings.

  FIG. 47A is a schematic top view of the touch sensor 595. FIG. The touch sensor 595 includes a plurality of electrodes 531, a plurality of electrodes 532, a plurality of wirings 541, and a plurality of wirings 542 over a substrate 590. The substrate 590 is provided with an FPC 550 that is electrically connected to each of the plurality of wirings 541 and the plurality of wirings 542.

  FIG. 47B is an enlarged view of a region surrounded by a dashed line in FIG. The electrode 531 has a shape in which a plurality of rhombus electrode patterns are arranged in the horizontal direction on the paper surface. The rhomboid electrode patterns arranged in a row are electrically connected to each other. Similarly, the electrode 532 has a shape in which a plurality of rhombus electrode patterns are continuous in the vertical direction of the drawing, and the rhombus electrode patterns arranged in a row are electrically connected to each other. In addition, the electrode 531 and the electrode 532 partially overlap each other and intersect each other. At this intersection, an insulator is sandwiched so that the electrode 531 and the electrode 532 are not electrically short-circuited.

  In addition, as illustrated in FIG. 47C, the electrode 532 may include a plurality of electrodes 533 having a rhombus shape and a bridge electrode 534. The island-shaped electrodes 533 are arranged side by side in the vertical direction of the paper, and two adjacent electrodes 533 are electrically connected by a bridge electrode 534. With such a structure, the electrode 533 and the electrode 531 can be formed at the same time by processing the same conductive film. Therefore, variations in the film thickness can be suppressed, and variations in resistance value and light transmittance of each electrode can be suppressed depending on the location. Note that although the electrode 532 includes the bridge electrode 534 here, the electrode 531 may have such a configuration.

  In addition, as shown in FIG. 47D, the inside of the rhomboid electrode pattern of the electrodes 531 and 532 shown in FIG. 47B may be hollowed out so that only the outline portion remains. At this time, in the case where the widths of the electrode 531 and the electrode 532 are so narrow that they are not visually recognized by the user, a light-shielding material such as a metal or an alloy may be used for the electrode 531 and the electrode 532 as described later. Alternatively, the electrode 531 or the electrode 532 illustrated in FIG. 47D may include the bridge electrode 534.

  One electrode 531 is electrically connected to one wiring 541. One electrode 532 is electrically connected to one wiring 542.

  Here, in the case where the touch sensor is formed by overlapping the touch sensor 595 on the display surface of the display panel, it is preferable to use a light-transmitting conductive material for the electrode 531 and the electrode 532. In the case where a light-transmitting conductive material is used for the electrode 531 and the electrode 532 and light from the display panel is extracted through the electrode 531 or the electrode 532, the same conductive property is provided between the electrode 531 and the electrode 532. It is preferable to dispose the conductive film containing a conductive material as a dummy pattern. Thus, by filling a part of the gap between the electrode 531 and the electrode 532 with the dummy pattern, the variation in light transmittance can be reduced. As a result, luminance unevenness of light transmitted through the touch sensor 595 can be reduced.

  As the light-transmitting conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide to which gallium is added can be used. Note that a film containing graphene can also be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat.

  Alternatively, a metal or an alloy that is thin enough to transmit light can be used. For example, a metal such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy containing the metal can be used. Alternatively, a nitride of the metal or alloy (eg, titanium nitride) or the like may be used. Alternatively, a stacked film in which two or more of the conductive films containing the above materials are stacked may be used.

  Alternatively, the electrode 531 and the electrode 532 may be a conductive film that is processed so as to be invisible to the user. For example, by processing such a conductive film in a lattice shape (mesh shape), high conductivity and high visibility of the display device can be obtained. At this time, the conductive film preferably has a portion with a width of 30 nm to 100 μm, preferably 50 nm to 50 μm, more preferably 50 nm to 20 μm. In particular, a conductive film having a pattern width of 10 μm or less is preferable because it is extremely difficult for the user to visually recognize the conductive film.

  As an example, FIGS. 48A to 48D are schematic views in which a part of the electrode 531 or the electrode 532 (a part surrounded by a one-dot chain line circle in FIG. 47B) is enlarged. FIG. 48A shows an example in which a grid-like conductive film 561 is used. At this time, it is preferable that the conductive film 561 be disposed so as not to overlap with a display element included in the display device because light from the display device is not blocked. In that case, it is preferable that the direction of the lattice is the same as the arrangement of the display elements, and the period of the lattice is an integral multiple of the period of the arrangement of the display elements.

  FIG. 48B shows an example of a lattice-shaped conductive film 562 processed so that a triangular opening is formed. With such a structure, the resistance can be further reduced as compared with the case illustrated in FIG.

  Alternatively, as illustrated in FIG. 48C, a conductive film 563 having a pattern shape without periodicity may be used. With such a configuration, it is possible to suppress the occurrence of moire when superimposed on the display unit of the display device. Note that moire here refers to an interference pattern caused by diffraction or interference when external light or the like is transmitted through a conductive film or the like provided with a minute width and at equal intervals, or when external light is reflected. Say.

  Alternatively, conductive nanowires may be used for the electrode 531 and the electrode 532. FIG. 48D illustrates an example in which the nanowire 564 is used. By dispersing the adjacent nanowires 564 at an appropriate density so that the nanowires 564 are in contact with each other, a two-dimensional network is formed, and the conductive film can function as a highly light-transmitting conductive film. For example, nanowires having an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm can be used. As the nanowire 564, an Ag nanowire, a metal nanowire such as a Cu nanowire or an Al nanowire, or a carbon nanotube can be used. For example, in the case of Ag nanowires, the light transmittance can be 89% or more and the sheet resistance value can be 40 or more and 100 or less Ω / □.

  In FIG. 47A and the like, the upper surface shape of the electrode 531 and the electrode 532 is an example in which a plurality of rhombuses are connected in one direction. However, the shape of the electrode 531 and the electrode 532 is not limited thereto, Various upper surface shapes such as a belt shape (rectangular shape), a belt shape having a curve, and a zigzag shape can be used. In the above description, the electrode 531 and the electrode 532 are shown to be arranged so as to be orthogonal to each other. However, they are not necessarily arranged to be orthogonal, and the angle formed by the two electrodes is less than 90 degrees. There may be.

  FIGS. 49A to 49C illustrate an example in which an electrode 536 and an electrode 537 having a thin upper surface shape are used instead of the electrode 531 and the electrode 532. FIG. 49A shows an example in which linear electrodes 536 and 537 are arranged in a grid pattern.

  FIG. 49B illustrates an example in which the electrode 536 and the electrode 537 have zigzag upper surface shapes. At this time, as shown in FIG. 49 (B), the center positions of the respective straight line portions are not overlapped, but are arranged relatively shifted so that the length of the portion where the electrode 536 and the electrode 537 face each other in parallel is long. The length can be increased, the mutual capacitance between the electrodes is increased, and the detection sensitivity is improved, which is preferable. Alternatively, as illustrated in FIG. 49C, if the upper surface shape of the electrode 536 and the electrode 537 is a shape in which a part of the zigzag linear portion protrudes, the center positions of the linear portions may be overlapped. Since the lengths of the opposing portions can be increased, the mutual capacitance between the electrodes can be increased.

  FIGS. 50A, 50B, and 50C are enlarged views of the region surrounded by the alternate long and short dash line in FIG. 49B, and FIGS. 50A and 50B are enlarged views of the region surrounded by the alternate long and short dashed line in FIG. D) (E) and (F) respectively. In each figure, an electrode 536, an electrode 537, and an intersection 538 where these intersect are shown. As shown in FIGS. 50B and 50E, the straight portions of the electrodes 536 and 537 in FIGS. 50A and 50D may be meandering so as to have corners, As shown in FIGS. 50C and 50F, it may have a meandering shape so that the curve is continuous.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, structural examples of light-emitting elements that can be used for the EL element 785 described in Embodiment 5 and the light-emitting element 350R described in Embodiment 6 will be described. Note that the EL layer 220 described in this embodiment corresponds to the EL layer 786 and the EL layer 353 described in the other embodiments.

<Configuration of light emitting element>
A light-emitting element 230 illustrated in FIG. 51A has a structure in which an EL layer 220 is sandwiched between a pair of electrodes (an electrode 218 and an electrode 222). Note that in the following description of this embodiment, as an example, the electrode 218 is used as an anode and the electrode 222 is used as a cathode.

  Further, the EL layer 220 may be formed including at least a light emitting layer, and may have a stacked structure including a functional layer other than the light emitting layer. As the functional layer other than the light emitting layer, a substance having a high hole-injecting property, a substance having a high hole-transporting property, a substance having a high electron-transporting property, a substance having a high electron-injecting property, A layer containing a high substance) or the like can be used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be used in appropriate combination.

  In the light-emitting element 230 illustrated in FIG. 51A, a current flows due to a potential difference applied between the electrode 218 and the electrode 222, and holes and electrons are recombined in the EL layer 220 to emit light. In other words, a light emitting region is formed in the EL layer 220.

  In the present invention, light emitted from the light emitting element 230 is extracted to the outside from the electrode 218 or the electrode 222 side. Therefore, either the electrode 218 or the electrode 222 is formed using a light-transmitting substance.

  Note that a plurality of EL layers 220 may be stacked between the electrode 218 and the electrode 222 as in the light-emitting element 231 illustrated in FIG. In the case of an n-layer (n is a natural number of 2 or more) layered structure, between the mth (m is a natural number of 1 or more and smaller than n) EL layer 220 and the (m + 1) th EL layer 220 In this case, it is preferable to provide the charge generation layer 220a. The structure excluding the electrode 218 and the electrode 222 corresponds to the EL layer 117 in the above embodiment.

The charge generation layer 220a can be formed using a composite material of an organic compound and a metal oxide. Examples of the metal oxide include vanadium oxide, molybdenum oxide, and tungsten oxide. As the organic compound, various compounds such as an aromatic amine compound, a carbazole derivative, an aromatic hydrocarbon, an oligomer having such a basic skeleton, a dendrimer, and a polymer can be used. As the organic compound, it is preferable to use a hole transporting organic compound having a hole mobility of 10 ⁻⁶ cm ² / Vs or more. Note that other than these substances, any substance that has a property of transporting more holes than electrons may be used. Note that these materials used for the charge generation layer 220a are excellent in carrier-injection property and carrier-transport property, and thus can realize low-current driving and low-voltage driving of the light-emitting element 230. In addition to the composite material, the above-described metal oxide, organic compound and alkali metal, alkaline earth metal, alkali metal compound, alkaline earth metal compound, or the like can be used for the charge generation layer 220a.

  Note that the charge generation layer 220a may be formed by combining a composite material of an organic compound and a metal oxide with another material. For example, a layer including a composite material of an organic compound and a metal oxide may be combined with a layer including one compound selected from electron donating substances and a compound having a high electron transporting property. Alternatively, a layer including a composite material of an organic compound and a metal oxide may be combined with a transparent conductive film.

  The light-emitting element 231 having such a structure hardly transfers energy between the adjacent EL layers 220 and can be easily formed as a light-emitting element having both high light emission efficiency and a long lifetime. It is also easy to obtain phosphorescence emission with one emission layer and fluorescence emission with the other.

  Note that the charge generation layer 220a has a function of injecting holes into one EL layer 220 formed in contact with the charge generation layer 220a when a voltage is applied to the electrodes 218 and 222, It has a function of injecting electrons into the other EL layer 220.

  The light-emitting element 231 illustrated in FIG. 51B can obtain various emission colors by changing the type of the light-emitting material used for the EL layer 220. Further, by using a plurality of light emitting materials having different emission colors as the light emitting material, broad spectrum light emission or white light emission can be obtained.

  When white light emission is obtained using the light-emitting element 231 illustrated in FIG. 51B, the combination of the plurality of EL layers may be any structure that emits white light including red, blue, and green light. And a structure having an EL layer containing a blue fluorescent material as a light emitting material and an EL layer containing green and red phosphorescent materials as a light emitting material. Alternatively, an EL layer that emits red light, an EL layer that emits green light, and an EL layer that emits blue light can be used. Alternatively, white light emission can be obtained even with a structure having an EL layer that emits light in a complementary color relationship. In a stacked element in which two EL layers are stacked, when the emission colors from these EL layers are in a complementary color relationship, the complementary color relationship may be a combination of blue and yellow or blue-green and red. .

  In the structure of the stacked element described above, by arranging the charge generation layer between the stacked light emitting layers, high luminance light emission can be obtained while keeping the current density low, and a long life element can be realized. it can.

Note that quantum dots can also be used as the light emitting material. A quantum dot is a semiconductor nanocrystal having a size of several nm, and is composed of about 1 × 10 ³ to 1 × 10 ⁶ atoms. Quantum dots shift their energy depending on their size, so even if the quantum dots are made of the same material, the emission wavelength differs depending on the size, and the emission wavelength can be easily adjusted by changing the size of the quantum dots used be able to.

In addition, since the quantum dot has a narrow emission spectrum peak width, light emission with good color purity can be obtained. Furthermore, the theoretical internal quantum efficiency of quantum dots is said to be almost 100%, which is much higher than 25% of organic compounds that exhibit fluorescence and is equivalent to organic compounds that exhibit phosphorescence. For this reason, a light-emitting element with high emission efficiency can be obtained by using quantum dots as a light-emitting material. In addition, since the quantum dot which is an inorganic compound is excellent in the essential stability, a preferable light-emitting element can be obtained from the viewpoint of life.

Materials constituting the quantum dot include periodic table group 14 element, periodic table group 15 element, periodic table group 16 element, compound composed of a plurality of periodic table group 14 elements, periodic table group 4 to periodic table. Compound of group 14 element and periodic table group 16 element, periodic table group 2 element and periodic table group 16 element, periodic table group 13 element and periodic table group 15 element A compound of a periodic table group 13 element and a periodic table group 17 element, a compound of a periodic table group 14 element and a periodic table group 15 element, a periodic table group 11 element and a periodic table group 17 element Examples thereof include compounds, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide , Gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium phosphide, aluminum arsenide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, indium telluride, sulfide Indium, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, Tellurium, Hou , Carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide, calcium telluride, beryllium sulfide, beryllium selenide, Beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide , Copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, triiron tetroxide, iron oxide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide, titanium oxide, zirconium oxide, silicon nitride, nitride Germanium, aluminum oxide Barium titanate, selenium, zinc and cadmium compound, indium, arsenic and phosphorus compound, cadmium, selenium and sulfur compound, cadmium, selenium and tellurium compound, indium, gallium and arsenic compound, indium, gallium and selenium compound Examples thereof include, but are not limited to, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. Moreover, you may use what is called an alloy type quantum dot whose composition is represented by arbitrary ratios. For example, an alloy type quantum dot of cadmium, selenium, and sulfur is one of effective means for obtaining blue light emission because the emission wavelength can be changed by changing the content ratio of elements.

The structure of the quantum dot includes a core type, a core-shell type, and a core-multishell type, and any of them may be used, but the shell is covered with another inorganic material that covers the core and has a wider band gap. By forming, the influence of defects and dangling bonds existing on the nanocrystal surface can be reduced. Thereby, in order to greatly improve the quantum efficiency of light emission, it is preferable to use a core-shell type or core-multishell type quantum dot. Examples of the shell material include zinc sulfide and zinc oxide.

In addition, since the quantum dots have a high ratio of surface atoms, they are highly reactive and tend to aggregate. Therefore, it is preferable that a protective agent is attached or a protective group is provided on the surface of the quantum dots. Aggregation can be prevented and solubility in a solvent can be increased by attaching the protective agent or providing a protective group. It is also possible to reduce the reactivity and improve the electrical stability. Examples of the protecting agent (or protecting group) include polyoxyethylene alkyl ethers such as polyoxyethylene lauryl ether, polyoxyethylene stearyl ether, polyoxyethylene oleyl ether, tripropylphosphine, tributylphosphine, trihexylphosphine, Trialkylphosphines such as octylphosphine, polyoxyethylene alkylphenyl ethers such as polyoxyethylene n-octylphenyl ether, polyoxyethylene n-nonylphenyl ether, tri (n-hexyl) amine, tri (n-octyl) Tertiary amines such as amine and tri (n-decyl) amine, tripropylphosphine oxide, tributylphosphine oxide, trihexylphosphine oxide, trioctylphosphite Organic phosphorus compounds such as oxide and tridecylphosphine oxide, polyethylene glycol diesters such as polyethylene glycol dilaurate and polyethylene glycol distearate, and organic nitrogen compounds such as nitrogen-containing aromatic compounds such as pyridine, lutidine, collidine and quinolines , Hexylamine, octylamine, decylamine, dodecylamine, tetradecylamine, hexadecylamine, octadecylamine and other amino alkanes, dibutyl sulfide and other dialkyl sulfides, dimethyl sulfoxide and dibutyl sulfoxide and other dialkyl sulfoxides, and thiophene Organic sulfur compounds such as sulfur-containing aromatic compounds, higher fatty acids such as palmitic acid, stearic acid, oleic acid, alcohols, sorbitan fatty acid esters Fatty acid modified polyesters, tertiary amine modified polyurethanes and polyethylene imines, and the like.

Since the quantum dot has a band gap that increases as the size decreases, the size of the quantum dot is appropriately adjusted so that light having a desired wavelength can be obtained. As the crystal size decreases, the emission of quantum dots shifts to the blue side, that is, to the higher energy side, so changing the size of the quantum dots changes the wavelength of the spectrum in the ultraviolet, visible, and infrared regions. The emission wavelength can be adjusted over a region. The size (diameter) of the quantum dots is usually 0.5 nm to 20 nm, preferably 1 nm to 10 nm. In addition, as the quantum dot has a narrower size distribution, the emission spectrum becomes narrower and light emission with good color purity can be obtained. The shape of the quantum dots is not particularly limited, and may be spherical, rod-shaped, disk-shaped, or other shapes. In addition, since the quantum rod which is a rod-shaped quantum dot exhibits the light which has the directivity polarized in the c-axis direction, the light emitting element with more favorable external quantum efficiency can be obtained by using a quantum rod as a luminescent material. .

By the way, in many EL elements, luminous efficiency is improved by dispersing a luminescent material in a host material. However, the host material needs to be a substance having singlet excitation energy or triplet excitation energy higher than that of the luminescent material. is there. In particular, when a blue phosphorescent material is used, it is extremely difficult to develop a host material having a triplet excitation energy higher than that and having an excellent lifetime. Here, since the quantum dots can maintain the light emission efficiency even if the light emitting layer is composed of only the quantum dots without using a host material, a light emitting element that is preferable from this point of view can also be obtained. When the light emitting layer is formed only with quantum dots, the quantum dots preferably have a core-shell structure (including a core-multishell structure).

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

  A display module 8000 shown in FIG. 52 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. 8011.

  The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

  The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

  As the touch panel 8004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.

  The backlight 8007 has a light source 8008. 52 illustrates the configuration in which the light source 8008 is provided over the backlight 8007, the invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may be omitted.

  The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006. The frame 8009 may have a function as a heat sink.

  The printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

  The display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

  FIG. 53A to FIG. 53G illustrate electronic devices. These electronic devices include a housing 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or operation switch), a connection terminal 5006, a sensor 5007 (force, displacement, position, speed, Measure acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 5008, and the like.

  FIG. 53A illustrates a mobile computer which can include a switch 5009, an infrared port 5010, and the like in addition to the above components. FIG. 53B illustrates a portable image playback device (eg, a DVD playback device) provided with a recording medium, which includes a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above components. it can. FIG. 53C illustrates a goggle type display which can include a second display portion 5002, a support portion 5012, an earphone 5013, and the like in addition to the above components. FIG. 53D illustrates a portable game machine that can include the memory medium reading portion 5011 and the like in addition to the above objects. FIG. 53E illustrates a digital camera with a television receiving function, which can include an antenna 5014, a shutter button 5015, an image receiving portion 5016, and the like in addition to the above objects. FIG. 53F illustrates a portable game machine that can include the second display portion 5002, the recording medium reading portion 5011, and the like in addition to the above objects. FIG. 53G illustrates a portable television receiver that can include a charger 5017 and the like capable of transmitting and receiving signals in addition to the above components.

  The electronic devices illustrated in FIGS. 53A to 53G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying programs or data recorded on the recording medium It can have a function of displaying on the section. Further, in an electronic device having a plurality of display units, one display unit mainly displays image information and another one display unit mainly displays character information, or the plurality of display units consider parallax. It is possible to have a function of displaying a three-dimensional image, etc. by displaying the obtained image. Furthermore, in an electronic device having an image receiving unit, a function for capturing a still image, a function for capturing a moving image, a function for correcting a captured image automatically or manually, and a captured image on a recording medium (externally or incorporated in a camera) A function of saving, a function of displaying a photographed image on a display portion, and the like can be provided. Note that the functions of the electronic devices illustrated in FIGS. 53A to 53G are not limited to these, and can have various functions.

  FIG. 53H illustrates a smart watch, which includes a housing 7302, a display panel 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like.

  A display panel 7304 mounted on a housing 7302 also serving as a bezel portion has a non-rectangular display region. Note that the display panel 7304 may have a rectangular display region. The display panel 7304 can display an icon 7305 indicating time, another icon 7306, and the like.

  Note that the smart watch illustrated in FIG. 53H can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying programs or data recorded on the recording medium It can have a function of displaying on the section.

  In addition, a speaker, a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current are included in the housing 7302. , Voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared measurement function), microphone, and the like. Note that a smart watch can be manufactured by using a light-emitting element for the display panel 7304.

  The electronic device described in this embodiment includes a display portion for displaying some information. The display device described in any one of Embodiments 3 to 5 can be applied to the display portion.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

11 Substrate 12 Insulating film 13 Conductive film 14 Insulating film 15 Insulating film 16 Insulating film 17 Insulating film 17 Oxide semiconductor film 18_1 Source / drain region 18_2 Source / drain region 18i Channel region 19a Oxide semiconductor film 19b Oxide semiconductor film 19c Common electrode 21a Conductive film 21b Conductive film 21c Conductive film 27 Insulating film 29 Conductive film 51 Liquid crystal element 52 Transistor 55 Capacitor element 62 Wiring 70 Pixel 70a Pixel 70b Pixel 70c Pixel 70d Pixel 70e Pixel 70f Pixel 71 Pixel portion 74 Scan line drive circuit 75 Common line 76 Signal line driver circuit 77 Scan line 78 Wire 79 Signal line 80 Display device 100 Semiconductor device 100A Semiconductor device 100B Semiconductor device 100C Semiconductor device 100D Semiconductor device 100E Semiconductor device 100F Semiconductor device 100G Semiconductor device 102 Substrate 04 insulating film 106 gate electrode 107 oxide semiconductor film 108 oxide semiconductor film 108_1 oxide semiconductor film 108_2 oxide semiconductor film 108_3 oxide semiconductor film 108b oxide semiconductor film 108d drain region 108f region 108i channel region 108s source region 110 insulating film 110_0 insulating film 111 oxide semiconductor film 111_0 oxide semiconductor film 111a oxide semiconductor film 111b oxide semiconductor film 112 conductive film 112_0 conductive film 116 insulating film 117 EL layer 118 insulating film 120a conductive film 120b conductive film 120c conductive film 122 insulating film 123 conductive film 124 conductive film 140 mask 141a opening 141b opening 142 opening 143 opening 144 opening 145 opening 150 transistor 150A transistor 150B transistor 150 C transistor 150D transistor 150E transistor 150F transistor 150G transistor 160 capacitor element 218 electrode 220 EL layer 220a charge generation layer 222 electrode 230 light emitting element 231 light emitting element 301 display unit 302 pixel 302B subpixel 302G subpixel 302R subpixel 302t transistor 303c capacitor 303g scanning Line driver circuit 303s Image signal line driver circuit 303t Transistor 311 Wiring 319 Terminal 321 Insulating film 328 Partition 350R Light emitting element 351R Lower electrode 351Ra Transflective electrode 352 Upper electrode 353 EL layer 353a EL layer 353b EL layer 354 Intermediate layer 360 Adhesive layer 367BM Light shielding Film 367p Antireflection layer 367R Colored film 380B Light emitting module 380G Light emitting module 380R Light emitting module 4 0a pixel 400b pixel 401 pulse voltage output circuit 402 the current detection circuit 403 capacitor 410 touch panel 411 substrate 412 substrate 413 FPC
414 conductive film 419a conductive film 419b conductive film 420a liquid crystal element 420b liquid crystal element 421 electrode 422 electrode 423 liquid crystal 424 insulating film 426 opening 428a conductive film 428b conductive film 429a conductive film 429b conductive film 431 colored film 453 wiring 454 wiring 459a sensor electrode 459b Sensor electrode 461 Wiring 463 Transistor 464 Liquid crystal element 465_1 Block 465_2 Block 467_1 Block 467_4 Block 471 Electrode 471_1 Electrode 471_2 Electrode 472 Electrode 472_1 Electrode 472_4 Electrode 501 Display portion 503 Adhesive layer 504 Insulating film 505 Touch panel 509 FPC
510 Substrate 511 Substrate 513 Adhesive layer 515 Insulating film 531 Electrode 532 Electrode 533 Electrode 534 Bridge electrode 536 Electrode 537 Electrode 538 Intersection 541 Wiring 542 Wiring 550 FPC
555 region 561 conductive film 562 conductive film 563 conductive film 564 nanowire 590 substrate 591 electrode 592 electrode 593 insulating film 594 wiring 595 touch sensor 597 adhesive layer 598 wiring 599 connection layer 601 substrate 602 substrate 604 insulating film 606 gate wiring 607 capacitance wiring 609 capacitance Wiring 611b Pixel electrode 612b Pixel electrode 616 Insulating film 618 Insulating film 620a Wiring 620b Drain electrode 622 Insulating film 629 Transistor 630 Capacitor element 641b Opening 650 Transistor 651 Transistor 661 Capacitor element 662 Capacitor element 671 Slit 673 Colored film 674 Slit 675 Protrusion 677 Alignment film 678 Alignment film 680 Liquid crystal layer 681 Liquid crystal element 682 Liquid crystal element 700A Display device 700B Display device 700C Display device 70 Substrate 702 a pixel portion 704 source driver circuit portion 705 substrate 706 gate driver circuit unit 708 FPC terminal portion 710 wiring 711 wiring portion 712 sealing material 716 FPC
734 Insulating film 736 Colored film 738 Light shielding film 746 Alignment film 748 Alignment film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulation film 766 Insulation film 768 Insulation film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 781 Adhesive layer 782 Conductive film 783 Insulating film 784 Conductive film 785 EL element 786 EL layer 790 Capacitor element 791 Anisotropic conductive film 4616 Wiring 5000 Housing 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support unit 5013 Earphone 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 Charger 7302 7304 display panel 7305 icon 7306 icon 7311 operation button 7312 operation button 7313 connection terminals 7321 band 7322 clasp 8000 display module 8001 top cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Back light 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (11)

A transistor,
A first insulating film;
A capacitor element including a third insulating film between a pair of electrodes,
The transistor is
A first oxide semiconductor film on the first insulating film;
A second insulating film on the first oxide semiconductor film;
A second oxide semiconductor film on the second insulating film;
And a third insulating film on the first oxide semiconductor film and the second oxide semiconductor film,
The first oxide semiconductor film includes:
A channel region overlapping with the second oxide semiconductor film;
A source region in contact with the third insulating film;
A drain region in contact with the third insulating film,
The source region and the drain region have one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a noble gas;
One of the pair of electrodes of the capacitor element includes the second oxide semiconductor film,
Semiconductor device. A transistor,
A first insulating film;
A capacitor element including a third insulating film between a pair of electrodes,
The transistor is
A gate electrode;
The first insulating film on the gate electrode;
A first oxide semiconductor film on the first insulating film;
A second insulating film on the first oxide semiconductor film;
A second oxide semiconductor film on the second insulating film;
And a third insulating film on the first oxide semiconductor film and the second oxide semiconductor film,
The first oxide semiconductor film includes:
A channel region overlapping with the second oxide semiconductor film;
A source region in contact with the third insulating film;
A drain region in contact with the third insulating film,
The source region and the drain region have one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a noble gas;
One of the pair of electrodes of the capacitor element includes the second oxide semiconductor film,
Semiconductor device. A transistor,
A first insulating film;
A capacitor element including a third insulating film between a pair of electrodes,
The transistor is
A gate electrode;
The first insulating film on the gate electrode;
A first oxide semiconductor film on the first insulating film;
A second insulating film on the first oxide semiconductor film;
A second oxide semiconductor film on the second insulating film;
And a third insulating film on the first oxide semiconductor film and the second oxide semiconductor film,
The gate electrode is electrically connected to the second oxide semiconductor film;
The first oxide semiconductor film includes:
A channel region overlapping with the second oxide semiconductor film;
A source region in contact with the third insulating film;
A drain region in contact with the third insulating film,
The source region and the drain region have one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a noble gas;
One of the pair of electrodes of the capacitor element includes the second oxide semiconductor film,
Semiconductor device. In any one of Claim 1 thru | or 3,
The transistor is
A fourth insulating film on the third insulating film;
A first conductive film electrically connected to the source region through an opening provided in the third insulating film and the fourth insulating film;
A second conductive film electrically connected to the drain region through an opening provided in the third insulating film and the fourth insulating film,
Semiconductor device. In claim 4,
A fifth insulating film on the fourth insulating film, the first conductive film, and the second conductive film;
A third conductive film on the fifth insulating film;
The other of the pair of electrodes of the capacitive element includes the third conductive film;
Semiconductor device. In any one of Claims 1 thru | or 5,
The capacitive element has translucency in visible light,
Semiconductor device. In any one of Claims 1 thru | or 7,
The first oxide semiconductor film and the second oxide semiconductor film are:
In-M-Zn oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Sn or Hf).
Semiconductor device. In any one of Claims 1 thru | or 7,
The third insulating film contains nitrogen or hydrogen;
Semiconductor device. In any one of Claims 1 thru | or 8,
The second insulating film contains oxygen;
Semiconductor device. A semiconductor device according to any one of claims 1 to 9,
A liquid crystal element,
Display device. A semiconductor device according to any one of claims 1 to 10,
A switch, a speaker, a display unit or a housing;
Electronic equipment having